Sony CXP81952M Cmos 8-bit single chip microcomputer Datasheet

CXP81952M/81960M
CMOS 8-bit Single Chip Microcomputer
Description
The CXP81952M/81960M is a CMOS 8-bit microcomputer which consists of A/D converter, serial
interface, timer/counter, time base timer, vector
interruption, high precision timing pattern generation
circuit, PWM generator, PWM for tuner, 32kHz
timer/event counter, remote control reception circuit,
and FRC capture unit, as well as basic configurations
like 8-bit CPU, ROM, RAM and I/O port. They are
integrated into a single chip.
Also the CXP81952M/81960M provides sleep/stop
functions which enable to lower power consumption
and ultra-low speed instruction mode in 32kHz
operation.
100 pin QFP (PIastic)
100 pin LQFP (PIastic)
Structure
Silicon gate CMOS IC
Features
• A wide instruction set (213 instructions) which covers various types of data
— 16-bit operation/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle
200ns at 20MHz operation (4.5 to 5.5V)
333ns at 12MHz operation (2.7 to 5.5V)
122µs at 32kHz operation
• Incorporated ROM capacity
52K bytes (CXP81952M), 60K bytes (CXP81960M)
• Incorporated RAM capacity
2048 bytes
• Peripheral functions
— A/D converter
8 bits, 12 channels, successive approximation system
(Conversion time of 16µs at 20MHz)
— Serial Interface
Incorporated buffer RAM (1 to 32 bytes auto transfer), 1 channel
Incorporated 8-bit and 8-stage FIFO
(1 to 8 bytes auto transfer), 1 channel
— Timer
8-bit timer, 8-bit timer/counter, 19-bit time base timer,
32kHz timer/counter
— High precision timing pattern generator PPG: maximum of 19 pins, 32 stages programmable
RTG: 5 pins, 2 channels
— PWM/DA gate output
PWM: 12 bits, 2 channels (Repetitive frequency of 78kHz at 20MHz)
DA gate pulse output: 13 bits, 4 channels
— FRC capture unit
Incorporated 26-bit and 8-stage FIFO
— PWM output
14 bits, 1 channel
— Remote control reception circuit
8-bit pulse measurement counter with on-chip 6-stage FIFO
• Interruption
20 factors, 15 vectors, multi-interruption possible
• Standby mode
Sleep/stop
• Package
100-pin plastic QFP/LQFP
• Piggyback/evaluator
CXP81900M
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95511A69-PS
8 BIT TIMER 1
PI3/TO
ADJ
PE2/PWM0
PE4/DAA0
PE6/DAB0
PE3/PWM1
PE5/DAA1
PE7/DAB1
12 BIT PWM GENERATOR CH1
12 BIT PWM GENERATOR CH0
14 BIT PWM GENERATOR
PI2/PWM
FIFO
REMOCON INPUT
PI1/RMC
PG6/EXI0
PG7/EXI1
8 BIT TIMER/COUNTER 0
FIFO
RAM
AVss
PE1/EC
SERIAL
INTERFACE UNIT
(CH1)
PI7/SI1
PI6/SO1
PI5/SCK1
A/D CONVERTER
AVDD
SERIAL
INTERFACE UNIT
(CH0)
12
2
2
4
2
2
PE0/INT0
NMI
PE1/INT2
PI4/INT1/NMI
XTAL
RST
MP
VDD
CH0
CH1
REALTIME
PULSE
GENERATOR
32kHz
TIMER/COUNTER
PRESCALER/
TIME BASE TIMER
RAM
2048 BYTES
5
RAM
PROGRAMMABLE
PATTERN
GENERATOR
2
Vss
CLOCK
GENERATOR/
SYSTEM CONTROL
AA
19
FIFO
ROM
52K/60K BYTES
SPC700
CPU CORE
FRC
CAPTURE UNIT
INTERRUPT CONTROLLER
AVREF
CS0
SI0
SO0
SCK0
AN0 to AN3
PF0/AN4
to
PF7/AN11
PA0/PPO0
to
PC2/PPO18
PC0 to PC7
PD0 to PD7
PE0 to PE1
PE2 to PE7
PF0 to PF3
PF4 to PF7
PG0 to PG7
PH0 to PH7
8
8
2
6
4
4
8
8
8
PJ0 to PJ7
PI1 to PI7
PB0 to PB7
8
7
PA0 to PA7
8
PORT B
TEX
TX
EXTAL
PC3/RTO3
to
PC7/RTO7
PORT A
PORT C
PORT D
PORT E
PORT F
PORT G
PORT H
PORT I
–2–
PORT J
Block Diagram
CXP81952M/81960M
CXP81952M/81960M
PI5/SCK1
PI4/INT1/NMI
PI3/TO/ADJ
PI2/PWM
PI1/RMC
TEX
TX
VDD
VSS
NC
PA7/PPO7
PA6/PPO6
PA5/PPO5
PA4/PPO4
PA3/PPO3
PA2/PPO2
PA1/PPO1
PA0/PPO0
PB7/PPO15
PB6/PPO14
Pin Assignment 1 (Top View) 100-pin QFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PB5/PPO13
1
80
PI6/SO1
PB4/PPO12
2
79
PI7/SI1
PB3/PPO11
3
78
PE0/INT0
PB2/PPO10
4
77
PE1/EC/INT2
PB1/PPO9
5
76
PE2/PWM0
PB0/PPO8
6
75
PE3/PWM1
PC7/RTO7
7
74
PE4/DAA0
PC6/RTO6
8
73
PE5/DAA1
PC5/RTO5
9
72
PE6/DAB0
PC4/RTO4
10
71
PE7/DAB1
PC3/RTO3
11
70
PG0
PC2/PPO18
12
69
PG1
PC1/PPO17
13
68
PG2
PC0/PPO16
14
67
PG3
PJ7
15
66
PG4
PJ6
16
65
PG5
PJ5
17
64
PG6/EXI0
PJ4
18
63
PG7/EXI1
PJ3
19
62
AN0
PJ2
20
61
AN1
PJ1
21
60
AN2
PJ0
22
59
AN3
PD7
23
58
PF0/AN4
PD6
24
57
PF1/AN5
PD5
25
56
PF2/AN6
PD4
26
55
PF3/AN7
PD3
27
54
AVDD
PD2
28
53
AVREF
PD1
29
52
AVSS
PD0
30
51
PF4/AN8
PF5/AN9
PF6/AN10
PF7/AN11
SCK0
SO0
SI0
CS0
EXTAL
XTAL
VSS
RST
MP
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 90) is always connected to VDD.
2. Vss (Pins 41 and 88) are both connected to GND.
3. MP (Pin 39) is always connected to GND.
–3–
CXP81952M/81960M
PE0/INT0
PI7/SI1
PI6/SO1
PI5/SCK1
PI4/INT1/NMI
PI3/TO/ADJ
PI2/PWM
PI1/RMC
TEX
TX
VDD
VSS
NC
PA7/PPO7
PA6/PPO6
PA5/PPO5
PA4/PPO4
PA3/PPO3
PA2/PPO2
PA1/PPO1
PA0/PPO0
PB7/PPO15
PB6/PPO14
PB5/PPO13
PB4/PPO12
Pin Assignment 2 (Top View) 100-pin LQFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PB3/PPO11
1
75
PB2/PPO10
2
74
PE2/PWM0
PB1/PPO9
3
73
PE3/PWM1
PE1/EC/INT2
PB0/PPO8
4
72
PE4/DAA0
PC7/RTO7
5
71
PE5/DAA1
PC6/RTO6
6
70
PE6/DAB0
PC5/RTO5
7
69
PE7/DAB1
PC4/RTO4
8
68
PG0
PC3/RTO3
9
67
PG1
PC2/PPO18
10
66
PG2
PC1/PPO17
11
65
PG3
PC0/PPO16
12
64
PG4
PJ7
13
63
PG5
PJ6
14
62
PG6/EXI0
PJ5
15
61
PG7/EXI1
PJ4
16
60
AN0
PJ3
17
59
AN1
PJ2
18
58
AN2
PJ1
19
57
AN3
PJ0
20
56
PF0/AN4
PD7
21
55
PF1/AN5
PD6
22
54
PF2/AN6
PD5
23
53
PF3/AN7
PD4
24
52
AVDD
PD3
25
51
AVREF
Note) 1. NC (Pin 88) is always connected to VDD.
2. Vss (Pins 39 and 86) are both connected to GND.
3. MP (Pin 37) is always connected to GND.
–4–
AVSS
PF4/AN8
PF5/AN9
PF6/AN10
PF7/AN11
SO0
SCK0
SI0
CS0
EXTAL
XTAL
VSS
MP
RST
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PD0
PD1
PD2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP81952M/81960M
Pin Description
Symbol
I/O
Description
Output/
Real-time output
(Port A)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)
PB0/PPO8
to
PB7/PPO15
Output/
Real-time output
(Port B)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)
PC0/PPO16
to
PC2/PPO18
I/O/
Real-time output
PC3/RTO3
to
PC7/RTO7
I/O/
Real-time output
PA0/PPO0
to
PA7/PPO7
(Port C)
8-bit I/O port. I/O can be set
in a unit of single bits.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)
Programmable pattern generator (PPG)
output.
Functions as high precision real-time
pulse output port.
(19 pins)
Real-time pulse generator (RTG) output.
Functions as high precision real-time
pulse output port. (5 pins)
(Port D)
8-bit I/O port. I/O can be set in a unit of 4bits.
Can drive 12mA sink current.
(8 pins)
PD0 to PD7
I/O
PE0/INT0
Input/Input
Input pin to request external interruption.
Active at the falling edge.
PE1/EC/INT2
Input/Input/Input
External event input
pin for timer/counter.
PE2/PWM0
Output/Output
PE3/PWM1
Output/Output
PE4/DAA0
Output/Output
PE5/DAA1
Output/Output
PE6/DAB0
Output/Output
PE7/DAB1
Output/Output
AN0 to AN3
Input
Analog input pins to A/D converter. (12 pins)
PF0/AN4
to
PF3/AN7
Input/Input
PF4/AN8
to
PF7/AN11
Output/Input
(Port F)
8-bit port. Lower 4 bits are for input; upper 4 bits are for output.
Lower 4 bits also serve as standby release input pin.
(8 pins)
SCK0
I/O
Serial clock (CH0) I/O pin.
SO0
Ouput
Serial data (CH0) output pin.
SI0
Input
Serial data (CH0) input pin.
CS0
Input
Serial chip select (CH0) input pin.
(Port E)
8-bit port.
Lower 2 bits
are for input;
upper 6 bits
are for output.
(8 pins)
Input pin to request
external interruption.
Active at the falling edge.
PWM output pins.
(2 pins)
DA gate pulse output pins.
(4 pins)
–5–
CXP81952M/81960M
Symbol
I/O
Description
PG0 to PG4
PG5
PG6/EXI0
Input
(Port G)
8-bit input port.
(8 pins)
External input pin to FRC capture unit.
PG7/EXI1
(Port H)
8-bit output port; N-ch open drain output of medium drive voltage (12V)
and large current (12mA).
(8 pins)
PH0 to PH7
Output
PI1/RMC
I/O/Input
Remote control reception circuit input pin.
PI2/PWM
I/O/Output
14-bit PWM output pin.
PI3/TO/ADJ
I/O/Output/Output
PI4/INT1/
NMI
I/O/Input/Input
PI5/SCK1
I/O/I/O
PI6/SO1
I/O/Output
Serial data (CH1) output pin.
PI7/SI1
I/O/Input
Serial data (CH1) input pin.
PJ0 to PJ7
I/O
EXTAL
Input
XTAL
Output
TEX
Input
TX
Output
Connects a crystal oscillator for 32kHz timer clock. When used as
event counter, input to TEX pin and leave TX pin open. (Feedback
resistor is not removed.)
RST
Input
System reset pin; active at Low level.
MP
Input
Microprocessor mode input pin. Always connect to GND.
Timer/counter, 32kHz oscillation adjustment output
pin.
Input pin to request external interruption and
non-maskable interruption. Active at the falling edge.
Serial clock (CH1) I/O pin.
(Port J)
8-bit I/O port. I/O and standby release input can be set in a unit of
single bits.
Connects a crystal oscillator for system clock. When supplying the
external clock, input the external clock to EXTAL pin and input opposite
phase clock to XTAL pin.
Positive power supply pin of A/D converter.
AVDD
AVREF
(Port I)
7-bit I/O port.
I/O port can be
set in a unit of
single bits.
(7 pins)
Input
Reference voltage input pin of A/D converter.
AVss
GND pin of A/D converter.
VDD
Positive power supply pin.
Vss
GND pin. Connect both Vss pins to GND.
–6–
CXP81952M/81960M
Input/Output Circuit Formats for Pins
Pin
When reset
Circuit format
Port A
AA
AA
Port B
PA0/PPO0
to
PA7/PPO7
PB0/PPO8
to
PB7/PPO15
AAAA
AAAA
PPO data
Port A or Port B
Data bus
RD (Port A or Port B)
Hi-Z
Output becomes active from high
impedance by data writing to port register.
16 pins
Port C
PC0/PPO16
to
PC2/PPO18
AAAA
AAAA
AAAA
PPO, RTO data
Input
protection
circuit
Port C data
PC3/RTO3
to
PC7/RTO7
AA
AA
AA
Hi-Z
IP
Port C direction
(Every bit)
Data bus
RD (Port C)
8 pins
Port D
PD0 to PD7
AAAA
AAAA
AAAA
AAAA
AA
AA
AA
Large
current
12mA
Port D data
IP
Port D direction
(Every 4 bits)
PD0 to 3
PD4 to 7
Data bus
RD (Port D)
8 pins
–7–
Hi-Z
CXP81952M/81960M
Pin
Circuit format
Port E
PE0/INT0
Data bus
A
AA A
IP
RD
(Port E)
Interruption circuit
When reset
Hi-Z
Input protection circuit
1 pin
A
A A
Port E
PE1/EC/INT2
Data bus
IP
RD (Port E)
1 pin
Hi-Z
Input protection circuit
Interruption circuit/
event counter
Port E
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
DA gate output
or PWM output
MPX
Hi-Z control
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
Port E data
AA
AA
Hi-Z
Port/DA output
selection
Data bus
RD (Port E)
4 pins
Port E
AA
AA
AAAA AA
AAAA
AA
AAAA
AAAA
DA gate output
MPX
Hi-Z control
PE6/DAB0
PE7/DAB1
Port E data
Port/DA output
selection
Data bus
2 pins
RD (Port E)
–8–
AA
AA
High level
CXP81952M/81960M
Pin
When reset
Circuit format
AAAA
AA
AA
AA
AAAA
Input multiplexer
AN0 to AN3
4 pins
Port F
Hi-Z
A/D converter
IP
Input multiplexer
PF0/AN4
to
PF3/AN7
A/D converter
IP
Hi-Z
Data bus
4 pins
RD (Port F)
AAAA
AAAAAAAA
AAAA
Port F
PF4/AN8
to
PF7/AN11
Port F data
Data bus
RD
(Port F)
4 pins
Port/AD selection
AA
AA
AA
AA
IP
Hi-Z
A/D
converter
Input multiplexer
Port G
AAAA
Schmitt input
PG0 to PG5
Data bus
IP
6 pins
Hi-Z
RD (Port G)
Port G
AAAA
Schmitt input
PG6/EXI0
PG7/EXI1
FRC capture unit
IP
2 pins
RD (Port G)
AA
AA
Port H
PH0 to PH7
Medium drive
voltage 12V
AAAA
AAAA
Port H data
Data bus
8 pins
Hi-Z
Data bus
Large current
12mA
RD (Port H)
–9–
Hi-Z
CXP81952M/81960M
Pin
AAAA
AAAAAA
AAAA AA
AA
AAAA
AAAA
AA
AA
AA
AAAA
AAAA
AAAA
AAAA
AA
AA
A
A
When reset
Circuit format
Port I
Port I function
selection
PI2 ... From 14-bit PWM
PI3 ... From timer/counter,
32kHz timer
PI2/PWM
PI3/TO/ADJ
MPX
Port I data
Port I direction
Data bus
2 pins
Hi-Z
IP
RD (Port I)
Port I
Port I data
PI1/RMC
PI4/INT1/NMI
PI7/SI1
Port I direction
RD (Port I)
PI1 ... To remote control circuit
PI4 ... To interruption circuit
PI7 ... To serial CH1
3 pins
Hi-Z
IP
Data bus
Schmitt input
AAAA
AAAA
AA
AAAA AA
AA
AAAA
AA
AA
AA
AAAA AA
AA
AA
Port I
Port I function
selection
PI5/SCK1
PI6/SO1
From serial CH1
MPX
Port I data
MPX
Port I direction
Note)
PI5 is Schmitt input
PI6 is inverter input
Data bus
2 pins
IP
RD (Port I)
To serial CH1
– 10 –
Hi-Z
CXP81952M/81960M
Pin
AAAA
AAAA
AAAA
AA
AA
AA
Circuit format
Port J
Port J data
Port J direction
PJ0 to PJ7
IP
Data bus
A
RD
(Port J)
Edge detection
Standby release
Data bus
8 pins
AA
AAAA
When reset
Hi-Z
RD (Port J direction)
CS0
SI0
Schmitt input
IP
2 pins
SO0
SO0 from SIO
1 pin
SO0 output enable
Internal serial clock
from SIO
SCK0
External serial clock to SIO
Schmitt input
1 pin
2 pins
AA
AA
AA
AA
EXTAL
AA
AA
AA
AA
AA
AA
IP
SCK0 output enable
EXTAL
XTAL
Hi-Z
To SIO
A
Hi-Z
Hi-Z
• Diagram shows the circuit
composition during
oscillation.
IP
• Feedback resistor is
removed during stop mode.
XTAL
– 11 –
Oscillation
CXP81952M/81960M
Pin
TEX
TX
2 pins
RST
AA
AA
AA
AA
TEX
When reset
Circuit format
A
32kHz
timer counter
IP
TX
AA
AA
AA AA
AA
AAAA
• Diagram shows the circuit
composition during
oscillation.
• Feedback resistor is
removed during 32kHz
oscillation circuit stop
by software.
At this time TEX pin
outputs Low level and TX
pin outputs High level.
Oscillation
Pull-up resistor
Mask option
Schmitt input
Low level
OP
IP
1 pin
MP
IP
1 pin
– 12 –
CPU mode
Hi-Z
CXP81952M/81960M
Absolute Maximum Ratings
Item
(Vss = 0V reference)
Symbol
VDD
Supply voltage
AVDD
Rating
Unit
–0.3 to +7.0
AVss to +7.0∗1
V
V
Remarks
V
Input voltage
VIN
–0.3 to +0.3
–0.3 to +7.0∗2
Output voltage
VOUT
–0.3 to +7.0∗2
V
Medium drive output voltage
VOUTP
–0.3 to +15.0
V
High level output current
IOH
–5
mA
High level total output current
∑IOH
–50
mA
Total of output pins
IOL
15
mA
Pins excluding large current outputs
(value per pin)
IOLC
20
mA
Large current output pin (value per pin∗3)
Low level total output current
∑IOL
130
mA
Total of output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
AVSS
Low level output current
V
600
380
mW
PH pin
QFP
LQFP
∗1 AVDD and VDD should be set to the same voltage.
∗2 VIN and VOUT should not exceed VDD + 0.3V.
∗3 The large current operation transistors are the N-CH transistors of the PD and PH ports.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding those conditions may adversely
affect the reliability of the LSI.
– 13 –
CXP81952M/81960M
Recommended Operating Conditions
Item
Supply voltage
Analog supply voltage
High level
input voltage
Symbol
Min.
Max.
Unit
Remarks
4.5
5.5
V
2.7
5.5
V
fc = 20MHz or less Guaranteed operation
range for high-speed
mode (1/2 frequency
fc = 12MHz or less dividing clock)
2.7
5.5
V
Guaranteed operation range for low-speed
mode (1/16 frequency dividing clock)
2.5
5.5
V
Guaranteed operation range by TEX clock
2.0
5.5
V
2.7
5.5
V
Guaranteed data hold range for stop mode
∗1
VIH
0.7VDD
VDD
V
∗2
VIHS
0.8VDD
VDD
V
5.5
V
VDD
AVDD
VIHEX
VIL
Low level
input voltage
VILS
VILEX
Operating temperature Topr
∗1
∗2
∗3
∗4
∗5
∗6
∗7
∗8
(Vss = 0V reference)
CMOS Schmitt input∗3 and PE0/INT0
CMOS Schmitt input∗6
VDD – 0.4 VDD + 0.3
V
VDD – 0.2 VDD + 0.2
V
EXTAL∗4, ∗7 and TEX∗5, ∗7
EXTAL∗4, ∗8 and TEX∗5, ∗8
0
0.3VDD
V
∗2, ∗7
0
0.2VDD
V
∗2, ∗8
0
0.2VDD
V
–0.3
0.4
V
CMOS Schmitt input∗3 and PE0/INT0
EXTAL∗4, ∗7 and TEX∗5, ∗7
–0.3
0.2
V
EXTAL∗4, ∗8 and TEX∗5, ∗8
–20
+75
°C
AVDD and VDD should be set to the same voltage.
Normal input ports (PC, PD, PF0 to PF3, PG, PI and PJ), MP
SCK0, RST, PE1/EC/INT2, PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1
Specifies only when the external clock is input.
Specifies only when the external event count clock is input.
CS0, SI0 and PG
In case of 4.5 to 5.5V supply voltage (VDD).
In case of 2.7 to 3.3V supply voltage (VDD).
– 14 –
CXP81952M/81960M
Electrical Characteristics
DC Characteristics (VDD = 4.5 to 5.5V)
Item
High level
output voltage
Low level
output voltage
Symbol
VOH
VOL
(Ta = –20 to +75°C, Vss = 0V reference)
Pins
Conditions
Min.
Typ.
Max.
Unit
PA to PD,
PE2 to PE7,
PF4 to PF7,
PH (VOL only)
PI1 to PI7
PJ, SO0, SCK0
VDD = 4.5V, IOH = –0.5mA
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
PD, PH
IIHE
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12.0mA
1.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIH = 5.5V
0.1
10
µA
–10
µA
IILR
VDD = 5.5V,
VIL = 0.4V
–0.1
RST∗1
–1.5
–400
µA
I/O leakage
current
IIZ
PA to PG,
PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST∗1
VDD = 5.5V,
VI = 0, 5.5V
±10
µA
Open drain
output leakage
current (in N-CH
Tr OFF state)
ILOH
PH
VDD = 5.5V
VOH = 12V
50
µA
39
60
mA
39
100
µA
2.1
10
mA
7
30
µA
10
µA
20
pF
IILE
Input current
EXTAL
IIHT
IILT
TEX
High speed mode (1/2 frequency
dividing clock) operation
IDD1
VDD = 5.5V, 20MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
IDDS1
Supply
current∗2
Sleep mode
IDD2
IDDS2
VDD
VDD = 5.5V, 20MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
Stop mode
IDDS3
Input capacity
CIN
VDD = 5.5V, termination of 20MHz
and 32kHz oscillation
Other than VDD,
Clock 1MHz
Vss, AVDD, and
0V other than the measured pins
AVss
10
∗1 For RST pin, specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistor is selected.
∗2 When all output pins are open.
– 15 –
CXP81952M/81960M
DC Characteristics (VDD = 2.7 to 3.3V)
Item
High level
output voltage
Low level
output voltage
Symbol
VOH
VOL
(Ta = –20 to +75°C, Vss = 0V reference)
Pins
Conditions
Min.
Typ.
Max.
Unit
PA to PD,
PE2 to PE7,
PF4 to PF7,
PH (VOL only)
PI1 to PI7
PJ, SO0, SCK0
VDD = 2.7V, IOH = –0.12mA
2.5
V
VDD = 2.7V, IOH = –0.45mA
2.1
V
PD, PH
IIHE
VDD = 2.7V, IOL = 1.0mA
0.25
V
VDD = 2.7V, IOL = 1.4mA
0.4
V
VDD = 2.7V, IOL = 4.5mA
0.9
V
VDD = 3.3V, VIH = 3.3V
0.3
20
µA
VDD = 3.3V, VIL = 0.3V
–0.3
–20
µA
VDD = 3.3V, VIH = 3.3V
0.1
10
µA
–10
µA
IILR
VDD = 3.3V,
VIL = 0.3V
–0.1
RST∗1
–0.9
–200
µA
I/O leakage
current
IIZ
PA to PG,
PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST∗1
VDD = 3.3V,
VI = 0, 3.3V
±10
µA
Open drain
output leakage
current
ILOH
PH
VDD = 3.3V,
VOH = 12V
50
µA
13
25
mA
0.7
2.0
mA
10
µA
20
pF
IILE
Input current
EXTAL
IIHT
IILT
TEX
12MHz crystal oscillation (C1 = C2 = 15pF)
IDD1
Supply
current∗2
IDDS1
IDDS3
VDD = 3.0V ± 0.3V∗3
Sleep mode
VDD
VDD = 3.0V ± 0.3V
Stop mode
(EXTAL and TEX pins oscillation stop)
VDD = 3.0V ± 0.3V
Input capacity
CIN
Other than VDD,
Clock 1MHz
Vss, AVDD, and
0V other than the measured pins
AVss
10
∗1 For RST pin, specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistor is selected.
∗2 When all output pins are open.
∗3 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to “00” and
operating in high-speed mode (1/2 dividing clock).
– 16 –
CXP81952M/81960M
AC Characteristics
(1) Clock timing
Item
(Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V reference)
Symbol
System clock frequency
fC
Pins
Conditions
XTAL
EXTAL
Fig. 1,
1
20
1
12
Fig. 2
VDD = 4.5 to 5.5V
tXL,
tXH
XTAL
EXTAL
Fig. 1,
System clock input
rise and fall times
XTAL
EXTAL
Fig. 1, Fig. 2
(External clock drive)
EC
Fig. 3
Event count clock input
rise and fall times
tCR,
tCF
tEH,
tEL
tER,
tEF
EC
Fig. 3
System clock frequency
fC
TEX
TX
Fig. 2 VDD = 2.5 to 5.5V
(32kHz clock applied condition)
Event count clock input
pulse width
tTL,
tTH
tTR,
tTF
TEX
Fig. 3
TEX
Fig. 3
Event count clock input
rise and fall times
Max.
VDD = 4.5 to 5.5V
System clock input
pulse width
Event count clock input
pulse width
Min.
Fig. 2 (External clock drive)
23
Unit
MHz
ns
37.5
200
tsys × 4∗1
ns
ns
20
ns
32.768
kHz
10
µs
20
ms
∗1 tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2
bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Fig. 1. Clock timing
1/fc
VDD – 0.4V
EXTAL
0.4V
tXH
tCF
tXL
tCR
Fig. 2. Clock applied condition
AAAA
AAAAA
AAAAA
AAAA
AAAAA
AAAAA
AAAA AAAAAAAAAA
Crystal oscillation
Ceramic oscillation
EXTAL
C1
32kHz clock applied condition
crystal oscillation
External clock
EXTAL
XTAL
C2
TEX
XTAL
TX
C1
74HC04
C2
Fig. 3. Event count clock timing
0.8VDD
TEX
EC
0.2VDD
tEH
tTH
tEF
tTF
tEL
tTL
– 17 –
tER
tTR
CXP81952M/81960M
(2) Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
Condition
Min.
Max.
Unit
CS ↓ → SCK
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 200
ns
CS ↑ → SCK
floating delay time
tDCSKF SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 200
ns
CS ↓ → SO
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 200
ns
CS ↓ → SO
floating delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS
High level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK
cycle time
Input mode
SCK0
2tsys + 200
ns
tKCY
16000/fc
ns
SCK
High and Low level widths
tKH
tKL
tsys + 100
ns
SCK0
Output mode
8000/fc – 100
ns
SI input setup time
(for SCK ↑)
SCK input mode
SI0
–tsys + 100
ns
tSIK
200
ns
SI input hold time
(for SCK ↑)
SI0
2tsys + 100
ns
tKSI
100
ns
SCK ↓ → SO delay time
tKSO
SO0
Output mode
Input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
2tsys + 200
ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Note 2) CS, SCK, SI and SO represents CS0, SCK0, SI0 and SO0, respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
– 18 –
CXP81952M/81960M
Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Symbol
Pin
Condition
Min.
Max.
Unit
CS ↓ → SCK
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 250
ns
CS ↑ → SCK
floating delay time
tDCSKF SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 200
ns
CS ↓ → SO
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 250
ns
CS ↓ → SO
floating delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS
High level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK
cycle time
Input mode
SCK0
2tsys + 200
ns
tKCY
16000/fc
ns
SCK
High and Low level widths
tKH
tKL
tsys + 100
ns
SCK0
Output mode
8000/fc – 150
ns
SI input setup time
(for SCK ↑)
SCK input mode
SI0
–tsys + 100
ns
tSIK
200
ns
SI input hold time
(for SCK ↑)
SI0
2tsys + 100
ns
tKSI
100
ns
SCK ↓ → SO delay time
tKSO
SO0
Output mode
Input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
2tsys + 250
ns
125
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Note 2) CS, SCK, SI and SO represents CS0, SCK0, SI0 and SO0, respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF.
– 19 –
CXP81952M/81960M
Fig. 4. Serial transfer timing (CH0)
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tSIK
tKSI
0.8VDD
Input
data
SI0
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output
data
0.2VDD
– 20 –
CXP81952M/81960M
Serial transfer (CH1)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
Condition
tKCY
SCK1
SCK1 High and Low
level widths
tKH
tKL
SCK1
SI1 input setup time
(for SCK1 ↑)
tSIK
SI1
SI1 input hold time
(for SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
Max.
Unit
2tsys + 200
ns
8000/fc
ns
tsys + 100
ns
4000/fc – 100
ns
SCK1 input mode
100
ns
SCK1 output mode
200
ns
tsys + 200
ns
100
ns
Input mode
SCK1 cycle time
Min.
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
tsys + 200
ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Serial transfer (CH1)
Item
(Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Symbol
Pin
SCK1 cycle time
tKCY
SCK1
SCK1 High and Low
level widths
tKH
tKL
SCK1
SI1 input setup time
(for SCK1 ↑)
tSIK
SI1
SI1 input hold time
(for SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
Condition
Min.
Max.
Unit
2tsys + 200
ns
8000/fc
ns
tsys + 100
ns
4000/fc – 150
ns
SCK1 input mode
100
ns
SCK1 output mode
200
ns
tsys + 200
ns
100
ns
Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
tsys + 250
ns
125
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF.
– 21 –
CXP81952M/81960M
Fig. 5. Serial transfer CH1 timing
tKCY
tKL
tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD
SI1
Input data
0.2VDD
tKSO
0.8VDD
Output data
SO1
0.2VDD
– 22 –
CXP81952M/81960M
(4) A/D converter characteristics
(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)
Item
Symbol
Pins
Conditions
Min.
Typ.
Max.
Unit
8
Bits
±1
LSB
±2
LSB
Resolution
Ta = 25°C
VDD = AVDD = AVREF = 5.0V
VSS = AVSS = 0V
Linearity error
Absolute error
160/fADC∗1
12/fADC∗1
tCONV
tSAMP
Conversion time
Sampling time
Reference input voltage VREF
Analog input voltage
VIAN
VDD = AVDD = 4.5 to 5.5V
AVREF
AVREF current
IREFS
µs
AVDD
AVDD – 0.5
0.6
Operating mode
1.0
mA
10
µA
Sleep mode
Stop mode
32kHz operating mode
AVREF
V
V
0
AN0 to AN11
IREF
µs
(Ta = –20 to +75°C, VDD = AVDD = 2.7 to 3.3V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V reference)
Item
Symbol
Pins
Conditions
Min.
Typ.
Max.
Unit
8
Bits
±1
LSB
±2
LSB
Resolution
Ta = 25°C
VDD = AVDD = AVREF = 3.0V
VSS = AVSS = 0V
Linearity error
Absolute error
160/fADC∗1
12/fADC∗1
tCONV
tSAMP
Conversion time
Sampling time
Reference input voltage VREF
Analog input voltage
VIAN
AVREF
AVREF current
IREFS
AVDD
0
Operating mode
AVREF
µs
VDD = AVDD = 2.7 to 3.3V AVDD – 0.3
AN0 to AN11
IREF
µs
V
0.3
0.7
mA
10
µA
Sleep mode
Stop mode
32kHz operating mode
Fig. 6. Definitions of A/D converter terms
Digital conversion value
FFH
FEH
∗1 The value of fADC is as follows by selecting ADC
operation clock (MSC: Address 01FFH bit 0).
When PS2 is selected, fADC = fc/2
When PS1 is selected, fADC = fc
Linearity error
01H
00H
VFT
VZT
Analog input
– 23 –
V
CXP81952M/81960M
(4) Interruption, reset input
(Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V reference)
Item
Symbol
Pins
Conditions
External interruption
High and Low level widths
tIH
tIL
INT0
INT1
INT2
NMI
PJ0 to PJ7
Reset input Low level width
tRSL
RST
Min.
Max.
Unit
1
µs
32/fc
µs
Fig. 7. Interruption input timing
INT0
INT1
INT2
NMI
PJ0 to PJ7
(During standby release input)
(Falling edge)
tIH
tIL
0.8VDD
0.2VDD
Fig. 8. Reset input timing
tRSL
RST
0.2VDD
(Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V reference)
(5) Others
Item
Symbol
EXI input
High and Low level widths
Note)
tEIH
tEIL
Pins
Conditions
EXI0
EXI1
tsys = 2000/fc
Min.
Max.
tFRC × 8 + 200 + tsys
Unit
ns
tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
tFRC = 1000/fc [ns]
Fig. 9. Other timings
tEIH
EXI0
EXI1
tEIL
0.8VDD
0.2VDD
– 24 –
CXP81952M/81960M
Appendix
Fig. 10. Recommended oscillation circuit
(i)
AAAA
AAAA
AAAA
EXTAL
AAAA
AAAA
AAAA
(ii)
TEX
XTAL
Rd
C1
RIVER
ELETEC
CO., LTD.
Rd
C2
Manufacturer
Model
TX
C2
C1
Rd (Ω)
Circuit
example
0
(i)
0
(i)
18
470K
(ii)
2∗1
0∗1
(i)
fc (MHz)
C1 (pF)
C2 (pF)
8.00
10
10
5
5
8.00
16 (12)
16 (12)
10.00
16 (12)
16 (12)
12.00
12
12
16.00
12
12
32.768kHz
30
20.00
2∗1
10.00
HC-49/U03
12.00
16.00
HC-49/U (-S)
KINSEKI LTD.
P3
NIHON DENPA
AT-51
KOGYO CO., LTD
∗1 Typical
Mask option table
Content
Item
Reset pin pull-up resistor
Non-existent
Existent
– 25 –
CXP81952M/81960M
Characteristics Curve
IDD vs. VDD
IDD vs. fc
(fc = 16MHz, Ta = 25°C, Typical)
(VDD = 5V, Ta = 25°C, Typical)
20.0
10.0
1/16 dividing mode
1/2 dividing mode
5.0
30
SLEEP mode
1.0
32kHz mode
(instruction)
0.5
0.1
(100µA)
0.05
(50µA)
32kHz
SLEEP mode
IDD – Supply current [mA]
IDD – Supply current [mA]
40
1/2 dividing mode
1/4 dividing mode
20
1/4 dividing mode
10
1/16 dividing mode
0.01
(10µA)
SLEEP mode
3
4
5
6
5
10
16
fc – System clock [MHz]
0
VDD – Supply voltage [V]
20
IDD vs. fc
IDD vs. VDD
(VDD = 3.0V, Ta = 25°C, Typical)
(fc = 12MHz, Ta = 25°C, Typical)
40
1/2 dividing mode
20.0
1/4 dividing mode
10.0
1/16 dividing mode
30
SLEEP mode
1.0
0.5
0.1
(100µA)
0.05
(50µA)
IDD – Supply current [mA]
IDD – Supply current [mA]
5.0
20
1/2 dividing mode
10
1/4 dividing mode
0.01
(10µA)
1/16 dividing mode
SLEEP mode
3
4
5
6
0 1
VDD – Supply voltage [V]
– 26 –
5
10
fc – System clock [MHz]
15
CXP81952M/81960M
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1
0.15 – 0.05
15.8 ± 0.4
+ 0.4
14.0 – 0.01
17.9 ± 0.4
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12 M
0° to 15°
DETAIL A
0.8 ± 0.2
(16.3)
0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
QFP-100P-L01
LEAD TREATMENT
EIAJ CODE
∗QFP100-P-1420-A
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.4g
JEDEC CODE
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗
14.0 ± 0.1
75
51
76
(15.0)
50
0.5 ± 0.2
A
26 (0.22)
100
1
0.5 ± 0.08
+ 0.08
0.18 – 0.03
25
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0.1 ± 0.1
0° to 10°
0.5 ± 0.2
Package Outline
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY/PHENOL RESIN
SONY CODE
LQFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP100-P-1414-A
LEAD MATERIAL
42 ALLOY
JEDEC CODE
PACKAGE WEIGHT
– 27 –
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