Cypress CY2XP41ZXC Crystal to lvpecl clock generator Datasheet

CY2XP41
Crystal to LVPECL Clock Generator
Features
Functional Description
■
One LVPECL output pair
■
External crystal frequency: 25.0 MHz
■
Selectable Output Frequency: 62.5 MHz or 75 MHz
■
Low RMS phase jitter at 75 MHz, using 25 MHz crystal (1.5
MHz–10 MHz): 0.27 ps (typical)
■
Low RMS phase jitter at 62.5 MHz, using 25 MHz crystal (1.5
MHz–10 MHz): 0.38 ps (typical)
■
Pb-free 8-Pin TSSOP package
■
Supply voltage: 3.3V
■
Commercial Temperature Range
The CY2XP41 is a PLL (Phase Locked Loop) based high
performance clock generator. It is optimized to generate high
performance clock frequencies for DVD-R applications. It uses
Cypress’s low noise VCO technology to achieve less than 1 ps
typical RMS phase jitter, that meets application jitter
requirements. The CY2XP41 has a crystal oscillator interface
input and one LVPECL output pair.
Logic Block Diagram
XIN
Crystal
Oscillator
External
Crystal
PLL
CLK
CLK#
XOUT
FS
Cypress Semiconductor Corporation
Document #: 001-48923 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 12, 2008
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CY2XP41
Pinouts
Figure 1. Pin Diagram - 8 Pin TSSOP
VDD
1
8
VDD
VSS
2
7
CLK
XOUT
3
6
CLK#
XIN
4
5
FS
Table 1. Pin Definitions - 8 Pin TSSOP
Pin
Name
Type
Description
1, 8
VDD
Power
3.3V power supply. All supply current flows through pin 1
2
VSS
Power
Ground
3, 4
XOUT, XIN
XTAL output and input
Parallel resonant crystal interface
5
FS
LVCMOS/LVTTL input
Frequency Select Input, See “Frequency Table” on page 3
6,7
CLK#, CLK
LVPECL output
Differential Clock Output
Document #: 001-48923 Rev. *A
Page 2 of 8
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CY2XP41
Frequency Table
Input
Output Frequency (MHz)
Input Xtal Frequency (MHz)
FS
25
0
62.5
25
1
75.0
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
VDD
Supply Voltage
–0.5
4.4
V
VIN[1.]
Input Voltage, DC
Relative to VSS
–0.5
VDD + 0.5
V
TS
Temperature, Storage
Non Functional
–65
TJ
Temperature, Junction
ESDHBM
ESD Protection (Human Body Model) JEDEC STD 22-A114-B
UL–94
Flammability Rating
At 1/8 in.
V–0
ΘJA[2]
Thermal Resistance, Junction to
Ambient
0 m/s airflow
100
1 m/s airflow
91
2.5 m/s airflow
87
150
°C
135
°C
2000
V
°C/W
Operating Conditions
Parameter
Description
VDD
3.3V Supply Voltage
TA
Ambient Temperature, Commercial
TPU
Power up time for all VDD to reach minimum specified voltage (ensure power
ramps are monotonic)
Min
Max
Unit
3.135
3.465
V
0
70
°C
0.05
500
ms
Electrical Characteristics for Input
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VIL
Input Low Voltage
–
–
0.3*VDD
V
VIH
Input High Voltage
0.7*VDD
–
–
V
IIL
Input Low Current
FS = VSS
–50
–
–
µA
IIH
Input High Current
FS = VDD
–
–
115
µA
CIN
Input Capacitance
15
pF
DC Electrical Characteristics for Power Supplies
Parameter
IDD[3]
Description
Power Supply Current with output terminated
Min
Typ
Max
Unit
–
–
180
mA
Note
1. The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of
copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metallization. No vias are included in the model.
3. IDD includes ~16 mA of current that is dissipated externally in the output termination resistors.
Document #: 001-48923 Rev. *A
Page 3 of 8
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CY2XP41
DC Electrical Characteristics for LVPECL Output
Parameter
Description
Min
Typ
Max
Unit
VCM
Common-Mode Voltage (CLK + CLK#) / 2, defined in Figure 5 on page 5, using
Figure 2 on page 5 circuit.
175
–
2000
mV
VPP
Differential Peak Output Voltage, defined in Figure 5 on page 5, using Figure 2
on page 5 circuit.
350
780
850
mV
Min
Typ
Max
Unit
25
–
MHz
Crystal Characteristics
Parameter
Description
Mode of Oscillation
F
Fundamental
Frequency
–
ESR
Equivalent Series Resistance
–
–
50
Ω
CL
Crystal Load Capacitance
–
10
–
pF
CS
Shunt Capacitance
–
–
7
pF
DL
Crystal Drive Level
–
–
300
μW
Min
Typ
Max
Unit
AC Characteristics
Parameter
Description
FOUT
Output Frequency
TR/TF
Output Rise/Fall time
TJitter(φ)
RMS Phase Jitter (Random)
TDC
Duty Cycle
Document #: 001-48923 Rev. *A
Test Conditions
62.5
–
75.0
MHz
Defined in Figure 5 on page 5
–
350
–
ps
75 MHz, (1.5 MHz - 10 MHz filter), 3.3V
–
0.27
–
ps
62.5 MHz, (1.5 MHz - 10 MHz filter), 3.3V
–
0.38
–
ps
Defined in Figure 4 on page 5
45
–
55
%
Page 4 of 8
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CY2XP41
Measurement Definitions
Figure 2. Output Load AC Test Circuit
3.3V
3.3V
CLK
Z=50Ω
CLK#
Z=50Ω
110Ω
110Ω
62Ω
62Ω 2pF
Measurement
Point
2pF
Figure 3. RMS Phase Jitter
Phase Noise
Noise Power
Phase Noise Mask
40dB/Decade
20dB/Decade
1.5MHz
10MHz
Offset Frequency
RMS Jitter = v Area Under the Masked Phase Noise Plot
Figure 4. Output Duty Cycle
CLK
TDC =
CLK#
TPW
TPERIOD
TPW
TPERIOD
Figure 5. Output Rise and Fall Time and Peak-Peak Voltage Swing
CLK
80%
VPP
20%
CLK#
TR
TF
VCM
VSS
Document #: 001-48923 Rev. *A
Page 5 of 8
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CY2XP41
Crystal Input Interface
Application Information
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins degrades performance. To achieve optimum jitter performance, good power supply isolation practices are advised.
Figure 6. shows a typical filtering scheme. Since all of the current
flows through pin 1, the resistance and inductance between this
pin and the supply is minimized. A 0.01 or 0.1 µF ceramic chip
capacitor is also located close to this pin to provide a short and
low impedance AC path to ground. A ~5 to 10 µF tantalum
capacitor is also located in the vicinity of this device.
Figure 6. Power Supply Filtering
Figure 7. Crystal Input Interface
XIN
External
Crystal
C1
XOUT
C2
V DD
(Pin 8)
VDD
(Pin 1)
The CY2XP41 is characterized with 10 pF parallel resonant
crystals. The capacitor values shown in Figure 7. are determined
using a 25 MHz 10 pF parallel resonant crystal and are chosen
to minimize the ppm error. Cypress recommends the
following C1 and C2 values: C1 = C2 = 6.8pF.
3.3V
0.1μF
0.01 µF
10µF
Termination for 3.3V LVPECL Output
CLK and CLK# are pull up drivers that generate ECL/LVPECL
compatible outputs. Therefore, terminating resistors (DC current
path to ground) or current sources are used for functionality.
Matched impedance techniques are used to maximize operating
frequency and minimize signal distortion. Figure 2 on page 5
shows a termination scheme that is recommended as a
guideline. Other suitable clock layouts exist and it is recommended that the board designers simulate to guarantee compatibility across all printed circuit and process variations. Cypress
recommends the following RU and RD values: RU=110Ω and
RD=62Ω. This is a 40Ω load, which is used to achieve the
specified common mode and peak-to-peak voltage swing. For
optimal signal integrity, 40Ω traces are recommended.
Document #: 001-48923 Rev. *A
Page 6 of 8
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CY2XP41
Ordering Information
Part Number
Package Type
Product Flow
CY2XP41ZXC
8-Pin TSSOP
Commercial, 0°C to 70°C
CY2XP41ZXCT
8-Pin TSSOP–Tape and Reel
Commercial, 0°C to 70°C
Package Drawing and Dimensions
Figure 8. 8-Pin Thin Shrunk Small Outline Package (4.40mm Body) Z8
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
8
0.65[0.025]
BSC.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
0.25[0.010]
BSC
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
0.05[0.002]
0.15[0.006]
2.90[0.114]
3.10[0.122]
SEATING
PLANE
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85093-*A
Document #: 001-48923 Rev. *A
Page 7 of 8
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CY2XP41
Document History Page
Document Title: CY2XP41 Crystal to LVPECL Clock Generator
Document Number: 001-48923
REV.
ECN NO.
Submission
Date
Orig. of
Change
**
2669117
03/05/09
XHT/CXQ/
KVM
New data sheet
*A
2718433
06/12/09
WWZ/HMT
No change. Submit to ECN for product launch.
Description of Change
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© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
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OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-48923 Rev. *A
Revised June 12, 2008
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