CY62146ESL MoBL® 4-Mbit (256K x 16) Static RAM Features ■ Very high speed: 45 ns mode reduces power consumption by more than 99% when deselected (CE HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when: ■ Wide voltage range: 2.2V–3.6V and 4.5V–5.5V ■ Deselected (CE HIGH) ■ Ultra low standby power ❐ Typical Standby current: 1 μA ❐ Maximum Standby current: 7 μA ■ Outputs are disabled (OE HIGH) ■ Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) ■ Write operation is active (CE LOW and WE LOW) ■ Ultra low active power ❐ Typical active current: 2 mA at f = 1 MHz ■ Easy memory expansion with CE and OE features ■ Automatic power down when deselected ■ CMOS for optimum speed and power ■ Available in Pb-free 44-pin TSOP II package To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the “Truth Table” on page 10 for a complete description of read and write modes. Functional Description The CY62146ESL is a high performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption when addresses are not toggling. Placing the device into standby For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Logic Block Diagram SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 256K x 16 RAM Array IO0–IO7 IO8–IO15 • BHE WE CE OE BLE A17 A15 A16 A13 A14 A11 Cypress Semiconductor Corporation Document #: 001-43142 Rev. ** A12 COLUMN DECODER 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 04, 2008 [+] Feedback CY62146ESL MoBL® Pin Configuration Figure 1. 44-Pin TSOP II (Top View) [1] A4 A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 NC A8 A9 A10 A11 A12 Product Portfolio Power Dissipation Product Range VCC Range (V) [2] Speed (ns) Operating ICC, (mA) f = 1MHz Typ CY62146ESL Industrial 2.2V–3.6V and 4.5V–5.5V 45 2 [3] f = fmax Standby, ISB2 (μA) Max Typ [3] Max Typ [3] Max 2.5 15 20 1 7 Notes 1. NC pins are not connected on the die. 2. Datasheet specifications are not guaranteed for VCC in the range of 3.6V to 4.5V. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3V, and VCC = 5V, TA = 25°C. Document #: 001-43142 Rev. ** Page 2 of 12 [+] Feedback CY62146ESL MoBL® Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Latch up Current...................................................... >200 mA Operating Range Supply Voltage to Ground Potential..................–0.5V to 6.0V Device Range Ambient Temperature VCC[6] DC Voltage Applied to Outputs in High-Z State[4, 5] ...........................................–0.5V to 6.0V CY62146ESL Industrial –40°C to +85°C 2.2V–3.6V, and 4.5V–5.5V DC Input Voltage[4, 5] ........................................–0.5V to 6.0V Electrical Characteristics Over the Operating Range 45 ns Parameter VOH VOL VIH VIL Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Test Conditions 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 2.7 < VCC < 3.6 IOH = –1.0 mA 2.4 2.4 Max IOH = –1.0 mA IOL = 0.1 mA 0.4 2.7 < VCC < 3.6 IOL = 2.1mA 0.4 4.5 < VCC < 5.5 IOL = 2.1mA 0.4 2.2 < VCC < 2.7 1.8 VCC + 0.3 2.7 < VCC < 3.6 2.2 VCC + 0.3 4.5 < VCC < 5.5 2.2 VCC + 0.5 2.2 < VCC < 2.7 –0.3 0.6 2.7 < VCC < 3.6 –0.3 0.8 4.5 < VCC < 5.5 –0.5 0.8 Input Leakage Current Output Leakage Current GND < VO < VCC, Output Disabled GND < VI < VCC ICC VCC Operating Supply Current f = fmax = 1/tRC f = 1 MHz Unit V 4.5 < VCC < 5.5 IIX ISB2 Typ [3] 2.2 < VCC < 2.7 IOZ ISB1 Min V V V –1 +1 μA –1 +1 μA 15 20 mA 2 2.5 1 7 μA 1 7 μA VCC = VCCmax IOUT = 0 mA, CMOS levels Automatic CE Power CE > VCC − 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, down Current — CMOS f = fmax (Address and Data Only), Inputs f = 0 (OE, BHE, BLE and WE), VCC = VCC(max) Automatic CE Power CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, down Current — CMOS f = 0, VCC = VCC(max) Inputs Notes 4. VIL(min) = –2.0V for pulse durations less than 20 ns. 5. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 6. Full Device AC operation assumes a 100 μs ramp time from 0 to VCC (min) and 200 μs wait time after VCC stabilization. Document #: 001-43142 Rev. ** Page 3 of 12 [+] Feedback CY62146ESL MoBL® Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF TSOP II Unit 77 °C/W 13 °C/W Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board AC Test Loads and Waveforms R1 VCC VCC OUTPUT 10% GND R2 Rise Time = 1 V/ns 30 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V TH Parameters 2.5V 3.0V 5.0V Unit R1 16667 1103 1800 Ω R2 15385 1554 990 Ω RTH 8000 645 639 Ω VTH 1.20 1.75 1.77 V Document #: 001-43142 Rev. ** Page 4 of 12 [+] Feedback CY62146ESL MoBL® Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR [7] Chip Deselect to Data Retention Time tR [8] Operation Recovery Time Conditions Min Typ[3] Max 1.5 CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V VCC = 1.5V Unit V 1 7 μA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC VCC(min) VDR > 1.5V tCDR VCC(min) tR CE Notes 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs. Document #: 001-43142 Rev. ** Page 5 of 12 [+] Feedback CY62146ESL MoBL® Switching Characteristics Over the Operating Range [9] Parameter Description 45 ns Min Max Unit Read Cycle tRC Read Cycle Time 45 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 45 ns tDOE OE LOW to Data Valid 22 ns 18 ns LOW-Z[10] tLZOE OE LOW to tHZOE OE HIGH to High-Z[10, 11] tLZCE CE LOW to Low-Z[10] ns 45 10 ns 5 ns 10 High-Z[10, 11] ns ns tHZCE CE HIGH to tPU CE LOW to Power Up tPD CE HIGH to Power Down 45 ns tDBE BLE/BHE LOW to Data Valid 22 ns tLZBE tHZBE BLE/BHE LOW to Low-Z[10] BLE/BHE HIGH to HIGH-Z[10, 11] 18 0 ns ns 5 ns 18 ns Write Cycle[12] tWC Write Cycle Time 45 ns tSCE CE LOW to Write End 35 ns tAW Address Setup to Write End 35 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 35 ns tBW BLE/BHE LOW to Write End 35 ns tSD Data Setup to Write End 25 ns tHD Data Hold from Write End 0 ns tHZWE tLZWE WE LOW to High-Z[10, 11] [10] WE HIGH to Low-Z 18 10 ns ns Notes 9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3V, and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 4. 10. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document #: 001-43142 Rev. ** Page 6 of 12 [+] Feedback CY62146ESL MoBL® Switching Waveforms Figure 2. Read Cycle No.1: Address Transition Controlled. [13, 14] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 3. Read Cycle No. 2: OE Controlled [14, 15] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/BLE tHZBE tDBE tLZBE HIGH IMPEDANCE HIGHIMPEDANCE DATA VALID DATA OUT tLZCE tPU VCC SUPPLY CURRENT ICC 50% 50% ISB Notes 13. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL. 14. WE is HIGH for read cycle. 15. Address valid before or similar to CE, BHE, BLE transition LOW. Document #: 001-43142 Rev. ** Page 7 of 12 [+] Feedback CY62146ESL MoBL® Switching Waveforms (continued) Figure 4. Write Cycle No 1: WE Controlled [12, 16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE DATA IO tSD NOTE 18 tHD DATAIN tHZOE Figure 5. Write Cycle 2: CE Controlled [12, 16, 17] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA IO tHD DATAIN NOTE 18 tHZOE Notes 16. Data IO is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 18. During this period, the IOs are in output state. Do not apply input signals. Document #: 001-43142 Rev. ** Page 8 of 12 [+] Feedback CY62146ESL MoBL® Switching Waveforms (continued) Figure 6. Write Cycle 3: WE controlled, OE LOW [17] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA tPWE WE tSD DATA IO NOTE 18 tHD DATAIN tLZWE tHZWE Figure 7. Write Cycle 4: BHE/BLE Controlled, OE LOW [17] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tHZWE DATA IO NOTE 18 tSD tHD DATAIN tLZWE Document #: 001-43142 Rev. ** Page 9 of 12 [+] Feedback CY62146ESL MoBL® Truth Table CE WE OE BHE BLE H X X X X High-Z Inputs/Outputs Deselect/Power down Mode Standby (ISB) Power L X X H H High-Z Output Disabled Active (ICC) L H L L L Data Out (IO0–IO15) Read Active (ICC) L H L H L Data Out (IO0–IO7); IO8–IO15 in High-Z Read Active (ICC) L H L L H Data Out (IO8–IO15); IO0–IO7 in High-Z Read Active (ICC) L H H L L High-Z Output Disabled Active (ICC) L H H H L High-Z Output Disabled Active (ICC) L H H L H High-Z Output Disabled Active (ICC) L L X L L Data In (IO0–IO15) Write Active (ICC) L L X H L Data In (IO0–IO7); IO8–IO15 in High-Z Write Active (ICC) L L X L H Data In (IO8–IO15); IO0–IO7 in High-Z Write Active (ICC) Ordering Information Speed (ns) 45 Ordering Code CY62146ESL-45ZSXI Document #: 001-43142 Rev. ** Package Diagram Package Type 51-85087 44-pin Thin Small Outline Package Type II (Pb-free) Operating Range Industrial Page 10 of 12 [+] Feedback CY62146ESL MoBL® Package Diagrams Figure 8. 44-Pin TSOP II, 51-85087 51-85087-*A Document #: 001-43142 Rev. ** Page 11 of 12 [+] Feedback CY62146ESL MoBL® Document History Page Document Title: CY62146ESL MoBL® 4-Mbit (256K x 16) Static RAM Document Number: 001-43142 REV. ECN NO. Issue Date ** 1875228 See ECN Orig. of Change Description of Change VKN/AESA New Data Sheet © Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-43142 Rev. ** Revised January 04, 2008 Page 12 of 12 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback