Cypress CY62148CV25LL-70BAI 512k x 8 mobl static ram Datasheet

CY62148CV25/30/33
MoBL™
512K x 8 MoBL Static RAM
Features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The device also
has an automatic power-down feature that significantly reduces power consumption by 80% when addresses are not toggling. The device can be put into standby mode when deselected (CE HIGH).
• High Speed
— 55 ns and 70 ns availability
• Low voltage range:
— CY62148CV25: 2.2V–2.7V
— CY62148CV30: 2.7V–3.3V
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18).
— CY62148CV33: 3.0V–3.6V
• Pin compatible with CY62148V
• Ultra low active power
— Typical active current: 1.5 mA @ f = 1MHz
•
•
•
•
— Typical active current: 5.5 mA @ f = fmax (70 ns speed)
Low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
The CY62148CV25/30/33 are high-performance CMOS static
RAMs organized as 512K words by 8 bits. This device features
Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
The CY62148CV25/30/33 are available in a 36-ball FBGA
package.
Logic Block Diagram
I/O0
Data in Drivers
I/O1
512K x 8
ARRAY
I/O2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O3
I/O4
I/O5
COLUMN
DECODER
CE
I/O6
POWER
DOWN
I/O7
A10
A 11
A 12
A13
A14
A15
A16
A17
A18
WE
OE
Cypress Semiconductor Corporation
Document #: 38-05035 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 7, 2001
CY62148CV25/30/33
MoBL™
Pin Configurations[1,2]
FBGA (Top View)
1
2
3
4
5
6
A0
A1
NC
A3
A6
A8
A
I/O4
A2
WE
A4
A7
I/O0
B
DNU
A5
I/O1
C
VSS
VCC
D
VCC
VSS
E
I/O2
F
I/O5
I/O6
A18
A17
I/O7
OE
CE
A16
A15
I/O3
G
A9
A10
A11
A12
A13
A14
H
Maximum Ratings
DC Voltage Applied to Outputs
in High Z State[3] ...................................–0.5V to VCC + 0.3V
(Above which the useful life may be impaired. For user guidelines, not tested.)
DC Input Voltage[3] ................................–0.5V to VCC + 0.3V
Output Current into Outputs (LOW).. ...........................20 mA
Storage Temperature .... .............................–65°C to +150°C
Static Discharge Voltage..........................................>2001V
Ambient Temperature with
Power Applied. ............................................–55°C to +125°C
MIL-STD-883, Method 3015)
Latch-Up Current >...................................................>200 mA
Supply Voltage to Ground Potential.....–0.5V to Vccmax + 0.5V
Operating Range
Product
CY62148CV25
CY62148CV30
CY62148CV33
Range
Industrial
Ambient Temperature
–40°C to +85°C
VCC
2.2V to 2.7V
2.7V to 3.3V
3.0V to 3.6V
Product Portfolio
Power Dissipation (Industrial)
Operating (ICC)
VCC Range
Product
CY62148CV25
CY62148CV30
CY62148CV33
f = 1 MHz
Standby (ISB2)
f = fmax
Min.
Typ.[4]
Max.
Speed
Typ.[4]
Max.
Typ.[4]
Max.
Typ.[4]
Max.
2.2V
2.5V
2.7V
55 ns
1.5 mA
3 mA
7 mA
15 mA
5 µA
15 µA
70 ns
1.5 mA
3 mA
5.5 mA
12 mA
55 ns
1.5 mA
3 mA
7 mA
15 mA
7 µA
15 µA
70 ns
1.5 mA
3 mA
5.5 mA
12 mA
55 ns
1.5 mA
3 mA
7 mA
15 mA
8 µA
20 µA
70 ns
1.5 mA
3 mA
5.5 mA
12 mA
2.7V
3.0V
3.0V
3.3V
3.3V
3.6V
Notes:
1. NC pins are not connected to the die.
2. C3 (DNU) can be left as NC or Vss to ensure proper application.
3. VIL(min.) = –2.0V for pulse durations less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05035 Rev. *A
Page 2 of 13
CY62148CV25/30/33
MoBL™
Electrical Characteristics Over the Operating Range
CY62148CV25-55
Parameter
Description
Test Conditions
Min.
Typ.
[4]
Max.
VOH
Output HIGH Voltage
IOH = –0.1 mA
VCC = Min.
VOL
Output LOW Voltage
IOL = 0.1 mA
VCC = MinV
VIH
Input HIGH Voltage
1.8
VCC+
0.3V
VIL
Input LOW Voltage
–0.3
IIX
Input Load Current
GND < VI < VCC
IOZ
Output Leakage
Current
GND < VO < VCC, Output
Disabled
ICC
VCC Operating Supply
Current
f = fMAX = 1/tRC
ISB1
Automatic CE
Power-Down Current
— CMOS Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f = 0 (OE,WE)
ISB2
Automatic CE
Power-Down Current
— CMOS Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.6V
f = 1 MHz
2.0
Description
V
1.8
VCC +
0.3V
V
0.6
–0.3
0.6
V
–1
+1
–1
+1
µA
–1
+1
–1
+1
µA
7
15
5.5
12
mA
1.5
3
1.5
3
mA
5
15
5
15
µA
Min.
Typ.[4]
Max.
Output HIGH Voltage
IOH = –1.0 mA
VCC = Min.
VOL
Output LOW Voltage
IOL = 2.1 mA
VCC = MinV
VIH
Input HIGH Voltage
2.2
VCC+
0.5V
VIL
Input LOW Voltage
–0.3
IIX
Input Load Current
GND < VI < VCC
IOZ
Output Leakage
Current
GND < VO < VCC, Output
Disabled
ICC
VCC Operating Supply
Current
f = fMAX = 1/tRC
ISB1
Automatic CE
Power-Down Current
— CMOS Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f = 0 (OE,WE)
ISB2
Automatic CE
Power-Down Current
— CMOS Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.6V
Document #: 38-05035 Rev. *A
VCC = 3.6V
IOUT = 0 mA
CMOS Levels
Unit
0.4
VOH
f = 1 MHz
Max.
V
0.4
VCC = 3.6V
IOUT = 0 mA
CMOS Levels
Test Conditions
Min. Typ.[4]
2.0
CY62148CV30-55
Parameter
CY62148CV25-70
2.4
CY62148CV30-70
Min. Typ.[4]
Max.
2.4
Unit
V
0.4
0.4
V
2.2
VCC +
0.5V
V
0.8
–0.3
0.8
V
–1
+1
–1
+1
µA
–1
+1
–1
+1
µA
12
25
7
15
mA
1.5
3
1.5
3
mA
7
15
7
15
µA
Page 3 of 13
CY62148CV25/30/33
MoBL™
CY62148CV33-55
Parameter
Description
Test Conditions
Min.
Typ.[4]
Max.
VOH
Output HIGH Voltage
IOH = –1.0 mA
VCC = 3.0V
VOL
Output LOW Voltage
IOL = 2.1 mA
VCC = 3.0V
VIH
Input HIGH Voltage
2.2
VCC +
0.5V
VIL
Input LOW Voltage
–0.3
IIX
Input Load Current
GND < VI < VCC
IOZ
Output Leakage
Current
GND < VO < VCC, Output
Disabled
ICC
VCC Operating Supply
Current
f = fMAX = 1/tRC
ISB1
Automatic CE
Power-Down Current
— CMOS Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f = 0 (OE,WE)
ISB2
Automatic CE
Power-Down Current
— CMOS Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.6V
f = 1 MHz
2.4
CY62148CV33-70
Min.
Typ.[4]
Max.
2.4
Unit
V
0.4
0.4
V
2.2
VCC+
0.5V
V
0.8
–0.3
0.8
V
–1
+1
–1
+1
µA
–1
+1
–1
+1
µA
VCC = 3.6V
IOUT = 0 mA
CMOS Levels
7
15
5.5
12
mA
1.5
3
1.5
3
mA
8
20
8
20
µA
Capacitance[5
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ.)
Max.
Unit
6
pF
8
pF
Thermal Resistance
Description
Thermal Resistance[5]
(Junction to Ambient)
Test Conditions
Symbol
BGA
Unit
Still Air, soldered on a 3 x 4.5 inch, two-layer printed
circuit board
ΘJA
55
°C/W
ΘJC
16
°C/W
Thermal Resistance[5]
(Junction to Case)
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05035 Rev. *A
Page 4 of 13
CY62148CV25/30/33
MoBL™
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
OUTPUT
VCC Typ
R2
30 pF
GND
Fall time: 1 V/ns
Rise Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
90%
10%
90%
10%
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.5V
3.0V
3.3V
Unit
R1
16.6
1.105
1.216
K Ohms
R2
15.4
1.550
1.374
K Ohms
RTH
8.0
0.645
0.645
K Ohms
VTH
1.20
1.75
1.75
Volts
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[5]
Chip Deselect to Data
Retention Time
tR[6]
Operation Recovery
Time
Min.
Typ.[4]
1.5
VCC = 1.5V
CE > VCC − 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V
3
Max.
Unit
Vccmax
V
10
µA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min.)
VDR > 1.5V
tCDR
VCC(min.)
tR
CE
Note:
6. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs.
Document #: 38-05035 Rev. *A
Page 5 of 13
CY62148CV25/30/33
MoBL™
Switching Characteristics Over the Operating Range[7]
55 ns
Parameter
Description
Min.
70 ns
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
55
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z[8]
10
tLZCE
CE LOW to Low Z
[8]
25
CE HIGH to High Z
tPU
CE LOW to Power-Up
tPD
10
ns
35
ns
ns
25
20
CE HIGH to Power-Down
70
10
0
ns
ns
25
0
55
ns
ns
5
20
[8, 9]
tHZCE
10
5
OE HIGH to High Z
ns
70
55
[9]
tHZOE
70
55
ns
ns
70
ns
[10, 11]
WRITE CYCLE
tWC
Write Cycle Time
55
70
ns
tSCE
CE LOW to Write End
45
60
ns
tAW
Address Set-Up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
45
50
ns
tSD
Data Set-Up to Write End
30
30
ns
tHD
Data Hold from Write End
0
0
ns
[8, 9]
tHZWE
WE LOW to High Z
tLZWE
WE HIGH to Low Z[8]
20
5
25
10
ns
ns
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30 pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05035 Rev. *A
Page 6 of 13
CY62148CV25/30/33
MoBL™
Switching Waveforms
Read Cycle No. 1 [12, 13]
tRC
ADDRESS
tOHA
DATA OUT
tAA
DATA VALID
PREVIOUS DATA VALID
Read Cycle No. 2 [13, 14]
tRC
CE
tACE
OE
DATA OUT
tHZOE
tHZCE
tDOE
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPD
tPU
ICC
50%
50%
ISB
[10, 15, 16]
Write Cycle No. 1 (WE Controlled)
tWC
ADDRESS
CE
tAW
tSA
WE
tHA
tPWE
OE
tSD
DATA I/O
NOTE 17
tHD
DATAIN VALID
tHZOE
Notes:
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05035 Rev. *A
Page 7 of 13
CY62148CV25/30/33
MoBL™
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)
[10, 15, 16]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
WE
tSD
DATA I/O
tHD
DATAIN VALID
Write Cycle No. 3 (WE Controlled, OE LOW)
[11, 16]
tWC
ADDRESS
CE
tAW
WE
tHA
tSA
tSD
DATA I/O
NOTE 17
tHZWE
Document #: 38-05035 Rev. *A
tHD
DATAIN VALID
tLZWE
Page 8 of 13
CY62148CV25/30/33
MoBL™
Typical DC and AC Parameters
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.)
Operating Current vs. Supply Voltage
MoBL
12.0
10.0
8.0
(f = fmax, 55ns)
6.0
(f = fmax, 70ns)
10.0
8.0
(f = fmax, 55ns)
6.0
(f = fmax, 70ns)
10.0
2.0
4.0
2.0
(f = 1 MHz)
0.0
3.3
3.0
3.6
SUPPLY VOLTAGE (V)
(f = 1 MHz)
0.0
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
0.0
2.2
2.5 2.7
SUPPLY VOLTAGE (V)
(f = fmax, 70ns)
6.0
2.0
(f = 1 MHz)
(f = fmax, 55ns)
8.0
4.0
4.0
MoBL
12.0
ICC (mA)
MoBL
ICC (mA)
ICC (mA)
12.0
14.0
14.0
14.0
12.0
12.0
12.0
10.0
10.0
10.0
MoBL
8.0
ISB (µA)
8.0
MoBL
ISB (µA)
ISB (µA)
Standby Current vs. Supply Voltage
MoBL
8.0
6.0
6.0
6.0
4.0
4.0
4.0
2.0
2.0
2.0
0
0
2.2 2.5 2.7
SUPPLY VOLTAGE (V)
0
3.0
2.7
3.3
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
MoBL
MoBL
60
60
50
50
50
40
40
40
30
30
30
20
10
TAA (ns)
60
TAA (ns)
TAA (ns)
MoBL
20
10
0
10
0
2.2
2.5
2.7
0
2.7
SUPPLY VOLTAGE (V)
20
3.0
3.3
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Truth Table
CE
WE
OE
Inputs/Outputs
H
X
X
High Z
Deselect/Power-Down
Standby (ISB)
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High Z
Output Disabled
Active (ICC)
Document #: 38-05035 Rev. *A
Mode
Power
Page 9 of 13
CY62148CV25/30/33
MoBL™
Ordering Information
Speed
(ns)
Ordering Code
70
CY62148CV25LL-70BAI
BA36B
36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
CY62148CV25LL-70BVI
BV36A
36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62148CV30LL-70BAI
BA36B
36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
CY62148CV30LL-70BVI
BV36A
36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62148CV33LL-70BAI
BA36B
36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
CY62148CV33LL-70BVI
BV36A
36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62148CV25LL-55BAI
BA36B
36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
CY62148CV25LL-55BVI
BV36A
36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62148CV30LL-55BAI
BA36B
36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
CY62148CV30LL-55BVI
BV36A
36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62148CV33LL-55BAI
BA36B
36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
CY62148CV33LL-55BVI
BV36A
36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
55
Document #: 38-05035 Rev. *A
Package
Name
Package Type
Operating
Range
Industrial
Page 10 of 13
CY62148CV25/30/33
MoBL™
Package Diagrams
36-Ball (7.00 mm x 8.5 mm x 1.2 mm) Thin BGA BA36B
51-85105-*C
Document #: 38-05035 Rev. *A
Page 11 of 13
CY62148CV25/30/33
MoBL™
Package Diagrams (continued)
36-Lead VFBGA (6 x 8 x 1 mm) BV36A
51-85149-**
MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05035 Rev. *A
Page 12 of 13
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62148CV25/30/33
MoBL™
Document Title: CY62148CV25/30/33 MoBL™ 512K x 8 MoBL Static RAM
Document Number: 38-05035
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
109951
12/02/01
SZV
Change from Spec number: 38-01126 to 38-05035
*A
110643
05/01/02
MGN
Advance to Final, Improved Typical and Max Icc values, added BV package
Document #: 38-05035 Rev. *A
Page 13 of 13
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