Cypress CY7C1018CV33 128k x 8 static ram Datasheet

CY7C1018CV33
128K x 8 Static RAM
Features
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
• Pin- and function-compatible with CY7C1018BV33
• High speed
— tAA = 8, 10, 12, 15 ns
• CMOS for optimum speed/power
• Center power/ground pinout
• Data retention at 2.0V
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Available in 300-mil-wide 32-pin SOJ
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
Functional Description[1]
The CY7C1018CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
The CY7C1018CV33 is available in a standard 300-mil-wide
SOJ.
Logic Block Diagram
Pin Configurations
SOJ
Top View
A0
A1
A2
A3
I/O0
INPUT BUFFER
CE
I/O0
I/O1
VCC
V SS
I/O1
I/O2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
512 x 256 x 8
ARRAY
I/O3
I/O2
I/O3
WE
A4
A5
A6
A7
I/O4
I/O5
I/O6
POWER
DOWN
COLUMN
DECODER
CE
I/O7
OE
A16
32
31
30
29
28
27
26
A15
A14
A13
OE
I/O7
I/O6
VSS
VCC
I/O5
I/O4
A12
A11
A10
A9
A8
25
24
23
22
21
20
19
18
17
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Selection Guide
7C1018CV33-8
7C1018CV33-10
7C1018CV33-12
7C1018CV33-15
Unit
Maximum Access Time
8
10
12
15
ns
Maximum Operating Current
95
90
85
80
mA
Maximum Standby Current
5
5
5
5
mA
Note:
1. For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05131 Rev. *C
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 13, 2002
CY7C1018CV33
DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current..................................................... > 200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage on VCC to Relative GND[2] ... –0.5V to + 4.6V
Range
DC Voltage Applied to Outputs[7]
in High-Z State .......................................–0.5V to VCC + 0.5V
Ambient Temperature
VCC
0°C to +70°C
3.3V ± 10%
Commercial
Electrical Characteristics Over the Operating Range
7C1018CV33 7C1018CV33 7C1018CV33 7C1018CV33
-8
-10
-12
-15
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
VOH
Output HIGH Voltage
VCC = Min.,
IOH = – 4.0 mA
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
VIH
Input HIGH Voltage
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
VIL
Input LOW Voltage[2]
–0.3
0.8
–0.3
0.8
–0.3
0.8
2.4
2.4
0.4
2.4
0.4
Min.
Max.
2.4
0.4
Unit
V
0.4
V
2.0
VCC
+ 0.3
V
–0.3
0.8
V
IIX
Input Load Current
GND < VI < VCC
–1
+1
–1
+1
–1
+1
–1
+1
µA
IOZ
Output Leakage
Current
GND < VI < VCC,
Output Disabled
–1
+1
–1
+1
–1
+1
–1
+1
µA
IOS[3]
Output Short
Circuit Current
VCC = Max.,
VOUT = GND
ICC
VCC Operating
Supply Current
ISB1
ISB2
–300
-300
–300
-300
mA
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
95
90
85
80
mA
Automatic CE
Power-down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
15
15
15
15
mA
Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
5
5
5
5
mA
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
8
pF
8
pF
Notes:
2. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05131 Rev. *C
Page 2 of 7
CY7C1018CV33
AC Test Loads and Waveforms[5]
10-, 12-, 15-ns devices:
8-ns devices:
Z = 50Ω
R 317Ω
3.3V
OUTPUT
50 Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
OUTPUT
30 pF*
R2
351Ω
30 pF
1.5V
(b)
(a)
High-Z characteristics: R 317Ω
ALL INPUT PULSES
3.0V
90%
3.3V
90%
10%
GND
OUTPUT
10%
Rise Time: 1 V/ns
(c)
Switching Characteristics
Fall Time: 1 V/ns
(d)
Over the Operating Range[6]
7C1018CV33-8
Parameter
R2
351Ω
5 pF
Description
Min.
Max.
7C1018CV33-10 7C1018CV33-12 7C1018CV33-15
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
8
tOHA
Data Hold from Address
Change
tACE
CE LOW to Data Valid
8
10
12
15
ns
tDOE
OE LOW to Data Valid
5
5
6
7
ns
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to High-Z[7, 8]
[8]
tLZCE
CE LOW to Low-Z
tHZCE
CE HIGH to High-Z[7, 8]
tPU[9]
tPD[9]
CE LOW to Power-up
Write
10
8
3
3
0
3
3
0
3
0
8
3
0
10
ns
7
6
ns
ns
7
0
12
ns
ns
0
6
5
ns
15
3
0
5
4
15
12
3
0
4
CE HIGH to Power-down
12
10
ns
ns
15
ns
Cycle[10, 11]
tWC
Write Cycle Time
8
10
12
15
ns
tSCE
CE LOW to Write End
7
8
9
10
ns
tAW
Address Set-up to Write End
7
8
9
10
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
6
7
8
10
ns
tSD
Data Set-up to Write End
5
5
6
8
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low-Z[8]
3
3
3
3
ns
tHZWE
WE LOW to
High-Z[7, 8]
4
5
6
7
ns
Notes:
5. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thèvenin
load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (d) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. This parameter is guaranteed by design and is not tested.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these
signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05131 Rev. *C
Page 3 of 7
CY7C1018CV33
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
DATA OUT
tHZCE
tLZOE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
ICC
50%
50%
ISB
Write Cycle No. 1 (CE Controlled)[15, 16]
tWC
ADDRESS
tSCE
CE
tSA
tSCE
tHA
tAW
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Notes:
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for Read cycle.
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05131 Rev. *C
Page 4 of 7
CY7C1018CV33
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[15, 16]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 17
tHZOE
Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
NOTE 17
DATA I/O
tHD
DATA VALID
tLZWE
tHZWE
Truth Table
CE
OE
WE
I/O0–I/O7
Mode
Power
H
X
X
High-Z
Power-down
Standby (ISB)
X
X
X
High-Z
Power-down
Standby (ISB)
L
L
H
Data Out
Read
Active (ICC)
L
X
L
Data In
Write
Active (ICC)
L
H
H
High-Z
Selected, Outputs Disabled
Active (ICC)
Note:
17. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05131 Rev. *C
Page 5 of 7
CY7C1018CV33
Ordering Information
Speed
(ns)
Ordering Code
8
CY7C1018CV33-8VC
Package
Name
V32
Package Type
32-lead 300-mil Molded SOJ
10
CY7C1018CV33-10VC
V32
32-lead 300-mil Molded SOJ
12
CY7C1018CV33-12VC
V32
32-lead 300-mil Molded SOJ
15
CY7C1018CV33-15VC
V32
32-lead 300-mil Molded SOJ
Operating
Range
Commercial
Package Diagram
32-lead (300-mil) Molded SOJ V32
51-85041-*A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05131 Rev. *C
Page 6 of 7
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1018CV33
Document History Page
Document Title: CY7C1018CV33 128K x 8 Static RAM
Document Number: 38-05131
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
109426
12/14/01
HGK
New Data Sheet
*A
113432
04/10/02
NSL
AC Test Loads split based on speed
*B
115046
05/30/02
HGK
ICC and ISB1 modified
*C
116476
09/16/02
CEA
Add applications foot note on data sheet, pg 1.
Document #: 38-05131 Rev. *C
Page 7 of 7