Cypress CY7C1041CV33-12VC 256k x 16 static ram Datasheet

CY7C1041CV33
256K x 16 Static RAM
Features
HIGH Enable (BHE) is LOW, then data from I/O pins
(I/O8–I/O15) is written into the location specified on the
address pins (A0–A17).
• Pin equivalent to CY7C1041BV33
• High speed
— tAA = 10 ns
• Low active power
— 324 mW (max.)
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 – I/O7. If Byte HIGH Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O0–I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
Functional Description[1]
The CY7C1041CV33 is a high-performance CMOS Static
RAM organized as 262,144 words by 16 bits.
The CY7C1041CV33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout, as well
as a 48-ball fine-pitch ball grid array (FBGA) package.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable
(BLE) is LOW, then data from I/O pins (I/O0–I/O7), is written
into the location specified on the address pins (A0–A17). If Byte
Logic Block Diagram
Pin Configuration
SOJ
TSOP II
Top View
256K × 16
ARRAY
1024 x 4096
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
I/O0–I/O7
I/O8–I/O15
A9
A10
A 11
A 12
A 13
A14
A15
A16
A17
COLUMN
DECODER
BHE
WE
CE
OE
BLE
1
44
2
3
4
43
42
41
40
39
38
5
6
7
8
9
10
37
36
35
34
33
11
12
32
31
30
29
28
27
13
14
15
16
17
18
19
20
21
22
26
25
24
23
A17
A16
A15
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
-8
-10
-12
-15
-20
Unit
8
10
12
15
20
ns
Commercial
100
90
85
80
75
mA
Industrial
110
100
95
90
85
mA
Commercial/
Industrial
10
10
10
10
10
mA
Shaded areas contain advance information.
Note:
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05134 Rev. *D
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised October 18, 2002
CY7C1041CV33
Pin Configurations
48-ball Mini FBGA
Document #: 38-05134 Rev. *D
(Top View)
4
3
1
2
BLE
OE
A0
I/O0
BHE
I/O1
5
6
A1
A2
NC
A
A3
A4
CE
I/O8
B
I/O 2
A5
A6
I/O10 I/O9
C
VSS
I/O3
A17
A7
I/O11 VCC
D
VCC
I/O4
NC
A16
I/O12
VSS
E
I/O6
I/O5
A14
A15
I/O13 I/O14
F
I/O7
NC
A12
A13
WE
I/O15
G
NC
A8
A9
A10
A11
NC
H
Page 2 of 11
CY7C1041CV33
Maximum Ratings
DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Current into Outputs (LOW) ........................................ 20 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Range
Ambient
Temperature
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V
VCC
Commercial
0°C to +70°C
3.3V ± 0.3V
DC Voltage Applied to Outputs
in High-Z State[2] ....................................–0.5V to VCC + 0.5V
Industrial
–40°C to +85°C
DC Electrical Characteristics Over the Operating Range
-8
Parameter
Description
-10
-12
-15
-20
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Test Conditions
VOH
Output HIGH Voltage VCC = Min.,
IOH = –4.0 mA
2.4
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL[2]
Input LOW Voltage
IIX
Input Load Current
GND < VI < VCC
–1
+1
–1
+1
–1
+1
–1
+1
–1
+1
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC,
Output Disabled
–1
+1
–1
+1
–1
+1
–1
+1
–1
+1
µA
ICC
VCC Operating
Supply Current
VCC = Max., f = fMAX = Comm’l
1/tRC
Indus.
100
90
85
80
75
mA
110
100
95
90
85
mA
ISB1
Automatic CE
Power-down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
40
40
40
40
40
mA
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
10
10
10
10
10
mA
VCC = Min.,
IOL = 8.0 mA
2.4
0.4
2.4
0.4
2.4
0.4
2.4
0.4
V
0.4
V
2.0 VCC 2.0 VCC 2.0 VCC 2.0 VCC 2.0 VCC V
+ 0.3
+ 0.3
+ 0.3
+ 0.3
+ 0.3
–0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8
Comm’l
Indus.
V
Shaded areas contain advance information.
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max.
Unit
8
pF
8
pF
Notes:
2. Minimum voltage is–2.0V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05134 Rev. *D
Page 3 of 11
CY7C1041CV33
AC Switching Characteristics[4] Over the Operating Range
-8
Parameter
Description
-10
Min. Max. Min.
-12
Max.
Min.
-15
Max.
Min.
-20
Max.
Min.
Max.
Unit
Read Cycle
tpower[5]
VCC(typical) to the first access
1
1
1
1
1
µs
tRC
Read Cycle Time
8
10
12
15
20
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
8
10
12
15
20
ns
tDOE
OE LOW to Data Valid
4
5
6
7
8
ns
8
ns
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to High-Z[6, 7]
tLZCE
CE LOW to Low-Z[7]
tHZCE
CE HIGH to
8
3
10
3
0
0
4
3
High-Z[6, 7]
4
5
6
ns
3
7
ns
8
tPU
CE LOW to Power-Up
CE HIGH to Power-Down
8
10
12
15
20
ns
tDBE
Byte Enable to Data Valid
4
5
6
7
8
ns
tLZBE
Byte Enable to Low-Z
tHZBE
Byte Disable to High-Z
0
6
0
6
0
ns
tPD
0
0
ns
ns
0
7
3
0
20
3
0
6
3
0
15
3
0
5
3
0
12
3
0
6
ns
0
7
ns
8
ns
Write Cycle[8, 9]
tWC
Write Cycle Time
8
10
12
15
20
ns
tSCE
CE LOW to Write End
6
7
8
10
10
ns
tAW
Address Set-Up to Write End
6
7
8
10
10
ns
tHA
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tPWE
WE Pulse Width
6
7
8
10
10
ns
tSD
Data Set-Up to Write End
4
5
6
7
8
ns
tHD
Data Hold from Write End
0
0
0
0
0
ns
3
3
3
3
3
ns
WE HIGH to Low-Z
[7]
tHZWE
WE LOW to High-Z
[6, 7]
tBW
Byte Enable to End of Write
tLZWE
4
6
5
7
6
8
7
10
8
10
ns
ns
Shaded areas contain advance information.
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of
either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the Write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05134 Rev. *D
Page 4 of 11
CY7C1041CV33
AC Test Loads and Waveforms[10]
12-, 15-, 20-ns Devices
8-, 10-ns Devices
Z = 50Ω
50 Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
R 317Ω
3.3V
OUTPUT
OUTPUT
30 pF*
R2
351Ω
30 pF
1.5V
(b)
(a)
High-Z Characteristics
R 317Ω
3.0V
90%
GND
3.3V
ALL INPUT PULSES
90%
10%
OUTPUT
10%
(c)
Rise Time: 1 V/ns
R2
351Ω
5 pF
Fall Time: 1 V/ns
(d)
Switching Waveforms
Read Cycle No. 1[11, 12]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled) [12, 13]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
IICC
CC
50%
IISB
SB
Notes:
10. AC characteristics (except High-Z) for all 8-ns and 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the
Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
12. WE is HIGH for Read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05134 Rev. *D
Page 5 of 11
CY7C1041CV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[14, 15]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATAI/O
Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATAI/O
Notes:
14. Data I/O is high-impedance if OE or BHE and/or BLE = VIH.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05134 Rev. *D
Page 6 of 11
CY7C1041CV33
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Truth Table
CE
OE
WE
BLE
BHE
H
X
X
X
X
High-Z
High-Z
Power-down
Standby (ISB)
L
L
H
L
L
Data Out
Data Out
Read All Bits
Active (ICC)
L
L
H
L
H
Data Out
High-Z
Read Lower Bits Only
Active (ICC)
L
L
H
H
L
High-Z
Data Out
Read Upper Bits Only
Active (ICC)
L
X
L
L
L
Data In
Data In
Write All Bits
Active (ICC)
L
X
L
L
H
Data In
High-Z
Write Lower Bits Only
Active (ICC)
L
X
L
H
L
High-Z
Data In
Write Upper Bits Only
Active (ICC)
L
H
H
X
X
High-Z
High-Z
Selected, Outputs Disabled
Active (ICC)
Document #: 38-05134 Rev. *D
I/O0–I/O7
I/O8–I/O15
Mode
Power
Page 7 of 11
CY7C1041CV33
Ordering Information
CY7C1041CV33
Speed
(ns)
10
Ordering Code
CY7C1041CV33-10BAC
CY7C1041CV33-10VC
12
48-ball Fine Pitch BGA
44-lead (400-mil) Molded SOJ
CY7C1041CV33-10ZC
Z44
44-pin TSOP II Z44
CY7C1041CV33-10BAI
BA48B
48-ball Fine Pitch BGA
CY7C1041CV33-10VI
V34
44-lead (400-mil) Molded SOJ
CY7C1041CV33-10ZI
Z44
44-pin TSOP II Z44
CY7C1041CV33-12BAC
BA48B
48-ball Fine Pitch BGA
V34
44-lead (400-mil) Molded SOJ
CY7C1041CV33-12ZC
Z44
44-pin TSOP II Z44
CY7C1041CV33-12BAI
BA48B
48-ball Fine Pitch BGA
CY7C1041CV33-12VI
V34
44-lead (400-mil) Molded SOJ
CY7C1041CV33-12ZI
Z44
44-pin TSOP II Z44
CY7C1041CV33-15BAC
CY7C1041CV33-15VC
20
BA48B
Package Type
V34
CY7C1041CV33-12VC
15
Package
Name
BA48B
48-ball Fine Pitch BGA
V34
44-lead (400-mil) Molded SOJ
CY7C1041CV33-15ZC
Z44
44-pin TSOP II Z44
CY7C1041CV33-15BAI
BA48B
48-ball Fine Pitch BGA
CY7C1041CV33-15VI
V34
44-lead (400-mil) Molded SOJ
CY7C1041CV33-15ZI
Z44
44-pin TSOP II Z44
CY7C1041CV33-20BAC
CY7C1041CV33-20VC
BA48B
48-ball Fine Pitch BGA
V34
44-lead (400-mil) Molded SOJ
CY7C1041CV33-20ZC
Z44
44-pin TSOP II Z44
CY7C1041CV33-20BAI
BA48B
48-ball Fine Pitch BGA
CY7C1041CV33-20VI
V34
44-lead (400-mil) Molded SOJ
CY7C1041CV33-20ZI
Z44
44-pin TSOP II Z44
Document #: 38-05134 Rev. *D
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 8 of 11
CY7C1041CV33
Package Diagrams
48-ball (7.00 mm x 8.5 mm x 1.2 mm) FBGA BA48B
51-85106-*D
44-lead (400-mil) Molded SOJ V34
51-85082-*B
Document #: 38-05134 Rev. *D
Page 9 of 11
CY7C1041CV33
Package Diagrams (continued)
44-pin TSOP II Z44
51-85087-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05134 Rev. *D
Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1041CV33
Document History Page
Document Title: CY7C1041CV33 256K x 16 Static RAM
Document Number: 38-05134
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
109513
12/13/01
HGK
New Data Sheet
*A
112440
12/20/01
BSS
Updated 51-85106 from revision *A to *C
*B
112859
03/25/02
DFP
Added CY7C1042CV33 in BGA package
Removed 1042 BGA option pin ACC Final Data Sheet
*C
116477
09/16/02
CEA
Add applications foot note to data sheet
*D
119797
10/21/02
DFP
Added 20-ns speed bin
Document #: 38-05134 Rev. *D
Page 11 of 11
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