Cypress CY7C1354BV25 256k x 36/512k x 18 pipelined sram with noblâ ¢ architecture Datasheet

CY7C1354BV25
CY7C1356BV25
256K x 36/512K x 18 Pipelined SRAM with
NoBL™ Architecture
Features
Functional Description
• Pin-compatible and functionally equivalent to ZBT™
• Supports 225-MHz bus operations with zero wait states
— Available speed grades are 225, 200 and 166 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 2.5V power supply
• Fast clock-to-output times
The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x
36 and 512K x 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL) logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1354BV25 and
CY7C1356BV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1354BV25
and CY7C1356BV25 are pin compatible and functionally
equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
— 2.8 ns (for 225-MHz device)
— 3.2ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP, 119 BGA, and 165 fBGA packages
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1354BV25 and BWa–BWb for
CY7C1356BV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram-CY7C1354BV25 (256K x 36)
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWa
BWb
BWc
BWd
MEMORY
ARRAY
WRITE
DRIVERS
A
M
P
S
WE
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
ZZ
E
O
U
T
P
U
T
D
A
T
A
S
T
E
E
R
I
N
G
INPUT
REGISTER 0
B
U
F
F
E
R
S
DQs
DQPa
DQPb
DQPc
DQPd
E
E
READ LOGIC
SLEEP
CONTROL
Cypress Semiconductor Corporation
Document #: 38-05292 Rev. *E
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised August 10, 2004
CY7C1354BV25
CY7C1356BV25
Logic Block Diagram-CY7C1356BV25 (512K x 18)
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
BWb
S
E
N
S
E
A
M
P
S
WE
O
U
T
P
U
T
O
U
T
P
U
T
D
A
T
A
R
E
G
I
S
T
E
R
S
B
U
F
F
E
R
S
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
ZZ
DQs
DQPa
DQPb
E
INPUT
REGISTER 0 E
READ LOGIC
Sleep
Control
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
CY7C1354BV25-225
CY7C1356BV25-225
CY7C1354BV25-200
CY7C1356BV25-200
CY7C1354BV25-166
CY7C1356BV25-166
Unit
2.8
250
35
3.2
220
35
3.5
180
35
ns
mA
mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05292 Rev. *E
Page 2 of 27
CY7C1354BV25
CY7C1356BV25
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC
DQPb
NC
DQb
NC
DQb
VDDQ VDDQ
VSS
VSS
NC
DQb
DQb
NC
DQb
DQb
DQb
DQb
VSS
VSS
VDDQ
V
DDQ
CY7C1356BV25
(512K × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document #: 38-05292 Rev. *E
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
E(36)
E(72)
VSS
VDD
E(288)
E(144)
A
A
A
A
A
A
A
E(36)
E(72)
VSS
VDD
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQb
DQb
DQb
DQb
NC
VSS
VDD
NC
NC
VDD
VSS
ZZ
DQb
DQa
DQa
DQb
VDDQ VDDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa DQPb
NC
DQa
VSS
VSS
VDDQ VDDQ
NC
DQa
DQa
NC
DQPa
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
CY7C1354BV25
(256K × 36)
E(288)
E(144)
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DQPc
DQc
DQc
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
E(18)
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
E(18)
A
100-pin TQFP Packages
Page 3 of 27
CY7C1354BV25
CY7C1356BV25
Pin Configurations (continued)
119-ball BGA Pinout
CY7C1354BV25 (256K × 36) – 14 × 22 BGA
1
2
3
4
5
6
7
A
VDDQ
A
A
E(18)
A
A
VDDQ
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
NC
DQc
CE2
A
DQPc
A
A
VSS
ADV/LD
VDD
NC
A
A
VSS
CE3
A
DQPb
NC
NC
DQb
DQc
DQc
VSS
CE1
VSS
DQb
DQb
OE
A
VSS
DQb
VDDQ
BWb
DQb
DQb
WE
VDD
VSS
NC
DQb
VDD
DQb
VDDQ
CLK
NC
VSS
BWa
DQa
DQa
DQa
DQa
VDDQ
R
T
U
VDDQ
DQc
VSS
DQc
DQc
DQc
VDDQ
DQc
VDD
BWc
VSS
NC
DQd
DQd
DQd
DQd
BWd
VDDQ
DQd
VSS
DQa
DQd
VSS
CEN
A1
VSS
DQd
VSS
DQa
DQa
DQd
DQPd
VSS
A0
VSS
DQPa
DQa
NC
A
MODE
VDD
NC
E(72)
A
A
NC
A
A
NC
E(36)
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
VSS
CY7C1356BV25 (512K x 18)–14 x 22 BGA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Document #: 38-05292 Rev. *E
1
2
3
4
5
6
7
VDDQ
A
A
E(18)
A
A
VDDQ
NC
CE2
A
A
NC
A
VSS
ADV/LD
VDD
NC
A
NC
DQb
A
VSS
CE3
A
DQPa
NC
NC
CE1
VSS
NC
DQa
OE
A
VSS
DQa
VDDQ
VSS
VSS
NC
NC
DQa
VDD
DQa
NC
VDDQ
DQa
NC
DQb
VSS
VDDQ
NC
VSS
NC
DQb
VDDQ
DQb
NC
VDD
BWb
VSS
NC
WE
VDD
NC
NC
DQb
VSS
CLK
VSS
NC
DQb
NC
VSS
NC
DQa
NC
VDDQ
DQb
VSS
NC
VDDQ
DQb
NC
VSS
CEN
A1
BWa
VSS
VSS
DQa
NC
NC
DQPb
VSS
A0
VSS
NC
DQa
NC
NC
A
MODE
VDD
NC
A
E(72)
A
A
E(36)
A
A
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Page 4 of 27
CY7C1354BV25
CY7C1356BV25
Pin Configurations (continued)
165-Ball fBGA Pinout
1
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
E(288)
A
R
CY7C1354BV25 (256K × 36) – 13 × 15 fBGA
3
4
5
6
7
8
9
10
11
ADV/LD
A
A
NC
CLK
CEN
WE
OE
E(18)
A
E(144)
VSS
VSS
VSS
VDD
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQb
DQPb
DQb
CE1
BWc
BWb
CE3
BWd
VSS
VDD
BWa
VSS
NC
A
CE2
DQPc
DQc
NC
DQc
VDDQ
VDDQ
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
NC
DQd
DQc
NC
DQd
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQb
NC
DQa
DQb
ZZ
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQPd
DQd
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
DQa
DQPa
NC
E(72)
A
A
TDI
A1
TDO
A
A
A
NC
MODE
E(36)
A
A
TMS
A0
TCK
A
A
A
A
8
9
10
11
A
A
CY7C1356BV25 (512K × 18) – 13 × 15 fBGA
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
E(288)
A
CE1
BWb
NC
CE3
CEN
ADV/LD
A
NC
BWa
CLK
E(144)
VSS
VDD
OE
VSS
A
VSS
VSS
WE
VSS
VSS
E(18)
VSS
VSS
VDD
VDDQ
VDDQ
NC
NC
DQPa
DQa
R
NC
A
CE2
NC
NC
NC
DQb
VDDQ
VDDQ
7
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
NC
DQb
DQb
NC
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQa
DQa
ZZ
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
DQPb
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
NC
NC
NC
E(72)
A
A
TDI
A1
TDO
A
A
A
NC
MODE
E(36)
A
A
TMS
A0
TCK
A
A
A
A
Document #: 38-05292 Rev. *E
Page 5 of 27
CY7C1354BV25
CY7C1356BV25
Pin Definitions
Pin Name
I/O Type
Pin Description
A0, A1, A
InputSynchronous
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK.
BWa, BWb, BWc, BWd
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls
DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd.
WE
InputSynchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
ADV/LD
InputSynchronous
Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new address.
CLK
InputClock
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device.
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
OE
InputAsynchronous
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state and when the device has been
deselected.
CEN
InputSynchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized
by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting
CEN does not deselect the device, CEN can be used to extend the previous cycle when
required.
DQa, DQb, DQc, DQd
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A[17:0] during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE and the internal control logic. When OE is
asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in
a three-state condition. The outputs are automatically three-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE.
DQPa, DQPb, DQPc
DQPd
I/OSynchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to
DQ[31:0]. During write sequences, DQPa is controlled by BWa, DQPb is controlled by
BWb, DQPc is controlled by BWc, and DQPd is controlled by BWd.
MODE
TDO
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. MODE should not change states
during operation. When left floating MODE will default HIGH, to an interleaved burst
order.
JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Synchronous
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge
Synchronous of TCK.
TCK
VDD
VDDQ
JTAG-Clock
Power Supply
Clock input to the JTAG circuitry.
Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Document #: 38-05292 Rev. *E
Page 6 of 27
CY7C1354BV25
CY7C1356BV25
Pin Definitions (continued)
Pin Name
I/O Type
VSS
NC
E(18,36,72, 144, 288)
Ground
–
–
ZZ
InputAsynchronous
Pin Description
Ground for the device. Should be connected to ground of the system.
No connects. This pin is not connected to the die.
These pins are not connected. They will be used for expansion to the 18M, 36M,
72M, 144M and 288M densities.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved. During normal operation, this pin can be
connected to Vss or left floating.
Functional Overview
The
CY7C1354BV25
and
CY7C1356BV25
are
synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(tCO) is 3.2 ns (200-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BW[d:a] can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 3.2 ns
(200-MHz device) provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will three-state following
the next clock rise.
Document #: 38-05292 Rev. *E
Burst Read Accesses
The CY7C1354BV25 and CY7C1356BV25 have an on-chip
burst counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to A0–A16 is loaded
into the Address Register. The write signals are latched into
the Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354BV25 and DQa,b/DQPa,b
for CY7C1356BV25). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the
Address Register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354BV25 & DQa,b/DQPa,b for
CY7C1356BV25) (or a subset for byte write operations, see
Write Cycle Description table for details) inputs is latched into
the device and the write is complete.
The data written during the Write operation is controlled by BW
(BWa,b,c,d for CY7C1354BV25 and BWa,b for CY7C1356BV25)
signals. The CY7C1354BV25/ CY7C1356BV25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the Write Enable input (WE) with the selected
Byte Write Select (BW) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly
simplify Read/Modify/Write sequences, which can be reduced
to simple byte write operations.
Page 7 of 27
CY7C1354BV25
CY7C1356BV25
Because the CY7C1354BV25 and CY7C1356BV25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The Output Enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354BV25 and DQa,b/DQPa,b
for CY7C1356BV25) inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ and DQP (DQa,b,c,d/
DQPa,b,c,d for CY7C1354BV25 and DQa,b/DQPa,b for
CY7C1356BV25) are automatically three-stated during the
data portion of a write cycle, regardless of the state of OE.
the subsequent clock rise, the chip enables (CE1, CE2, and
CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BWa,b,c,d for CY7C1354BV25 and
BWa,b for CY7C1356BV25) inputs must be driven in each
cycle of the burst write in order to write the correct bytes of
data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Burst Write Accesses
The CY7C1354BV25/CY7C1356BV25 has an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four WRITE operations without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load the initial address, as described in the Single
Write Access section above. When ADV/LD is driven HIGH on
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD − 0.2V
35
mA
tZZS
Device operation to ZZ
ZZ > VDD − 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ active to sleep current
This parameter is sampled
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
2tCYC
ns
2tCYC
0
ns
ns
Truth Table[1, 2, 3, 4, 5, 6, 7]
Operation
Address
Used
CE ZZ
ADV/LD
WE
BWx
OE
CEN CLK
DQ
Deselect Cycle
None
H
L
L
X
X
X
L
L-H
Three-State
Continue Deselect Cycle
None
X
L
H
X
X
X
L
L-H
Three-State
Read Cycle (Begin Burst)
External
L
L
L
H
X
L
L
L-H
Data Out (Q)
Read Cycle (Continue Burst)
Next
X
L
H
X
X
L
L
L-H
Data Out (Q)
NOP/Dummy Read (Begin Burst)
External
L
L
L
H
X
H
L
L-H
Three-State
Dummy Read (Continue Burst)
Next
X
L
H
X
X
H
L
L-H
Three-State
Write Cycle (Begin Burst)
External
L
L
L
L
L
X
L
L-H
Data In (D)
Write Cycle (Continue Burst)
Next
X
L
H
X
L
X
L
L-H
Data In (D)
NOP/WRITE ABORT (Begin Burst) None
L
L
L
L
H
X
L
L-H
Three-State
WRITE ABORT (Continue Burst)
Next
X
L
H
X
H
X
L
L-H
Three-State
IGNORE CLOCK EDGE (Stall)
Current
X
L
X
X
X
X
H
L-H
-
SLEEP MODE
None
X
H
X
X
X
X
X
X
Three-State
Notes:
1. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW[a:d]. See Write Cycle Description table for details.
3. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = 1 inserts wait states.
6. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[a:d] = Three-state when
OE is inactive or when the device is deselected, and DQs = data when OE is active
Document #: 38-05292 Rev. *E
Page 8 of 27
CY7C1354BV25
CY7C1356BV25
Linear Burst Address Table
(MODE = GND)
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
Second
Address
Third
Address
Fourth
Address
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
01
10
11
00
01
10
11
00
01
00
11
10
01
10
11
00
11
00
01
00
01
10
BWb
BWa
10
11
00
01
10
11
10
01
00
11
Partial Write Cycle Description[1, 2, 3, 8]
Function (CY7C1354BV25)
WE
BWd
BWc
Read
H
X
X
X
X
Write –No bytes written
L
H
H
H
H
Write Byte a– (DQa and DQPa)
L
H
H
H
L
Write Byte b – (DQb and DQPb)
L
H
H
L
H
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)
L
H
L
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
L
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)
L
L
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
L
H
L
H
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
WE
BWb
BWa
Read
H
x
x
Write – No Bytes Written
L
H
H
Write Byte a − (DQa and DQPa)
L
H
L
Write Byte b – (DQb and DQPb)
L
L
H
Write Both Bytes
L
L
L
Function (CY7C1356BV25)
Note:
8. Table only lists a partial listing of the byte write combinations. Any combination of BW[a:d] is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05292 Rev. *E
Page 9 of 27
CY7C1354BV25
CY7C1356BV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1354BV25/CY7C1356BV25 incorporates a serial
boundary scan Test Access Port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
port operates in accordance with IEEE Standard 1149.1-1900,
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 2.5V I/O logic levels.
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Disabling the JTAG Feature
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port–Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
Document #: 38-05292 Rev. *E
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The ×36 configuration has a 69-bit-long
register, and the ×18 configuration has a 69-bit-long register.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller
cannot be used to load address, data, or control signals into
the SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
Page 10 of 27
CY7C1354BV25
CY7C1356BV25
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant to the 1149.1 standard.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1-compliant.
When the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
Document #: 38-05292 Rev. *E
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
Bypass
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 11 of 27
CY7C1354BV25
CY7C1356BV25
TAP Controller State Diagram[9]
1
TEST-LOGIC
RESET
0
TEST-LOGIC/
IDLE
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
SHIFT-IR
0
1
1
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
1
EXIT1-DR
0
1
0
UPDATE-IR
1
0
Note:
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05292 Rev. *E
Page 12 of 27
CY7C1354BV25
CY7C1356BV25
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
2
1
0
Selection
Circuitry
TDO
Instruction Register
TDI
31 30
29
.
.
2
1
0
1
0
Identification Register
68 .
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[10, 11]
Parameter
VOH1
VOH2
VOL1
VOL2
VIH
VIL
IX
IX
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Input Load Current TMS and TDI
Test Conditions
IOH = –2.0 mA
IOH = –100 µA
IOL = 2.0 mA
IOL = 100 µA
1.7
–0.3
–30
–30
GND ≤ VI ≤ VDDQ
GND ≤ VI ≤ VDDQ
TAP AC Switching Characteristics Over the Operating Range
Parameter
Min.
1.7
2.0
Max.
Unit
V
V
0.7
V
0.2
V
VDD + 0.3
V
0.7
V
30
µA
30
µA
[12, 13]
Description
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
tTL
TCK Clock LOW
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
tTDIS
TDI Set-up to TCK Clock Rise
tCS
Capture Set-up to TCK Rise
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
Min.
100
Max.
40
40
Unit
ns
MHz
ns
ns
10
10
10
ns
ns
ns
10
ns
10
Notes:
10. All voltage referenced to ground.
11. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) > −0.5V for t < tTCYC/2.
12. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
13. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document #: 38-05292 Rev. *E
Page 13 of 27
CY7C1354BV25
CY7C1356BV25
TAP AC Switching Characteristics Over the Operating Range (continued)[12, 13]
Parameter
tTDIH
TDI Hold after Clock Rise
tCH
Capture Hold after clock rise
Output Times
Description
Min.
10
10
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
tTDOV
tTDOX
Max.
Unit
ns
ns
20
ns
ns
0
TAP Timing and Test Conditions
1.25V for 2.5V VDDQ
ALL INPUT PULSES
50Ω
2.5V
1.25V
TDO
VSS
Z0 = 50Ω
(a)
CL = 20 pF
tTH
GND
1.5 ns
1.5 ns
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
Document #: 38-05292 Rev. *E
tTDOX
Page 14 of 27
CY7C1354BV25
CY7C1356BV25
Identification Register Definitions
Instruction Field
CY7C1354BV25
CY7C1356BV25
Revision Number (31:29)
001
Cypress Device ID (28:12)
01011001000100110
001
Cypress JEDEC ID (11:1)
00000110100
00000110100
ID Register Presence (0)
1
1
Description
Reserved for version number.
01011001000010110 Reserved for future use.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
69
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100
Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.
Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function
and is therefore not 1149.1-compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Document #: 38-05292 Rev. *E
Page 15 of 27
CY7C1354BV25
CY7C1356BV25
Boundary Scan Exit Order (×36) (continued)
Boundary Scan Exit Order (×36)
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
119-Ball ID
K4
H4
M4
F4
B4
G4
C3
B3
D6
H7
G6
E6
D7
E7
F6
G7
H6
T7
K7
L6
N6
P7
N7
M6
L7
K6
P6
T4
A3
C5
B5
A5
C6
A6
P4
Document #: 38-05292 Rev. *E
165-Ball ID
B6
B7
A7
B8
A8
A9
B10
A10
C11
E10
F10
G10
D10
D11
E11
F11
G11
H11
J10
K10
L10
M10
J11
K11
L11
M11
N11
R11
R10
P10
R9
P9
R8
P8
R6
Bit #
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
119-Ball ID
N4
R6
T5
T3
R2
R3
P2
P1
L2
K1
N2
N1
M2
L1
K2
Not Bonded
(Preset to 1)
H1
G2
E2
D1
H2
G1
F2
E1
D2
C2
A2
E4
B2
L3
G3
G5
L5
B6
165-Ball ID
P6
R4
P4
R3
P3
R1
N1
L2
K2
J2
M2
M1
L1
K1
J1
Not Bonded
(Preset to 1)
G2
F2
E2
D2
G1
F1
E1
D1
C1
B2
A2
A3
B3
B4
A4
A5
B5
A6
Page 16 of 27
CY7C1354BV25
CY7C1356BV25
Boundary Scan Exit Order (×18) (continued)
Boundary Scan Exit Order (×18)
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
119-Ball ID
K4
H4
M4
F4
B4
G4
C3
B3
T2
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
D6
E7
F6
G7
H6
T7
K7
L6
N6
P7
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
T6
A3
C5
B5
A5
C6
A6
P4
N4
Document #: 38-05292 Rev. *E
165-Ball ID
B6
B7
A7
B8
A8
A9
B10
A10
A11
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
C11
D11
E11
F11
G11
H11
J10
K10
L10
M10
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
R11
R10
P10
R9
P9
R8
P8
R6
P6
Bit #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
119-Ball ID
R6
T5
T3
R2
R3
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
P2
N1
M2
L1
K2
Not Bonded
(Preset to 1)
H1
G2
E2
D1
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
C2
A2
E4
B2
Not Bonded
(Preset to 0
G3
Not Bonded
(Preset to 0
L5
B6
165-Ball ID
R4
P4
R3
P3
R1
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
N1
M1
L1
K1
J1
Not Bonded
(Preset to 1)
G2
F2
E2
D2
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
B2
A2
A3
B3
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
A4
B5
A6
Page 17 of 27
CY7C1354BV25
CY7C1356BV25
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
Range
Ambient
Temperature
VDD/VDDQ
DC to Outputs in three-state ............... –0.5V to VDDQ + 0.5V
Commercial
0°C to +70°C
2.5V +
_ 5%
DC Input Voltage....................................–0.5V to VDD + 0.5V
Industrial
–40°C to +85°C
Electrical Characteristics Over the Operating Range[14, 15]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VDD
Power Supply Voltage
2.375
2.625
V
VDDQ
I/O Supply Voltage
2.375
VDD
V
VOH
Output HIGH Voltage
VDD = Min., IOH = −1.0 mA
VOL
Output LOW Voltage
VDD = Min., IOL= 1.0 mA
0.4
V
VIH
Input HIGH Voltage
VDDQ = 2.5V
1.7
VDD + 0.3V
V
VIL
Input LOW Voltage[14]
VDDQ = 2.5V
–0.3
0.7
V
Input Load Current
GND ≤ VI ≤ VDDQ
–5
5
µA
–30
30
µA
IX
2.0
Input Current of MODE
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
V
5
µA
4.4-ns cycle, 225 MHz
250
mA
5-ns cycle, 200 MHz
220
mA
6-ns cycle, 166 MHz
180
mA
–5
ISB1
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected, All speed grades
VIN ≥ VIH or VIN ≤ VIL, f = fMAX =
1/tCYC
50
mA
ISB2
Automatic CE
Max. VDD, Device Deselected, All speed grades
Power-down
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
Current—CMOS Inputs f = 0
35
mA
ISB3
Automatic CE
Max. VDD, Device Deselected, All speed grades
Power-down
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
Current—CMOS Inputs f = fMAX = 1/tCYC
50
mA
ISB4
Automatic CE
Power-down
Current—TTL Inputs
40
mA
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
All speed grades
Shaded areas contain advance information.
Capacitance[16]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 2.5V VDDQ = 2.5V
BGA Max.
fBGA Max.
TQFP Max.
Unit
5
5
5
pF
5
5
5
pF
7
7
5
pF
Notes:
14. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2).
15. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05292 Rev. *E
Page 18 of 27
CY7C1354BV25
CY7C1356BV25
AC Test Loads and Waveforms
R=1667Ω
2.5V
OUTPUT
ALL INPUT PULSES
Output
Z0 = 50Ω
RL = 50Ω
VL = 1.25V
VDD
5 pF
INCLUDING
JIG AND
SCOPE
(a)
0V
R = 1538Ω
90%
10%
[16]
90%
10%
1.25V
< 1.0 ns
< 1.0 ns
(c)
(b)
Thermal Resistance[16]
Parameters
Description
QJA
Thermal Resistance
(Junction to Ambient)
QJC
Thermal Resistance
(Junction to Case)
Test Conditions
BGA Typ.
fBGA Typ.
TQFP Typ.
Unit
Notes
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per EIA
/ JESD51.
25
27
25
°C/W
17
6
6
9
°C/W
17
Switching Characteristics Over the Operating Range
[ 21, 22]
-225
Parameter
tPower[17]
-200
Max.
Min.
-166
Max.
Min.
Max.
Unit
Description
Min.
VCC (typical) to the first access read or write
1
1
1
ms
4.4
5
6
ns
Clock
tCYC
Clock Cycle Time
FMAX
Maximum Operating Frequency
tCH
Clock HIGH
1.8
2.0
2.4
ns
tCL
Clock LOW
1.8
2.0
2.4
ns
225
200
166
MHz
Output Times
tCO
Data Output Valid After CLK Rise
2.8
3.2
3.5
ns
tEOV
OE LOW to Output Valid
2.8
3.2
3.5
ns
tDOH
Data Output Hold After CLK Rise
1.25
tCHZ
Clock to High-Z[18, 19, 20]
1.25
tCLZ
[18, 19, 20]
Clock to Low-Z
1.25
tEOHZ
OE HIGH to Output High-Z[18, 19, 20]
tEOLZ
OE LOW to Output
Low-Z[18, 19, 20]
1.5
2.8
1.5
1.5
3.2
1.5
2.8
1.5
ns
3.5
1.5
3.2
ns
ns
3.5
ns
0
0
0
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
1.4
1.5
1.5
ns
tDS
Data Input Set-up Before CLK Rise
1.4
1.5
1.5
ns
tCENS
CEN Set-up Before CLK Rise
WE, BWx Set-up Before CLK Rise
1.4
1.5
1.5
ns
1.4
1.5
1.5
ns
tWES
tALS
1.4
1.5
1.5
ns
ADV/LD Set-up Before CLK Rise
Shaded areas contain advance information.
Notes:
16. Tested initially and after any design or process changes that may affect these parameters.
17. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be
initiated.
18. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
19. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
20. This parameter is sampled and not 100% tested.
21. Timing reference level is 1.5V when VDDQ = 2.5V.
22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05292 Rev. *E
Page 19 of 27
CY7C1354BV25
CY7C1356BV25
Switching Characteristics Over the Operating Range (continued)[ 21, 22]
-225
Parameter
Description
Min.
-200
Max.
Min.
-166
Max.
Min.
Max.
Unit
tCES
Chip Select Set-up
1.4
1.5
1.5
ns
tAH
Address Hold After CLK Rise
0.4
0.5
0.5
ns
Hold Times
tDH
Data Input Hold After CLK Rise
0.4
0.5
0.5
ns
tCENH
CEN Hold After CLK Rise
0.4
0.5
0.5
ns
tWEH
WE, BWx Hold After CLK Rise
0.4
0.5
0.5
ns
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
0.4
0.5
0.5
ns
0.4
0.5
0.5
ns
tALH
tCEH
Switching Waveforms
Read/WriteTiming[23,24,25]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCH
tCL
CEN
tCES
tCEH
CE
ADV/LD
WE
BWx
A1
ADDRESS
A2
tCO
tAS
tDS
tAH
Data
tDH
D(A1)
tCLZ
D(A2)
D(A2+1)
tDOH
Q(A3)
tOEV
Q(A4)
tCHZ
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
tOEHZ
tDOH
tOELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes:
23. For this waveform ZZ is tied low.
24. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
25. Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved).Burst operations are optional.
Document #: 38-05292 Rev. *E
Page 20 of 27
CY7C1354BV25
CY7C1356BV25
Switching Waveforms (continued)
NOP,STALL AND DESELECT CYCLES[23,24,26]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
ADDRESS
A5
tCHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Note:
26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle
Document #: 38-05292 Rev. *E
Page 21 of 27
CY7C1354BV25
CY7C1356BV25
Switching Waveforms (continued)
ZZ Mode Timing [27, 28]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Note:
27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
28. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05292 Rev. *E
Page 22 of 27
CY7C1354BV25
CY7C1356BV25
Ordering Information
Speed
(MHz)
225
Ordering Code
CY7C1354BV25-225AC
Package
Name
Package Type
Operating
Range
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Commercial
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Industrial
CY7C1356BV25-225AC
CY7C1354BV25-225AI
CY7C1356BV25-225AI
CY7C1354BV25-225BGC
BG119
119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
BG119
119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Industrial
CY7C1356BV25-225BGC
CY7C1354BV25-225BGI
CY7C1356BV25-225BGI
CY7C1354BV25-225BZC
BB165A
165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Commercial
BB165A
165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Industrial
CY7C1356BV25-225BZC
CY7C1354BV25-225BZI
CY7C1356BV25-225BZI
200
CY7C1354BV25-200AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Commercial
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Industrial
CY7C1356BV25-200AC
CY7C1354BV25-200AI
CY7C1356BV25-200AI
CY7C1354BV25-200BGC
BG119
119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
BG119
119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Industrial
CY7C1356BV25-200BGC
CY7C1354BV25-200BGI
CY7C1356BV25-200BGI
CY7C1354BV25-200BZC
BB165A
165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Commercial
BB165A
165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Industrial
CY7C1356BV25-200BZC
CY7C1354BV25-200BZI
CY7C1356BV25-200BZI
166
CY7C1354BV25-166AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Commercial
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Industrial
CY7C1356BV25-166AC
CY7C1354BV25-166AI
CY7C1356BV25-166AI
CY7C1354BV25-166BGC
BG119
119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
BG119
119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Industrial
CY7C1356BV25-166BGC
CY7C1354BV25-166BGI
CY7C1356BV25-166BGI
CY7C1354BV25-166BZC
BB165A
165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Commercial
BB165A
165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Industrial
CY7C1356BV25-166BZC
166
CY7C1354BV25-166BZI
CY7C1356BV25-166BZI
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05292 Rev. *E
Page 23 of 27
CY7C1354BV25
CY7C1356BV25
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05292 Rev. *E
Page 24 of 27
CY7C1354BV25
CY7C1356BV25
Package Diagrams (continued)
119-Lead BGA (14 x 22 x 2.4mm) BG119
51-85115-*B
Document #: 38-05292 Rev. *E
Page 25 of 27
CY7C1354BV25
CY7C1356BV25
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
ZBT is a registered trademark of Integrated Device Technology. No Bus Latency and NoBL are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05292 Rev. *E
Page 26 of 27
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1354BV25
CY7C1356BV25
Document History Page
Document Title: CY7C1354BV25/CY7C1356BV25 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05292
REV.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
114767
08/08/02
RCS
New Data Sheet
*A
117938
08/20/02
RCS
Added A0 and A1 to 165 FBGA pinout
*B
126206
04/11/03
DPM
Removed Preliminary status
Removed 250-MHz Speed bin
Added 225-MHz speed bin
Increased TCO, TEOV, TCHZ, TEOHZ for 200 MHz to 3.2 ns from 3.0 ns
Updated JTAG revision number and device depth
Updated JTAG boundary scan orders
Added tPower specification
Changed footnotes ordering
Added Industrial operating range
Changed Capacitance table to have TQFP, BGA, and fBGA columns
*C
206704
See ECN
NJY
Removed footnote 13 “Minimum voltage equals –2.0V for pulse durations of less than 20 ns.”
Removed footnote 14 “TA is the case temperature.”
Changed footnote 15 from “Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot:
VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms“
to footnote 13 “ Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot:
VIL(AC)> -2V (Pulse width less than tCYC/2)“
Added footnote 14 “ TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200ms. During
this time VIH < VDD and VDDQ < VDD“
Changed footnote 20 from “ Test conditions shown in (a), (b) and (c) of AC Test Loads “ to
“Test conditions shown in (a) of AC Test Loads unless otherwise noted “
Updated ZZ Mode Electrical Characteristics
Updated ISB1 and ISB3 currents in Electrical Characteristics table
Updated the Test Condition in Thermal Resistance table
Updated Ordering Information
*D
239272
See ECN
VBL
Changed Bit #24 on ID register definitions on page 15 from “0“ to “1”
Update Ordering Info
*E
280209
See ECN
NJY
Changed balls B4 and A5 from BWd and BWb to NC and ball A4 from BWc
to BWb for 165-ball FBGA package for CY7C1356BV25
Changed balls C11 from DQPb to DQPa and balls D11,E11,F11 and G11
from DQb to DQa for CY7C1356BV25.
Document #: 38-05292 Rev. *E
Page 27 of 27

Open as PDF

Similar pages