1CY 7C40 2 CY7C401/CY7C403 CY7C402/CY7C404 64 x 4 Cascadable FIFO 64 x 5 Cascadable FIFO Features words. Both the CY7C403 and CY7C404 have an output enable (OE) function. • 64 x 4 (CY7C401 and CY7C403) 64 x 5 (CY7C402 and CY7C404) High-speed first-in first-out memory (FIFO) • Processed with high-speed CMOS for optimum speed/power • 25-MHz data rates • 50-ns bubble-through time—25 MHz • Expandable in word width and/or length • 5-volt power supply ± 10% tolerance, both commercial and military • Independent asynchronous inputs and outputs • TTL-compatible interface • Output enable function available on CY7C403 and CY7C404 • Capable of withstanding greater than 2001V electrostatic discharge • Pin compatible with MMI 67401A/67402A The devices accept 4- or 5-bit words at the data input (DI0 – DIn) under the control of the shift in (SI) input. The stored words stack up at the output (DO0 – DOn) in the order they were entered. A read command on the shift out (SO) input causes the next to last word to move to the output and all data shifts down once in the stack. The input ready (IR) signal acts as a flag to indicate when the input is ready to accept new data (HIGH), to indicate when the FIFO is full (LOW), and to provide a signal for a cascading. The output ready (OR) signal is a flag to indicate the output contains valid data (HIGH), to indicate the FIFO is empty (LOW), and to provide a signal for cascading. Parallel expansion for wider words is accomplished by logically ANDing the IR and OR signals to form composite signals. Serial expansion is accomplished by tying the data inputs of one device to the data outputs of the previous device. The IR pin of the receiving device is connected to the SO pin of the sending device, and the OR pin of the sending device is connected to the SI pin of the receiving device. Functional Description Reading and writing operations are completely asynchronous, allowing the FIFO to be used as a buffer between two digital machines of widely differing operating frequencies. The 25-MHz operation makes these FIFOs ideal for high-speed communication and controller applications. The CY7C401 and CY7C403 are asynchronous first-in first-out (FIFOs) organized as 64 four-bit words. The CY7C402 and CY7C404 are similar FIFOs organized as 64 five-bit Logic Block Diagram Pin Configurations DIP SI IR INPUT CONTROL LOGIC WRITE POINTER OUTPUT ENABLE WRITE MULTIPLEXER OE DI 0 DI 1 DI 2 DATAIN DIP 1 16 2 15 3 14 CY7C401 4 13 CY7C403 5 12 6 11 10 7 9 8 DO0 DO1 MEMORY ARRAY DI 3 (CY7C401) NC (CY7C403) OE IR SI DI 0 DI 1 DI 2 DI 3 GND DATAIN (DI 4) VCC SO OR DO 0 DO 1 DO 2 DO 3 MR (CY7C402) NC (CY7C404) OE IR SI DI 0 DI 1 DI 2 DI 3 DI 4 GND 1 18 2 17 3 16 CY7C402 4 15 CY7C404 5 14 6 13 12 7 11 8 10 9 C401–2 DO2 DO3 VCC SO OR DO 0 DO 1 DO 2 DO 3 DO 4 MR C401–4 LCC LCC (DO 4) MR MASTER RESET READ MULTIPLEXER OUTPUT CONTROL LOGIC READ POINTER SI DI 0 DI 1 DI 2 NC SO OR 3 2 1 2019 4 18 NC 5 17 OR CY7C401 6 CY7C403 16 DO 7 15 DO 8 14 DO 910111213 SI 0 1 2 DI DI DI DI 0 1 2 3 3 2 1 2019 4 18 OR 5 17 DO 0 6 CY7C402 16 DO 1 CY7C404 7 15 DO 2 8 14 DO 3 910111213 C401–1 C401–3 C401–5 Selection Guide Operating Frequency (MHz) Maximum Operating Current (mA) Commercial 7C401/2–5 7C40X–10 7C40X–15 7C40X–25 5 10 15 25 75 75 75 75 90 90 90 Military Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 March 1986 – Revised April 1995 CY7C401/CY7C403 CY7C402/CY7C404 Maximum Ratings Output Current, into Outputs (LOW)............................ 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current ..................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage to Ground Potential ............... –0.5V to +7.0V Range Ambient Temperature VCC DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V Commercial 0°C to +70°C 5V ±10% DC Input Voltage............................................ –3.0V to +7.0V Military –55°C to +125°C 5V ±10% [1] Power Dissipation ..........................................................1.0W Electrical Characteristics Over the Operating Range (Unless Otherwise Noted) [2] 7C40X–10, 15, 25 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Leakage Current VCD[3] Input Diode Clamp Voltage[3] IOZ Min. Max. Unit 2.4 V 0.4 V 2.0 6.0 V –3.0 0.8 V GND ≤ VI ≤ VCC –10 +10 µA Output Leakage Current GND ≤ VOUT ≤ VCC, VCC = 5.5V Output Disabled (CY7C403 and CY7C404) –50 +50 µA IOS Output Short Circuit Current[4] VCC = Max., VOUT = GND –90 mA ICC Power Supply Current VCC = Max., IOUT = 0 mA Commercial 75 mA Military 90 mA Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 4.5V Max. Unit 5 pF 7 pF Notes: 1. TA is the “instant on” case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. The CMOS process does not provide a clamp diode. However, the FIFO is insensitive to –3V dc input levels and –5V undershoot pulses of less than 10 ns (measured at 50% output). 4. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. 5. Tested initially and after any design or process changes that may affect these parameters. 2 CY7C401/CY7C403 CY7C402/CY7C404 AC Test Loads and Waveforms R1 437Ω 5V OUTPUT OUTPUT R2 272Ω 30 pF ALL INPUT PULSES R1 437Ω 5V 3.0V R2 272Ω 5 pF INCLUDING JIG AND SCOPE GND (b) 90% 10% ≤ 5 ns INCLUDING JIG AND SCOPE (a) 90% 10% ≤ 5 ns C401–6 C401–7 Equivalent to: THÉVENIN EQUIVALENT OUTPUT 167Ω 1.73V C401–8 Switching Characteristics Over the Operating Range[2, 6] Parameter Description 7C401–5 7C402–5 Test Conditions Min. Note 8 Max. 7C40X–10 7C40X–15 7C40X–25[7] Min. Min. Min. 5 Max. 10 Max. Unit 25 MHz fO Operating Frequency tPHSI SI HIGH Time tPLSI SO LOW Time tSSI Data Set-Up to SI Note 9 tHSI Data Hold from SI Note 9 60 tDLIR Delay, SI HIGH to IR LOW tDHIR Delay, SI LOW to IR HIGH tPHSO SO HIGH Time 20 tPLSO SO LOW Time 45 tDLOR Delay, SO HIGH to OR LOW tDHOR Delay, SO LOW to OR HIGH tSOR Data Set-Up to OR HIGH 0 tHSO Data Hold from SO LOW 5 tBT Bubble-Through Time tSIR Data Set-Up to IR Note 10 5 5 5 5 ns tHIR Data Hold from IR Note 10 30 30 30 20 ns tPIR Input Ready Pulse HIGH 20 20 20 15 ns tPOR Output Ready Pulse HIGH 20 20 20 15 ns tPMR MR Pulse Width 40 30 25 25 ns tDSI MR HIGH to SI HIGH 40 35 25 10 ns tDOR MR LOW to OR LOW 85 40 35 35 ns tDIR MR LOW to IR HIGH 85 40 35 35 ns tLZMR MR LOW to Output LOW 50 40 35 25 ns tOOE Output Valid from OE LOW — 35 30 20 ns tHZOE Output High Z from OE HIGH — 30 25 15 ns 20 20 20 11 ns 45 30 25 20 ns 0 0 0 0 ns 40 75 40 0 5 10 10 28/30 ns ns ns 19/21 ns 34/37 ns 0 5 95 ns 20 35 55 ns 21/22 11 25 40 0 200 40 20 25 80 20 35 45 20 75 Note 12 30 40 75 Note 11 15 Max. ns 5 65 10 ns 50/60 ns Notes: 6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30-pF load capacitance, as in part (a) of AC Test Loads and Waveforms. 7. Commercial/Military 8. I/fO > t PHSI + t DHIR, I/f O > tPHSO + t DHOR 9. tSSI and tHSI apply when memory is not full. 10. tSIR and t HIR apply when memory is full, SI is high and minimum bubble-through (tBT ) conditions exist. 11. All data outputs will be at LOW level after reset goes HIGH until data is entered into the FIFO. 12. HIGH-Z transitions are referenced to the steady-state VOH –500 mV and VOL +500 mV levels on the output. tHZOE is tested with 5-pF load capacitance as in part (b) of AC Test Loads and Waveforms. 3 CY7C401/CY7C403 CY7C402/CY7C404 Operational Description Application of the 7C403–25/7C404–25 at 25 MHz Application of the CY7C403 or CY7C404 Cypress CMOS FIFOs requires knowledge of characteristics that are not easily specified in a datasheet, but which are necessary for reliable operation under all conditions, so we will specify them here. Concept Unlike traditional FIFOs, these devices are designed using a dual-port memory, read and write pointer, and control logic. The read and write pointers are incremented by the SO and SI respectively. The availability of an empty space to shift in data is indicated by the IR signal, while the presence of data at the output is indicated by the OR signal. The conventional concept of bubble-through is absent. Instead, the delay for input data to appear at the output is the time required to move a pointer and propagate an OR signal. The output enable (OE) signal provides the capability to OR tie multiple FIFOs together on a common bus. When an empty FIFO is filled with initial information at maximum “shift in” SI frequency, followed by immediate shifting out of the data also at maximum “shift out” SO frequency, the designer must be aware of a window of time which follows the initial rising edge of the OR signal, during which time the SO signal is not recognized. This condition exists only at high-speed operation where more than one SO may be generated inside the prohibited window. This condition does not inhibit the operation of the FIFO at full-frequency operation, but rather delays the full 25-MHz operation until after the window has passed. Resetting the FIFO Upon power-up, the FIFO must be reset with a master reset (MR) signal. This causes the FIFO to enter an empty condition signified by the OR signal being LOW at the same time the IR signal is HIGH. In this condition, the data outputs (DO0 – DO n) will be in a LOW state. There are several implementation techniques for managing the window so that all SO signals are recognized: 1. The first involves delaying SO operation such that it does not occur in the critical window. This can be accomplished by causing a fixed delay of 40 ns “initiated by the SI signal only when the FIFO is empty” to inhibit or gate the SO activity. However, this requires that the SO operation be at least temporarily synchronized with the input SI operation. In synchronous applications this may well be possible and a valid solution. Shifting Data In Data is shifted in on the rising edge of the SI signal. This loads input data into the first word location of the FIFO. On the falling edge of the SI signal, the write pointer is moved to the next word position and the IR signal goes HIGH, indicating the readiness to accept new data. If the FIFO is full, the IR will remain LOW until a word of data is shifted out. 2. Another solution not uncommon in synchronous applications is to only begin shifting data out of the FIFO when it is more than half full. This is a common method of FIFO application, as earlier FIFOs could not be operated at maximum frequency when near full or empty. Although Cypress FIFOs do not have this limitation, any system designed in this manner will not encounter the window condition described above. Shifting Data Out Data is shifted out of the FIFO on the falling edge of the SO signal. This causes the internal read pointer to be advanced to the next word location. If data is present, valid data will appear on the outputs and the OR signal will go HIGH. If data is not present, the OR signal will stay LOW indicating the FIFO is empty. Upon the rising edge of SO, the OR signal goes LOW. The data outputs of the FIFO should be sampled with edge-sensitive type D flip-flops (or equivalent), using the SO signal as the clock input to the flip-flop. 3. The window may also be managed by not allowing the first SO signal to occur until the window in question has passed. This can be accomplished by delaying the SO 40 ns from the rising edge of the initial OR signal. This however involves the requirement that this only occurs on the first occurrence of data being loaded into the FIFO from an empty condition and therefore requires the knowledge of IR and SI conditions as well as SO. Bubble-Through Two bubble-through conditions exist. The first is when the device is empty. After a word is shifted into an empty device, the data propagates to the output. After a delay, the OR flag goes HIGH, indicating valid data at the output. 4. Handshaking with the OR signal is a third method of avoiding the window in question. With this technique the rising edge of SO, or the fact that SO signal is HIGH, will cause the OR signal to go LOW. The SO signal is not taken LOW again, advancing the internal pointer to the next data, until the OR signal goes LOW. This ensures that the SO pulse that is initiated in the window will be automatically extended long enough to be recognized. The second bubble-through condition occurs when the device is full. Shifting data out creates an empty location that propagates to the input. After a delay, the IR flag goes HIGH. If the SI signal is HIGH at this time, data on the input will be shifted in. 5. There remains the decision as to what signal will be used to latch the data from the output of the FIFO into the receiving source. The leading edge of the SO signal is most appropriate because data is guaranteed to be stable prior to and after the SO leading edge for each FIFO. This is a solution for any number of FIFOs in parallel. Possible Minimum Pulse Width Violation at the Boundary Conditions If the handshaking signals IR and OR are not properly used to generate the SI and SO signals, it is possible to violate the minimum (effective) SI and SO positive pulse widths at the full and empty boundaries. Any of the above solutions will ensure the correct operation of a Cypress FIFO at 25 MHz. The specific implementation is left to the designer and is dependent on the specific application needs. When this violation occurs, the operation of the FIFO is unpredictable. It must then be reset, and all data is lost. 4 CY7C401/CY7C403 CY7C402/CY7C404 Switching Waveforms Data In Timing Diagram I/fO I/fO SHIFT IN tPHSI tPLSI tDHIR INPUT READY tHSI tDLIR DATA IN tSSI C401–9 Data Out Timing Diagram I/fO I/fO SHIFT OUT tPHSO tPLSO tDHOR OUTPUT READY tDLOR tHSO tSOR DATA OUT C401–10 Bubble Through, Data Out To Data In Diagram SHIFT OUT SHIFT IN tBT INPUT READY tPIR DATA IN tSIR tHIR C401–11 5 CY7C401/CY7C403 CY7C402/CY7C404 Switching Waveforms (continued) Bubble Through, Data In To Data Out Diagram SHIFT IN SHIFT OUT tBT tPOR OUTPUT READY tSOR DATA OUT C401–12 Master Reset Timing Diagram tPMR MASTER RESET tDIR INPUT READY tDOR OUTPUT READY tDSI SHIFT IN tLZMR DATA OUT C401–13 Output Enable Timing Diagram OUTPUT ENABLE tHZOE tOOE DATA OUT NOTE 10 C401–14 6 CY7C401/CY7C403 CY7C402/CY7C404 Typical DC and AC Characteristics OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.2 1.4 1.0 1.2 60 50 40 0.8 1.0 0.6 4.5 5.0 20 0.8 VIN =5.0V TA =25°C 0.4 4.0 30 5.5 6.0 VCC =5.5V VIN =5.0V 0.0 –55 25 0 0.0 125 1.0 AMBIENTTEMPERATURE (°C) SUPPLY VOLTAGE (V) 1.3 1.6 1.2 1.4 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE NORMALIZED FREQUENCY vs. AMBIENT TEMPERATURE NORMALIZED FREQUENCY vs. SUPPLY VOLTAGE 140 120 100 1.1 1.2 80 1.0 60 1.0 0.9 40 0.8 0.8 0.7 4.0 VCC =5.0V TA =25°C 10 4.5 5.0 5.5 6.0 VCC =5.0V TA =25°C 20 0.6 –55 25 0 0.0 125 1.0 AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) TYPICAL FREQUENCY CHANGE vs. OUTPUT LOADING 2.0 3.0 4.0 OUTPUT VOLTAGE (V) NORMALIZED I CC vs. FREQUENCY 1.6 1.1 1.5 1.0 1.4 0.9 1.3 0.8 1.2 0.7 1.1 1.0 0.0 0 200 400 600 0 800 1000 5 10 15 20 25 30 35 C401–15 FREQUENCY (MHz) CAPACITANCE (pF) 7 CY7C401/CY7C403 CY7C402/CY7C404 FIFO Expansion[13, 14, 15, 16, 17] 128 x 4 Application[18] SHIFT IN INPUT READY DATA IN SI IR OR SO DO0 DI0 DO0 DO1 DI1 DO1 DO2 DI2 DO2 DO3 DI3 SI IR OR SO DI0 DI1 DI2 DI3 MR MR MR OUTPUT READY SHIFT OUT DATA OUT DO3 C401–16 192 x 12 Application[19] SHIFT OUT IR SO SI OR DI0 DO0 DI1 DO1 DO2 DI2 DI3 MR DO3 IR SI DI0 DI1 DI2 DI3 MR SO OR DO0 DO1 DO2 DO3 IR SO SI OR DI0 DO0 DI1 DO1 DO2 DI2 DI3 MR DO3 COMPOSITE INPUT READY SHIFT IN IR SO SI OR DI0 DO0 DI1 DO1 DO2 DI2 DI3 MR DO3 IR SI DI0 DI1 DI2 DI3 MR SO OR DO0 DO1 DO2 DO3 IR SO SI OR DI0 DO0 DI1 DO1 DO2 DI2 DI3 MR DO3 IR SO SI OR DI0 DO0 DI1 DO1 DO2 DI2 DI3 MR DO3 IR SI DI0 DI1 DI2 DI3 MR SO OR DO0 DO1 DO2 DO3 IR SO SI OR DI0 DO0 DI1 DO1 DO2 DI2 DI3 MR DO3 COMPOSITE OUTPUT READY MR C401–17 Notes: 13. When the memory is empty, the last word read will remain on the outputs until the master reset is strobed or a new data word bubbles through to the output. However, OR will remain LOW, indicating data at the output is not valid. 14. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data, and stays LOW until the new data has appeared on the outputs. Anytime OR is HIGH, there is valid, stable data on the outputs. 15. If SO is held HIGH while the memory is empty and a word is written into the input, that word will ripple through the memory to the output. OR will go HIGH for one internal cycle (at least tORL ) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO, they will line up behind the first word and will not appear on the outputs until SO has been brought LOW. 16. When the master reset is brought LOW, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the master reset goes HIGH, then the data on the inputs will be written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the master reset is ended, then IR will go HIGH, but the data on the inputs will not enter the memory until SI goes HIGH. 17. All Cypress FIFOs will cascade with other Cypress FIFOs. However, hey may not cascade with pin-compatible FIFOs from other manufacturers. 18. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices. 19. FIFOs are expandable in depth and width. However, in forming wider words two external gates are required to generate composite input and output ready flags. This need is due to the variation of delays of the FIFOs. 8 CY7C401/CY7C403 CY7C402/CY7C404 Ordering Information Speed (MHz) Ordering Code Package Name Package Type Operating Range 5 CY7C401–5PC P1 16-Lead (300-Mil) Molded DIP Commercial 10 CY7C401–10DC D2 16-Lead (300-Mil) CerDIP Commercial CY7C401–10PC P1 16-Lead (300-Mil) Molded DIP CY7C401–10DMB D2 16-Lead (300-Mil) CerDIP CY7C401–10LMB L61 20-Pin Square Leadless Chip Carrier CY7C401–15DC D2 16-Lead (300-Mil) CerDIP CY7C401–15PC P1 16-Lead (300-Mil) Molded DIP CY7C401–15DMB D2 16-Lead (300-Mil) CerDIP CY7C401–15LMB L61 20-Pin Square Leadless Chip Carrier CY7C401–25DC D2 16-Lead (300-Mil) CerDIP CY7C401–25PC P1 16-Lead (300-Mil) Molded DIP CY7C401–25DMB D2 16-Lead (300-Mil) CerDIP CY7C401–25LMB L61 20-Pin Square Leadless Chip Carrier 15 25 Speed (MHz) Ordering Code Package Name Package Type Military Commercial Military Commercial Military Operating Range 5 CY7C402–5PC P3 18-Lead (300-Mil) Molded DIP Commercial 10 CY7C402–10DC D4 18-Lead (300-Mil) CerDIP Commercial CY7C402–10PC P3 20-Pin Square Leadless Chip Carrier CY7C402–10DMB D4 18-Lead (300-Mil) CerDIP CY7C402–10LMB L61 20-Pin Square Leadless Chip Carrier CY7C402–15DC D4 18-Lead (300-Mil) CerDIP CY7C402–15PC P3 18-Lead (300-Mil) Molded DIP CY7C402–15DMB D4 18-Lead (300-Mil) CerDIP CY7C402–15LMB L61 20-Pin Square Leadless Chip Carrier CY7C402–25DC D4 18-Lead (300-Mil) CerDIP CY7C402–25PC P3 18-Lead (300-Mil) Molded DIP CY7C402–25DMB D4 18-Lead (300-Mil) CerDIP CY7C402–25LMB L61 20-Pin Square Leadless Chip Carrier 15 25 9 Military Commercial Military Commercial Military CY7C401/CY7C403 CY7C402/CY7C404 Ordering Information (continued) Speed (MHz) 10 15 25 Speed (MHz) 10 15 25 Ordering Code Package Name Package Type CY7C403–10DC D2 16-Lead (300-Mil) CerDIP CY7C403–10PC P1 16-Lead (300-Mil) Molded DIP CY7C403–10DMB D2 16-Lead (300-Mil) CerDIP CY7C403–10LMB L61 20-Pin Square Leadless Chip Carrier CY7C403–15DC D2 16-Lead (300-Mil) CerDIP CY7C403–15PC P1 16-Lead (300-Mil) Molded DIP CY7C403–15DMB D2 16-Lead (300-Mil) CerDIP CY7C403–15LMB L61 20-Pin Square Leadless Chip Carrier CY7C403–25DC D2 16-Lead (300-Mil) CerDIP CY7C403–25PC P1 16-Lead (300-Mil) Molded DIP CY7C403–25DMB D2 16-Lead (300-Mil) CerDIP CY7C403–25LMB L61 20-Pin Square Leadless Chip Carrier Ordering Code Package Name Package Type CY7C404–10DC D4 18-Lead (300-Mil) CerDIP CY7C404–10PC P3 18-Lead (300-Mil) Molded DIP CY7C404–10DMB D4 18-Lead (300-Mil) CerDIP CY7C404–10LMB L61 20-Pin Square Leadless Chip Carrier CY7C404–15DC D4 18-Lead (300-Mil) CerDIP CY7C404–15PC P3 18-Lead (300-Mil) Molded DIP CY7C404–15DMB D4 18-Lead (300-Mil) CerDIP CY7C404–15LMB L61 20-Pin Square Leadless Chip Carrier CY7C404–25DC D4 18-Lead (300-Mil) CerDIP CY7C404–25PC P3 18-Lead (300-Mil) Molded DIP CY7C404–25DMB D4 18-Lead (300-Mil) CerDIP CY7C404–25LMB L61 20-Pin Square Leadless Chip Carrier 10 Operating Range Commercial Military Commercial Military Commercial Military Operating Range Commercial Military Commercial Military Commercial Military CY7C401/CY7C403 CY7C402/CY7C404 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameters Switching Characteristics Subgroups Parameters Subgroups VOH 1, 2, 3 fO 7, 8, 9, 10, 11 VOL 1, 2, 3 tPHSI 7, 8, 9, 10, 11 VIH 1, 2, 3 tPLSI 7, 8, 9, 10, 11 VIL Max. 1, 2, 3 tSSI 7, 8, 9, 10, 11 IIX 1, 2, 3 tHSI 7, 8, 9, 10, 11 IOZ 1, 2, 3 tDLIR 7, 8, 9, 10, 11 IOS 1, 2, 3 tDHIR 7, 8, 9, 10, 11 ICC 1, 2, 3 tPHSO 7, 8, 9, 10, 11 tPLSO 7, 8, 9, 10, 11 tDLOR 7, 8, 9, 10, 11 tDHOR 7, 8, 9, 10, 11 tSOR 7, 8, 9, 10, 11 tHSO 7, 8, 9, 10, 11 tBT 7, 8, 9, 10, 11 tSIR 7, 8, 9, 10, 11 tHIR 7, 8, 9, 10, 11 tPIR 7, 8, 9, 10, 11 tPOR 7, 8, 9, 10, 11 tPMR 7, 8, 9, 10, 11 tDSI 7, 8, 9, 10, 11 tDOR 7, 8, 9, 10, 11 tDIR 7, 8, 9, 10, 11 tLZMR 7, 8, 9, 10, 11 tOOE 7, 8, 9, 10, 11 tHZOE 7, 8, 9, 10, 11 Document #: 38–00040–H 11 CY7C401/CY7C403 CY7C402/CY7C404 Package Diagrams 16-Lead (300-Mil) CerDIP D2 MIL-STD-1835 18-Lead (300-Mil) CerDIP D4 D- 2 Config.A MIL-STD-1835 20-Pin Square Leadless Chip Carrier L61 MIL-STD-1835 C–2A 12 D-8 Config.A CY7C401/CY7C403 CY7C402/CY7C404 Package Diagrams (continued) 16-Lead (300-Mil) Molded DIP P1 18-Lead (300-Mil) Molded DIP P3 © Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.