Cypress CYM9260 64k(128k, 256k, 512k) x 72 sram module Datasheet

CYM9260
CYM9261B
CYM9262A
CYM9263
62A
64K x 72 SRAM Module
128K x 72 SRAM Module
256K x 72 SRAM Module
512K x 72 SRAM Module
Features
• Operates at 66 MHz
• Uses 64K x 18, 128K x 18, or 256K x 18 high performance
synchronous SRAMs
• 168-position Angled DIMM from Amp p/n 179508-2
• 3.3V inputs/data outputs
Functional Description
The CYM9260, CYM9261, CYM9262, and the CYM9263 are
high-performance synchronous memory modules organized
as 64K(9260), 128K(9261), 256K(9262), or 512K(9263) by 72
bits. These modules are constructed from either 128K x
18(9260,9261B,9262A) or 256K x 18 (9263) SRAMs in plastic
surface mount packages on an epoxy laminate board with
pins. The modules are designed to be incorporated into large
memory arrays.
The module is configured as either one or two banks, where
each bank has separate chip select and output enable controls. Separate clocks are provided for every pair of SRAMs’s.
Multiple ground pins and on-board decoupling capacitors ensure high performance with maximum noise immunity.
All components on the cache modules are surface mounted on
a multi-layer epoxy laminate (FR-4) substrate. The contact
pins are plated with 150 micro-inches of nickel covered by 30
micro-inches of gold flash.
Logic Block Diagram - CYM9260
R4
A[15:0]
Vcc3
R2
WE[7:0]
R3
ADSP
A15:0
OE[0:1]
OE0
ADSP
OE
CS0
CS
CS[0:1]
(4) 64K x 18 SRAM
Vcc3
DQ[0:15]
DQP[0:1]
D[0:63]
DP[0:7]
WEH
WEL
CLK
ADSC
BANK 0
CLK[0:3]
CLK[0]
CLK[1]
CLK[2]
CLK[3]
R1
R1, R2, R3, R4 are optional resistors
R1, R2, R4 are mounted for access using ADSC
R3, R2, R4 are mounted for access using ADSP
64Kx72
PD1
GND
PD0
NC
BANK 0
Cypress Semiconductor Corporation
Document #: 38-05002 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised March 27, 2002
CYM9260
CYM9261B
CYM9262A
CYM9263
Logic Block Diagram - CYM9261B/CYM9262A
Vcc3
Vcc3
R2
WE[0:7]
R3
ADSP
A17:0
OE[0:1]
OE0
ADSP
OE
CE0
CS
CS[0:1]
(4) 128K x 18 SRAM
R4
A[17:0]
DQ[0:15]
DQP[0:1]
D[0:63]
DP[0:7]
WEH
WEL
A17:0
CLK[3]
(4) 128K x 18 SRAM
BANK 0
CLK[0:3]
CLK[0]
CLK[1]
CLK[2]
CLK
ADSC
R1
D[0:15]
DQ[0:1]
ADSP
R1, R2, R3, R4 are optional resistors
R1, R2, R4 are mounted for access using ADSC
R3, R2, R4 are mounted for access using ADSP
OE1
CE1
OE
CS
WEH
WEL
BANK 0
256KX72
GND
GND
BANK 0 & 1
Document #: 38-05002 Rev. **
ADSC
BANK 1
CLK
CLK[2]
CLK[3]
PD0
GND
CLK[0]
CLK[1]
128Kx72
PD1
NC
Page 2 of 12
CYM9260
CYM9261B
CYM9262A
CYM9263
Logic Block Diagram - CYM9263
Vcc3
Vcc3
WE[0:7]
R3
ADSP
A17:0
OE[0:1]
OE0
ADSP
OE
CE0
CS
CS[0:1]
(4) 256K x 18 SRAM
R2
R4
A[17:0]
DQ[0:15]
DQP[0:1]
D[0:63]
DP[0:7]
WEH
WEL
A17:0
R1, R2, R3, R4 are optional resistors
R1, R2, R4 are mounted for access using ADSC
R3, R2, R4 are mounted for access using ADSP
(4) 256K x 18 SRAM
BANK 0
CLK[0:3]
CLK[0]
CLK[1]
CLK[2]
CLK[3]
CLK
ADSC
R1
D[0:15]
DQ[0:1]
ADSP
OE1
CE1
OE
CS
WEH
WEL
NC
NC
ADSC
BANK 0 & 1
BANK 1
CLK
CLK[3]
PD0
CLK[0]
CLK[1]
CLK[2]
512KX72
PD1
Selection Guide
Synchronous Cache Module
Part Number
CYM9260-66
CYM9261B-66
CYM9262A-66
CYM9263-66
Cache Size
64 K x 72
128 K x 72
256 K x 72
512 K x 72
SRAMs Used
4 of 64K x 18
4 of 128K x 18
8 of 128K x 18
8 of 256K x 18
System Clock (MHz)
66
66
66
66
Data tCDV
10.3 ns
10.3 ns
10.3 ns
10.3 ns
Document #: 38-05002 Rev. **
Page 3 of 12
CYM9260
CYM9261B
CYM9262A
CYM9263
Pin Configuration
Dual Read-Out SIMM (DIMM)
Top View
Document #: 38-05002 Rev. **
GND
D63
D62
VCC3
D60
D58
GND
D56
D55
GND
1
2
3
4
5
6
7
8
9
10
85
86
87
88
89
90
91
92
93
94
GND
DP7
D61
GND
D59
D57
GND
DP6
D54
VCC3
D53
D51
GND
D49
DP5
VCC3
D46
D44
GND
D42
D40
GND
D39
D37
GND
D35
D33
GND
CLK3
GND
DP3
D30
VCC3
D28
D26
GND
D24
D23
GND
D21
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
D52
D50
GND
D48
D47
GND
D45
D43
GND
D41
DP4
VCC3
D38
D36
GND
D34
D32
GND
CLK2
GND
D31
D29
GND
D27
D25
GND
DP2
D22
VCC3
D20
D19
GND
D17
DP1
VCC3
D14
D12
GND
D10
D8
GND
D7
D5
GND
D3
D1
VCC3
PD0
NC
GND
A16
A14
GND
A12
A10
GND
A8
A6
VCC3
A4
A2
A0
GND
CLK1
GND
WE7
WE5
GND
WE3
WE1
GND
OE1
CS1
GND
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
75
77
78
79
80
81
82
83
84
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
D18
GND
D16
D15
GND
D13
D11
GND
D9
DP0
VCC3
D6
D4
GND
D2
D0
GND
PD1
A17
GND
A15
A13
VCC3
A11
A9
GND
A7
A5
GND
A3
A1
ADSP
GND
CLK0
GND
WE6
WE4
GND
WE2
WE0
VCC3
OE0
CS0
GND
Page 4 of 12
CYM9260
CYM9261B
CYM9262A
CYM9263
Pin Definitions
Signal
Description
VCC3
3V Supply
GND
Ground
A[17:0]
Addresses From Processor
OE[1:0]
Output Enables For The Two Banks
WE[7:0]
Byte Write Enables
CS[1:0]
Chip Select For The Two Banks
PD0–PD1
Presence Detect Output Pins
D[63:0]
Data Lines From Processor
DP[7:0]
Data Parity Lines From Processor
CLK[0:3]
Clock Lines To The Module
ADSP
Address Strobe From The Processor
NC
Signal Not Connected On Module
RSVD
Reserved
Presence Detect Pins
PD1
PD0
CYM9260 - 64K x 72
GND
NC
CYM9261 - 128K x 72
NC
GND
CYM9262 - 256K x 72
GND
GND
CYM9263 - 512K x 72
NC
NC
Document #: 38-05002 Rev. **
Page 5 of 12
CYM9260
CYM9261B
CYM9262A
CYM9263
Maximum Ratings
DC Input Voltage ........................................... –0.5V to +4.6V
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –55°C to +125°C
Operating Range
Ambient Temperature
with Power Applied ........................................ –0°C to +70°C
Range
Commercial
3.3V Supply Voltage to Ground Potential ..... –0.5V to +4.5V
Ambient
Temperature
VCC
0°C to +70°C
3.3V ± 5%
DC Voltage Applied to Outputs
in High Z State .............................................. –0.5V to +4.6V
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Condition
Min.
Max.
Unit
2.2
VCC + 0.3
V
–0.3
0.8
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VOH
Output HIGH Voltage
VCC = Min., IOH = –4 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8 mA
0.4
V
ICC
(9260)
VCC Operating Supply Current
VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC
1000
mA
ICC
2.4
V
(9261)
VCC Operating Supply Current
VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC
1000
mA
ICC
(9262)
VCC Operating Supply Current
VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC
1200
mA
ICC
(9263)
VCC Operating Supply Current
VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC
2400
mA
Capacitance[1]
Parameter
Description
CA
Address Input Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
CI
Control Input Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
CO
Input/Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Clock Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
CCLK
9260
9261
9262
9263
9260
9261
9262
9263
9260
9261
9262
9263
9260
9261
9262
9262
Max.
24
14
20
40
24
16
20
40
9
5
8
16
6
3
5
10
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05002 Rev. **
Page 6 of 12
CYM9260
CYM9261B
CYM9262A
CYM9263
AC Test Loads and Waveforms[3]
R1
VCCQ
OUTPUT
ALL INPUT PULSES
OUTPUT
3.3V
RL = 50 Ω
VL =1.5V
(a)
INCLUDING
JIG AND
SCOPE
90%
10%
90%
10%
R2
5 pF
GND
≤ 3 ns
≤ 3 ns
(b)
[2]
Switching Characteristics Over the Operating Range
CYM9260/61/62/63
66 MHz
Parameter
Description
Min.
50 MHz
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
15
20
ns
tCH
Clock HIGH
6
8
ns
tCL
Clock LOW
6
8
ns
tAS
Address Set-Up Before CLK Rise
3.1
3.1
ns
tAH
Address Hold After CLK Rise
0.5
0.5
ns
tCDV
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
3
3
ns
tADS
ADSP, ADSC Set-Up Before CLK Rise
3.1
3.1
ns
tADSH
ADSP, ADSC Hold After CLK Rise
0. 5
0.5
ns
tWES
WH, WL Set-Up Before CLK Rise
3.1
3.1
ns
tWEH
WH, WL Hold After CLK Rise
0.5
0.5
ns
tDS
Data Input Set-Up Before CLK Rise
3.3
3.3
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
ns
tCSS
Chip Select Set-Up
3.1
3.1
ns
tCSH
Chip Select Hold After CLK Rise
0.5
tEOZ
OE HIGH to Output High Z[4]
tEOV
OE LOW to Output Valid
10.3
14
0.5
7
7
ns
7
7
ns
ns
ns
Notes:
2. Resistor values for VCCQ = 3.3V are R1 = 317Ω and R2 = 351 Ω.
3. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads. All measurements are made at room temperature.
4. tEOZ is specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
Document #: 38-05002 Rev. **
Page 7 of 12
CYM9260
CYM9261B
CYM9262A
CYM9263
Switching Waveforms
Single Read[5]
tCH
tCL
tCYC
CLK
tCSS
tCSH
CS
tAS
tAH
ADDRESS
ADSP
or
ADSC
tADS
[6]
tWES
tADSH
tWEH
[7]
WH, WL
tCDV
tDOH
DATA OUT
Single Write Timing (Using ADSC)
tCH
tCL
CLK
tCSS
tCSH
tAS
tAH
tADS
tADSH
CS
ADDRESS
ADSC
tWES
tWEH
WH, WL
tDS
tDH
DATA IN
DATA OUT
tEOZ
OE
Notes:
5. OE is LOW throughout this operation.
6. If ADSP is asserted while CS is HIGH, ADSP will be ignored.
7. ADSP has no effect on ADV, WL, and WH if CS is HIGH.
Document #: 38-05002 Rev. **
Page 8 of 12
CYM9260
CYM9261B
CYM9262A
CYM9263
Switching Waveforms (continued)
Single Write Cycle Using ADSP
tCH
tCL
CLK
tCSS
tCSH
CS
tAS
tAH
tADS
tADSH
ADDRESS
ADSP
tWES
tWEH
[7]
WH, WL
tDS
tDH
DATA IN
DATA OUT
tEOZ
OE
Output (Controlled by OE)
DATA OUT
tEOZ
tEOV
OE
Output Timing (Controlled by CS)
CLK
ADSC
tADS
tADSH
tCSS
tCSH
tADS
tADSH
tCSS
tCSH
CS
tCDV
tCSOZ
DATA OUT
Document #: 38-05002 Rev. **
Page 9 of 12
CYM9260
CYM9261B
CYM9262A
CYM9263
Switching Waveforms (continued)
Output Timing (Controlled by WH/ WL)
CLK
tADS
tADSH
tWES
tWEH
tADS
tADSH
ADSC and
ADSP
WH, WL
tWEOZ
tWEOV
DATA OUT
Ordering Information
Speed
(MHz)
50
66
Package
Name
Package Type
CYM9260-50C
PM43
168-Pin Dual-Readout SIMM (DIMM)
Sync 64K x 72
CYM9261B-50C
PM43
168-Pin Dual-Readout SIMM (SIMM)
Sync 128K x 72
CYM9262A-50C
PM43
168-Pin Dual-Readout SIMM (DIMM)
Sync 256K x 72
CYM9263-50C
PM44
168-Pin Dual-Readout SIMM (DIMM)
Sync 512K x 72
CYM9260-66C
PM43
168-Pin Dual-Readout SIMM (DIMM)
Sync 64K x 72
CYM9261B-66C
PM43
168-Pin Dual-Readout SIMM (SIMM)
Sync 128K x 72
CYM9262A-66C
PM43
168-Pin Dual-Readout SIMM (DIMM)
Sync 256K x 72
CYM9263-66C
PM44
168-Pin Dual-Readout SIMM (DIMM)
Sync 512K x 72
Ordering Code
Document #: 38-05002 Rev. **
Description
Operating
Range
Commercial
Page 10 of 12
CYM9260
CYM9261B
CYM9262A
CYM9263
Package Diagrams
168-Pin Single-Sided DIMM PM43
168-Pin Dual Sided DIMM PM44
Document #: 38-05002 Rev. **
Page 11 of 12
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CYM9260
CYM9261B
CYM9262A
CYM9263
Document Title: CYM9260, CYM9261B, CYM9262A, CYM9263 64K/128K/256K/512K x 72 SRAM Module
Document Number: 38-05002
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
114556
04/02/02
DSG
Document #: 38-05002 Rev. **
Description of Change
Change from Spec number: 38-M-00082 to 38-05002
Page 12 of 12
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