May 2006 DAC082S085 8-Bit Micro Power DUAL Digital-to-Analog Converter with Rail-to-Rail Output General Description Features The DAC082S085 is a full-featured, general purpose DUAL 8-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7V to 5.5V supply and consumes 210 µA at 3V and 320 µA at 5V. The DAC082S085 is packaged in 10-lead LLP and MSOP packages. The 10-lead LLP package makes the DAC082S085 the smallest DUAL DAC in its class. The on-chip output amplifier allows rail-torail output swing and the three wire serial interface operates at clock rates up to 40 MHz over the entire supply voltage range. Competitive devices are limited to 25 MHz clock rates at supply voltages in the 2.7V to 3.6V range. The serial interface is compatible with standard SPI™, QSPI, MICROWIRE and DSP interfaces. n n n n n n n n The reference for the DAC082S085 serves both channels and can vary in voltage between 1V and VA, providing the widest possible output dynamic range. The DAC082S085 has a 16-bit input shift register that controls the outputs to be updated, the mode of operation, the powerdown condition, and the binary input data. Both outputs can be updated simultaneously or individually depending on the setting of the two mode of operation bits. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt with three different termination options. The low power consumption and small packages of the DAC082S085 make it an excellent choice for use in battery operated equipment. The DAC082S085 is one of a family of pin compatible DACs, including the 10-bit DAC102S085 and the 12-bit DAC124S085. The DAC082S085 operates over the extended industrial temperature range of −40˚C to +105˚C. Guaranteed Monotonicity Low Power Operation Rail-to-Rail Voltage Output Power-on Reset to 0V Simultaneous Output Updating Wide power supply range (+2.7V to +5.5V) Industry’s Smallest Package Power Down Modes Key Specifications n n n n n n n Resolution 8 bits ± 0.5 LSB (max) INL DNL +0.18 / −0.13 LSB (max) Settling Time 4.5 µs (max) Zero Code Error +15 mV (max) Full-Scale Error −0.75 %FS (max) Power Consumption — Normal 270 µA (3.6V) / 410 µA (5.5V) max — Pwr Down 20 nA (3.6V) / 30 nA (5.5V) typ Applications n n n n Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage & Current Sources Programmable Attenuators Pin Configuration 20195601 20195602 SPI™ is a trademark of Motorola, Inc. © 2006 National Semiconductor Corporation DS201956 www.national.com DAC082S085 8-Bit Micro Power DUAL Digital-to-Analog Converter with Rail-to-Rail Output PRELIMINARY DAC082S085 Ordering Information Order Numbers Temperature Range Package Top Mark DAC082S085CISD −40˚C ≤ TA ≤ +105˚C LLP X77C DAC082S085CISDX −40˚C ≤ TA ≤ +105˚C LLP Tape-and-Reel X77C DAC082S085CIMM −40˚C ≤ TA ≤ +105˚C MSOP X76C DAC082S085CIMMX −40˚C ≤ TA ≤ +105˚C MSOP Tape-and-Reel X76C DAC082S085EVAL Evaluation Board Block Diagram 20195603 www.national.com 2 DAC082S085 Pin Descriptions LLP MSOP Pin No. Symbol Type Description 1 VA Supply 2 VOUTA Analog Output Channel A Analog Output Voltage. Power supply input. Must be decoupled to GND. 3 VOUTB Analog Output Channel B Analog Output Voltage. 4 NC Not Connected 5 NC 6 GND Ground Not Connected 7 VREFIN Analog Input Unbuffered reference voltage shared by all channels. Must be decoupled to GND. 8 DIN Digital Input Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC. Ground reference for all on-chip circuitry. 9 SYNC Digital Input Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 10 SCLK Digital Input Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin. 11 PAD (LLP only) Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package self-alignment during reflow. Ground 3 www.national.com DAC082S085 Absolute Maximum Ratings Operating Ratings (Notes 1, 2) (Notes 1, 2) Operating Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, VA 6.5V Supply Voltage, VA Voltage on any Input Pin −0.3V to 6.5V Input Current at Any Pin (Note 3) +1.0V to VA Any Digital Input Voltage (Note 7) 0.0V to 5.5V 0 to 1500 pF SCLK Frequency Up to 40 MHz 20 mA Power Consumption at TA = 25˚C See (Note 4) ESD Susceptibility (Note 5) Human Body Model Machine Model 2500V 250V Soldering Temperature, Infrared, 10 Seconds (Note 6) 235˚C Storage Temperature +2.7V to 5.5V Reference Voltage, VREFIN Output Load 10 mA Package Input Current (Note 3) −40˚C ≤ TA ≤ +105˚C Package Thermal Resistances Package θJA 10-Lead MSOP 240˚C/W 10-Lead LLP 250˚C/W −65˚C to +150˚C Electrical Characteristics Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 3 to 252. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25˚C, unless otherwise specified. Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) STATIC PERFORMANCE Resolution 8 Bits (min) Monotonicity 8 Bits (min) ± 0.14 ± 0.5 LSB (max) INL Integral Non-Linearity Over Decimal codes 3 to 252 DNL Differential Non-Linearity VA = 2.7V to 5.5V ZE Zero Code Error FSE GE ZCED TC GE +0.04 +0.18 LSB (max) −0.02 −0.13 LSB (min) IOUT = 0 +4 +15 mV (max) Full-Scale Error IOUT = 0 −0.1 −0.75 %FSR (max) Gain Error All ones Loaded to DAC register −0.2 −1.0 %FSR Zero Code Error Drift Gain Error Tempco −20 µV/˚C VA = 3V −0.7 ppm/˚C VA = 5V −1.0 ppm/˚C OUTPUT CHARACTERISTICS Output Voltage Range IOUT ZCO FSO www.national.com (Note 10) Output Current (Note 10) Zero Code Output Full Scale Output 0 VREFIN V (min) V (max) ±1 µA (max) VA = 3V, IOUT = 200 µA 1.3 mV VA = 3V, IOUT = 1 mA 6.0 mV VA = 5V, IOUT = 200 µA 7.0 mV VA = 5V, IOUT = 1 mA 10.0 mV VA = 3V, IOUT = 200 µA 2.984 V VA = 3V, IOUT = 1 mA 2.934 V VA = 5V, IOUT = 200 µA 4.989 V VA = 5V, IOUT = 1 mA 4.958 V 4 (Continued) Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 3 to 252. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25˚C, unless otherwise specified. Symbol IOS Parameter Output Short Circuit Current IO Continuous Output Current (Note 10) CL Maximum Load Capacitance ZOUT Typical (Note 9) Conditions Limits (Note 9) Units (Limits) VA = 3V, VOUT = 0V, Input Code = FFh -56 mA VA = 5V, VOUT = 0V, Input Code = FFh -69 mA VA = 3V, VOUT = 5V, Input Code = 00h 52 mA VA = 5V, VOUT = 5V, Input Code = 00h 75 mA Avaliable on each DAC output 11 mA (max) RL = ∞ 1500 pF RL = 2kΩ 1500 pF 7.5 Ω DC Output Impedance INPUT CHARACTERISTICS Input Range Minimum VREFIN 0.2 Input Range Maximum Input Impedance IIN Input Current (Note 10) VIL Input Low Voltage (Note 10) VIH Input High Voltage (Note 10) CIN Input Capacitance (Note 10) 1.0 V (min) VA V (max) ±1 µA (max) 60 kΩ VA = 3V 0.9 0.6 V (max) VA = 5V 1.5 0.8 V (max) VA = 3V 1.4 2.1 V (min) VA = 5V 2.1 2.4 V (min) 3 pF (max) POWER REQUIREMENTS VA Supply Voltage Minimum 2.7 V (min) Supply Voltage Maximum 5.5 V (max) fSCLK = 30 MHz IN Normal Supply Current (output unloaded) fSCLK = 0 IPD Power Down Supply Current (output unloaded, SYNC = 0V after PD mode loaded) All PD Modes, fSCLK = 30 MHz All PD Modes, fSCLK = 0 (Note 10) 5 VA = 2.7V to 3.6V 210 270 µA (max) VA = 4.5V to 5.5V 320 410 µA (max) VA = 2.7V to 3.6V 190 µA (max) VA = 4.5V to 5.5V 290 µA (max) VA = 2.7V to 3.6V 0.02 µA (max) VA = 4.5V to 5.5V 0.03 µA (max) VA = 2.7V to 3.6V 0.015 1.0 µA (max) VA = 4.5V to 5.5V 0.025 1.0 µA (max) www.national.com DAC082S085 Electrical Characteristics DAC082S085 A.C. and Timing Characteristics Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, RL = 2kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 3 to 252. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25˚C, unless otherwise specified. Symbol Parameter fSCLK SCLK Frequency ts Output Voltage Settling Time (Note 10) SR Output Slew Rate Glitch Impulse Conductions Typical Limits Units (Limits) 30 MHz (max) 4.5 µs (max) 40h to C0h code change 3 1 V/µs Code change from 80h to 7Fh 12 nV-sec 0.5 nV-sec Digital Feedthrough Digital Crosstalk 1 nV-sec DAC-to-DAC Crosstalk 3 nV-sec 200 kHz Multiplying Bandwidth VREFIN = 2.5V ± 0.1Vpp Total Harmonic Distortion VREFIN = 2.5V ± 0.1Vpp input frequency = 10kHz dB VA = 3V 0.8 µsec VA = 5V 0.5 µsec tWU Wake-Up Time 1/fSCLK SCLK Cycle Time 25 33 ns (min) tCH SCLK High time 7 10 ns (min) tCL SCLK Low Time 7 10 ns (min) tSS SYNC Set-up Time prior to SCLK Falling Edge 4 10 ns (min) tDS Data Set-Up Time prior to SCLK Falling Edge 1.5 3.5 ns (min) tDH Data Hold Time after SCLK Falling Edge 1.5 3.5 ns (min) tCFSR SCLK fall prior to rise of SYNC 0 3 ns (min) tSYNC SYNC High Time 6 10 ns (min) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified Note 3: When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed). Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms. Note 6: See the section entitled "Surface Mount" found in any post 1986 National Semiconductor Linear Data Book for methods of soldering surface mount devices. Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of VA, will not cause errors in the conversion result. For example, if VA is 3V, the digital input pins can be driven with a 5V logic device. 20195604 Note 8: To guarantee accuracy, it is required that VA and VREFIN be well bypassed. Note 9: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 10: This parameter is guaranteed by design and/or characterization and is not tested in production. www.national.com 6 DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB, which is VREF / 256 = VA / 256. DAC-to-DAC CROSSTALK is the glitch impulse transferred to a DAC output in response to a full-scale change in the output of another DAC. MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of VA. DIGITAL CROSSTALK is the glitch impulse transferred to a DAC output at mid-scale in response to a full-scale change in the input register of another DAC. DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus. MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3dB below the input sine wave on VREFIN with a full-scale code loaded into the DAC. POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output currents is the power consumed by the device without a load. FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded into the DAC and the value of VA x 255 / 256. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and FullScale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error. GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register changes. It is specified as the area of the glitch in nanovolt-seconds. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point method is used. INL for this product is specified over a limited range, per the Electrical Tables. LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is LSB = VREF / 2n where VREF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 8 for the DAC082S085. SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is updated. TOTAL HARMONIC DISTORTION (THD) is the measure of the harmonics present at the output of the DACs with an ideal sine wave applied to VREFIN. THD is measured in dB. WAKE-UP TIME is the time for the output to exit powerdown mode. This is the time from the falling edge of the 16th SCLK pulse to when the output voltage deviates from the power-down voltage of 0V. ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been entered. 7 www.national.com DAC082S085 MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output stability maintained. MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the input code increases. Specification Definitions DAC082S085 Transfer Characteristic 20195605 FIGURE 1. Input / Output Transfer Characteristic Timing Diagrams 20195606 FIGURE 2. Serial Timing Diagram www.national.com 8 fSCLK = 30 MHz, TA = 25C, Input Code Range 3 to 252, un- INL at VA = 3.0V INL at VA = 5.0V 20195652 20195653 DNL at VA = 3.0V DNL at VA = 5.0V 20195654 20195655 INL/DNL vs VREFIN at VA = 3.0V INL/DNL vs VREFIN at VA = 5.0V 20195656 20195657 9 www.national.com DAC082S085 Typical Performance Characteristics less otherwise stated DAC082S085 Typical Performance Characteristics fSCLK = 30 MHz, TA = 25C, Input Code Range 3 to 252, unless otherwise stated (Continued) INL/DNL vs fSCLK at VA = 2.7V INL/DNL vs VA 20195650 20195622 INL/DNL vs Clock Duty Cycle at VA = 3.0V INL/DNL vs Clock Duty Cycle at VA = 5.0V 20195624 20195625 INL/DNL vs Temperature at VA = 3.0V INL/DNL vs Temperature at VA = 5.0V 20195626 www.national.com 20195627 10 Zero Code Error vs. VA Zero Code Error vs. VREFIN 20195630 20195631 Zero Code Error vs. fSCLK Zero Code Error vs. Clock Duty Cycle 20195634 20195635 Zero Code Error vs. Temperature Full-Scale Error vs. VA 20195636 20195637 11 www.national.com DAC082S085 Typical Performance Characteristics fSCLK = 30 MHz, TA = 25C, Input Code Range 3 to 252, unless otherwise stated (Continued) DAC082S085 Typical Performance Characteristics fSCLK = 30 MHz, TA = 25C, Input Code Range 3 to 252, unless otherwise stated (Continued) Full-Scale Error vs. VREFIN Full-Scale Error vs. fSCLK 20195632 20195633 Full-Scale Error vs. Clock Duty Cycle Full-Scale Error vs. Temperature 20195638 20195639 Supply Current vs. VA Supply Current vs. Temperature 20195644 www.national.com 20195645 12 5V Glitch Response Power-On Reset 20195646 20195647 3V Wake-Up Time 5V Wake-Up Time 20195648 20195649 13 www.national.com DAC082S085 Typical Performance Characteristics fSCLK = 30 MHz, TA = 25C, Input Code Range 3 to 252, unless otherwise stated (Continued) DAC082S085 mended that VREFIN be driven by a voltage source with low output impedance. The reference voltage range is 1.0V to VA, providing the widest possible output dynamic range. 1.0 Functional Description 1.1 DAC SECTION The DAC082S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor strings that are followed by an output buffer. The reference voltage is externally applied at VREFIN and is shared by both DACs. 1.4 SERIAL INTERFACE The three-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs and operates at clock rates up to 40 MHz. See the Timing Diagram for information on a write sequence. A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked into the 16-bit serial input register on the falling edges of SCLK. To avoid misclocking data into the shift register, it is critical that SYNC not be brought low on a falling edge of SCLK (see Serial Timing Diagram, Figure 2). On the 16th falling clock edge, the last data bit is clocked in and the programmed function (a change in the DAC channel address, mode of operation and/or register contents) is executed. At this point the SYNC line may be kept low or brought high. Any data and clock pusles after the 16th falling clock edge will be ignored. In either case, SYNC must be brought high for the minimum specified time before the next write sequence is initiated with a falling edge of SYNC. Since the SYNC and DIN buffers draw more current when they are high, they should be idled low between write sequences to minimize power consumption. For simplicity, a single resistor string is shown in Figure 3. This string consists of 256 equal valued resistors with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight binary with an ideal output voltage of: VOUTA,B,C,D = VREFIN x (D / 256) where D is the decimal equivalent of the binary code that is loaded into the DAC register and can take on any value between 0 and 255. This configuration guarantees that the DAC is monotonic. 1.5 INPUT SHIFT REGISTER The input shift register, Figure 4, has sixteen bits. The first bit must be set to "0" and the second bit is an address bit. The address bit determines whether the register data is for DAC A or DAC B. This bit is followed by two bits that determine the mode of operation (writing to a DAC register without updating the outputs of both DACs, writing to a DAC register and updating the outputs of both DACs, writing to the register of both DACs and updating their outputs, or powering down both outputs). The final twelve bits of the shift register are the data bits. The data format is straight binary (MSB first, LSB last), with all 0’s corresponding to an output of 0V and all 1’s corresponding to a full-scale output of VREFIN - 1 LSB. The contents of the serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Timing Diagram, Figure 2. 20195607 FIGURE 3. DAC Resistor String 1.2 OUTPUT AMPLIFIERS The output amplifiers are rail-to-rail, providing an output voltage range of 0V to VA when the reference is VA. All amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and VA, in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the reference is less than VA, there is only a loss in linearity in the lowest codes. The output capabilities of the amplifier are described in the Electrical Tables. The output amplifiers are capable of driving a load of 2 kΩ in parallel with 1500 pF to ground or VA. The zero-code and full-scale outputs for given load currents are available in the Electrical Characterisics Table. 20195608 FIGURE 4. Input Register Contents Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the data transfer to the shift register is aborted and the write sequence is invalid. The DAC register is not updated and there is no change in the mode of operation or in the DAC output voltages. 1.3 RERENCE VOLTAGE The DAC082S085 has a single external reference that is shared by both channels. The reference pin, VREFIN, is not buffered and has an input impedance of 60 kΩ. It is recom- www.national.com 14 a 0.1µF capacitor and the VOUT pin with a 2.2µF capacitor will improve stability and reduce output noise. The LM4130 comes in a space-saving 5-pin SOT23. (Continued) 1.6 POWER-ON RESET The power-on reset circuit controls the output voltages of both DACs during power-up. Upon application of power, the DAC registers are filled with zeros and the output voltages are 0V. The outputs remain at 0V until a valid write sequence is made to the DAC. 1.7 POWER-DOWN MODES The DAC082S085 has four power-down modes, two of which are identical. In power-down, the supply current drops to 20 µA at 3V and 30 µA at 5V. The DAC082S085 is set in power-down mode by setting OP1 and OP0 to 11. Since this mode powers down both DACs, the first two bits of the shift register are used to select different output terminations for the DAC outputs. Setting PD and A0 to 00 or 11 causes the outputs to be tri-stated or set to a high impedance state. While setting PD and A0 to 01 or 10 causes the outputs to be terminated by 2.5 kΩ or 100 kΩ to ground respectively (see Table 1). 20195613 FIGURE 5. The LM4130 as a power supply 2.1.2 LM4050 Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a reference for the DAC082S085. It is available in 4.096V and 5V versions and comes in a space-saving 3-pin SOT23. TABLE 1. Power-Down Modes PD A0 OP1 OP0 0 0 1 1 Operating Mode High-Z outputs 0 1 1 1 2.5 kΩ to GND 1 0 1 1 100 kΩ to GND 1 1 1 1 High-Z outputs The bias generator, output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the powerdown modes. However, the contents of the DAC registers are unaffected when in power-down. Each DAC register maintains its value prior to the DAC082S085 being powered down unless it is changed during the write sequence which instructed it to recover from power down. Minimum power consumption is achieved in the power-down mode with SYNC and DIN idled low and SCLK disabled. The time to exit power-down (Wake-Up Time) is typically 0.8 µsec at 3V and 0.5 µsec at 5V. 2.0 Applications Information 20195614 FIGURE 6. The LM4050 as a power supply 2.1 USING REFERENCES AS POWER SUPPLIES While the simplicity of the DAC082S085 implies ease of use, it is important to recognize that the path from the reference input (VREFIN) to the VOUTs will have essentially zero Power Supply Rejection Ratio (PSRR). Therefore, it is necessary to provide a noise-free supply voltage to VREFIN. In order to utilize the full dynamic range of the DAC082S085, the supply pin (VA) and VREFIN can be connected together and share the same supply voltage. Since the DAC082S085 consumes very little power, a reference source may be used as the reference input and/or the supply voltage. The advantages of using a reference source over a voltage regulator are accuracy and stability. Some low noise regulators can also be used. Listed below are a few reference and power supply options for the DAC082S085. The minimum resistor value in the circuit of Figure 6 must be chosen such that the maximum current through the LM4050 does not exceed its 15 mA rating. The conditions for maximum current include the input voltage at its maximum, the LM4050 voltage at its minimum, and the DAC082S085 drawing zero current. The maximum resistor value must allow the LM4050 to draw more than its minimum current for regulation plus the maximum DAC082S085 current in full operation. The conditions for minimum current include the input voltage at its minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the DAC082S085 draws its maximum current. These conditions can be summarized as R(min) = ( VIN(max) − VZ(min) ) /IZ(max) and R(max) = ( VIN(min) − VZ(max) ) / ( (IDAC(max) + IZ(min) ) where VZ(min) and VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over temperature, IZ(max) is the maximum allowable current through the 2.1.1 LM4130 The LM4130, with its 0.05% accuracy over temperature, is a good choice as a reference source for the DAC082S085. The 4.096V version is useful if a 0 to 4.095V output range is desirable or acceptable. Bypassing the LM4130 VIN pin with 15 www.national.com DAC082S085 1.0 Functional Description DAC082S085 2.0 Applications Information tors are attractive due to their small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic capacitors are typically not a good choice due to their large size and have ESR values that may be too high at low temperatures. (Continued) LM4050, IZ(min) is the minimum current required by the LM4050 for proper regulation, and IDAC(max) is the maximum DAC082S085 supply current. 2.2 BIPOLAR OPERATION 2.1.3 LP3985 The LP3985 is a low noise, ultra low dropout voltage regulator with a 3% accuracy over temperature. It is a good choice for applications that do not require a precision reference for the DAC082S085. It comes in 3.0V, 3.3V and 5V versions, among others, and sports a low 30 µV noise specification at low frequencies. Since low frequency noise is relatively difficult to filter, this specification could be important for some applications. The LP3985 comes in a space-saving 5-pin SOT23 and 5-bump micro SMD packages. The DAC082S085 is designed for single supply operation and thus has a unipolar output. However, a bipolar output may be obtained with the circuit in Figure 9. This circuit will provide an output voltage range of ± 5 Volts. A rail-to-rail amplifier should be used if the amplifier supplies are limited to ± 5V. 20195617 FIGURE 9. Bipolar Operation The output voltage of this circuit for any code is found to be VO = (VA x (D / 256) x ((R1 + R2) / R1) - VA x R2 / R1) where D is the input code in decimal form. With VA = 5V and R1 = R2, VO = (10 x D / 256) - 5V A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2. 20195615 FIGURE 7. Using the LP3985 regulator An input capacitance of 1.0µF without any ESR requirement is required at the LP3985 input, while a 1.0µF ceramic capacitor with an ESR requirement of 5mΩ to 500mΩ is required at the output. Careful interpretation and understanding of the capacitor specification is required to ensure correct device operation. TABLE 2. Some Rail-to-Rail Amplifiers 2.1.4 LP2980 The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon grade. It is available in 3.0V, 3.3V and 5V versions, among others. 20195616 FIGURE 8. Using the LP2980 regulator Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor must be at least 1.0µF over temperature, but values of 2.2µF or more will provide even better performance. The ESR of this capacitor should be within the range specified in the LP2980 data sheet. Surface-mount solid tantalum capacitors offer a good combination of small size and ESR. Ceramic capaciwww.national.com 16 AMP PKGS LMC7111 DIP-8 SOT23-5 Typ VOS Typ ISUPPLY 0.9 mV 25 µA LM7301 SO-8 SOT23-5 0.03 mV 620 µA LM8261 SOT23-5 0.7 mV 1 mA SCLK. PC7 is taken low to transmit data to the DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the second byte of data to the DAC, after which PC7 should be raised to end the write sequence. (Continued) 2.3 DSP/MICROPROCESSOR INTERFACING Interfacing the DAC082S085 to microprocessors and DSPs is quite simple. The following guidelines are offered to hasten the design process. 2.3.1 ADSP-2101/ADSP2103 Interfacing Figure 10 shows a serial interface between the DAC082S085 and the ADSP-2101/ADSP2103. The DSP should be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control register and should be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length. Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled. 20195611 FIGURE 12. 68HC11 Interface 2.3.4 Microwire Interface Figure 13 shows an interface between a Microwire compatible device and the DAC082S085. Data is clocked out on the rising edges of the SK signal. As a result, the SK of the Microwire device needs to be inverted before driving the SCLK of the DAC082S085. 20195609 FIGURE 10. ADSP-2101/2103 Interface 2.3.2 80C51/80L51 Interface A serial interface between the DAC082S085 and the 80C51/ 80L51 microcontroller is shown in Figure 11. The SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line P3.3. This line is taken low when data is transmitted to the DAC082S085. Since the 80C51/80L51 transmits 8-bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that the 80C51/80L51 transmits data with the LSB first while the DAC082S085 requires data with the MSB first. 20195612 FIGURE 13. Microwire Interface 2.4 LAYOUT, GROUNDING, AND BYPASSING For best accuracy and minimum noise, the printed circuit board containing the DAC082S085 should have separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of these planes should be located in the same board layer. There should be a single ground plane. A single ground plane is preferred if digital return current does not flow through the analog ground area. Frequently a single ground plane design will utilize a "fencing" technique to prevent the mixing of analog and digital ground current. Separate ground planes should only be utilized when the fencing technique is inadequate. The separate ground planes must be connected in one place, preferably near the DAC082S085. Special care is required to guarantee that digital signals with fast edge rates do not pass over split ground planes. They must always have a continuous return path below their traces. The DAC082S085 power supply should be bypassed with a 10µF and a 0.1µF capacitor as close as possible to the device with the 0.1µF right at the device supply pin. The 10µF capacitor should be a tantalum type and the 0.1µF capacitor should be a low ESL, low ESR type. The power supply for the DAC082S085 should only be used for analog circuits. Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the board. The clock and data lines should have controlled impedances. 20195610 FIGURE 11. 80C51/80L51 Interface 2.3.3 68HC11 Interface A serial interface between the DAC082S085 and the 68HC11 microcontroller is shown in Figure 12. The SYNC line of the DAC082S085 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51. The 68HC11 should be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration causes data on the MOSI output to be valid on the falling edge of 17 www.national.com DAC082S085 2.0 Applications Information DAC082S085 Physical Dimensions inches (millimeters) unless otherwise noted 10-Lead MSOP Order Numbers DAC082S085CIMM NS Package Number MUB10A 10-Lead LLP Order Numbers DAC082S085CISD NS Package Number SDA10A www.national.com 18 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: [email protected] National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: [email protected] Tel: 81-3-5639-7560 DAC082S085 8-Bit Micro Power DUAL Digital-to-Analog Converter with Rail-to-Rail Output Notes