Vishay DG418DY-T1 Precision cmos analog switch Datasheet

DG417, DG418, DG419
Vishay Siliconix
Precision CMOS Analog Switches
DESCRIPTION
FEATURES
The DG417, DG418, DG419 monolithic CMOS analog
switches were designed to provide high performance
switching of analog signals. Combining low power, low
leakages, high speed, low on-resistance and small physical
size, the DG417 series is ideally suited for portable and
battery powered industrial and military applications requiring
high performance and efficient use of board space.
•
•
•
•
•
•
To achieve high-voltage ratings and superior switching
performance, the DG417 series is built on Vishay Siliconix’s
high voltage silicon gate (HVSG) process. Break-beforemake is guaranteed for the DG419, which is an SPDT
configuration. An epitaxial layer prevents latchup.
Each switch conducts equally well in both directions when
on, and blocks up to the power supply level when off.
The DG417 and DG418 respond to opposite control logic
levels as shown in the Truth Table.
± 15 V analog signal range
On-resistance - RDS(on): 20 
Fast switching action - tON: 100 ns
Ultra low power requirements - PD: 35 nW
TTL and CMOS compatible
MiniDIP and SOIC packaging
• 44 V supply max. rating
• 44 V supply max. rating
• Compliant to RoHS directive 2002/95/EC
BENEFITS
•
•
•
•
•
•
Wide dynamic range
Low signal errors and distortion
Break-before-make switching action
Simple interfacing
Reduced board space
Improved reliability
APPLICATIONS
•
•
•
•
•
•
•
Precision test equipment
Precision instrumentation
Battery powered systems
Sample-and-hold circuits
Military radios
Guidance and control systems
Hard disk drives
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG417
Dual-In-Line and SOIC
TRUTH TABLE
S
1
8
D
NC
2
7
V-
GND
3
6
IN
V+
4
5
VL
Logic
0
1
DG417
ON
OFF
DG418
OFF
ON
Logic "0" 0.8 V
Logic "1" 2.4 V
Top View
DG419
Dual-In-Line and SOIC
D
8
1
TRUTH TABLE DG419
S2
S1
2
7
V-
GND
3
6
IN
V+
4
5
VL
Logic
SW1
SW2
0
ON
OFF
1
OFF
ON
Logic "0" 0.8 V
Logic "1" 2.4 V
Top View
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
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1
DG417, DG418, DG419
Vishay Siliconix
ORDERING INFORMATION
Temp. Range
DG417, DG418
Package
Part Number
8-Pin Plastic MiniDIP
DG417DJ
DG417DJ-E3
DG418DJ
DG418DJ-E3
DG417DY
DG417DY-E3
DG417DY-T1
DG417DY-T1-E3
- 40 °C to 85 °C
8-Pin Narrow SOIC
DG418DY
DG418DY-E3
DG418DY-T1
DG418DY-T1-E3
DG419
8-Pin Plastic MiniDIP
DG419DJ
DG419DJ-E3
8-Pin Narrow SOIC
DG419DY
DG419DY-E3
DG419DY-T1
DG419DY-T1-E3
- 40 °C to 85 °C
ABSOLUTE MAXIMUM RATINGS
Parameter (Voltages referenced to V-)
V+
Limit
44
GND
VL
Unit
25
(GND - 0.3) to (V+) + 0.3
(V-) - 2 to (V+) + 2
or 30 mA, whichever occurs first
30
a
Digital Inputs , VS, VD
Current , (Any Terminal) Continuous
Current, S or D (Pulsed at 1 ms, 10 % Duty Cycle)
Storage Temperature
100
(AK Suffix)
- 65 to 150
(DJ, DY Suffix)
- 65 to 125
8-Pin Plastic MiniDIPc
b
Power Dissipation (Package)
8-Pin Narrow SOIC
e
d
V
mA
°C
400
400
mW
600
8-Pin CerDIP
Notes:
a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC board.
c. Derate 6 mW/°C above 75 °C.
d. Derate 6.5 mW/°C above 75 °C.
e. Derate 12 mW/°C above 75 °C.
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Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
DG417, DG418, DG419
Vishay Siliconix
SCHEMATIC DIAGRAM Typical Channel
V+
S
VL
VLevel
Shift/
Drive
VIN
V+
GND
D
V-
Figure 1.
SPECIFICATIONSa
A Suffix
D Suffix
- 55 °C to 125 °C - 40 °C to 85 °C
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V- = - 15 V
Parameter
Analog Switch
Symbol
Analog Signal Rangee
VANALOG
Drain-Source
On-Resistance
RDS(on)
VL = 5 V, VIN = 2.4 V, 0.8 Vf
IS = - 10 mA, VD = ± 12.5 V
V+ = 13.5 V, V- = - 13.5 V
V+ = 16.5, V- = - 16.5 V
VD = ± 15.5 V
ID(off)
VS = ± 15.5 V
DG417
DG418
DG419
Channel Off Leakage
Current
ID(on)
Typ.c
Full
IS(off)
Switch Off Leakage
Current
Temp.b
V+ = 16.5 V, V- = - 16.5 V
VS = VD = ± 15.5 V
DG417
DG418
DG419
Room
Full
20
Room
Full
Room
Full
Room
Full
Room
Full
Room
Full
- 0.1
- 0.1
- 0.1
- 0.4
- 0.4
Min.d
Max.d
Min.d
Max.d
Unit
- 15
15
- 15
15
V
35
45

nA
35
45
- 0.25
- 20
- 0.25
- 20
- 0.75
- 60
- 0.4
- 40
- 0.75
- 60
0.25
20
0.25
20
0.75
60
0.4
40
0.75
60
- 0.25
-5
- 0.25
-5
- 0.75
- 12
- 0.4
- 10
- 0.75
- 12
0.25
5
0.25
5
0.75
12
0.4
10
0.75
12
Digital Control
Input Current VIN Low
IIL
Full
0.005
- 0.5
0.5
- 0.5
0.5
Input Current VIN High
IIH
Full
0.005
- 0.5
0.5
- 0.5
0.5
DG417
DG418
Room
Full
100
175
250
175
250
DG417
DG418
Room
Full
60
145
210
145
210
DG419
Room
Full
175
250
175
250
DG419
Room
13
Room
60
µA
Dynamic Characteristics
Turn-On Time
tON
Turn-Off Time
tOFF
Transition Time
tTRANS
Break-Before-Make
Time Delay (DG403)
tD
Charge Injection
Q
Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
RL = 300 , CL = 35 pF
VS = ± 10 V
See Switching Time
Test Circuit
RL = 300 , CL = 35 pF
VS1 = ± 10 V, VS2 = ± 10 V
RL = 300 , CL = 35 pF
VS1 = VS2 = ± 10 V
CL = 10 nF, Vgen = 0 V, Rgen = 0 
5
ns
5
pC
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DG417, DG418, DG419
Vishay Siliconix
SPECIFICATIONSa
A Suffix
D Suffix
- 55 °C to 125 °C - 40 °C to 85 °C
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V- = - 15 V
Parameter
Symbol
Dynamic Characteristics
Source Off
CS(off)
Capacitance
Drain Off Capacitance
CD(off)
Channel On
Capacitance
CD(on)
VL = 5 V, VIN = 2.4 V, 0.8 Vf
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
DG417
DG418
DG417
DG418
DG419
Temp.b
Typ.c
Room
8
Room
8
Room
30
Room
35
Room
Full
Room
Full
Room
Full
Room
Full
0.001
Min.d
Max.d
Min.d
Max.d
Unit
pF
Power Supplies
Positive Supply Current
I+
Negative Supply
Current
I-
Logic Supply Current
IL
V+ = 16.5 V, V- = - 16.5 V
VIN = 0 or 5 V
IGND
Ground Current
- 0.001
1
5
-1
-5
0.001
- 0.0001
1
5
-1
-5
1
5
1
5
-1
-5
µA
-1
-5
SPECIFICATIONSa for Unipolar Supplies
A Suffix
- 55 °C to 125 °C
Test Conditions
Unless Otherwise Specified
V+ = 12 V, V- = 0 V
Parameter
Analog Switch
Symbol
Analog Signal Rangee
VANALOG
Drain-Source
On-Resistance
RDS(on)
VL = 5 V, VIN = 2.4 V, 0.8 Vf
Temp.b
Typ.c
Full
IS = - 10 mA, VD = 3.8 V
V+ = 10.8 V
Room
40
Room
110
Room
40
Room
60
Room
5
Room
0.001
Room
- 0.001
Room
0.001
Room
- 0.001
D Suffix
- 40 °C to 85 °C
Min.d
Max.d
Min.d
Max.d
Unit
0
12
0
12
V

Dynamic Characteristics
Turn-On Time
tON
Turn-Off Time
tOFF
Break-Before-Make
Time Delay
tD
Charge Injection
Q
Power Supplies
Positive Supply
Current
Negative Supply
Current
Logic Supply
Current
Ground
Current
RL = 300 , CL = 35 pF, VS = 8 V
See Switching Time Test Circuit
DG419 Only
RL = 300 , CL = 35 pF
CL = 10 nF, Vgen = 0 V, Rgen = 0 
I+
IIL
IGND
V+ = 13.2 V, VL = 5.25 V
VIN = 0 or 5 V
ns
pC
µA
Notes:
a. Refer to Process Option Flowchart.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
DG417, DG418, DG419
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
40
50
ID = - 10 mA
±5V
TA = 125 °C
40
30
R DS(on) ()
R DS(on) ()
±8V
30
± 10 V
± 12 V
± 15 V
20
± 20 V
25 °C
20
- 55 °C
10
10
0
0
- 20
- 15
- 10
-5
0
5
15
10
- 15
20
- 10
-5
0
5
10
VD - Drain Voltage (V)
RDS(on) vs. VD and Supply Voltage
RDS(on) vs. Temperature
30
200
V+ = 15 V
V- = - 15 V
VL = 5 V
20
V+ = 16.5 V
V- = - 16.5 V
VL = 5 V
VIN = 0 V
150
CL = 10 nF
1 nF
DG417/418: I D(off), IS(off)
DG419: I S(off)
10
500 pF
Q (pC)
100
I (pA)
15
VD - Drain Voltage (V)
0
100 pF
50
DG417/418: I D(on)
DG419: I D(off), ID(on)
- 10
0
- 20
- 30
- 50
- 15
- 10
-5
0
5
15
10
- 15
- 10
-5
0
5
10
VD or V S - Drain or Source Voltage (V)
VS - Source Voltage (V)
Leakage Currents vs. Analog Voltage
Drain Charge Injection
15
3.5
3.0
V TH (V)
2.5
VL = 7 V
2.0
1.5
VL = 5 V
1.0
0.5
0
5
10
15
20
25
30
35
40
(V+)
Input Switching Threshold vs. Supply Voltages
Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
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DG417, DG418, DG419
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
140
120
V+ = 15 V, V- = - 15 V
VL = 5 V, V IN = 3 V Pulse
100
tON
120
DG417/418/419
Source 2
DG419
Source 1
80
tOFF
(dB)
t ON , t OFF (ns)
100
80
60
60
40
40
20
V+ = 15 V
V- = - 15 V
VL = 5 V
20
0
0
- 55 - 40 - 20
0
20
40
60
80
100
1k
100
120
100 k
10 k
10M
1M
100M
f - Frequency (Hz)
Temperature (°C)
Crosstalk and Off Isolation vs. Frequency
Switching Time vs. Temperature
130
80
120
110
60
100
tON
V- = 0 V
VL = 5 V
VIN = 3 V
t ON , t OFF (ns)
t ON, t OFF (ns)
70
tON
90
V- = 0 V
VL = 5 V
VIN = 3 V
80
70
60
50
50
tOFF
tOFF
40
40
30
± 10
± 11
± 12
± 13
± 14
± 15
± 16
10
11
12
13
14
15
Supply Voltage (V)
V+ Supply Voltage (V)
Switching Time vs. Supply Voltages
Switching Time vs. V+
10 mA
16
1 µA
V+ = 15 V, V- = - 15 V
VL = 5 V, V IN = 5 V, 50 % D-Cycle
100 nA
V+ = 16.5 V, V- = - 16.5 V
VL = 5 V, V IN = 0 V
1 mA
I SUPPLY
I SUPPLY
10 nA
I+, I-
100 µA
I+, I10 µA
1 nA
100 pA
IL
IGND
10 pA
1 µA
1 pA
100 nA
100
1k
10 k
100 k
1M
10M
f - Frequency (Hz)
Power Supply Currents vs. Switching Frequency
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0.1 pA
- 55 - 40
- 20
0
20
40
60
80
100
120
Temperature (°C)
Supply Current vs. Temperature
Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
DG417, DG418, DG419
Vishay Siliconix
TEST CIRCUITS
VO is the steady state output with the switch on.
+5V
+ 15 V
3V
Logic
Input
VL
V+
S
± 10 V
tr < 20 ns
tf < 20 ns
50 %
0V
D
VO
tOFF
IN
GND
RL
300 
V-
CL
35 pF
- 15 V
CL (includes fixture and stray capacitance)
Switch
Input
VS
Switch
Output
0V
Note:
RL
VO = V S
VO
90 %
tON
Logic input waveform is inverted for switches that have the
opposite logic sense.
RL + rDS(on)
Figure 2. Switching Time (DG417, DG418)
+5V
+ 15 V
Logic
Input
VL
VS1
VS2
V+
S1
3V
tr < 20 ns
tf < 20 ns
0V
D
VO
S2
RL
300 
IN
Switch
Output
V-
GND
VS1 = VS2
VO
CL
35 pF
90 %
0V
tD
tD
CL (includes fixture and stray capacitance)
- 15 V
Figure 3. Break-Before-Make (DG419)
+5V
VL
VS1
VS2
+ 15 V
V+
S1
D
VO
Logic
Input
3V
0V
S2
RL
300 
IN
GND
tr < 20 ns
tf < 20 ns
50 %
tTRANS
CL
35 pF
tTRANS
VS1
V01
V-
- 15 V
90 %
Switch
Output
VS2
V02
10 %
CL (includes fixture and stray capacitance)
VO = VS
RL
RL + rDS(on)
Figure 4. Transition Time (DG419)
Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
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DG417, DG418, DG419
Vishay Siliconix
TEST CIRCUITS
Rg
+5V
- 15 V
VL
V+
S
VO
VO
D
VO
IN
INX
OFF
CL
10 nF
3V
ON
V-
GND
OFF
Q = VO x CL
- 15 V
Figure 5. Charge Injection
+ 15 V
+5V
C
+5V
C
+ 15 V
C
VL
S1
VS
VL
D
Rg = 50 
V+
S
VS
VO
D
Rg = 50 
50 
VO
C
V+
S2
RL
IN
0 V, 2.4 V
RL
GND
IN
V-
C
0.8 V
GND
C
V-
- 15 V
- 15 V
XTA LK Isolation = 20 log
C = RF bypass
Off Isolation = 20 log
VS
VO
VS
VO
Figure 7. Off Isolation
Figure 6. Crosstalk (DG419)
+5V
+ 15 V
C
C
VL
V+
S
VS
D
VO
Rg = 50 
RL
IN
0 V, 2.4 V
GND
V-
C
- 15 V
Figure 8. Insertion Loss
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Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
DG417, DG418, DG419
Vishay Siliconix
TEST CIRCUITS
+5V
+ 15 V
NC
+ 15 V
C
C
VL
C
V+
S
V+ S2
DG417/418
DG419
Meter
0 V, 2.4 V
IN
V-
0 V, 2.4 V
HP4192A
Impedance
Analyzer
or Equivalent
D
GND
Meter
HP4192A
Impedance
Analyzer
or Equivalent
IN
D2
D1
GND
f = 1 MHz
C
S1
VC
f = 1 MHz
- 15 V
- 15 V
Figure 9. Source/Drain Capacitances
APPLICATIONS
Switched Signal Powers Analog Switch
The analog switch in Figure 10 derives power from its input
signal, provided the input signal amplitude exceeds 4 V and
its frequency exceeds 1 kHz.
A positive input pulse turns on the clamping diode D1 and
charges C1. The charge stored on C1 is used to power the
chip; operation is satisfactory because the switch requires
less than 1 µA of stand-by supply current. Loading of the
signal source is imperceptible. The DG419’s on-resistance is
a low 100  for a 5 V input signal.
This circuit is useful when signals have to be routed to either
of two remote loads. Only three conductors are required: one
for the signal to be switched, one for the control signal and a
common return.
D1
C1
0.01 µF
VL
V+
S1
D
VOUT
Input
S2
RL2
10 k
IN
Control
DG419
GND
V-
RL1
10 k
Figure 10. Switched Signal Powers Remote SPDT Analog Switch
Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
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DG417, DG418, DG419
Vishay Siliconix
APPLICATIONS
Micropower UPS Transfer Switch
Programmable Gain Amplifier
When VCC drops to 3.3 V, the DG417 changes states,
closing SW1 and connecting the backup cell, as shown in
Figure 10. D1 prevents current from leaking back towards the
rest of the circuit. Current consumption by the CMOS analog
switch is around 100 pA; this ensures that most of the power
available is applied to the memory, where it is really needed.
In the stand-by mode, hundreds of A are sufficient to retain
memory data.
The DG419, as shown in figure 11, allows accurate gain
selection in a small package. Switching into virtual ground
reduces distortion caused by RDS(on) variation as a function
of analog signal amplitude.
When the 5 V supply comes back up, the resistor divider
senses the presence of at least 3.5 V, and causes a new
change of state in the analog switch, restoring normal
operation.
GaAs FET Driver
The DG419, as shown in figure 12 may be used as a GaAs
FET driver. It translates a TTL control signal into - 8 V, 0 V
level outputs to drive the gate.
V+
D1
SW1
VL
D
VCC
(5 V)
R1
VSENSE
453 k
S
+
DG417
Memory
3 V Li Cell
–
IN
GND
R2
383 k
V-
Figure 11. Micropower UPS Circuit
+5V
DG419
S1
S2
R1
VL
R2
GaAs FET
V+
S1
S2
IN
D
VOUT
D
DG419
5V
VIN
GND
-
V-
VOUT
+
-8V
Figure 12. Programmable Gain Amplifier
Figure 13. GaAs FET Driver
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70051.
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10
Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
5
E
1
3
2
H
4
S
h x 45
D
C
0.25 mm (Gage Plane)
A
e
B
All Leads
q
A1
L
0.004"
MILLIMETERS
INCHES
DIM
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.20
0.004
0.008
B
0.35
0.51
0.014
0.020
C
0.19
0.25
0.0075
0.010
D
4.80
5.00
0.189
0.196
E
3.80
4.00
0.150
e
0.101 mm
1.27 BSC
0.157
0.050 BSC
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.50
0.93
0.020
0.037
q
0°
8°
0°
8°
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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Package Information
Vishay Siliconix
PDIP: 8ĆLEAD
8
7
6
5
E1
1
2
Dim
A
A1
B
B1
C
D
E
E1
e1
eA
L
Q1
S
3
E
4
D
S
Q1
A
MILLIMETERS
Min
Max
INCHES
Min
Max
3.81
5.08
0.150
0.200
0.38
1.27
0.015
0.050
0.38
0.51
0.015
0.020
0.89
1.65
0.035
0.065
0.20
0.30
0.008
0.012
9.02
10.92
0.355
0.430
7.62
8.26
0.300
0.325
5.59
7.11
0.220
0.280
2.29
2.79
0.090
0.110
7.37
7.87
0.290
0.310
2.79
3.81
0.110
0.150
1.27
2.03
0.050
0.080
0.76
1.65
0.030
0.065
ECN: S-03946—Rev. E, 09-Jul-01
DWG: 5478
A1
15°
MAX
e1
B1
Document Number: 71259
05-Jul-01
L
B
C
NOTE: End leads may be half leads.
eA
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1
Package Information
Vishay Siliconix
CERDIP: 8ĆLEAD
8
7
6
MILLIMETERS
5
Dim
A
A1
B
B1
C
D
E
E1
e1
eA
L
L1
Q1
S
E
E1
1
2
3
4
D
S
e1
Q1
A
L1
A1
∝
L
INCHES
Min
Max
Min
Max
4.06
5.08
0.160
0.200
0.51
1.14
0.020
0.045
0.38
0.51
0.015
0.020
1.14
1.65
0.045
0.065
0.20
0.30
0.008
0.012
9.40
10.16
0.370
0.400
7.62
8.26
0.300
0.325
6.60
7.62
0.260
0.300
2.54 BSC
0.100 BSC
7.62 BSC
0.300 BSC
3.18
3.81
0.125
0.150
3.18
5.08
0.150
0.200
1.27
2.16
0.050
0.085
0.64
1.52
0.025
0.060
0°
15°
0°
15°
ECN: S-03946—Rev. C, 09-Jul-01
DWG: 5348
B1
B
Document Number: 71280
03-Jul-01
C
eA
∝
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1
VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
0.288
7.3
0.050
1.27
0.196
5.0
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
0.050
1.27
0.088
2.25
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
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1
APPLICATION NOTE
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
0.288
7.3
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
0.022
0.050
(0.559)
(1.270)
0.152
(3.861)
0.047
(1.194)
0.246
(6.248)
(0.711)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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22
Document Number: 72606
Revision: 21-Jan-08
Legal Disclaimer Notice
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
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including but not limited to the warranty expressed therein.
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Document Number: 91000
Revision: 11-Mar-11
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