Vishay DG428 Single 8-ch/differential 4-ch latchable analog multiplexer Datasheet

DG428/429
Vishay Siliconix
Single 8-Ch/Differential 4-Ch Latchable Analog Multiplexers
Low rDS(on): 55 Low Charge Injection: 1 pC
On-Board TTL Compatible
Address Latches
High Speed—tTRANS: 160 ns
Break-Before-Make
Low Power Consumption: 0.3 mW
Improved System Accuracy
Microprocessor Bus Compatible
Easily Interfaced
Reduced Crosstalk
High Throughput
Improved Reliability
Data Acquisition Systems
Automatic Test Equipment
Avionics and Military Systems
Communication Systems
Microprocessor-Controlled
Analog Systems
Medical Instrumentation
The DG428/DG429 analog multiplexers have on-chip address
and control latches to simplify design in microprocessor based
applications. Break-before-make switching action protects
against momentary crosstalk of adjacent input signals.
several devices. All control inputs, address (Ax) and enable
(EN) are TTL compatible over the full specified operating
temperature range.
The DG428 selects one of eight single-ended inputs to a
common output, while the DG429 selects one of four
differential inputs to a common differential output.
The silicon-gate CMOS process enables operation over a
wide range of supply voltages. The absolute maximum voltage
rating is extended to 44 V. Additionally, single supply operation
is also allowed and an epitaxial layer prevents latchup.
An on channel conducts current equally well in both directions.
In the off state each channel blocks voltages up to the power
supply rails. An enable (EN) function allows the user to reset
the multiplexer/demultiplexer to all switches off for stacking
On-board TTL-compatible address latches simplify the digital
interface design and reduce board space in bus-controlled
systems such as data acquisition systems, process controls,
avionics, and ATE.
1
18
RS
A0
2
17
A1
EN
3
16
A2
EN
4
GND
V–
5
S1
15
5
14
V+
S2
6
13
S5
S3
7
12
S6
S4
8
11
S7
D
9
10
S8
20 19
Latches
18
A2
Decoders/Drivers
17
GND
6
16
V+
S2
7
15
S5
S3
8
14
S6
9
S4
S1
1
10 11 12 13
S8
Decoders/Drivers
2
NC
4
3
D
V–
Latches
RS
WR
NC
PLCC
WR
DG428
A0
DG428
Dual-In-Line
A1
S7
Top View
Top View
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
www.vishay.com FaxBack 408-970-5600
5-1
DG428/429
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
RS
3
2
1
20 19
A1
NC
PLCC
WR
DG429
A0
DG429
Dual-In-Line and SOIC
WR
1
18
RS
A0
2
17
A1
EN
3
16
GND
EN
4
Latches
18
GND
15
V+
V–
5
Decoders/Drivers
17
VDD
S1a
6
16
S1b
S2a
7
15
S2b
S3a
8
14
S3b
14
S1b
S2a
6
13
S2b
S3a
7
12
S3b
S4a
8
11
S4b
Da
9
10
Db
9
10 11 12 13
Db
5
S4b
S1a
Da
4
NC
Decoders/Drivers
V–
S4a
Latches
Top View
Top View
TRUTH TABLE Ċ DG429
TRUTH TABLE Ċ DG428
Differential 4-Channel Multiplexer
8-Channel Single-Ended Multiplexer
A2
A1
A0
EN
WR
RS
On Switch
X
X
X
1
Maintains previous
switch condition
X
X
X
X
0
None (latches cleared)
WR
RS
On Switch
X
X
X
1
Maintains previous
switch condition
X
X
X
0
0
1
None
0
0
0
1
0
1
1
0
0
1
1
0
1
2
0
1
0
1
0
1
3
0
1
1
1
0
1
4
1
0
0
1
0
1
5
1
0
1
1
0
1
6
1
1
0
1
0
1
7
1
1
1
1
0
1
8
ORDERING INFORMATION Ċ DG428
Temp Range
–40 to 85_C
X
X
X
X
0
None (latches cleared)
Transparent Operation
Transparent Operation
Package
Part Number
18-Pin Plastic DIP
DG428DJ
20-Pin PLCC
DG428DN
www.vishay.com S FaxBack 408-970-5600
5-2
EN
Reset
Reset
X
A0
Latching
Latching
X
A1
X
X
0
0
1
None
0
0
1
0
1
1
0
1
1
0
1
2
1
0
1
0
1
3
1
1
1
0
1
4
Logic “0” = VAL 0.8 V
Logic “1” = VAH 2.4 V
X = Don’t Care
ORDERING INFORMATION Ċ DG429
Temp Range
–40
40 to 85_C
85 C
Package
Part Number
18-Pin Plastic DIP
DG429DJ
20-Pin PLCC
DG429DN
18-Pin Widebody SOIC
DG429DW
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
DG428/429
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (Package)b
18-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW
18-Pin CerDIPd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW
20-Pin PLCCf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW
Voltage Referenced to V–
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
Digital Inputsa, VS, VD . . . . . . . . . . . . . . . . . . . . . . . . (V–) –2 V to (V+) +2 V or
30 mA, whichever occurs first
28-Pin Widebody SOICf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Notes:
a. Signals on SX, DX or INX exceeding V+ or V– will be clamped by internal
diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 6.3 mW/_C above 75_C.
d. Derate 12 mW/_C above 75_C.
e. Derate 10 mW/_C above 75_C.
f.
Derate 6 mW/_C above 75_C.
Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Storage Temperature
(AK Suffix) . . . . . . . . . . . . . . . . . . –65 to 150_C
(DJ, DN Suffix) . . . . . . . . . . . . . . –65 to 125_C
SPECIFICATIONSa
Test Conditions
Unless Otherwise Specified
A Suffix
D Suffix
–55 to 125_C
–40 to 85_C
V+ = 15 V, V– = –15 V, WR = 0,
RS = 2.4 V, VIN = 2.4 V, 0.8 Vf
Tempb
rDS(on)
VD = "10 V, VAL = 0.8 V
IS = –1 mA, VAH = 2.4 V
Room
Full
55
DrDS(on)
–10 V < VS < 10 V
IS = –1 mA
Room
5
Source Off
Leakage Current
IS(off)
VS = "10 V, VD = #10 V
VEN = 0 V
Room
Full
"0.03
–0.5
–50
0.5
50
–0.5
–50
0.5
50
Drain Off
L k
Leakage
Current
C
t
ID(off)
Parameter
Symbol
Typc
Mind
Maxd
Mind
15
–15
Maxd
Unit
15
V
100
125
W
Analog Switch
Analog Signal Rangee
VANALOG
Drain-Source
On-Resistance
Greatest Change in rDS(on)
Between Channelsg
Drain On
L k
Leakage
Current
C
t
ID(on)
Full
–15
100
125
%
VD = "10 V
VS = #10 V
VEN = 0 V
DG428
Room
Full
"0.07
–1
–100
1
100
–1
–100
1
100
DG429
Room
Full
"0.05
–1
–50
1
50
–1
–50
1
50
VS = VD = "10 V
VEN = 2.4 V
VAL = 0
0.8
8V
VAH = 2.4 V
DG428
Room
Full
"0.07
–1
–100
1
100
–1
–100
1
100
DG429
Room
Full
"0.05
–1
–50
1
50
–1
–50
1
50
VA = 2.4 V
Full
0.01
1
1
VA = 15 V
Full
0.01
1
1
Full
–0.01
nA
A
Digital Control
Logic
g Input
p Current
I
Input
t Voltage
V lt
High
Hi h
IAH
Logic Input Current
Input Voltage Low
IAL
VEN = 0 V, 2.4 V, VA = 0 V
RS = 0 V, WR = 0 V
Logic Input Capacitance
Cin
f = 1 MHz
Room
8
Transition Time
tTRANS
See Figure 5
Room
Full
150
Break-Before-Make Interval
tOPEN
See Figure 4
Full
30
90
150
225
150
225
150
300
150
300
–1
mA
A
–1
pF
Dynamic Characteristics
250
300
10
250
300
10
ns
Enable and Write
Turn-On Time
tON(EN,WR)
See Figures 6 and 7
Room
Full
Enable and Reset
Turn-Off Time
tOFF(EN,RS)
See Figures 6 and 8
Room
Full
55
Q
VGEN = 0 V, RGEN = 0 W
CL = 1 nF, See Figure 9
Room
1
pC
Off Isolation
OIRR
VEN = 0 V, RL = 300 W, CL = 15 pF
VS = 7 VRMS, f = 100 kHz
Room
–75
dB
Source Off Capacitance
CS(off)
VS = 0 V, VEN = 0 V, f = 1 MHz
Room
11
Drain Off Capacitance
CD(off)
DG428
Room
40
DG429
Room
20
DG428
Room
54
DG429
Room
34
Charge Injection
VD = 0 V,
V, VEN = 0 V
f = 1 MHz
MH
Drain On Capacitance
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
CD(on)
pF
F
www.vishay.com S FaxBack 408-970-5600
5-3
DG428/429
Vishay Siliconix
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
V+ = 15 V, V– = –15 V, WR = 0, RS = 2.4
V, VIN = 2.4 V, 0.8 Vf
Tempb
Typc
A Suffix
D Suffix
–55 to 125_C
–40 to 85_C
Mind
Maxd
Mind
Maxd
Unit
Minimum Input Timing Requirements
Write Pulse Width
tW
AX, EN Data Set Up time
tS
AX, EN Data Hold Time
tH
Reset Pulse Width
tRS
See
2
S Figure
Fi
VS = 5 V, See Figure 3
Full
100
100
Full
100
100
Full
10
10
Full
100
100
ns
Power Supplies
Positive Supply Current
I+
Negative Supply Current
I–
VEN = 0 V,
V VA = 0,
0 RS = 5 V
Room
20
Room
–0.001
Symbol
100
mA
–5
Test Conditions
Unless Otherwise Specified
Parameter
100
–5
V+ = 12 V, V– = 0 V, WR = 0
RS = 2.4 V, VIN = 2.4 V, 0.8 Vf
Tempb
Typc
A Suffix
D Suffix
–55 to 125_C
–40 to 85_C
Mind
Maxd
Mind
Maxd
Unit
0
12
0
12
V
150
W
Analog Switch
Analog Signal Rangee
Drain-Source
On-Resistance
rDS(on) Matchg
VANALOG
Full
rDS(on)
VD = +10 V, VAL = 0.8 V
IS = –500 mA, VAH = 2.4 V
Room
80
DrDS(on)
0 V < VS < 10 V
IS = –1 mA
Room
5
Source Off
Leakage Current
IS(off)
VS = 0 V, 10 V, VD = 10 V, 0 V
VEN = 0 V
Room
Full
0.03
–0.5
–50
0.5
50
–0.5
–50
0.5
50
DG428
ID(off)
Room
Full
0.07
Drain Off
Leakage Current
–1
–100
1
100
–1
–100
1
100
DG429
Room
Full
0.05
–1
–50
1
50
–1
–50
1
50
DG428
Room
Full
0.07
–1
–100
1
100
–1
–100
1
100
DG429
Room
Full
0.05
–1
–50
1
50
–1
–50
1
50
Drain On
Leakage Current
ID(on)
VD = 0 V, 10 V
VS = 10 V,
V 0V
VEN = 0 V
VS = VD = 0 V, 10 V
VEN = 2.4 V
VAL = 0.8 V
VAH = 2.4 V
150
%
nA
A
Digital Control
VA = 2.4 V
Full
1
1
VA = 12 V
Full
1
1
IAL
VEN = 0 V, 2.4 V, VA = 0 V
RS = 0 V, WR = 0 V
Full
Transition Time
tTRANS
S1 = 10 V/2 V, S8 = 2 V/ 10 V
See Figure 5
Room
Full
160
Break-Before-Make
Interval
tOPEN
See Figure 4
Room
Full
40
Enable and Write
Turn-On Time
tON(EN, WR)
S1 =5 V
See Figures 6 and 7
Room
Full
110
300
400
300
400
Enable and Reset
Turn-Off Time
tOFF(EN, RS)
S1 =5 V
See Figures 6 and 8
Room
Full
70
300
400
300
400
Q
VGEN = 6 V, RGEN = 0 W
CL = 1 nF, See Figure 9
Room
4
pC
OIRR
VEN = 0 V, RL = 300 W, CL = 15 pF
VS = 7 VRMS, f = 100 kHz
Room
–75
dB
Logic
g Input
p Current
I
Input
t Voltage
V lt
High
Hi h
Logic Input Current
Input Voltage Low
IAH
–1
A
mA
–1
Dynamic Characteristics
Charge Injection
Off Isolation
www.vishay.com S FaxBack 408-970-5600
5-4
280
350
25
10
280
350
25
10
ns
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
DG428/429
Vishay Siliconix
Test Conditions
Unless Otherwise Specified
Parameter
V+ = 12 V, V– = 0 V, WR = 0
RS = 2.4 V, VIN = 2.4 V, 0.8 Vf
Symbol
Tempb
Typc
A Suffix
D Suffix
–55 to 125_C
–40 to 85_C
Mind
Maxd
Mind
Maxd
Unit
Minimum Input Timing Requirements
Write Pulse Width
tW
AX, EN
Data Set Up Time
tS
AX, EN
Data Hold Time
tH
Reset Pulse Width
tRS
I+
Full
100
100
Full
100
100
Full
10
10
VS = 5 V, See Figure 3
Full
100
100
VEN = 0 V, VA = 0, RS = 5 V
Room
S Figure
See
Fi
2
ns
Power Supplies
Positive Supply Current
20
100
100
mA
Notes:
a.
b.
c.
d.
e.
f.
g.
Refer to PROCESS OPTION FLOWCHART.
Room = 25_C, Full = as determined by the operating temperature suffix.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
Guaranteed by design, not subject to production test.
VIN = input voltage to perform proper function.
r DS(on) MAX – r DS(on) MIN
Dr DS(on) +
x 100%
r
AVE
ǒ
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
DS(on)
Ǔ
www.vishay.com S FaxBack 408-970-5600
5-5
DG428/429
Vishay Siliconix
_ rDS(on) vs. VD and Supply Voltage
r DS(on)– Drain-Source On-Resistance ( )
r DS(on)– Drain-Source On-Resistance ( )
120
5 V
100
10 V
80
12 V
8 V
15 V
60
40
20 V
20
0
–20 –16 –12 –8
rDS vs. VD and Temperature
100
140
90
80
70
125_C
60
85_C
50
25_C
40
–55_C
30
20
–40_C
V+ = 15 V
V– = –15 V
10
0
–4
0
4
8
12
16
20
–15
–10
Single Supply rDS(on) vs. VD and Supply
30
V+ = 7.5 V
120
10 V
12 V
15 V
80
20 V
15
20
10
IS(off)
0
ID(on), ID(off)
–10
–20
0
–30
4
8
12
16
20
–15
VD – Drain Voltage (V)
–10
–5
0
5
10
15
VS,VD – Source, Drain Voltage (V)
ID, IS Leakages vs. Temperature
Switching Times vs. Power Supply Voltage
10 nA
250
V+ = 15 V
V– = –15 V
VS, VD = 14 V
200
1 nA
tTRANS
IS (off)
Time (ns)
I S, I D – Leakage Current
10
40
0
ID(on), ID(off)
100 pA
150
tON(EN)
100
tOFF(EN)
10 pA
50
1 pA
0
–55 –35
–15
5
25
45
65
Temperature (C_)
www.vishay.com S FaxBack 408-970-5600
5-6
5
V+ = 15 V
V– = –15 V
VS = –VD for ID(off)
VD = VS for ID(on)
V– = 0 V
160
0
ID, IS Leakage Currents vs. Analog Voltage
40
I S, I D – Current (pA)
r DS(on)– Drain-Source On-Resistance ( )
200
–5
VD – Drain Voltage (V)
VD – Drain Voltage (V)
85
105
125
”5
”10
”15
”20
Supply Voltage (V)
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
DG428/429
Vishay Siliconix
_ Charge Injection vs. Analog Voltage
Switching Times vs. Single Supply
350
V– = 0 V
60
300
40
V+ = 12 V
V– = 0 V
Q – Charge (pC)
Time (ms)
250
200
tTRANS
150
tON
20
0
–20
100
tOFF
–40
V+ = 15 V
V– = –15 V
50
–60
0
5
10
15
–15
20
–10
–5
V+ – Positive Supply (V)
0
5
10
15
VS – Source Voltage (V)
Off-Isolation vs. Frequency
Supply Current vs. Switching Frequency
8
–140
I+
EN = 5 V
AX = 0 or 5 V
6
–120
4
Supply Current (ma)
OIRR (dB)
–100
–80
–60
–40
2
IGND
0
–2
–4
–6
I–
–20
–8
1k
10 k
100 k
1M
10 M
1k
10 k
f – Frequency (Hz)
100 k
1M
10 M
f – Frequency (Hz)
Input Switching Threshold
vs. PositiveSupply Voltage
Switching Times vs. Temperature
200
3
V+ = 15 V
V– = –15 V
tTRANS
2.5
150
V TH (V)
Time (nS)
2
tON
100
tOFF
1.5
1
50
0.5
0
–55 –35
0
–15
5
25
45
65
Temperature (C_)
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
85
105
125
0
5
10
15
20
V+ Positive – Supply Voltage (V)
www.vishay.com S FaxBack 408-970-5600
5-7
DG428/429
Vishay Siliconix
V+
VREF
GND
D
EN
DO
QO
V+
V–
AX
Dn
Level
Shift
Qn
Decode/
Drive
S1
Latches
WR
CLK
RESET
V+
Sn
RS
V–
V–
FIGURE 1.
3V
RS
3V
50%
WR
50%
0V
tRS
0V
tW
tS
A0, A1, (A2)
EN
3V
tOFF(RS)
tH
VO
80%
0V
80%
Switch
Output
20%
0V
FIGURE 2.
FIGURE 3.
+15 V
+2.4 V
V+
RS
EN
Logic
Input
All S and Da
+5 V
tr <20 ns
tf <20 ns
3V
50%
0V
DG428
DG429
A0, A1, (A2)
GND
50 Db, D
WR
VO
VS
V–
–15 V
300 35 pF
80%
Switch
Output
VO
0V
tOPEN
FIGURE 4. Break-Before-Make
www.vishay.com FaxBack 408-970-5600
5-8
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
DG428/429
Vishay Siliconix
+15 V
V+
RS
+2.4 V
"10 V
S1
EN
S2 – S7
A0
A1
A2
DG428
WR
GND
#10 V
S8
V–
50 Logic
Input
VO
D
tr <20 ns
tf <20 ns
3V
50%
0V
300 35 pF
–15 V
VS1
90%
Switch
Output
+15 V
RS
+2.4 V
0V
10%
#10 V
S1b
EN
VS8
S1a – S4a, Da
S2b and S3b
A0
A1
VO
V+
S4b
DG429
WR
GND
V–
#10 V
Db
50 tTRANS
S1 ON
tTRANS
S8 ON
VO
300 35 pF
–15 V
FIGURE 5. Transition Time
+15 V
+2.4 V
V+
RS
EN
S1
S2 – S8
A0
A1
A2
GND
–5V
DG428
WR
50 VO
D
V–
300 35 pF
Logic
Input
tr <20 ns
tf <20 ns
3V
50%
0V
–15 V
tON(EN)
tOFF(EN)
0V
+15 V
+2.4 V
Switch
Output
V+
RS
EN
A0
S1b
50 VO
WR
Db
V–
300 90%
VO
S1a – S4a, Da
S2b – S4b
A1
GND
–5V
DG429
VO
35 pF
–15 V
FIGURE 6. Enable tON/tOFF Time
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
www.vishay.com FaxBack 408-970-5600
5-9
DG428/429
Vishay Siliconix
+15 V
EN
A0, A1, (A2)
+2.4 V
V+
S1 or S1b
+5 V
3 V
WR
50%
Remaining
Switches
RS
0 V
VO
DG428
DG429
WR
GND
Db, D
VO
V–
300 W
tON(WR)
Switch
Output
20%
35 pF
0V
–15 V
FIGURE 7. Write Turn-On Time tON(WR)
+15 V
+2.4 V
EN
A0, A1, (A2)
V+
S1 or S1b
3 V
+5 V
RS
50%
Remaining
Switches
RS
GND
DG42
DG429
0 V
tOFF(RS)
VO
Db, D
WR
80%
VO
V–
300 W
35 pF
Switch
Output
0V
–15 V
FIGURE 8. Reset Turn-Off Time tOFF(RS)
+15 V
V+
A0, A1, (A2)
Rg
RS
S
D
IN
Vg
VO
OFF
EN
ON
OFF
DVO
VO
CL
1 nF
3V
GND
2.4 V
WR
V–
DVO is the measured voltage error due to
charge injection. The charge in coulombs is Q =
CL x DVO
–15 V
FIGURE 9. Charge Injection
www.vishay.com FaxBack 408-970-5600
5-10
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
DG428/429
Vishay Siliconix
The internal structure of the DG428/DG429 includes a 5-V
logic interface with input protection circuitry followed by a latch,
level shifter, decoder and finally the switch constructed with
parallel n- and p-channel MOSFETs (see Figure 1).
Bus Interfacing
The DG428/DG429 minimize the amount of interface
hardware between a microprocessor system bus and the
analog system being controlled or measured. The internal TTL
compatible latches give these multiplexers write-only memory,
that is, they can be programmed to stay in a particular switch
state (e.g., switch 1 on) until the microprocessor determines it
is necessary to turn different switches on or turn all switches off
(see Figure 10).
The input protection on the logic lines A0, A1, A2, EN and
control lines WR, RS shown in Figure 1 minimizes
susceptibility to ESD that may be encountered during handling
and operational transients.
The input latches become transparent when WR is held low;
therefore, these multiplexers operate by direct command of the
coded switch state on A2, A1, A0. In this mode the DG428 is
identical to the popular DG408. The same is true of the DG429
versus the popular DG409.
The logic interface is a CMOS logic input with its supply voltage
from an internal +5 V reference voltage. The output of the input
inverter feeds the data input of a D type latch. The level
sensitive D latch continuously places the DX input signal on the
QX output when the WR input is low, resulting in transparent
latch operation. As soon as WR returns high the latch holds the
data last present on the Dn input, subject to the “Minimum Input
Timing Requirements” table.
During system power-up, RS would be low, maintaining all
eight switches in the off state. After RS returned high the
DG428 maintains all switches in the off state.
Following the latches the Qn signals are level shifted and
decoded to provide proper drive levels for the CMOS switches.
This level shifting ensures full on/off switch operation for any
analog signal level between the V+ and V– supply rails.
When the system program performs a write operation to the
address assigned to the DG428, the address decoder
provides a CS active low signal which is gated with the WRITE
(WR) control signal. At this time the data on the DATA BUS (that
will determine which switch to close) is stabilizing. When the
WR signal returns to the high state, (positive edge) the input
latches of the DG428 save the data from the DATA BUS. The
coded information in the A0, A1, A2 and EN latches is decoded
and the appropriate switch is turned on.
The EN pin is used to enable the address latches during the
WR pulse. It can be hard wired to the logic supply or to V+ if one
of the channels will always be used (except during a reset) or
it can be tied to address decoding circuitry for memory mapped
operation. The RS pin is used as a master reset. All latches are
cleared regardless of the state of any other latch or control line.
The WR pin is used to transfer the state of the address control
lines to their latches, except during a reset or when EN is low
(see Truth Tables).
The EN latch allows all switches to be turned off under program
control. This becomes useful when two or more DG428s are
cascaded to build 16-line and larger multiplexers.
+15 V
V+
Data Bus
S1
15 V
Analog
Inputs
A0, A1, A2, EN
DG428
Processor
System
Bus
RS
RESET
+5 V
S8
WRITE
WR
Address
Bus
V–
D
Analog
Output
Address
Decoder
– 15 V
FIGURE 10.Bus Interface
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
www.vishay.com FaxBack 408-970-5600
5-11