DG428, DG429 Vishay Siliconix Single 8-Ch/Differential 4-Ch Latchable Analog Multiplexers DESCRIPTION FEATURES The DG428, DG429 analog multiplexers have on-chip address and control latches to simplify design in microprocessor based applications. Break-before-make switching action protects against momentary crosstalk of adjacent input signals. The DG428 selects one of eight single-ended inputs to a common output, while the DG429 selects one of four differential inputs to a common differential output. An on channel conducts current equally well in both directions. In the off state each channel blocks voltages up to the power supply rails. An enable (EN) function allows the user to reset the multiplexer/demultiplexer to all switches off for stacking several devices. All control inputs, address (Ax) and enable (EN) are TTL compatible over the full specified operating temperature range. The silicon-gate CMOS process enables operation over a wide range of supply voltages. The absolute maximum voltage rating is extended to 44 V. Additionally, single supply operation is also allowed and an epitaxial layer prevents latchup. • Halogen-free according to IEC 61249-2-21 Definition • Low RDS(on): 55 • Low Charge Injection: 1 pC • On-Board TTL Compatible Address Latches • High Speed - tTRANS: 160 ns • Break-Before-Make • Low Power Consumption: 0.3 mW • Compliant to RoHS Directive 2002/95/EC On-board TTL-compatible address latches simplify the digital interface design and reduce board space in bus-controlled systems such as data acquisition systems, process controls, avionics, and ATE. BENEFITS • Improved System Accuracy • Microprocessor Bus Compatible • Easily Interfaced • Reduced Crosstalk • High Throughput • Improved Reliability APPLICATIONS • Data Acquisition Systems • Automatic Test Equipment • Avionics and Military Systems • Communication Systems • Microprocessor-Controlled Analog Systems • Medical Instrumentation FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG428 Dual-In-Line DG428 WR NC RS 3 2 1 20 19 A1 A0 PLCC WR 1 18 RS A0 2 17 A1 EN 3 Latches 16 A2 EN 4 Latches 18 V- 4 Decoders/Drivers 15 GND V- 5 Decoders/Drivers 17 GND S1 6 16 V+ S2 7 15 S5 S3 8 14 S6 6 13 S5 S3 7 12 S6 S4 8 11 S7 D 9 10 S8 9 10 11 12 13 S7 S2 S8 V+ D 14 NC 5 S4 S1 A2 Top View Top View Document Number: 70063 S11-1350–Rev. K, 04-Jul-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG428, DG429 Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION NC RS 3 2 1 20 19 A1 WR DG429 PLCC A0 DG429 Dual-In-Line and SOIC WR 1 18 RS A0 2 17 A1 EN 3 16 GND EN 4 Latches 18 GND 15 V+ V- 5 Decoders/Drivers 17 VDD S1a 6 16 S1b S2a 7 15 S2b S3a 8 14 S3b 14 S1b S2a 6 13 S2b S3a 7 12 S3b S4a 8 11 S4b Da 9 10 Db 9 10 11 12 13 S4b 5 Db S1a S4a 4 NC Decoders/Drivers V- Da Latches Top View Top View TRUTH TABLE - DG428 TRUTH TABLE - DG429 8-Channel Single-Ended Multiplexer A2 A1 A0 EN WR RS Differential 4-Channel Multiplexer On Switch Latching X X A0 EN X X X X WR RS On Switch 1 Maintains previous switch condition X 0 None (latches cleared) Latching X 1 Maintains previous switch condition X 0 None (latches cleared) X Reset X A1 X Reset X X X Transparent Operation X Transparent Operation X X X 0 0 1 None X X 0 0 1 None 0 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 1 0 1 2 0 1 1 0 1 2 0 1 0 1 0 1 3 1 0 1 0 1 3 0 1 1 1 0 1 4 1 1 1 0 1 4 1 0 0 1 0 1 5 1 0 1 1 0 1 6 1 1 0 1 0 1 7 1 1 1 1 0 1 8 Logic "0" = VAL 0.8 V Logic "1" = VAH 2.4 V X = Don’t Care ORDERING INFORMATION - DG428 ORDERING INFORMATION - DG429 Temp Range Temp Range Package 18-pin Plastic DIP - 40 °C to 85 °C 20-pin PLCC Part Number DG428DJ DG428DN-E3 Part Number 18-pin Plastic DIP DG428DJ-E3 DG428DN Package - 40 °C to 85 °C DG429DJ-E3 DG429DN 20-pin PLCC DG429DN-E3 18-pin Widebody SOIC www.vishay.com 2 DG429DJ DG429DW DG429DW-E3 Document Number: 70063 S11-1350–Rev. K, 04-Jul-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG428, DG429 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Voltages Referenced to VDigital Inputs a, Parameter V+ Symbol GND 25 (V-) - 2 V to (V+) + 2 V or 30 mA, whichever occurs first 30 Current (Any Terminal) Peak Current, S or D (Pulsed at 1 ms, 10 % Duty Cycle Max) 100 (AK Suffix) - 65 to 150 (DJ, DN Suffix) - 65 to 125 18-pin Plastic DIPc Power Dissipation (Package)b d 18-pin CerDIP 20-pin PLCC Unit 44 VS, VD Storage Temperature Limit f 28-Pin Widebody SOICf V mA °C 470 900 800 mW 450 Notes: a. Signals on SX, DX or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads soldered or welded to PC board. c. Derate 6.3 mW/°C above 75 °C. d. Derate 12 mW/°C above 75 °C. e. Derate 10 mW/°C above 75 °C. f. Derate 6 mW/°C above 75 °C. Document Number: 70063 S11-1350–Rev. K, 04-Jul-11 www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG428, DG429 Vishay Siliconix SPECIFICATIONSa Parameter Analog Switch Symbol Analog Signal Rangee VANALOG Test Conditions Unless Otherwise Specified V+ = 15 V, V- = - 15 V, WR = 0, RS = 2.4 V, VIN = 2.4 V, 0.8 Vf Temp.b A Suffix - 55 °C to 125 °C Typ.c Full Min.d - 15 D Suffix - 40 °C to 85 °C Max.d Min.d 15 - 15 Max.d Unit 15 V 100 125 RDS(on) VD = ± 10 V, VAL = 0.8 V IS = - 1 mA, VAH = 2.4 V Room Full 55 RDS(on) - 10 V < VS < 10 V IS = - 1 mA Room 5 Source Off Leakage Current IS(off) VS = ± 10 V, VEN = 0 V, VD = ± 10 V Room Full ± 0.03 - 0.5 - 50 0.5 50 - 0.5 - 50 0.5 50 ID(off) Room Full Room Full Room Full ± 0.07 Drain Off Leakage Current -1 - 100 -1 - 50 -1 - 100 1 100 1 50 1 100 -1 - 100 -1 - 50 -1 - 100 1 100 1 50 1 100 -1 - 50 1 50 -1 - 50 1 50 Drain-Source On-Resistance Greatest Change in RDS(on) Between Channelsg Drain On Leakage Current ID(on) VEN = 0 V VD = ± 10 V VS = ± 10 V VS = VD = ± 10 V VEN = 2.4 V VAL= 0.8 V VAH = 2.4 V DG428 DG429 DG428 ± 0.05 ± 0.07 100 125 % nA Room Full ± 0.05 VA = 2.4 V Full 0.01 1 1 VA = 15 V Full 0.01 1 1 Full - 0.01 Room 8 Room Full 150 Full Room Full Room Full 30 90 Room 1 pC dB DG429 Digital Control Logic Input Current Input Voltage High IAH Logic Input Current Input Voltage Low IAL Logic Input Capacitance Cin VEN = 0 V, 2.4 V, VA = 0 V RS = 0 V, WR = 0 V f = 1 MHz Transition Time tTRANS See Figure 5 Break-Before-Make Interval tOPEN See Figure 4 -1 µA -1 pF Dynamic Characteristics Enable and Write Turn-On Time tON(EN,WR) See Figure 6 and 7 Enable and Reset Turn-Off Time tOFF(EN,RS) See Figure 6 and 8 Q VGEN = 0 V, RGEN = 0 CL = 1 nF, See Figure 9 Charge Injection Off Isolation OIRR Source Off Capacitance CS(off) Drain Off Capacitance Drain On Capacitance CD(off) CD(on) Room - 75 Room 11 DG428 Room 40 DG429 Room 20 DG428 Room 54 DG429 Room 34 VD = 0 V VEN = 0 V f = 1 MHz Minimum Input Timing Requirements tW Write Pulse Width AX, EN Data Set Up time tS AX, EN Data Hold Time tH Reset Pulse Width tRS See Figure 2 VS = 5 V, See Figure 3 10 10 150 225 150 300 150 225 150 300 55 VEN = 0 V, RL = 300 CL = 15 pF, VS = 7 VRMS f = 100 kHz VS = 0 V, VEN = 0 V, f = 1 MHz 250 300 250 300 ns pF Full 100 100 Full 100 100 Full 10 10 Full 100 100 ns Power Supplies Positive Supply Current I+ Negative Supply Current I- www.vishay.com 4 VEN = VA = 0, RS = 5 V Room 20 Room - 0.001 100 -5 100 -5 µA Document Number: 70063 S11-1350–Rev. K, 04-Jul-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG428, DG429 Vishay Siliconix SPECIFICATIONSa (for single supply) Parameter Analog Switch Symbol Analog Signal Rangee VANALOG Test Conditions Unless Otherwise Specified V+ = 12 V, V- = 0 V, WR = 0, RS = 2.4 V, VIN = 2.4 V, 0.8 Vf A Suffix - 55°C to 125 °C Temp.b Typ.c Full D Suffix - 40 °C to 85 °C Min.d Max.d Min.d Max.d Unit 0 12 0 12 V 150 Drain-Source On-Resistance RDS(on) VD = ± 10 V, VAL = 0.8 V IS = - 500 µA, VAH = 2.4 V RDS(on) Matchg RDS(on) 0 V < VS < 10 V IS = - 1 mA Room 5 Source Off Leakage Current IS(off) VS = 0 V, 10 V, VEN = 0 V, VD = 10 V, 0 V Room Full ± 0.03 - 0.5 - 50 0.5 50 - 0.5 - 50 0.5 50 ID(off) Room Full Room Full Room Full ± 0.07 Drain Off Leakage Current -1 - 100 -1 - 50 -1 - 100 1 100 1 50 1 100 -1 - 100 -1 - 50 -1 - 100 1 100 1 50 1 100 -1 - 50 1 50 -1 - 50 1 50 Drain On Leakage Current VD = 0 V, 10 V VS = 10 V, 0 V VEN = 0 V VS = VD = 0 V, 10 V VEN = 2.4 V VAL= 0.8 V VAH = 2.4 V ID(on) DG428 DG429 DG428 DG429 Room 80 Room Full ± 0.05 ± 0.07 ± 0.05 150 % nA Digital Control Full Full IAL VA = 2.4 V VA = 12 V VEN = 0 V, 2.4 V, VA = 0 V RS = 0 V, WR = 0 V Transition Time tTRANS S1 = 10 V/ 2 V, S8 = 2 V/ 10 V See Figure 5 160 Break-Before-Make Interval tOPEN See Figure 4 Room Full Room Full Room Full 110 300 400 300 400 Room Full 70 300 400 300 400 Room 4 pC Room - 75 dB Logic Input Current Input Voltage High IAH Logic Input Current Input Voltage Low Dynamic Characteristics Enable and WriteTurn-On Time tON(EN,WR) Enable and Reset Turn-Off Time tOFF(EN,RS) Charge Injection Off Isolation Q OIRR Minimum Input Timing Requirements tW Write Pulse Width AX, EN Data Set Up time tS tH AX, EN Data Hold Time tRS Reset Pulse Width Power Supplies Positive Supply Current I+ S1 = 5 V See Figure 6 and 7 S1 = 5 V See Figure 6 and 8 VGEN = 6 V, RGEN = 0 CL = 1 nF, See Figure 9 VEN = 0 V, RL = 300 CL = 15 pF, VS = 7 VRMS f = 100 kHz Full VS = 5 V, See Figure 3 Full Full Full Full VEN = 0 V, VA = 0, RS = 5 V Room See Figure 2 1 1 -1 40 µA -1 280 350 25 10 280 350 25 10 100 100 10 100 20 1 1 100 100 10 100 100 ns ns 100 µA Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25 °C, full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. ( ) g. RDS(on) = RDS(on) MAX – RDS(on) MIN RDS(on) AVE x 100 % Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Document Number: 70063 S11-1350–Rev. K, 04-Jul-11 www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG428, DG429 Vishay Siliconix TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted) 100 RDS(on) – Drain-Source On-Resistance (Ω) RDS(on) – Drain-Source On-Resistance (Ω) 140 120 100 ±5V ± 10 V 80 ± 12 V ±8V ± 15 V 60 40 ± 20 V 20 0 - 20 - 16 - 12 - 8 - 4 0 4 8 VD – Drain Voltage (V) 90 80 70 125 °C 60 85 °C 50 16 - 55 °C 30 20 - 40 °C V+ = 15 V V- = - 15 V 10 0 12 25 °C 40 20 - 15 -5 0 5 10 15 VD – Drain Voltage (V) RDS(on) vs. VD and Supply Voltage RDS(on) vs. VD and Temperature 40 200 V+ = 15 V V- = - 15 V VS = -VD for I D(off) VD = V S for I D(on) V- = 0 V 30 V+ = 7.5 V 160 120 IS, ID– Current (pA) RDS(on) – Drain-Source On-Resistance (Ω) - 10 10 V 12 V 15 V 80 20 V 20 10 IS(off) 0 ID(on), ID(off) - 10 40 - 20 0 - 30 0 4 8 12 VD – Drain Voltage (V) 16 20 - 15 - 10 -5 0 5 10 VS,VD – Source, Drain Voltage (V) 15 ID , IS Leakage Currents vs. Analog Voltage Single Supply RDS(on) vs. VD and Supply 10 nA 250 200 1 nA tTRANS IS (off) Time (ns) IS, ID – Leakage Current V+ = 15 V V- = - 15 V VS, VD = ± 14 V ID(on), ID(off) 100 pA 150 tON(EN) 100 tOFF(EN) 10 pA 50 1 pA - 55 - 35 0 - 15 5 25 45 65 Temperature (°C) 85 105 ID , IS Leakages vs. Temperature www.vishay.com 6 125 "5 "10 "15 "20 Supply Voltage (V) Switching Times vs. Power Supply Voltage Document Number: 70063 S11-1350–Rev. K, 04-Jul-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG428, DG429 Vishay Siliconix TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted) 350 V- = 0 V 60 300 40 V+ = 12 V V- = 0 V Q – Charge (pC) Time (ms) 250 200 tTRANS 150 tON 20 0 - 20 100 tOFF - 40 50 V+ = 15 V V- = - 15 V - 60 0 5 10 15 20 - 15 - 10 -5 0 5 VS – Source Voltage (V) V+ – Positive Supply (V) Switching Times vs. Single Supply 10 15 Charge Injection vs. Analog Voltage 8 - 140 I+ EN = 5 V AX = 0 or 5 V 6 - 120 Supply Current (mA) 4 OIRR (dB) - 100 - 80 - 60 2 IGND 0 -2 -4 - 40 -6 I- 20 -8 1k 10 k 100 k f – Frequency (Hz) 1M 10 M 1k 10 k 100 k 1M 10 M f – Frequency (Hz) Supply Currents vs. Switching Frequency Off-Isolation vs. Frequency 200 3 V+ = 15 V V- = - 15 V tTRANS 2.5 150 tON 100 V TH (V) Time (nS) 2 tOFF 1.5 1 50 0.5 0 - 55 - 35 0 - 15 45 25 5 65 Temperature (°C) 85 105 Switching Times vs. Temperature Document Number: 70063 S11-1350–Rev. K, 04-Jul-11 125 0 5 10 15 V+ Positive – Supply Voltage (V) 20 Input Switching Threshold vs. Positive Supply Voltage www.vishay.com 7 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG428, DG429 Vishay Siliconix SCHEMATIC DIAGRAM (Typical Channel) V+ GND VREF D EN DO QO V+ V- AX Dn Level Shift Qn Decode/ Drive S1 Latches WR CLK RESET V+ Sn RS VV- Figure 1. TIMING DIAGRAMS 3V RS 3V 50 % 0V 50 % WR tRS 0V tW tOFF(RS) tS A0, A1, (A2) EN 3V tH VO 80 % 0V 80 % Switch Output 20 % 0V Figure 2. Figure 3. TEST CIRCUITS + 15 V + 2.4 V V+ RS EN Logic Input All S and Da +5V tr < 20 ns tf < 20 ns 3V 50 % 0V DG428 DG429 A0, A1, (A2) GND 50 Ω Db, D WR VO VS V- - 15 V 300 Ω 35 pF 80 % Switch Output VO 0V tOPEN Figure 4. Break-Before-Make www.vishay.com 8 Document Number: 70063 S11-1350–Rev. K, 04-Jul-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG428, DG429 Vishay Siliconix TEST CIRCUITS + 15 V V+ RS + 2.4 V ± 10 V S1 EN S2 - S 7 A0 DG428 A1 A2 WR GND ± 10 V S8 50 Ω Logic Input VO D V- tr < 20 ns tf < 20 ns 3V 50 % 0V 300 Ω 35 pF - 15 V VS1 90 % Switch Output + 15 V 0V V+ RS + 2.4 V VO S1b EN 10 % ± 10 V VS8 S1a - S 4a, Da S2b and S3b A0 S4b DG429 A1 GND tTRANS S1 ON WR V- ± 10 V Db 50 Ω tTRANS S8 ON VO 300 Ω 35 pF - 15 V Figure 5. Transition Time + 15 V + 2.4 V V+ RS EN S1 S2 - S 8 A0 A1 A2 GND -5V DG428 WR VO D V- 50 Ω 300 Ω 35 pF Logic Input 3V 50 % tr < 20 ns tf < 20 ns 0V - 15 V tON(EN) tOFF(EN) 0V + 15 V + 2.4 V Switch Output V+ RS EN A0 S1b 50 Ω VO WR Db V300 Ω 90 % VO S1a - S 4a, Da S2b - S 4b A1 GND -5V DG429 VO 35 pF - 15 V Figure 6. Enable tON/tOFF Time Document Number: 70063 S11-1350–Rev. K, 04-Jul-11 www.vishay.com 9 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG428, DG429 Vishay Siliconix TEST CIRCUITS + 15 V EN A0, A1, (A2) + 2.4 V V+ S1 or S1b +5V 3 V WR Remaining Switches RS 50 % 0 V VO DG428 DG429 WR GND Db, D VO V300 Ω tON(WR) Switch Output 20 % 35 pF 0V - 15 V Figure 7. Write Turn-On Time tON(WR) + 15 V + 2.4 V EN A0, A1, (A2) V+ S1 or S1b 3 V +5V RS Remaining Switches RS GND DG42 DG429 WR 50 % 0 V tOFF(RS) VO Db, D 80 % VO Switch Output V300 Ω 35 pF 0V - 15 V Figure 8. Reset Turn-Off Time tOFF(RS) + 15 V V+ A0, A1, (A2) Rg RS D S IN Vg VO OFF EN ON OFF ΔVO VO CL 1 nF 3V GND 2.4 V WR VΔVO is the measured voltage error due to charge injection. The charge in coulombs is Q = CL x ΔVO - 15 V Figure 9. Charge Injection www.vishay.com 10 Document Number: 70063 S11-1350–Rev. K, 04-Jul-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG428, DG429 Vishay Siliconix DETAILED DESCRIPTION APPLICATIONS HINTS The internal structure of the DG428, DG429 includes a 5 V logic interface with input protection circuitry followed by a latch, level shifter, decoder and finally the switch constructed with parallel n- and p-channel MOSFETs (see Figure 1). Bus Interfacing The input protection on the logic lines A0, A1, A2, EN and control lines WR, RS shown in Figure 1 minimizes susceptibility to ESD that may be encountered during handling and operational transients. The logic interface is a CMOS logic input with its supply voltage from an internal + 5 V reference voltage. The output of the input inverter feeds the data input of a D type latch. The level sensitive D latch continuously places the DX input signal on the QX output when the WR input is low, resulting in transparent latch operation. As soon as WR returns high the latch holds the data last present on the Dn input, subject to the "Minimum Input Timing Requirements" table. Following the latches the Qn signals are level shifted and decoded to provide proper drive levels for the CMOS switches. This level shifting ensures full on/off switch operation for any analog signal level between the V+ and V- supply rails. The EN pin is used to enable the address latches during the WR pulse. It can be hard wired to the logic supply or to V+ if one of the channels will always be used (except during a reset) or it can be tied to address decoding circuitry for memory mapped operation. The RS pin is used as a master reset. All latches are cleared regardless of the state of any other latch or control line. The WR pin is used to transfer the state of the address control lines to their latches, except during a reset or when EN is low (see Truth Tables). The DG428, DG429 minimize the amount of interface hardware between a microprocessor system bus and the analog system being controlled or measured. The internal TTL compatible latches give these multiplexers write-only memory, that is, they can be programmed to stay in a particular switch state (e.g., switch 1 on) until the microprocessor determines it is necessary to turn different switches on or turn all switches off (see Figure 10). The input latches become transparent when WR is held low; therefore, these multiplexers operate by direct command of the coded switch state on A2, A1, A0. In this mode the DG428 is identical to the popular DG408. The same is true of the DG429 versus the popular DG409. During system power-up, RS would be low, maintaining all eight switches in the off state. After RS returned high the DG428 maintains all switches in the off state. When the system program performs a write operation to the address assigned to the DG428, the address decoder provides a CS active low signal which is gated with the WRITE (WR) control signal. At this time the data on the DATA BUS (that will determine which switch to close) is stabilizing. When the WR signal returns to the high state, (positive edge) the input latches of the DG428 save the data from the DATA BUS. The coded information in the A0, A1, A2 and EN latches is decoded and the appropriate switch is turned on. The EN latch allows all switches to be turned off under program control. This becomes useful when two or more DG428s are cascaded to build 16-line and larger multiplexers. + 15 V V+ Data Bus S1 15 V Analog Inputs A0, A1, A2, EN DG428 Processor System Bus RS RESET +5V S8 WRITE WR Address Bus V- D Analog Output Address Decoder - 15 V Figure 10. Bus Interface Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?70063. Document Number: 70063 S11-1350–Rev. K, 04-Jul-11 www.vishay.com 11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix PLCC: 2OĆLEAD D–SQUARE A2 MILLIMETERS D1–SQUARE B1 B e1 D2 Document Number: 71263 02-Jul-01 INCHES Min Max Min Max 4.20 4.57 0.165 0.180 2.29 3.04 0.090 0.120 0.51 – 0.020 – 0.331 0.553 0.013 0.021 0.661 0.812 0.026 0.032 9.78 10.03 0.385 0.395 8.890 9.042 0.350 0.356 7.37 8.38 0.290 0.330 1.27 BSC 0.050 BSC ECN: S-03946—Rev. C, 09-Jul-01 DWG: 5306 A1 A Dim A A1 A2 B B1 D D1 D2 e1 0.101 mm 0.004″ www.vishay.com 1 Package Information Vishay Siliconix SOIC (WIDEĆBODY): 18ĆLEAD MILLIMETERS 18 17 16 15 14 13 12 11 Dim A A1 B C D E e H L 10 E 1 2 3 4 5 6 7 8 9 INCHES Min Max Min 2.15 2.90 0.085 0.114 0.10 0.30 0.004 0.012 0.35 0.45 0.014 0.018 0.23 0.28 0.009 0.011 11.25 12.45 0.443 0.490 7.25 8.00 0.285 0.315 1.27 BSC Max 0.050 BSC 9.80 10.60 0.386 0.417 0.60 1.00 0.024 0.039 0_ 8_ 0_ 8_ ECN: S-03946—Rev. C, 09-Jul-01 DWG: 5302 D H C A ALL LEADS 0.101 mm A1 e Document Number: 71266 02-Jul-01 B L 0.004″ www.vishay.com 1 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1