DG611/612/613 Vishay Siliconix High-Speed, Low-Glitch D/CMOS Analog Switches DESCRIPTION FEATURES The DG611/612/613 feature high-speed low-capacitance lateral DMOS switches. Charge injection has been minimized to optimize performance in fast sample-and-hold applications. • • • • • • • Each switch conducts equally well in both directions when on and blocks up to 16 Vp-p when off. Capacitances have been minimized to ensure fast switching and low-glitch energy. To achieve such fast and clean switching performance, the DG611/612/613 are built on the Vishay Siliconix proprietary D/CMOS process. This process combines n-channel DMOS switching FETs with low-power CMOS control logic and drivers. An epitaxial layer prevents latchup. The DG611 and DG612 differ only in that they respond to opposite logic levels. The versatile DG613 has two normally open and two normally closed switches. It can be given various configurations, including four SPST, two SPDT, one DPDT. Fast Switching - tON: 12 ns Low Charge Injection: ± 2 pC Wide Bandwidth: 500 MHz 5 V CMOS Logic Compatible Low rDS(on): 18 Ω Low Quiescent Power : 1.2 nW Single Supply Operation Pb-free Available RoHS* COMPLIANT BENEFITS • • • • • • Improved Data Throughput Minimal Switching Transients Improved System Performance Easily Interfaced Low Insertion Loss Minimal Power Consumption APPLICATIONS • • • • • • • • For additional information see Applications Note AN207 (FaxBack number 70605). Fast Sample-and-Holds Synchronous Demodulators Pixel-Rate Video Switching Disk/Tape Drives DAC Deglitching Switched Capacitor Filters GaAs FET Drivers Satellite Receivers FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG611 DG611 D1 IN1 NC IN2 D2 Key 3 IN1 1 16 IN2 D1 2 15 D2 S1 4 V- 5 NC 6 S1 3 14 S2 V- 4 Dual-In-Line 13 and SOIC V+ GND 5 12 VL S4 6 11 S3 D4 7 10 D3 IN4 8 9 IN3 Top View GND S4 2 1 20 19 LCC Top View 7 8 18 S2 17 V+ 16 NC 15 VL 14 9 10 11 12 13 S3 Four SPST Switches per Package TRUTH TABLE Logic 0 1 DG611 ON OFF DG612 OFF ON Logic "0" ≤ 1 V Logic "1" ≥ 4 V D4 IN4 NC IN3 D3 * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 70057 S-71155–Rev. H, 11-Jun-07 www.vishay.com 1 DG611/612/613 Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG613 DG613 IN1 1 16 IN2 D1 2 15 D2 S1 3 14 S2 VGND 4 Dual-In-Line 13 V+ and SOIC 5 VL Top View 12 S4 6 11 S3 D4 7 10 D3 9 IN3 IN4 8 D1 IN1 NC Key 3 2 1 IN2 D2 20 19 S1 4 18 S2 V- 5 17 V+ NC 6 16 NC GND S4 LCC Top View 7 15 8 14 9 10 11 12 13 VL S3 Four SPST Switches per Package TRUTH TABLE Logic SW1, SW4 0 OFF SW2, SW3 ON 1 ON OFF Logic "0" ≤ 1 V Logic "1" ≥ 4 V D4 IN4 NC IN3 D3 ORDERING INFORMATION Temp Range Package Part Number DG611/612 16-Pin Plastic DIP - 40 to 85 °C 16-Pin Narrow SOIC DG611DJ DG611DJ-E3 DG612DJ DG612DJ-E3 DG611DY DG611DY-E3 DG611DY-T1 DG611DY-T1-E3 DG612DY DG612DY-E3 DG612DY-T1 DG612DY-T1-E3 DG613 16-Pin Plastic DIP DG613DJ DG613DJ-E3 16-Pin Narrow SOIC DG613DY DG613DY-E3 DG613DY-T1 DG613DY-T1-E3 - 40 to 85 °C www.vishay.com 2 Document Number: 70057 S-71155–Rev. H, 11-Jun-07 DG611/612/613 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Parameter Limit V+ to V- - 0.3 to 21 V+ to GND - 0.3 to 21 V- to GND - 19 to 0.3 - 1 to (V+) + 1 or 20 mA, whichever occurs first (V-) - 1 to (V+) + 1 or 20 mA, whichever occurs first (V-) - 0.3 to (V+) + 16 or 20 mA, whichever occurs first ± 30 VL to GND VIN a VS, VDa Continuous Current (Any Terminal) Current, S or D (Pulsed at 1 µs, 10 % Duty Cycle) Storage Temperature ± 100 CerDIP - 65 to 150 Plastic - 65 to 125 16-Pin Plastic DIPc Power Dissipation (Package)b V mA °C 470 d 16-Pin Narrow SOIC e Unit 600 16-Pin CerDIP 900 20-Pin LCCe 900 mW Notes: a. Signals on SX, DX, or INX exceeding V+ or V– will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC Board. c. Derate 6 mW/°C above 75 °C. d. Derate 7.6 mW/°C above 75 °C. e. Derate 12 mW/°C above 75 °C. RECOMMENDED OPERATING RANGE Parameter Limit V+ 5 to 21 VVL - 10 to 0 VIN VANALOG Document Number: 70057 S-71155–Rev. H, 11-Jun-07 4 to V+ 0 to VL Unit V V- to (V+) - 5 www.vishay.com 3 DG611/612/613 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified V+ = 15 V, V- = - 3 V Parameter Analog Switch Symbol VL = 5 V, VIN = 4 V, 1 Vf Analog Signal Rangee VANALOG V- = - 5 V, V+ = 12 V Switch On-Resistance Resistance Match Bet Ch. rDS(on) ΔrDS(on) IS = - 1 mA, VD = 0 V Source Off Leakage IS(off) VS = 0 V, VD = 10 V Drain Off Leakage Current ID(off) VS = 10 V, VD = 0 V Switch On Leakage Current ID(on) VS = V D = 0 V Tempb Typc Full Room Full Room Room Hot Room Hot Room Hot A Suffix - 55 to 125 °C D Suffix - 40 to 85 °C Mind Maxd Mind 7 -5 -5 18 45 60 2 ± 0.001 - 0.25 - 20 ± 0.001 - 0.25 - 20 ± 0.001 - 0.4 - 40 0.25 20 0.25 20 0.4 40 - 0.25 - 20 - 0.25 - 20 - 0.4 - 40 Maxd Unit 7 V 45 60 Ω 0.25 20 0.25 20 0.4 40 nA Digital Control Input Voltage High VIH Full Input Voltage Low VIL Input Current IIN Input Capacitance CIN Full Room Hot Room 4 0.005 -1 - 20 4 1 1 20 -1 - 20 1 1 20 5 V µA pF Dynamic Characteristics Off State Input Capacitance CS(off) VS = 0 V Room Off State Output Capacitance CD(off) VD = 0 V Room 2 On State Input Capacitance CS(on) VS = V D = 0 V Room 10 3 pF BW RL = 50 Ω Room 500 Timee tON Room 12 25 25 Turn-Off Timee tOFF RL = 300 Ω, CL = 3 pF VS = ± 2 V, See Test Circuit, Figure 2 Room 8 20 20 Turn-On Time tON tOFF Room Full Room Full 19 Turn-Off Time RL = 300 Ω, CL = 75 pF VS = ± 2 V, See Test Circuit, Figure 2 35 50 25 35 35 50 25 35 Q CL = 1 nF, VS = 0 V Room 4 ΔQ CL = 1 nF, |VS| ≤ 3 V Room 3 4 4 Room 74 Room 87 Room Full Room Full Room Full Room Full 0.005 Bandwidth Turn-On Charge Injectione Ch. Injection Change e,g Off Isolatione OIRR Crosstalke XTALK RIN = 50 Ω, RL = 50 Ω f = 5 MHz RIN = 10 Ω, RL = 50 Ω f = 5 MHz MHz 16 ns pC dB Power Supplies Positive Supply Current I+ Negative Supply Current I- Logic Supply Current IL VIN = 0 V or 5 V Ground Current www.vishay.com 4 IGND - 0.005 1 5 -1 -5 0.005 - 0.005 1 5 -1 -5 1 5 -1 -5 1 5 µA -1 -5 Document Number: 70057 S-71155–Rev. H, 11-Jun-07 DG611/612/613 Vishay Siliconix SPECIFICATIONS FOR UNIPOLAR SUPPLIESa Test Conditions Unless Otherwise Specified V+ = 15 V, V- = - 3 V A Suffix - 55 to 125 °C D Suffix - 40 to 85 °C Mind Maxd Mind 7 0 VL = 5 V, VIN = 4 V, 1 Vf Tempb 7 V rDS(on) IS = - 1 mA, VD = 1 V Room 25 60 60 Ω Turn-On Timee tON Room 15 30 30 Turn-Off Timee tOFF RL = 300 Ω, CL = 3 pF VS = 2 V, See Test Circuit, Figure 2 Room 10 25 25 Parameter Analog Switch Symbol Analog Signal Rangee Switch On-Resistance VANALOG Typc Full 0 Maxd Unit Dynamic Characteristics ns Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25 °C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. g. ΔQ = |Q at VS = 3 V - Q at VS = - 3 V|. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 400 3 350 2 V+ = 12 V V- = - 5 V 300 I S, I D – Leakage Current (pA) r DS(on) – Drain-Source On-Resistance (Ω) IS = - 1 mA V+ = 5 V V- = - 5 V 250 V+ = 15 V V- = - 3 V 200 150 100 V+ = 15 V V- = - 3 V 1 IS(off), ID(off) 0 -1 -2 ID(on) 50 0 -5 -4 -2 0 2 4 6 VD – Drain Voltage (V) 8 10 rDS(on) vs. VD and Power Supply Voltages Document Number: 70057 S-71155–Rev. H, 11-Jun-07 12 -3 -4 -2 0 2 4 6 8 VD or VS – Drain or Source Voltage (V) 10 Leakage Current vs. Analog Voltage www.vishay.com 5 DG611/612/613 Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 6 24 20 tON 18 4 16 Time (ns) V TH – Logic Input Voltage (V) 22 V+ = 15 V V- = - 3 V 5 3 2 14 tOFF 12 10 8 V+ = 15 V V- = - 3 V RL = 300 Ω CL = 10 pF 6 1 4 2 0 0 0 5 10 - 55 15 5 25 45 65 85 105 Input Switching Threshold vs. VL Switching Times vs. Temperature 125 20 V+ = 15 V V- = - 3 V V+ = 15 V V- = - 3 V IS = - 1 mA 350 300 10 Qd 250 Charge (pC) r DS(on) – Drain-Source On-Resistance (Ω) - 15 Temperature (°C) 400 200 150 0 Qs 25 °C 100 - 10 125 °C 50 - 55 °C 0 - 20 -4 -2 0 2 4 6 8 VD – Drain Voltage (V) 10 12 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 VANALOG – Analog Voltage (V) rDS(on) vs. VD and Temperature Charge Injection vs. Analog Voltage 10 nA 0 1 nA -4 RL = 50 Ω Insertion Loss (dB) I S(off), I D(off)– Leakage (A) - 35 VL – Logic Supply Voltage (V) 100 pA ID(on) 10 pA IS(off), ID(off) 1 pA -8 - 12 - 3 dB Point - 16 - 20 - 24 0.1 pA - 55 - 25 0 25 50 Temperature (°C) 75 100 Leakage Currents vs. Temperature www.vishay.com 6 125 1 10 100 1000 f – Frequency (MHz) - 3 dB Bandwidth/Insertion Loss vs. Frequency Document Number: 70057 S-71155–Rev. H, 11-Jun-07 DG611/612/613 Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted - 120 6 V+ = 15 V V- = - 3 V V+ = 15 V V- = - 3 V VL = 5 V CX = 0, 5 V 5 4 - 100 Supply Current (mA) 3 Crosstalk (dB) - 80 - 60 Off Isolation - 40 I+ 2 1 IL 0 -1 I- -2 -3 -4 -5 - 20 1 10 1k 100 100 k 100 k 1M 10 M f – Frequency (Hz) f – Frequency (MHz) Crosstalk and Off Isolation vs. Frequency Supply Currents vs. Switching Frequency SCHEMATIC DIAGRAM (TYPICAL CHANNEL) V+ VL S Input Logic INX Level Translator Driver D DMOS Switch V- Figure 1. TEST CIRCUITS +5V + 15 V VL V+ D Logic Input ±2V S tr < 10 ns tf < 10 ns 5V VO 50 % 0V VS = ± 2 V 90 % IN GND V- RL 300 Ω CL Switch Output 20 % 0V tON tOFF VCL (includes fixture and stray capacitance) VO = V S RL RL + rDS(on) Figure 2. Switching Time Document Number: 70057 S-71155–Rev. H, 11-Jun-07 www.vishay.com 7 DG611/612/613 Vishay Siliconix TEST CIRCUITS +5V C VL S1 VS +5V Rg = 50 Ω + 15 V + 15 V C V+ D1 50 Ω IN1 1 V, 4 V Rg V+ D VL S IN Vg NC VO 1 V, 4 V CL 1 nF 5V GND S2 VO D2 RL IN2 GND V- C VVS XTA LK Isolation = 20 log -3V VO C = RF bypass -3V Figure 4. Crosstalk Figure 3. Charge Injection APPLICATIONS High-Speed Sample-and-Hold Pixel-Rate Switch In a fast sample-and-hold application, the analog switch characteristics are critical. A fast switch reduces aperture uncertainty. A low charge injection eliminates offset (step) errors. A low leakage reduces droop errors. The CLC111, a fast input buffer, helps to shorten acquisition and settling times. A low leakage, low dielectric absorption hold capacitor must be used. Polycarbonate, polystyrene and polypropylene are good choices. The JFET output buffer reduces droop due to its low input bias current. (See Figure 5.) Windows, picture-in-picture, title overlays are economically generated using a high-speed analog switch such as the DG613. For this application the two video sources must be sync locked. The glitch-less analog switch eliminates halos. (See Figure 6.) GaAs FET Drivers Figure 7 illustrates a high-speed GaAs FET driver. To turn the GaAs FET on 0 V are applied to its gate via S1, whereas to turn it off, - 8 V are applied via S2. This high-speed, low-power driver is especially suited for applications that require a large number of RF switches, such as phased array radars. +5V Input Buffer + 12 V Output Buffer Analog Input CLC111 S D + LF356 - 75 Ω 5 V Control ± 5 V Output to A/D IN 1/ 4 CHOLD 650 pF Polystyrene DG611 -5V Figure 5. High-Speed Sample-and-Hold www.vishay.com 8 Document Number: 70057 S-71155–Rev. H, 11-Jun-07 DG611/612/613 Vishay Siliconix APPLICATIONS +5V + 12 V Output Buffer Background D + Composite Output 75 Ω CLC410 - 75 Ω 1/ CLC114 2 250 Ω Titles 250 Ω 75 Ω 5 V Control 1/ 2 DG613 -5V Figure 6. A Pixel-Rate Switch Creates Title Overlays +5V S1 VL V+ D1 RF IN GaAs RF OUT IN1 1/ 2 DG613 S2 5V D2 IN2 GND V- -8V Figure 7. A High-Speed GaAs FET Driver that Saves Power Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?70057. Document Number: 70057 S-71155–Rev. H, 11-Jun-07 www.vishay.com 9 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 18-Jul-08 www.vishay.com 1