Intel DJLXTLAD0SE000 Advanced 8-port 10/100 mbps phy transceiver Datasheet

Intel® LXT9785 and Intel® LXT9785E
Advanced 8-Port 10/100 Mbps PHY
Transceivers
Datasheet
The Intel® LXT9785 and Intel® LXT9785E are 8-port Fast Ethernet PHY Transceivers
supporting IEEE 802.3 physical layer applications at 10 Mbps and 100 Mbps. These devices
provide Serial/Source Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and
Reduced Media Independent Interface (RMII) for switching and other independent port
applications. The LXT9785 and LXT9785E are identical except for the IP telephony features
included in the LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785
that detects Data Terminal Equipment (DTE) requiring power from the switch over a CAT5
cable. The system uses the information collected by the LXT97985E to apply power if the DTE
at the far end requires power over the cable, such as an IP telephone.
Each network port can provide a twisted-pair (TP) or Low-Voltage Positive Emitter Coupled
Logic (LVPECL) interface. The twisted-pair interface supports 10 Mbps and 100 Mbps
(10BASE-T and 100BASE-TX) Ethernet over twisted-pair. The LVPECL interface supports
100 Mbps (100BASE-FX) Ethernet over fiber-optic media.
The LXT9785/LXT9785E provides three discrete LED driver outputs for each port. The devices
support both half-duplex and full-duplex operation at 10 Mbps and 100 Mbps and require only a
single 2.5 V power supply.
Applications

Enterprise switches
IP telephony switches

Storage Area Networks
Multi-port Network Interface Cards (NICs)
Product Features

Eight IEEE 802.3-compliant 10BASE-T or
100BASE-TX ports with integrated filters.
100BASE-FX fiber-optic capability on all
ports.
2.5 V operation.
Low power consumption; 250 mW per port
typical.
Multiple RMII or SMII/SS-SMII ports for
independent PHY port operation.
Auto MDI/MDIX crossover capability.
Proprietary Optimal Signal Processing™
architecture improves SNR by 3 dB over
ideal analog filters.
Optimized for dual-high stacked RJ-45
applications.
MDIO sectionalization into 2x4 or 1x8
configurations.

Supports both auto-negotiation systems and
legacy systems without auto-negotiation
capability.
Robust baseline wander correction.
Configurable through the MDIO port or
external control pins.
JTAG boundary scan.
208-pin PQFP: LXT9785HC,
LXT9785EHC, LXT9785HE.
241-ball BGA: LXT9785BC,
LXT9785EBC.
196-ball BGA: LXT9785MBC
DTE detection for remote powering
applications (LXT9785E only).
Extended temperature operation of -40oC to
+85oC (LXT9785HE).
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
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Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® LXT9785 and Intel® LXT9785E may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Copyright © 2003, Intel Corporation
2
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Contents
Contents
1.0
Introduction.................................................................................................................................. 18
1.1
1.2
What You Will Find in This Document ................................................................................ 18
Related Documents ............................................................................................................ 18
2.0
Block Diagram ............................................................................................................................. 19
3.0
Pin/Ball Assignments and Signal Descriptions ........................................................................ 20
3.1
3.2
3.3
3.4
3.5
3.6
4.0
PQFP Pin Assignments ...................................................................................................... 20
3.1.1 PQFP Pin Assignments – RMII Configuration ....................................................... 21
3.1.2 PQFP Pin Assignments – SMII Configuration........................................................ 26
3.1.3 PQFP Pin Assignments – SS-SMII Configuration.................................................. 31
PQFP Signal Descriptions .................................................................................................. 36
3.2.1 Signal Name Conventions ..................................................................................... 36
3.2.2 PQFP Signal Descriptions – RMII, SMII, and SS-SMII Configurations.................. 36
BGA23 Ball Assignments.................................................................................................... 51
3.3.1 RMII BGA23 Ball List ............................................................................................. 52
3.3.2 SMII BGA23 Ball List ............................................................................................. 62
3.3.3 SS-SMII BGA23 Ball List ....................................................................................... 72
BGA23 Signal Descriptions ................................................................................................ 82
3.4.1 Signal Name Conventions ..................................................................................... 82
3.4.2 Signal Descriptions – RMII, SMII, and SS-SMII Configurations............................. 82
BGA15 Ball Assignments.................................................................................................... 98
3.5.1 BGA15 Ball List...................................................................................................... 99
BGA15 Signal Descriptions ..............................................................................................109
3.6.1 Signal Name Conventions ...................................................................................109
3.6.2 Signal Descriptions – SMII and SS-SMII Configurations .....................................109
Functional Description..............................................................................................................116
4.1
4.2
4.3
Introduction .......................................................................................................................116
4.1.1 OSP™ Architecture .............................................................................................116
4.1.2 Comprehensive Functionality ..............................................................................117
4.1.2.1 Sectionalization ....................................................................................117
Interface Descriptions .......................................................................................................117
4.2.1 10/100 Network Interface.....................................................................................117
4.2.1.1 Twisted-Pair Interface ..........................................................................118
4.2.1.2 MDI Crossover (MDIX).........................................................................119
4.2.1.3 Fiber Interface......................................................................................119
Media Independent Interface (MII) Interfaces...................................................................119
4.3.1 Global MII Mode Select .......................................................................................119
4.3.2 Internal Loopback ................................................................................................120
4.3.3 RMII Data Interface..............................................................................................120
4.3.4 Serial Media Independent Interface (SMII) and Source SynchronousSerial Media Independent Interface (SS-SMII) ....................................................121
4.3.4.1 SMII Interface.......................................................................................121
4.3.4.2 Source Synchronous-Serial Media Independent Interface ..................121
4.3.5 Configuration Management Interface ..................................................................121
4.3.6 MII Isolate ............................................................................................................121
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
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Contents
4.4
4.5
4.6
4.7
4.8
4.9
4
4.3.7 MDIO Management Interface .............................................................................. 121
4.3.8 MII Sectionalization.............................................................................................. 123
4.3.9 MII Interrupts........................................................................................................ 123
4.3.10 Global Hardware Control Interface ...................................................................... 124
4.3.11 FIFO Initial Fill Values.......................................................................................... 124
Operating Requirements................................................................................................... 125
4.4.1 Power Requirements ........................................................................................... 125
4.4.2 Clock/SYNC Requirements ................................................................................. 125
4.4.2.1 Reference Clock .................................................................................. 125
4.4.2.2 TxCLK Signal (SS-SMII only)............................................................... 125
4.4.2.3 TxSYNC Signal (SMII/SS-SMII)........................................................... 125
4.4.2.4 RxSYNC Signal (SS-SMII only) ........................................................... 125
4.4.2.5 RxCLK Signal (SS-SMII only) .............................................................. 126
Initialization ....................................................................................................................... 126
4.5.1 MDIO Control Mode............................................................................................. 126
4.5.2 Hardware Control Mode....................................................................................... 126
4.5.3 Power-Down Mode .............................................................................................. 127
4.5.3.1 Global (Hardware) Power Down .......................................................... 128
4.5.3.2 Port (Software) Power Down ............................................................... 128
4.5.4 Reset ................................................................................................................... 128
4.5.5 Hardware Configuration Settings......................................................................... 129
Link Establishment............................................................................................................ 129
4.6.1 Auto-Negotiation .................................................................................................. 129
4.6.1.1 Base Page Exchange .......................................................................... 129
4.6.1.2 Manual Next Page Exchange .............................................................. 130
4.6.1.3 Controlling Auto-Negotiation ................................................................ 130
4.6.1.4 Link Criteria.......................................................................................... 130
4.6.1.5 Parallel Detection................................................................................. 131
4.6.1.6 Reliable Link Establishment While Auto MDI/MDIX is
Enabled in Forced Speed Mode .......................................................... 131
Serial MII Operation.......................................................................................................... 132
4.7.1 SMII Reference Clock.......................................................................................... 135
4.7.2 TxSYNC Pulse (SMII/SS-SMII)............................................................................ 135
4.7.3 Transmit Data Stream.......................................................................................... 135
4.7.3.1 Transmit Enable................................................................................... 135
4.7.3.2 Transmit Error ...................................................................................... 135
4.7.4 Receive Data Stream........................................................................................... 136
4.7.4.1 Carrier Sense....................................................................................... 136
4.7.4.2 Receive Data Valid .............................................................................. 136
4.7.4.3 Receive Error ....................................................................................... 136
4.7.4.4 Receive Status Encoding..................................................................... 136
4.7.5 Collision ............................................................................................................... 136
4.7.6 Source Synchronous-Serial Media Independent Interface .................................. 137
RMII Operation ................................................................................................................. 141
4.8.1 RMII Reference Clock.......................................................................................... 141
4.8.2 Transmit Enable................................................................................................... 142
4.8.3 Carrier Sense & Data Valid.................................................................................. 142
4.8.4 Receive Error....................................................................................................... 142
4.8.5 Out-of-Band Signaling ......................................................................................... 142
4.8.6 4B/5B Coding Operations .................................................................................... 142
100 Mbps Operation ......................................................................................................... 145
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Contents
4.9.1
4.9.2
4.10
4.11
4.12
4.13
4.14
5.0
100BASE-X Network Operations .........................................................................145
100BASE-X Protocol Sublayer Operations..........................................................145
4.9.2.1 PCS Sublayer ......................................................................................145
4.9.3 PMA Sublayer ......................................................................................................147
4.9.3.1 Link ......................................................................................................148
4.9.3.2 Link Failure Override............................................................................148
4.9.3.3 Carrier Sense/Data Valid (RMII) ..........................................................148
4.9.3.4 Carrier Sense (SMII) ............................................................................148
4.9.3.5 Receive Data Valid (SMII)....................................................................148
4.9.3.6 Twisted-Pair PMD Sublayer .................................................................149
4.9.3.7 Fiber PMD Sublayer.............................................................................149
10 Mbps Operation ...........................................................................................................150
4.10.1 Preamble Handling ..............................................................................................150
4.10.2 Dribble Bits ..........................................................................................................151
4.10.3 Link Test ..............................................................................................................151
4.10.3.1 Link Failure ..........................................................................................151
4.10.4 Jabber ..................................................................................................................151
DTE Discovery Process ....................................................................................................152
4.11.1 Definitions ............................................................................................................152
4.11.2 Interaction between Processor, MAC, and PHY ..................................................153
4.11.3 Management Interface and Control .....................................................................153
4.11.4 DTE Discovery Process Flow ..............................................................................154
4.11.5 DTE Discovery Behavior......................................................................................155
Monitoring Operations ......................................................................................................157
4.12.1 Monitoring Auto-Negotiation ................................................................................157
4.12.2 Per-Port LED Driver Functions ............................................................................157
4.12.3 Out-of-Band Signaling .........................................................................................158
4.12.4 Boundary Scan Interface .....................................................................................159
4.12.5 State Machine ......................................................................................................159
4.12.6 Instruction Register ..............................................................................................159
4.12.7 Boundary Scan Register ......................................................................................159
Cable Diagnostics Overview .............................................................................................160
4.13.1 Features...............................................................................................................160
4.13.2 Operation .............................................................................................................160
4.13.2.1 Short and Long Cable Testing Requirements ......................................160
4.13.2.2 Precision ..............................................................................................160
4.13.3 Implementation Considerations ...........................................................................161
4.13.4 Basic Implementation ..........................................................................................161
Link Hold-Off Overview .....................................................................................................162
4.14.1 Features...............................................................................................................162
4.14.2 Operation .............................................................................................................163
Application Information ............................................................................................................164
5.1
5.2
Design Recommendations................................................................................................164
General Design Guidelines ...............................................................................................164
5.2.1 Power Supply Filtering .........................................................................................164
5.2.2 Power and Ground Plane Layout Considerations................................................165
5.2.2.1 Chassis Ground ...................................................................................165
5.2.3 MII Terminations ..................................................................................................165
5.2.4 Twisted-Pair Interface ..........................................................................................165
5.2.4.1 Magnetic Requirements .......................................................................166
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
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Contents
5.3
5.2.5 The Fiber Interface .............................................................................................. 166
5.2.6 LED Circuit........................................................................................................... 167
Typical Application Circuits............................................................................................... 168
6.0
Test Specifications.................................................................................................................... 173
7.0
Register Definitions................................................................................................................... 199
8.0
Package Specifications............................................................................................................. 221
9.0
Ordering Information................................................................................................................. 227
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Intel® LXT9785/LXT9785E Block Diagram ................................................................................. 19
Intel® LXT9785 and Intel® LXT9785E RMII 208-Pin PQFP Assignments .................................. 21
Intel® LXT9785/LXT9785E SMII 208-Pin PQFP Assignments ................................................... 26
Intel® LXT9785/LXT9785E SS-SMII 208-Pin PQFP Assignments ............................................. 31
Intel® LXT9785/LXT9785E 241-Ball BGA23 Assignments (Top View)...................................... 51
Intel® LXT9785MBC 196-Ball BGA15 Assignments (Top View) ................................................ 98
Intel® LXT9785/LXT9785E Interfaces ...................................................................................... 118
Intel® LXT9785/LXT9785E Internal Loopback.......................................................................... 120
Intel® LXT9785/LXT9785E Management Interface Read Frame Structure.............................. 122
Intel® LXT9785/LXT9785E Management Interface Write Frame Structure .............................. 122
Intel® LXT9785/LXT9785E Port Address Scheme ................................................................... 123
Intel® LXT9785/LXT9785E Interrupt Logic ............................................................................... 124
Intel® LXT9785/LXT9785E Initialization Sequence .................................................................. 127
Intel® LXT9785/LXT9785E Auto-Negotiation Operation........................................................... 131
Intel® LXT9785/LXT9785E Typical SMII Interface Diagram ..................................................... 133
Intel® LXT9785/LXT9785E Typical SMII Quad Sectionalization Diagram ................................ 134
Intel® LXT9785/LXT9785E 100 Mbps Serial MII Data Flow ..................................................... 135
Intel® LXT9785/LXT9785E Serial MII Transmit Synchronization ............................................. 136
Intel® LXT9785/LXT9785E Serial MII Receive Synchronization .............................................. 137
Intel® LXT9785/LXT9785E Typical SS-SMII Interface Diagram ............................................... 139
Intel® LXT9785/LXT9785E Typical SS-SMII Quad Sectionalization Diagram .......................... 140
Intel® LXT9785/LXT9785E SS-SMII Transmit Timing .............................................................. 141
Intel® LXT9785/LXT9785E SS-SMII Receive Timing ............................................................... 141
Intel® LXT9785/LXT9785E RMII Data Flow ............................................................................. 142
Intel® LXT9785/LXT9785E Typical RMII Interface Diagram..................................................... 143
Intel® LXT9785/LXT9785E Typical RMII Quad Sectionalization Diagram................................ 144
Intel® LXT9785/LXT9785E 100BASE-X Frame Format ........................................................... 145
Intel® LXT9785/LXT9785E Protocol Sublayers ........................................................................ 146
Typical IP Telephone System Connection................................................................................ 152
Intel® LXT9785E Negotiation Flow Chart ................................................................................. 156
Intel® LXT9785/LXT9785E LED Pulse Stretching .................................................................... 158
Intel® LXT9785/LXT9785E RMII Programmable Out-of-Band Signaling.................................. 158
LED Circuit ............................................................................................................................... 167
Intel® LXT9785/LXT9785E Power and Ground Supply Connections ....................................... 168
Intel® LXT9785/LXT9785E Typical Twisted-Pair Interface ....................................................... 169
Recommended Intel® LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry ...... 170
Recommended Intel® LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry ......... 171
ON Semiconductor Triple PECL-to-LVPECL Translator .......................................................... 172
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
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Intel® LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing.............................................178
Intel® LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing............................................179
Intel® LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing.............................................180
Intel® LXT9785/LXT9785E SMII - 100BASE-FX Transmit Timing............................................181
Intel® LXT9785/LXT9785E SMII - 10BASE-T Receive Timing .................................................182
Intel® LXT9785/LXT9785E SMII - 10BASE-T Transmit Timing ................................................183
Intel® LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing.......................................184
Intel® LXT9785/LXT9785E SS-SMII - 100BASE-TX Transmit Timing......................................185
Intel® LXT9785/LXT9785E SS-SMII - 100BASE-FX Receive Timing.......................................186
Intel® LXT9785/LXT9785E SS-SMII - 100BASE-FX Transmit Timing......................................187
Intel® LXT9785/LXT9785E SS-SMII - 10BASE-T Receive Timing ...........................................188
Intel® LXT9785/LXT9785E SS-SMII - 10BASE-T Transmit Timing ..........................................189
Intel® LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing ............................................190
Intel® LXT9785/LXT9785E RMII - 100BASE-TX Transmit Timing ...........................................191
Intel® LXT9785/LXT9785E RMII - 100BASE-FX Receive Timing ............................................192
Intel® LXT9785/LXT9785E RMII - 100BASE-FX Transmit Timing ...........................................193
Intel® LXT9785/LXT9785E RMII - 10BASE-T Receive Timing.................................................194
Intel® LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing................................................195
Intel® LXT9785/LXT9785E Auto-Negotiation and Fast Link Pulse Timing ...............................196
Intel® LXT9785/LXT9785E Fast Link Pulse Timing ..................................................................196
Intel® LXT9785/LXT9785E MDIO Write Timing (MDIO Sourced by MAC)...............................197
Intel® LXT9785/LXT9785E MDIO Read Timing (MDIO Sourced by PHY) ...............................197
Intel® LXT9785/LXT9785E Power-Up Timing...........................................................................198
Intel® LXT9785/LXT9785E Reset Recovery Timing .................................................................198
PHY Identifier Bit Mapping........................................................................................................203
Intel® LXT9785/LXT9785E 208-Pin PQFP Plastic Package Specification ...............................221
Intel® LXT9785/LXT9785E 241-Ball BGA23 Package Specs - Top/Side View (LXT9785BC) .222
Intel® LXT9785/LXT9785E 241-Ball BGA23 Package Specs - Bottom View (LXT9785BC) ....223
Intel® LXT9785MBC 196-Ball BGA15 Package Specs - Top/Side View (LXT9785MBC) ........225
Ordering Information - Sample .................................................................................................228
Tables
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Intel® LXT9785/LXT9785E Signal Type Descriptions.................................................................20
Intel® LXT9785/LXT9785E RMII PQFP Pin List ......................................................................... 22
Intel® LXT9785/LXT9785E SMII PQFP Pin List ......................................................................... 27
Intel® LXT9785/LXT9785 SS-SMII PQFP Pin List...................................................................... 32
Intel® LXT9785/LXT9785E RMII Signal Descriptions – PQFP ................................................... 36
Intel® LXT9785/LXT9785E SMII / SS-SMII Common Signal Descriptions – PQFP ................... 39
Intel® LXT9785/LXT9785E SMII Specific Signal Descriptions – PQFP...................................... 39
Intel® LXT9785/LXT9785E SS-SMII Specific Signal Descriptions – PQFP................................ 40
Intel® LXT9785/LXT9785E MDIO Control Interface Signals – PQFP......................................... 41
Intel® LXT9785/LXT9785E Signal Detect – PQFP ..................................................................... 42
Intel® LXT9785/LXT9785E Network Interface Signal Descriptions – PQFP............................... 42
Intel® LXT9785/LXT9785E JTAG Test Signal Descriptions – PQFP.......................................... 43
Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP .................................... 43
Intel® LXT9785/LXT9785E LED Signal Descriptions – PQFP....................................................47
Intel® LXT9785/LXT9785E Power Supply Signal Descriptions – PQFP..................................... 48
Intel® LXT9785/LXT9785E Unused/Reserved Pins – PQFP...................................................... 50
Intel® LXT9785/LXT9785E Receive FIFO Depth Considerations............................................... 50
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
7
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Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Signal Name ...... 52
Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Ball Location ...... 57
Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Signal Name....... 62
Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball Location....... 67
Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Signal Name. 72
Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location. 77
Intel® LXT9785/LXT9785E RMII Signal Descriptions – BGA23 ................................................. 82
Intel® LXT9785/LXT9785E SMII / SS-SMII Common Signal Descriptions – BGA23 ................. 85
Intel® LXT9785/LXT9785E SMII Specific Signal Descriptions – BGA23 .................................... 85
Intel® LXT9785/LXT9785E SS-SMII Specific Signal Descriptions – BGA23 .............................. 86
Intel® LXT9785/LXT9785E MDIO Control Interface Signals – BGA23 ....................................... 87
Intel® LXT9785/LXT9785E Signal Detect – BGA23 ................................................................... 88
Intel® LXT9785/LXT9785E Network Interface Signal Descriptions – BGA23............................. 88
Intel® LXT9785/LXT9785E JTAG Test Signal Descriptions – BGA23........................................ 89
Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 .................................. 90
Intel® LXT9785/LXT9785E LED Signal Descriptions – BGA23 .................................................. 94
Intel® LXT9785/LXT9785E Power Supply Signal Descriptions – BGA23................................... 95
Intel® LXT9785/LXT9785E Unused/Reserved Pins – BGA23 .................................................... 97
Intel® LXT9785/LXT9785E Receive FIFO Depth Configurations ............................................... 97
Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name ......................... 99
Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location
(SMII/SS-SMII) ......................................................................................................................... 103
Intel® LXT9785 BGA15 Signal Descriptions ............................................................................ 109
Intel® LXT9785/LXT9785E MDIX Selection ............................................................................. 119
Intel® LXT9785/LXT9785E MII Mode Select ............................................................................ 120
Intel® LXT9785/9785E Global Hardware Configuration Settings ............................................. 129
Intel® LXT9785/LXT9785E SMII Signal Summary ................................................................... 132
Intel® LXT9785/LXT9785E RX Status Encoding Bit Definitions ............................................... 137
Intel® LXT9785/LXT9785E SS-SMII ......................................................................................... 138
4B/5B Coding ........................................................................................................................... 147
Next Page Message #5 Code Word Definitions ....................................................................... 155
BSR Mode of Operation ........................................................................................................... 159
Supported JTAG Instructions ................................................................................................... 159
Intel® LXT9785/LXT9785E Magnetics Requirements .............................................................. 166
Intel® LXT9785/LXT9785E Absolute Maximum Ratings .......................................................... 173
Intel® LXT9785/LXT9785E Operating Conditions .................................................................... 173
Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 2.5 V +/- 5%) . 174
Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%) . 175
Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics – SD Pins ....................... 175
Intel® LXT9785/LXT9785E Required Clock Characteristics ..................................................... 175
Intel® LXT9785/LXT9785E 100BASE-TX Transceiver Characteristics .................................... 176
Intel® LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics .................................... 176
Intel® LXT9785/LXT9785E 10BASE-T Transceiver Characteristics......................................... 177
Intel® LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Parameters ......................... 178
Intel® LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing Parameters ........................ 179
Intel® LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing Parameters ......................... 180
Intel® LXT9785/LXT9785E SMII - 100BASE-FX Transmit Timing Parameters ........................ 181
Intel® LXT9785/LXT9785E SMII - 10BASE-T Receive Timing Parameters ............................. 182
Intel® LXT9785/LXT9785E SMII-10BASE-T Transmit Timing Parameters .............................. 183
Intel® LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing Parameters ................... 184
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Contents
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
Intel® LXT9785/LXT9785E SS-SMII - 100BASE-TX Transmit Timing......................................185
Intel® LXT9785/LXT9785E SS-SMII - 100BASE-FX Receive Timing Parameters ...................186
Intel® LXT9785/LXT9785E SS-SMII - 100BASE-FX Transmit Timing Parameters ..................187
Intel® LXT9785/LXT9785E SS-SMII - 10BASE-T Receive Timing Parameters .......................188
Intel® LXT9785/LXT9785E SS-SMII - 10BASE-T Transmit Timing Parameters ......................189
Intel® LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing Parameters.........................190
Intel® LXT9785/LXT9785E RMII - 100BASE-TX Transmit Timing Parameters........................191
Intel® LXT9785/LXT9785E RMII - 100BASE-FX Receive Timing Parameters.........................192
Intel® LXT9785/LXT9785E RMII - 100BASE-FX Transmit Timing Parameters........................193
Intel® LXT9785/LXT9785E RMII - 10BASE-T Receive Timing Parameters .............................194
Intel® LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing Parameters ............................195
Intel® LXT9785/LXT9785E Auto-Negotiation and Fast Link Pulse Timing Parameters............196
Intel® LXT9785/LXT9785E MDIO Timing Parameters..............................................................197
Intel® LXT9785/LXT9785E Power-Up Timing Parameters .......................................................198
Intel® LXT9785/LXT9785E Reset Recovery Timing Parameters .............................................198
Intel® LXT9785/LXT9785E Register Set...................................................................................199
Control Register (Address 0) ....................................................................................................200
Status Register (Address 1)......................................................................................................201
PHY Identification Register 1 (Address 2) ................................................................................203
PHY Identification Register 2 (Address 3) ................................................................................203
Auto-Negotiation Advertisement Register (Address 4) .............................................................204
Auto-Negotiation Link Partner Base Page Ability Register (Address 5) ...................................205
Auto-Negotiation Expansion Register (Address 6) ...................................................................206
Auto-Negotiation Next Page Transmit Register (Address 7) ....................................................206
Auto-Negotiation Link Partner Next Page Receive Register (Address 8).................................207
Port Configuration Register (Address 16, Hex 10) ...................................................................207
Quick Status Register (Address 17, Hex 11) ............................................................................209
Interrupt Enable Register (Address 18, Hex 12).......................................................................211
Interrupt Status Register (Address 19, Hex 13)........................................................................212
LED Configuration Register (Address 20, Hex 14) ...................................................................213
Receive Error Count Register (Address 21, Hex 15)................................................................214
RMII Out-of-Band Signaling Register (Address 25, Hex 19) ....................................................215
Trim Enable Register (Address 27, Hex 1B).............................................................................216
Cable Diagnostics Register (Address 29, Hex 1D)...................................................................217
Intel® LXT9785/LXT9785E Register Bit Map............................................................................219
Intel® LXT9785MBC 196-Ball BGA15 Package Dimensions ...................................................226
Product Information ..................................................................................................................227
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
9
Contents
Revision History
Revision Number: 007
Revision Date: August 28, 2003
Page
10
Description
21
Modified Figure 2 “Intel® LXT9785 and Intel® LXT9785E RMII 208-Pin PQFP Assignments”.
22
Modified Table 2 “Intel® LXT9785/LXT9785E RMII PQFP Pin List”.
26
Modified Figure 3 “Intel® LXT9785/LXT9785E SMII 208-Pin PQFP Assignments”.
27
Modified Table 3 “Intel® LXT9785/LXT9785E SMII PQFP Pin List”.
31
Modified Figure 4 “Intel® LXT9785/LXT9785E SS-SMII 208-Pin PQFP Assignments”.
32
Modified Table 4 “Intel® LXT9785/LXT9785 SS-SMII PQFP Pin List”.
36
Modified Table 5 “Intel® LXT9785/LXT9785E RMII Signal Descriptions – PQFP”.
40
Modified Table 8 “Intel® LXT9785/LXT9785E SS-SMII Specific Signal Descriptions – PQFP”.
43
Modified Table 13 “Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP”.
50
Modified Table 16 “Intel® LXT9785/LXT9785E Unused/Reserved Pins – PQFP”.
51
Replaced old Figures 5, 6, and 7 with Figure 5 “Intel® LXT9785/LXT9785E 241-Ball BGA23
Assignments (Top View)”.
52
Modified Table 18 “Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by
Signal Name”.
57
Modified Table 19 “Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Ball
Location”.
62
Modified Table 20 “Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by
Signal Name”.
67
Modified Table 21 “Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball
Location”
72
Modified Table 22 “Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by
Signal Name”.
77
Modified Table 23 “Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by
Ball Location”.
82
Modified Table 23 “Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by
Ball Location”.
86
Modified Table 27 “Intel® LXT9785/LXT9785E SS-SMII Specific Signal Descriptions – BGA23”.
90
Modified Table 32 “Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23”.
97
Modified Table 35 “Intel® LXT9785/LXT9785E Unused/Reserved Pins – BGA23”.
98
Added Section 3.5, “BGA15 Ball Assignments” (including Figure 6 “Intel® LXT9785MBC 196-Ball
BGA15 Assignments (Top View)”, Table 37 “Intel® LXT9785MBC BGA15 Ball List in Alphanumeric
Order by Signal Name” through Table 39 “Intel® LXT9785 BGA15 Signal Descriptions”.
116
Added second paragraph under Section 4.1, “Introduction”.
117
Added note under Section 4.1.2.1, “Sectionalization”.
119
Added note under Table 40 “Intel® LXT9785/LXT9785E MDIX Selection”.
119
Added note under Section 4.3, “Media Independent Interface (MII) Interfaces”.
120
Added note to Table 41 “Intel® LXT9785/LXT9785E MII Mode Select”.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Contents
Revision Number: 007
Revision Date: August 28, 2003
Page
Description
120
Modified/added text under Section 4.3.2, “Internal Loopback”.
121
Modified text under Section 4.3.6, “MII Isolate”.
121
Section 4.3.7, “MDIO Management Interface”:
Added note under second paragraph.
Added last paragraph.
123
Added note under Section 4.3.8, “MII Sectionalization”.
124
Added new Section 4.3.11, “FIFO Initial Fill Values”
125
Modified paragraph three under Section 4.4.1, “Power Requirements”.
127
Added notes under second and last paragraphs under Section 4.5.3, “Power-Down Mode”.
128
Modified last bullet under Section 4.5.3.1, “Global (Hardware) Power Down”.
128
Added last paragraph to Section 4.5.4, “Reset”.
129
Modified Table 42 “Intel® LXT9785/9785E Global Hardware Configuration Settings”.
130
Change heading and modified last line under Section 4.6.1.2, “Manual Next Page Exchange”.
130
Section 4.6.1.4, “Link Criteria”:
Changed scrambler to descrambler in first line.
Modified second paragraph.
Added two new paragraphs.
131
Added second paragraph under Section 4.6.1.5, “Parallel Detection”.
131
Modified paragraphs under Section 4.6.1.6, “Reliable Link Establishment While Auto MDI/MDIX is
Enabled in Forced Speed Mode”.
136
Changed “1110” to “0101” under Section 4.7.4.3, “Receive Error”.
141
Added note under first paragraph of Section 4.8, “RMII Operation”
148
Changed “asynchronously” to “synchronously” in second paragraph under Section 4.9.3.3, “Carrier
Sense/Data Valid (RMII)”.
148
Modified last sentence in first paragraph under Section 4.9.3.4, “Carrier Sense (SMII)”.
149
Modified paragraph under Section 4.9.3.6.3, “Polarity Correction”.
149
Added note under Section 4.9.3.7, “Fiber PMD Sublayer”.
149
Added second paragraph under Section 4.9.3.7.1, “Far End Fault Indications”.
150
Modified/added text under Section 4.10.1, “Preamble Handling”.
151
Modified text under Section 4.10.4, “Jabber”.
152
Modified first paragraph under Section 4.11, “DTE Discovery Process”.
153
Modified Item 1 of Section 4.11.2, “Interaction between Processor, MAC, and PHY”.
154
Modified second paragraph under Section 4.11.4, “DTE Discovery Process Flow”.
155
Added Section 4.11.5, “DTE Discovery Behavior”
157
Added BGA15 information into first paragraph under Section 4.12.2, “Per-Port LED Driver
Functions”.
158
Added last sentence to first paragraph and note under first paragraph under Section 4.12.3, “Out-ofBand Signaling”.
160
Added Section 4.13, “Cable Diagnostics Overview”.
161
Modified/added text under Section 4.13.3, “Implementation Considerations”.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
11
Contents
Revision Number: 007
Revision Date: August 28, 2003
Page
12
Description
162
Added Section 4.14, “Link Hold-Off Overview”.
173
Modified Table 52 “Intel® LXT9785/LXT9785E Operating Conditions”
176
Modified Table 58 “Intel® LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics”
178195
Added note to Table 60 “Intel® LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing
Parameters” through Table 77 “Intel® LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing
Parameters”.
178
Added table note to Table 60 “Intel® LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing
Parameters”.
184
Added table note to Table 66 “Intel® LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing
Parameters”.
190
Added table note to Table 72 “Intel® LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing
Parameters”
198
Added software power-down and note to Table 80 “Intel® LXT9785/LXT9785E Power-Up Timing
Parameters”.
199
Modified paragraphs and added last paragraph under Section 7.0, “Register Definitions”.
199
Modified Table 82 “Intel® LXT9785/LXT9785E Register Set”.
200
Modified Table 83 “Control Register (Address 0)”.
201
Modified Table 84 “Status Register (Address 1)”.
203
Modified Table 85 “PHY Identification Register 1 (Address 2)”.
203
Modified Table 86 “PHY Identification Register 2 (Address 3)”
204
Modified Table 87 “Auto-Negotiation Advertisement Register (Address 4)”
205
Modified Table 88 “Auto-Negotiation Link Partner Base Page Ability Register (Address 5)”.
206
Modified Table 89 “Auto-Negotiation Expansion Register (Address 6)”.
206
Modified Table 90 “Auto-Negotiation Next Page Transmit Register (Address 7)”.
206
Modified Table 91 “Auto-Negotiation Link Partner Next Page Receive Register (Address 8)”.
207
Modified Table 92 “Port Configuration Register (Address 16, Hex 10)”. (Register bits 16.6, 16.4:3)
209
Modified Table 93 “Quick Status Register (Address 17, Hex 11)”. (Register bit 17.8)
211
Modified Table 94 “Interrupt Enable Register (Address 18, Hex 12)”
212
Modified Table 95 “Interrupt Status Register (Address 19, Hex 13)”
213
Modified Table 96 “LED Configuration Register (Address 20, Hex 14)”
214
Modified Table 97 “Receive Error Count Register (Address 21, Hex 15)”.
215
Modified Table 98 “RMII Out-of-Band Signaling Register (Address 25, Hex 19)”.
216
Modified Table 99 “Trim Enable Register (Address 27, Hex 1B)”. (Register bit 27.6)
217
Added Table 100 “Cable Diagnostics Register (Address 29, Hex 1D)”.
219
Modified Table 101 “Intel® LXT9785/LXT9785E Register Bit Map”.
226
Added Figure 102 “Intel® LXT9785MBC 196-Ball BGA15 Package Dimensions”
227
Modified table and figure under Section 9.0, “Ordering Information”.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Contents
Revision Number: 006 (INTERNAL RELEASE)
Revision Date: June 10, 2003
Page
Description
1
Changed "pseudo-ECL (PECL)" to "Low Voltage Positive Emitter Coupled Logic (LVPECL)" in the
second paragraph, front page.
36
Modified Table 5 “Intel® LXT9785/LXT9785E RMII Signal Descriptions – PQFP”. Added last
sentence to RXER0 through RXER7 signal description.
42
Modified Table 10 “Intel® LXT9785/LXT9785E Signal Detect – PQFP”.
42
Modified Table 11 “Intel® LXT9785/LXT9785E Network Interface Signal Descriptions – PQFP”,
43
Modified Table 13 “Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP”. Added
note to PREASEL signal description.
116
Modified Section 4.1, “Introduction”. Changed "Pseudo-ECL (PECL)" to "Low Voltage PECL
(LVPECL)" in the first paragraph, second sentence.
119
Replace text under Section 4.2.1.3, “Fiber Interface”.
120
Modified Section 4.3.2, “Internal Loopback”.
130
Modified last sentence under Section 4.6.1.4, “Link Criteria”.
131
Modified text under Section 4.6.1.5, “Parallel Detection”. Added second paragraph.
136
Modified text under Section 4.7.4.3, “Receive Error”.
145
Changed "PECL" to "LVPECL in third paragraph, first sentence under Section 4.9.1, “100BASE-X
Network Operations”.
146
Modified Figure 28 “Intel® LXT9785/LXT9785E Protocol Sublayers”.
148
Modified Section 4.9.3.3, “Carrier Sense/Data Valid (RMII)”. Changed “asynchronously to
“synchronously.”
148
Modified text under Section 4.9.3.4, “Carrier Sense (SMII)”. Revised last sentence in first paragraph.
149
Modified paragraph under Section 4.9.3.6.3, “Polarity Correction”.
149
Replaced text under Section 4.9.3.7, “Fiber PMD Sublayer”.
150
Modified Section 4.10.1, “Preamble Handling”. Added text to last paragraph.
151
Modified first sentence under Section 4.10.4, “Jabber”.
152
Modified first paragraph of Section 4.11, “DTE Discovery Process”.
153
Modified Item 1 of Section 4.11.2, “Interaction between Processor, MAC, and PHY”.
158
Modified Section 4.12.3, “Out-of-Band Signaling”. Added sentence to end of first paragraph.
166
Replaced text under Section 5.2.5, “The Fiber Interface”.
170
Replaced Figure 36 “Recommended Intel® LXT9785/LXT9785E-to-3.3 V Fiber Transceiver
Interface Circuitry”.
171
Replaced Figure 37 “Recommended Intel® LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface
Circuitry”.
173
Modified Table 52 “Intel® LXT9785/LXT9785E Operating Conditions”.
174
Modified Table 53 “Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO =
2.5 V +/- 5%)”.
175
Modified Table 54 “Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO =
3.3 V +/- 5%)”.
175
Added Table 55 “Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics – SD Pins”.
176
Modified Table 58 “Intel® LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics”.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
13
Contents
Revision Number: 006 (INTERNAL RELEASE)
Revision Date: June 10, 2003
Page
Description
200
Modified Table 83 “Control Register (Address 0)”.
201
Modified Table 84 “Status Register (Address 1)”.
204
Modified Table 87 “Auto-Negotiation Advertisement Register (Address 4)”.
205
Modified Table 88 “Auto-Negotiation Link Partner Base Page Ability Register (Address 5)”.
207
Modified Table 91 “Auto-Negotiation Link Partner Next Page Receive Register (Address 8)”.
207
Modified Table 92 “Port Configuration Register (Address 16, Hex 10)”.
209
Modified Table 93 “Quick Status Register (Address 17, Hex 11)”.
211
Modified Table 94 “Interrupt Enable Register (Address 18, Hex 12)”
212
Modified Table 95 “Interrupt Status Register (Address 19, Hex 13)”. Changed all references of RO/
SC to R/LH.
214
Modified Table 97 “Receive Error Count Register (Address 21, Hex 15)”.
215
Modified Table 98 “RMII Out-of-Band Signaling Register (Address 25, Hex 19)”. Added note to
Register bit 25.0.
216
Modified Table 99 “Trim Enable Register (Address 27, Hex 1B)”.
227
Modified Table 103 “Product Information”.
Revision Number: 005
Revision Date: January 2002
Page
14
Description
1
Added bullet to Product Features
49
Modified Table 12 “Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions” (Added
FIFOSEL1 and FIFOSEL0)
70
Added Section 2.6.1.6, “Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced
Speed Mode”
109
Modified Figure 38 “Recommended Intel® LXT9785/LXT9785E-to-3.3 V Fiber Transceiver
Interface Circuitry”
110
Added Figure 39 “Recommended Intel® LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface
Circuitry”
111
Added Figure 40 “ON Semiconductor Triple PECL-to-LVPECL Translator”
112
Modified Table 28 “Absolute Maximum Ratings”
112
Modified Table 29 “Operating Conditions”
114
Modified Table 31 “Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%)”(Output low
voltage SD pins - Max)
129
Modified Figure 53 “RMII - 100BASE-TX Receive Timing” and Table 49 “RMII - 100BASE-TX
Receive Timing Parameters”
131
Modified Figure 55 “RMII - 100BASE-FX Receive Timing” and Table 51 “RMII - 100BASE-FX
Receive Timing Parameters”
133
Modified Figure 57 “RMII - 10BASE-T Receive Timing” and Table 53 “RMII - 10BASE-T Receive
Timing Parameters”
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Contents
Revision Number: 005
Revision Date: January 2002
Page
Description
146
Modified Table 69 “Port Configuration Register (Address 16, Hex 10)” (Bits 16.5 and 16.6)
148
Modified Table 71 “Interrupt Enable Register (Address 18, Hex 12)”
168
Added product ordering table and diagram.
Revision Number: 003
Revision Date: April 2001
Page
Description
1
Modified and added new language to front page.
61
Reset: Modified language in first paragraph.
85
Added new section on DTE discovery.
93
Supported JTAG Instructions table: replaced long hit streams with hex.
97
LED Circuit: Modified paragraph language.
97
LED Circuit diagram: Modified diagram.
99
Replaced Typical Fiber Interface diagram.
102
Required Clock Characteristics table: Replaced SMII Input frequency and RMII Input frequency
symbol with “f”.
122
Auto-Negotiation and Fast Link Pulse Timing Parameters: FLP burst width under Typ = 2.
126
Control Register table: Modified table and table notes.
128
PHY Identification Register 2 (Address 3): Modified table.
128
PHY Identifier Bit Mapping: Modified diagram.
131
Auto-Negotiation Expansion: Modified table and table notes.
133
Port Configuration Register table: Modified table and table notes.
140
Trim Enable Register: Modified table (DTE Discovery).
141
Modified Register Bit Map table.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
15
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
1.0
Introduction
This document contains information on the Intel® LXT9785/LXT9785E Advanced 8-port
10/100 Mbps Fast Ethernet transceivers.
1.1
What You Will Find in This Document
This document contains the following sections:
• Section 3.0, “Pin/Ball Assignments and Signal Descriptions” on page 20
This section contains pin/ball assignments and signal descriptions for the following:
— Section 3.1, “PQFP Pin Assignments” on page 20
— Section 3.2, “PQFP Signal Descriptions” on page 36
— Section 3.3, “BGA23 Ball Assignments” on page 51
— Section 3.4, “BGA23 Signal Descriptions” on page 82
— Section 3.5, “BGA15 Ball Assignments” on page 98
— Section 3.6, “BGA15 Signal Descriptions” on page 109
•
•
•
•
•
•
1.2
Section 4.0, “Functional Description” on page 116
Section 5.0, “Application Information” on page 164
Section 6.0, “Test Specifications” on page 173
Section 7.0, “Register Definitions” on page 199
Section 8.0, “Package Specifications” on page 221
Section 9.0, “Ordering Information” on page 227
Related Documents
Document
Number
Document
Intel® LXT9785/LXT9785E Design and Layout Guide
249509
®
18
Intel LXT9785/LXT9785E Specification Update
249357
Intel® LXT9785/LXT9785E 100BASE-FX Fiber Optic Transceivers: Connecting a PECL/
LVPECL Interface
250781
IP Telephony and DTE Discovery Using Intel Ethernet® PHYs
249611
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
2.0
Block Diagram
Figure 1 provides the LXT9785/LXT9785E block diagram.
Figure 1. Intel® LXT9785/LXT9785E Block Diagram
8-Port Global
Functions
RMII/SMII Contr
ADD_<4:0>
MDIO
Management /
Mode Select
Logic & LED
Drivers
2
MDC
2
MDINT
RESET
PWRDN
Clock
Generator
REFCLK
SYNC (SMII only)
2
Register Set
Manchester
Encoder
TX PCS
TxDatan
Parallel/Serial
Converter
Scrambler
& Encoder
10
100
Pulse
Shaper
ECL
Driver
Auto
Negotiation
Mgmt
Counters
TP
Driver
+
TP /
Fiber
Out
+
Fiber
select n
Media
Select
Clock Generator
RX PCS
RxDatan
Port LED
Drivers
3
+
Adaptive EQ with BL
Wander Cancellation
100TX
-
Serial to
Parallel
Converter
Carrier Sense
Data Valid
Error Detect
TPFONn
-
Register Set
LEDn_<2:0>
TPFOPn
10
100
Manchester
Decoder
+
100FX
Slicer
-
Decoder &
Descrambler
TP /
Fiber In
TPFIPn
TPFINn
+
10BT
Per-Port Functions
PORT 0
-
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
19
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.0
Pin/Ball Assignments and Signal Descriptions
3.1
PQFP Pin Assignments
The following sections show PQFP pin assignments and signal descriptions:
• Section 3.1.1, “PQFP Pin Assignments – RMII Configuration” on page 21
• Section 3.1.2, “PQFP Pin Assignments – SMII Configuration” on page 26
• Section 3.1.3, “PQFP Pin Assignments – SS-SMII Configuration” on page 31
Table 1 lists the acronyms and descriptions for signal types.
Table 1.
Intel® LXT9785/LXT9785E Signal Type Descriptions
Acronym
20
Description
AI
Analog Input
AO
Analog Output
I
Input
O
Output
OD
Open Drain Output
ST
Schmitt Triggered Input
TS
Three-State-able Output
SL
Slew-rate Limited Output
IP
Weak Internal Pull-Up
ID
Weak Internal Pull-Down
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.1.1
PQFP Pin Assignments – RMII Configuration
Figure 2 and Table 2, “Intel® LXT9785/LXT9785E RMII PQFP Pin List” on page 22 provide
LXT9785/LXT9785 RMII PQFP pin assignments.
208 ........ VCCIO
207 ........ GNDIO
206 ........ RxData6_0
205 ........ RxData6_1
204 ........ TxData7_1
203 ........ TxData7_0
202 ........ TxEN7
201 ........ RxER7
200 ........ CRS_DV7
199 ........ GNDIO
198 ........ RxData7_0
197 ........ RxData7_1
196 ........ VCCD
195 ........ GNDD
194 ........ LED7_3
193 ........ LED7_2
192 ........ LED7_1
191 ........ LED6_3
190 ........ LED6_2
189 ........ LED6_1
188 ........ GNDIO
187 ........ LED5_3
186 ........ LED5_2
185 ........ LED5_1
184 ........ VCCD
183 ........ GNDD
182 ........ LED4_3
181 ........ LED4_2
180 ........ LED4_1
179 ........ SGND
178 ........ ModeSel1
177 ........ ModeSel0
176 ........ Section
175 ........ RESET
174 ........ PWRDWN
173 ........ G_FX/TP
172 ........ N/C
171....... TRST
170 ........ TCK
169 ........ TMS
168 ........ TDO
167 ........ TDI
166 ........ SD7
165 ........ SD6
164 ........ VCCPECL
163 ........ GNDPECL
162 ........ SD5
161 ........ SD4
160 ........ N/C
159 ........ N/C
158 ........ VCCR7
157 ........ TPFIP7
Figure 2. Intel® LXT9785 and Intel® LXT9785E RMII 208-Pin PQFP Assignments
Part #
LOT #
FPO #
LXT9785/9785E XX
XXXXXX
XXXXXXXX
Rev #
156 .........TPFIN7
155 .........GNDR7
154 .........TPFOP7
153 .........TPFON7
152 .........VCCT6/7
151 .........TPFON6
150 .........TPFOP6
149 .........GNDR6
148 .........GNDT6/7
147 .........TPFIN6
146 .........TPFIP6
145 .........VCCR6
144 .........VCCR5
143 .........TPFIP5
142 .........TPFIN5
141 .........GNDR5
140 .........TPFOP5
139 .........TPFON5
138 .........VCCT4/5
137 .........TPFON4
136 .........TPFOP4
135 .........GNDR4
134 .........GNDT4/5
133 .........TPFIN4
132 .........TPFIP4
131 .........VCCR4
130 .........VCCR3
129 .........TPFIP3
128 .........TPFIN3
127 .........GNDT2/3
126 .........GNDR3
125 .........TPFOP3
124 .........TPFON3
123 .........VCCT2/3
122 .........TPFON2
121 .........TPFOP2
120 .........GNDR2
119 .........TPFIN2
118 .........TPFIP2
117 .........VCCR2
116 .........VCCR1
115 .........TPFIP1
114 .........TPFIN1
113 .........GNDT0/1
112 .........GNDR1
111 .........TPFOP1
110 .........TPFON1
109 .........VCCT0/1
108 .........TPFON0
107 .........TPFOP0
106 .........GNDR0
105 .........TPFIN0
TxData1_1 ...... 53
RxData0_1 ...... 54
RxData0_0 ...... 55
VCCIO ...... 56
GNDIO ...... 57
CRS_DV0 ...... 58
RxER0/MDIX ...... 59
TxEN0 ...... 60
TxData0_0 ...... 61
TxData0_1 ...... 62
MDC0 ...... 63
MDIO0 ...... 64
VCCD ...... 65
GNDD ...... 66
MDINT0 ...... 67
LED3_3 ...... 68
LED3_2 ...... 69
LED3_1 ...... 70
LED2_3 ...... 71
LED2_2 ...... 72
LED2_1 ...... 73
GNDIO ...... 74
LED1_3 ...... 75
LED1_2 ...... 76
LED1_1 ...... 77
VCCD ...... 78
GNDD ...... 79
LED0_3 ...... 80
LED0_2 ...... 81
LED0_1 ...... 82
AMDIX_EN ...... 83
MDDIS ...... 84
CFG_3 ...... 85
CFG_2 ...... 86
CFG_1 ...... 87
ADD_4 ...... 88
ADD_3 ...... 89
ADD_2 ...... 90
ADD_1 ...... 91
ADD_0 ...... 92
TxSlew_1 ...... 93
TxSlew_0 ...... 94
SD_2P5V ...... 95
SD0 ...... 96
SD1 ...... 97
VCCPECL ...... 98
GNDPECL ...... 99
SD2 ...... 100
SD3 ...... 101
N/C ...... 102
VCCR0 ...... 103
TPFIP0 ...... 104
CRS_DV6.......1
RxER6/LINKHOLD..2
TxEN6.......3
TxData6_0.......4
TxData6_1.......5
REFCLK1.......6
RxData5_1.......7
RxData5_0.......8
GNDIO.......9
CRS_DV5.......10
RxER5/FIFOSEL1.....11
TxEN5.......12
TxData5_0.......13
TxData5_1.......14
RxData4_1.......15
RxData4_0.......16
CRS_DV4.......17
VCCIO.......18
GNDIO.......19
RxER4/FIFOSEL0.....20
TxEN4.......21
TxData4_0.......22
TxData4_1.......23
MDC1.......24
MDIO1.......25
MDINT1.......26
RxData3_1.......27
RxData3_0.......28
VCCIO.......29
GNDIO.......30
CRS_DV3.......31
RxER3.......32
TxEN3.......33
TxData3_0.......34
TxData3_1.......35
RxData2_1.......36
RxData2_0.......37
GNDIO.......38
CRS_DV2.......39
RxER2/PREASEL .....40
TxEN2.......41
TxData2_0.......42
TxData2_1.......43
REFCLK0.......44
RxData1_1.......45
RxData1_0.......46
VCCIO.......47
GNDIO.......48
CRS_DV1.......49
RxER1/PAUSE.......50
TxEN1.......51
TxData1_0.......52
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
21
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 2.
Intel® LXT9785/LXT9785E RMII PQFP Pin List
Symbol
Type
Reference for Full
Description
1
CRS_DV6
O, TS,
SL
Table 5 (page 36)
2
RxER6/
LINKHOLD
O, TS,
SL, ID,
I, ST
Table 5 (page 36)
3
TxEN6
I, ID
Table 5 (page 36)
4
TxData6_0
I, ID
Table 5 (page 36)
5
TxData6_1
I, ID
Table 5 (page 36)
6
REFCLK1
I
Table 5 (page 36)
7
RxData5_1
O, TS,
ID
Table 5 (page 36)
8
RxData5_0
O, TS
Table 5 (page 36)
9
GNDIO
–
Table 15 (page 48)
10
CRS_DV5
O, TS,
SL
Table 5 (page 36)
11
RxER5 /
FIFOSEL1
O, TS,
SL, ID,
I, ST
Table 5 (page 36)
12
TxEN5
I, ID
Table 5 (page 36)
13
TxData5_0
I, ID
Table 5 (page 36)
14
TxData5_1
I, ID
Table 5 (page 36)
15
RxData4_1
O,
TS,ID
Table 5 (page 36)
16
RxData4_0
O, TS
Table 5 (page 36)
17
CRS_DV4
O, TS,
SL
Table 5 (page 36)
Pin
22
Pin
Symbol
Type
Reference for Full
Description
30
GNDIO
–
Table 15 (page 48)
31
CRS_DV3
O, TS,
SL
Table 5 (page 36)
32
RxER3
O, TS,
SL, ID
Table 5 (page 36)
33
TxEN3
I, ID
Table 5 (page 36)
34
TxData3_0
I, ID
Table 5 (page 36)
35
TxData3_1
I, ID
Table 5 (page 36)
36
RxData2_1
O, TS,
ID
Table 5 (page 36)
37
RxData2_0
O, TS
Table 5 (page 36)
38
GNDIO
–
Table 15 (page 48)
39
CRS_DV2
O, TS,
SL
Table 5 (page 36)
40
RxER2
(PREASEL)
O, TS,
SL, ID,
I, ST
Table 5 (page 36)
41
TxEN2
I, ID
Table 5 (page 36)
42
TxData2_0
I, ID
Table 5 (page 36)
43
TxData2_1
I, ID
Table 5 (page 36)
44
REFCLK0
I
Table 5 (page 36)
45
RxData1_1
O, TS,
ID
Table 5 (page 36)
46
RxData1_0
O, TS
Table 5 (page 36)
47
VCCIO
–
Table 15 (page 48)
GNDIO
–
Table 15 (page 48)
18
VCCIO
–
Table 15 (page 48)
48
19
GNDIO
–
Table 15 (page 48)
49
CRS_DV1
O, TS,
SL
Table 5 (page 36)
20
RxER4 /
FIFOSEL0
O, TS,
SL, ID,
I, ST
Table 5 (page 36)
50
RxER1/
PAUSE
O, TS,
SL, ID,
I, ST
Table 5 (page 36)
21
TxEN4
I, ID
Table 5 (page 36)
51
TxEN1
I, ID
Table 5 (page 36)
22
TxData4_0
I, ID
Table 5 (page 36)
52
TxData1_0
I, ID
Table 5 (page 36)
23
TxData4_1
I, ID
Table 5 (page 36)
53
TxData1_1
I, ID
Table 5 (page 36)
24
MDC1
I, ST, ID
Table 8 (page 40)
RxData0_1
Table 8 (page 40)
O, TS,
ID
Table 5 (page 36)
MDIO1
I/O, TS,
SL, IP
54
25
55
RxData0_0
O, TS
Table 5 (page 36)
26
MDINT1
OD, TS,
SL, IP
Table 8 (page 40)
56
VCCIO
–
Table 15 (page 48)
27
RxData3_1
O, TS,
ID
Table 5 (page 36)
57
GNDIO
–
Table 15 (page 48)
28
RxData3_0
O, TS
Table 5 (page 36)
58
CRS_DV0
O, TS,
SL
Table 5 (page 36)
29
VCCIO
–
Table 15 (page 48)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Pin
Symbol
Type
Reference for Full
Description
87
CFG_1
I, ST, ID
Table 13 (page 43)
88
ADD_4
I, ST, ID
Table 13 (page 43)
Table 5 (page 36)
89
ADD_3
I, ST, ID
Table 13 (page 43)
Table 5 (page 36)
90
ADD_2
I, ST, ID
Table 13 (page 43)
ADD_1
I, ST, ID
Table 13 (page 43)
Pin
Symbol
Type
Reference for Full
Description
59
RxER0/
MDIX
O, TS,
SL, ID,
I, ST
Table 5 (page 36)
60
TxEN0
I, ID
61
TxData0_0
I, ID
62
TxData0_1
I, ID
Table 5 (page 36)
91
63
MDC0
I, ST, ID
Table 8 (page 40)
92
ADD_0
I, ST, ID
Table 13 (page 43)
64
MDIO0
I/O, TS,
SL, IP
Table 8 (page 40)
93
TxSLEW_1
I, ST, ID
Table 13 (page 43)
94
TxSLEW_0
I, ST, ID
Table 13 (page 43)
65
VCCD
–
Table 15 (page 48)
95
SD_2P5V
I, ST, ID
Table 10 (page 42)
66
GNDD
–
Table 15 (page 48)
96
SD0
I
Table 10 (page 42)
67
MDINT0
OD, TS,
SL, IP
Table 8 (page 40)
97
SD1
I
Table 10 (page 42)
VCCPECL
–
Table 15 (page 48)
LED3_3
OD, TS,
SO, IP
98
68
Table 14 (page 47)
99
GNDPECL
–
Table 15 (page 48)
69
LED3_2
OD, TS,
SL, IP
Table 14 (page 47)
100
SD2
I
Table 10 (page 42)
101
SD3
I
Table 10 (page 42)
70
LED3_1
OD, TS,
SL, IP
Table 14 (page 47)
102
N/C
–
Table 17 (page 50)
103
VCCR0
–
Table 15 (page 48)
104
TPFIP0
AO/AI
Table 11 (page 42)
105
TPFIN0
AO/AI
Table 11 (page 42)
106
GNDR0
–
Table 15 (page 48)
107
TPFOP0
AO/AI
Table 11 (page 42)
108
TPFON0
AO/AI
Table 11 (page 42)
109
VCCT0/1
–
Table 15 (page 48)
110
TPFON1
AO/AI
Table 11 (page 42)
111
TPFOP1
AO/AI
Table 11 (page 42)
112
GNDR1
–
Table 15 (page 48)
113
GNDT0/1
–
Table 15 (page 48)
LED2_3
OD, TS,
SL, IP
Table 14 (page 47)
72
LED2_2
OD, TS,
SL, IP
Table 14 (page 47)
73
LED2_1
OD, TS,
SL, IP
Table 14 (page 47)
74
GNDIO
–
Table 15 (page 48)
75
LED1_3
OD, TS,
SL, IP
Table 14 (page 47)
76
LED1_2
OD, TS,
SL, IP
Table 14 (page 47)
77
LED1_1
OD, TS,
SL, IP
Table 14 (page 47)
78
VCCD
–
Table 15 (page 48)
114
TPFIN1
AO/AI
Table 11 (page 42)
79
GNDD
–
Table 15 (page 48)
115
TPFIP1
AO/AI
Table 11 (page 42)
80
LED0_3
OD, TS,
SL, IP
Table 14 (page 47)
116
VCCR1
–
Table 15 (page 48)
VCCR2
–
Table 15 (page 48)
LED0_2
OD, TS,
SL, IP
117
81
Table 14 (page 47)
118
TPFIP2
AO/AI
Table 11 (page 42)
82
LED0_1
OD, TS,
SL, IP
Table 14 (page 47)
119
TPFIN2
AO/AI
Table 11 (page 42)
120
GNDR2
–
Table 15 (page 48)
83
AMDIX_EN
I, ST, IP
Table 13 (page 43)
121
TPFOP2
AO/AI
Table 11 (page 42)
84
MDDIS
I, ST, ID
Table 9 (page 41)
85
CFG_3
I, ST, ID
Table 13 (page 43)
86
CFG_2
I, ST, ID
Table 13 (page 43)
71
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
122
TPFON2
AO/AI
Table 11 (page 42)
123
VCCT2/3
–
Table 15 (page 48)
124
TPFON3
AO/AI
Table 11 (page 42)
23
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Pin
Symbol
Type
Reference for Full
Description
Pin
Symbol
Type
Reference for Full
Description
125
TPFOP3
AO/AI
Table 11 (page 42)
163
GNDPECL
–
Table 15 (page 48)
126
GNDR3
–
Table 15 (page 48)
164
VCCPECL
–
Table 15 (page 48)
127
GNDT2/3
–
Table 15 (page 48)
165
SD6
I
Table 10 (page 42)
128
TPFIN3
AO/AI
Table 11 (page 42)
166
SD7
I
Table 10 (page 42)
129
TPFIP3
AO/AI
Table 11 (page 42)
167
TDI
I, ST, IP
Table 12 (page 43)
130
VCCR3
–
Table 15 (page 48)
168
TDO
O, TS
Table 12 (page 43)
131
VCCR4
–
Table 15 (page 48)
169
TMS
I, ST, IP
Table 12 (page 43)
132
TPFIP4
AO/AI
Table 11 (page 42)
170
TCK
I, ST, ID
Table 12 (page 43)
133
TPFIN4
AO/AI
Table 11 (page 42)
171
TRST
I, ST, IP
Table 12 (page 43)
134
GNDT4/5
–
Table 15 (page 48)
172
N/C
–
Table 17 (page 50)
135
GNDR4
–
Table 15 (page 48)
173
G_FX/TP
I, ST, ID
Table 13 (page 43)
136
TPFOP4
AO/AI
Table 11 (page 42)
174
PWRDWN
I, ST, ID
Table 13 (page 43)
137
TPFON4
AO/AI
Table 11 (page 42)
175
RESET
I, ST, IP
Table 13 (page 43)
138
VCCT4/5
–
Table 15 (page 48)
176
SECTION
I, ST, ID
Table 13 (page 43)
139
TPFON5
AO/AI
Table 11 (page 42)
177
ModeSel0
I, ST, ID
Table 13 (page 43)
140
TPFOP5
AO/AI
Table 11 (page 42)
178
ModeSel1
I, ST, ID
Table 13 (page 43)
141
GNDR5
–
Table 15 (page 48)
179
SGND
–
Table 15 (page 48)
142
TPFIN5
AO/AI
Table 11 (page 42)
180
LED4_1
Table 14 (page 47)
143
TPFIP5
AO/AI
Table 11 (page 42)
OD, TS,
SL, IP
144
VCCR5
–
Table 15 (page 48)
181
LED4_2
OD, TS,
SL, IP
Table 14 (page 47)
145
VCCR6
–
Table 15 (page 48)
146
TPFIP6
AO/AI
Table 11 (page 42)
182
LED4_3
OD, TS,
SL, IP
Table 14 (page 47)
147
TPFIN6
AO/AI
Table 11 (page 42)
183
GNDD
–
Table 15 (page 48)
148
GNDT6/7
–
Table 15 (page 48)
184
VCCD
–
Table 15 (page 48)
149
GNDR6
–
Table 15 (page 48)
185
LED5_1
OD, TS,
SL, IP
Table 14 (page 47)
150
TPFOP6
AO/AI
Table 11 (page 42)
151
TPFON6
AO/AI
Table 11 (page 42)
186
LED5_2
OD, TS,
SL, IP
Table 14 (page 47)
187
LED5_3
OD, TS,
SL, IP
Table 14 (page 47)
188
GNDIO
–
Table 15 (page 48)
189
LED6_1
OD, TS,
SL, IP
Table 14 (page 47)
190
LED6_2
OD, TS,
SL, IP
Table 14 (page 47)
191
LED6_3
OD, TS,
SL, IP
Table 14 (page 47)
192
LED7_1
OD, TS,
SL, IP
Table 14 (page 47)
193
LED7_2
OD, TS,
SL, IP
Table 14 (page 47)
152
VCCT6/7
–
Table 15 (page 48)
153
TPFON7
AO/AI
Table 11 (page 42)
154
TPFOP7
AO/AI
Table 11 (page 42)
155
24
GNDR7
–
Table 15 (page 48)
156
TPFIN7
AO/AI
Table 11 (page 42)
157
TPFIP7
AO/AI
Table 11 (page 42)
158
VCCR7
–
Table 15 (page 48)
159
N/C
–
Table 17 (page 50)
160
N/C
–
Table 17 (page 50)
161
SD4
I
Table 10 (page 42)
162
SD5
I
Table 10 (page 42)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Pin
Symbol
Type
Reference for Full
Description
194
LED7_3
OD, TS,
SL, IP
Table 5 (page 36)
195
GNDD
–
Table 15 (page 48)
196
VCCD
–
Table 15 (page 48)
197
RxData7_1
O, TS,
ID
Table 5 (page 36)
198
RxData7_0
O, TS
Table 5 (page 36)
199
GNDIO
–
Table 15 (page 48)
200
CRS_DV7
O, TS,
SL
Table 5 (page 36)
201
RxER7
O, TS,
SL, ID
Table 5 (page 36)
202
TxEN7
I, ID
Table 5 (page 36)
203
TxData7_0
I, ID
Table 5 (page 36)
204
TxData7_1
I, ID
Table 5 (page 36)
205
RxData6_1
O, TS,
ID
Table 5 (page 36)
206
RxData6_0
O, TS
Table 5 (page 36)
207
GNDIO
–
Table 15 (page 48)
208
VCCIO
–
Table 15 (page 48)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
25
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.1.2
PQFP Pin Assignments – SMII Configuration
Figure 3 and Table 3, “Intel® LXT9785/LXT9785E SMII PQFP Pin List” on page 27 provide the
LXT9785/LXT9785E SMII PQFP pin assignments.
208 ........ VCCIO
207 ........ GNDIO
206 ........ RxData6
205 ........ N/C
204 ........ SYNC1
203 ........ TxData7
202 ........ N/C
201 ........ N/C
200 ........ N/C
199 ........ GNDIO
198 ........ RxData7
197 ........ N/C
196 ........ VCCD
195 ........ GNDD
194 ........ LED7_3
193 ........ LED7_2
192 ........ LED7_1
191 ........ LED6_3
190 ........ LED6_2
189 ........ LED6_1
188 ........ GNDIO
187 ........ LED5_3
186 ........ LED5_2
185 ........ LED5_1
184 ........ VCCD
183 ........ GNDD
182 ........ LED4_3
181 ........ LED4_2
180 ........ LED4_1
179 ........ SGND
178 ........ ModeSel_1
177 ........ ModeSel_0
176 ........ Section
175 ........ RESET
174 ........ PWRDWN
173 ........ G_FX/TP
172 ........ N/C
171....... TRST
170 ........ TCK
169 ........ TMS
168 ........ TDO
167 ........ TDI
166 ........ SD7
165 ........ SD6
164 ........ VCCPECL
163 ........ GNDPECL
162 ........ SD5
161 ........ SD4
160 ........ N/C
159 ........ N/C
158 ........ VCCR7
157 ........ TPFIP7
Figure 3. Intel® LXT9785/LXT9785E SMII 208-Pin PQFP Assignments
N/C.......1
.......2
N/C.......3
TxData6.......4
N/C.......5
REFCLK1.......6
N/C.......7
RxData5.......8
GNDIO.......9
N/C.......10
FIFOSEL1.......11
N/C.......12
TxData5.......13
N/C.......14
N/C.......15
RxData4.......16
N/C.......17
VCCIO.......18
GNDIO.......19
FIFOSEL0.......20
N/C.......21
TxData4.......22
N/C.......23
MDC1.......24
MDIO1.......25
MDINT1.......26
N/C.......27
RxData3.......28
VCCIO.......29
GNDIO.......30
N/C.......31
N/C.......32
N/C.......33
TxData3.......34
SYNC0.......35
N/C.......36
RxData2.......37
GNDIO.......38
N/C.......39
PREASEL.......40
N/C.......41
TxData2.......42
N/C.......43
REFCLK0.......44
N/C.......45
RxData1.......46
VCCIO.......47
GNDIO.......48
N/C.......49
PAUSE.......50
N/C.......51
TxData1.......52
LINKHOLD
LXT9785/9785E XX
XXXXXX
XXXXXXXX
Rev #
N/C ...... 53
N/C ...... 54
RxData0 ...... 55
VCCIO ...... 56
GNDIO ...... 57
N/C ...... 58
MDIX ...... 59
N/C ...... 60
TxData0 ...... 61
N/C ...... 62
MDC0 ...... 63
MDIO0 ...... 64
VCCD ...... 65
GNDD ...... 66
MDINT0 ...... 67
LED3_3 ...... 68
LED3_2 ...... 69
LED3_1 ...... 70
LED2_3 ...... 71
LED2_2 ...... 72
LED2_1 ...... 73
GNDIO ...... 74
LED1_3 ...... 75
LED1_2 ...... 76
LED1_1 ...... 77
VCCD ...... 78
GNDD ...... 79
LED0_3 ...... 80
LED0_2 ...... 81
LED0_1 ...... 82
AMDIX_EN ...... 83
MDDIS ...... 84
CFG_3 ...... 85
CFG_2 ...... 86
CFG_1 ...... 87
ADD_4 ...... 88
ADD_3 ...... 89
ADD_2 ...... 90
ADD_1 ...... 91
ADD_0 ...... 92
TxSlew_1 ...... 93
TxSlew_0 ...... 94
SD_2P5V ...... 95
SD0 ...... 96
SD1 ...... 97
VCCPECL ...... 98
GNDPECL ...... 99
SD2 ...... 100
SD3 ...... 101
N/C ...... 102
VCCR0 ...... 103
TPFIP0 ...... 104
Part #
LOT #
FPO #
156 ........ TPFIN7
155 ........ GNDR7
154 ........ TPFOP7
153 ........ TPFON7
152 ........ VCCT6/7
151 ........ TPFON6
150 ........ TPFOP6
149 ........ GNDR6
148 ........ GNDT6/7
147 ........ TPFIN6
146 ........ TPFIP6
145 ........ VCCR6
144 ........ VCCR5
143 ........ TPFIP5
142 ........ TPFIN5
141 ........ GNDR5
140 ........ TPFOP5
139 ........ TPFON5
138 ........ VCCT4/5
137 ........ TPFON4
136 ........ TPFOP4
135 ........ GNDR4
134 ........ GNDT4/5
133 ........ TPFIN4
132 ........ TPFIP4
131 ........ VCCR4
130 ........ VCCR3
129 ........ TPFIP3
128 ........ TPFIN3
127 ........ GNDT2/3
126 ........ GNDR3
125 ........ TPFOP3
124 ........ TPFON3
123 ........ VCCT2/3
122 ........ TPFON2
121 ........ TPFOP2
120 ........ GNDR2
119 ........ TPFIN2
118 ........ TPFIP2
117 ........ VCCR2
116 ........ VCCR1
115 ........ TPFIP1
114 ........ TPFIN1
113 ........ GNDT0/1
112 ........ GNDR1
111 ........ TPFOP1
110 ........ TPFON1
109 ........ VCCT0/1
108 ........ TPFON0
107 ........ TPFOP0
106 ........ GNDR0
105 ........ TPFIN0
26
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 3.
Intel® LXT9785/LXT9785E SMII PQFP Pin List
Pin
Symbol
1
N/C
2
N/C
(LINKHOLD)
3
N/C
4
TxData6
5
Type1
–
–
I, ID,
Reference for Full
Description
Pin
Symbol
Type1
Table 16 (page 50)
34
TxData3
I, ID
Table 6 (page 39)
35
SYNC0
I, ID
Table 7 (page 39)
Table 16 (page 50)
Reference for Full
Description
36
N/C
–
Table 16 (page 50)
–
Table 16 (page 50)
37
RxData2
O, TS
Table 6 (page 39)
I, ID
Table 6 (page 39)
38
GNDIO
–
Table 15 (page 48)
N/C
–
Table 16 (page 50)
39
N/C
–
Table 16 (page 50)
6
REFCLK1
I
Table 5 (page 36)
7
N/C
–
Table 16 (page 50)
40
PREASEL
I, ID,
ST
Table 16 (page 50)
8
RxData5
O, TS
Table 6 (page 39)
41
N/C
TxData2
–
Table 16 (page 50)
I, ID
Table 6 (page 39)
9
GNDIO
–
Table 15 (page 48)
42
10
N/C
–
Table 16 (page 50)
43
N/C
–
Table 16 (page 50)
11
FIFOSEL1
I, ID,
ST
Table 16 (page 50)
44
REFCLK0
I
Table 5 (page 36)
45
N/C
12
N/C
–
Table 16 (page 50)
46
RxData1
13
TxData5
I, ID
Table 6 (page 39)
47
14
N/C
–
Table 16 (page 50)
15
N/C
–
Table 16 (page 50)
16
RxData4
O, TS
Table 6 (page 39)
17
N/C
–
Table 16 (page 50)
18
VCCIO
–
19
GNDIO
20
–
Table 16 (page 50)
O, TS
Table 6 (page 39)
VCCIO
–
Table 15 (page 48)
48
GNDIO
–
Table 15 (page 48)
49
N/C
50
PAUSE
Table 15 (page 48)
51
N/C
–
Table 15 (page 48)
52
TxData1
FIFOSEL0
I, ID,
ST
Table 16 (page 50)
53
N/C
54
N/C
21
N/C
I, ID
Table 16 (page 50)
55
RxData0
22
TxData4
I, ID
Table 6 (page 39)
56
23
N/C
–
Table 16 (page 50)
24
MDC1
I, ST, ID
Table 9 (page 41)
25
MDIO1
I/O, TS,
SL, IP
Table 9 (page 41)
26
MDINT1
OD,
TS, SL,
IP
Table 9 (page 41)
–
27
N/C
Table 13 (page 43)
–
Table 16 (page 50)
I, ID
Table 6 (page 39)
–
Table 16 (page 50)
–
Table 16 (page 50)
O, TS
Table 6 (page 39)
VCCIO
–
Table 15 (page 48)
57
GNDIO
–
Table 15 (page 48)
58
N/C
–
Table 16 (page 50)
I, ID,
ST
Table 13 (page 43)
–
Table 16 (page 50)
I, ID
Table 6 (page 39)
–
Table 16 (page 50)
MDIX
60
N/C
61
TxData0
Table 16 (page 50)
62
N/C
63
MDC0
I, ST, ID
Table 9 (page 41)
64
MDIO0
I/O, TS,
SL, IP
Table 9 (page 41)
65
VCCD
–
Table 15 (page 48)
66
GNDD
–
Table 15 (page 48)
67
MDINT0
OD,
TS, SL,
IP
Table 9 (page 41)
RxData3
O, TS
Table 6 (page 39)
29
VCCIO
–
Table 15 (page 48)
30
GNDIO
–
Table 15 (page 48)
31
N/C
–
Table 16 (page 50)
32
N/C
–
Table 16 (page 50)
33
N/C
–
Table 16 (page 50)
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Table 16 (page 50)
59
28
Datasheet
–
I, ID,
ST
27
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Pin
Symbol
Type1
Reference for Full
Description
68
LED3_3
OD,
TS,
SO, IP
Table 14 (page 47)
69
LED3_2
OD,
TS, SL,
IP
Table 14 (page 47)
70
71
72
Table 14 (page 47)
LED2_3
OD,
TS, SL,
IP
Table 14 (page 47)
OD,
TS, SL,
IP
Table 14 (page 47)
LED2_2
73
LED2_1
OD,
TS, SL,
IP
Table 14 (page 47)
74
GNDIO
–
Table 15 (page 48)
75
LED1_3
OD,
TS, SL,
IP
Table 14 (page 47)
76
77
LED1_2
OD,
TS, SL,
IP
Table 14 (page 47)
LED1_1
OD,
TS, SL,
IP
Table 14 (page 47)
Symbol
Type1
92
ADD_0
I, ST, ID Table 13 (page 43)
93
TxSLEW_1
I, ST, ID
Table 13 (page 43)
94
TxSLEW_0
I, ST, ID
Table 13 (page 43)
95
SD_2P5V
I, ST, ID Table 10 (page 42)
96
SD0
I
Table 10 (page 42)
97
SD1
I
Table 10 (page 42)
98
VCCPECL
–
Table 15 (page 48)
99
GNDPECL
–
Table 15 (page 48)
100
SD2
I
Table 10 (page 42)
101
SD3
I
Table 10 (page 42)
102
N/C
–
Table 17 (page 50)
103
VCCR0
–
Table 15 (page 48)
104
TPFIP0
AI/AO
Table 11 (page 42)
105
TPFIN0
AI/AO
Table 11 (page 42)
106
GNDR0
–
Table 15 (page 48)
107
TPFOP0
AO/AI
Table 11 (page 42)
108
TPFON0
AO/AI
Table 11 (page 42)
109
VCCT0/1
–
Table 15 (page 48)
110
TPFON1
AO/AI
Table 11 (page 42)
111
TPFOP1
AO/AI
Table 11 (page 42)
112
GNDR1
–
Table 15 (page 48)
–
Table 15 (page 48)
78
VCCD
–
Table 15 (page 48)
113
GNDT0/1
79
GNDD
–
Table 15 (page 48)
114
TPFIN1
AI/AO
Table 11 (page 42)
OD,
TS, SL,
IP
Table 14 (page 47)
115
TPFIP1
AI/AO
Table 11 (page 42)
116
VCCR1
–
Table 15 (page 48)
117
VCCR2
–
Table 15 (page 48)
118
TPFIP2
AI/AO
Table 11 (page 42)
80
28
LED3_1
OD,
TS, SL,
IP
Reference for Full
Description
Pin
LED0_3
81
LED0_2
OD,
TS, SL,
IP
Table 14 (page 47)
82
LED0_1
OD,
TS, SL,
IP
Table 14 (page 47)
83
AMDIX_EN
I, ST, IP
Table 13 (page 43)
84
MDDIS
I, ST, ID
Table 8 (page 40)
85
CFG_3
I, ST, ID
Table 13 (page 43)
86
CFG_2
I, ST, ID
Table 13 (page 43)
87
CFG_1
I, ST, ID
Table 13 (page 43)
88
ADD_4
I, ST, ID
Table 13 (page 43)
89
ADD_3
I, ST, ID
Table 13 (page 43)
90
ADD_2
I, ST, ID
Table 13 (page 43)
91
ADD_1
I, ST, ID
Table 13 (page 43)
119
TPFIN2
AI/AO
Table 11 (page 42)
120
GNDR2
–
Table 15 (page 48)
121
TPFOP2
AO/AI
Table 11 (page 42)
122
TPFON2
AO/AI
Table 11 (page 42)
123
VCCT2/3
–
Table 15 (page 48)
124
TPFON3
AO/AI
Table 11 (page 42)
125
TPFOP3
AO/AI
Table 11 (page 42)
126
GNDR3
–
Table 15 (page 48)
127
GNDT2/3
–
Table 15 (page 48)
128
TPFIN3
AI/AO
Table 11 (page 42)
129
TPFIP3
AI/AO
Table 11 (page 42)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Reference for Full
Description
Pin
Symbol
–
Table 15 (page 48)
168
TDO
O, TS
Table 12 (page 43)
VCCR4
–
Table 15 (page 48)
169
TMS
I, ST, IP
Table 12 (page 43)
TPFIP4
AI/AO
Table 11 (page 42)
170
TCK
I, ST, ID
Table 12 (page 43)
133
TPFIN4
AI/AO
Table 11 (page 42)
171
TRST
I, ST, IP
Table 12 (page 43)
134
GNDT4/5
–
Table 15 (page 48)
172
N/C
–
Table 17 (page 50)
135
GNDR4
–
Table 15 (page 48)
173
G_FX/TP
I, ST, ID
Table 13 (page 43)
136
TPFOP4
AO/AI
Table 11 (page 42)
174
PWRDWN
I, ST, ID
Table 13 (page 43)
137
TPFON4
AO/AI
Table 11 (page 42)
175
RESET
I, ST, IP
Table 13 (page 43)
138
VCCT4/5
–
Table 15 (page 48)
176
Section
I, ST, ID
Table 13 (page 43)
139
TPFON5
AO/AI
Table 11 (page 42)
177
ModeSel0
I, ST, ID
Table 13 (page 43)
140
TPFOP5
AO/AI
Table 11 (page 42)
178
ModeSel1
I, ST, ID
Table 13 (page 43)
141
GNDR5
–
Table 15 (page 48)
179
SGND
142
TPFIN5
AI/AO
Table 11 (page 42)
143
TPFIP5
AI/AO
Table 11 (page 42)
144
VCCR5
–
Table 15 (page 48)
145
VCCR6
–
Table 15 (page 48)
146
TPFIP6
AI/AO
Table 11 (page 42)
147
TPFIN6
AI/AO
Table 11 (page 42)
148
GNDT6/7
–
Table 15 (page 48)
149
GNDR6
–
Table 15 (page 48)
150
TPFOP6
AO/AI
Table 11 (page 42)
151
TPFON6
AO/AI
Table 11 (page 42)
152
VCCT6/7
–
Table 15 (page 48)
153
TPFON7
AO/AI
Table 11 (page 42)
154
TPFOP7
AO/AI
Table 11 (page 42)
155
GNDR7
–
Table 15 (page 48)
Pin
Symbol
130
VCCR3
131
132
156
Type1
TPFIN7
AI/AO
Table 11 (page 42)
157
TPFIP7
AI/AO
Table 11 (page 42)
158
VCCR7
–
Table 15 (page 48)
159
N/C
–
Table 17 (page 50)
160
N/C
–
Table 17 (page 50)
161
SD4
I
Table 10 (page 42)
162
SD5
I
Table 10 (page 42)
163
GNDPECL
–
Table 15 (page 48)
164
VCCPECL
–
Table 15 (page 48)
165
SD6
I
Table 10 (page 42)
166
SD7
I
Table 10 (page 42)
167
TDI
I, ST, IP
Table 12 (page 43)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Type1
Reference for Full
Description
–
Table 15 (page 48)
Table 14 (page 47)
180
LED4_1
OD,
TS, SL,
IP
181
LED4_2
OD,
TS, SL,
IP
Table 14 (page 47)
182
LED4_3
OD,
TS, SL,
IP
Table 14 (page 47)
183
GNDD
–
Table 15 (page 48)
184
VCCD
–
Table 15 (page 48)
185
LED5_1
OD,
TS, SL,
IP
Table 14 (page 47)
186
LED5_2
OD,
TS, SL,
IP
Table 14 (page 47)
187
LED5_3
OD,
TS, SL,
IP
Table 14 (page 47)
188
GNDIO
–
Table 15 (page 48)
189
LED6_1
OD,
TS, SL,
IP
Table 14 (page 47)
190
LED6_2
OD,
TS, SL,
IP
Table 14 (page 47)
191
LED6_3
OD,
TS, SL,
IP
Table 14 (page 47)
192
LED7_1
OD,
TS, SL,
IP
Table 14 (page 47)
29
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
30
Pin
Symbol
Type1
Reference for Full
Description
193
LED7_2
OD,
TS, SL,
IP
Table 14 (page 47)
194
LED7_3
OD,
TS, SL,
IP
Table 5 (page 36)
195
GNDD
–
Table 15 (page 48)
196
VCCD
–
Table 15 (page 48)
Table 16 (page 50)
197
N/C
O, TS,
ID
198
RxData7
O, TS
Table 6 (page 39)
199
GNDIO
–
Table 15 (page 48)
200
N/C
–
Table 16 (page 50)
201
N/C
–
Table 16 (page 50)
202
N/C
–
Table 16 (page 50)
203
TxData7
I, ID
Table 6 (page 39)
204
SYNC1
I, ID
Table 5 (page 36)
205
N/C
–
Table 16 (page 50)
206
RxData6
O, TS
Table 6 (page 39)
207
GNDIO
–
Table 15 (page 48)
208
VCCIO
–
Table 15 (page 48)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.1.3
PQFP Pin Assignments – SS-SMII Configuration
Figure 4 and Table 4, “Intel® LXT9785/LXT9785 SS-SMII PQFP Pin List” on page 32 provide
the LXT9785/LXT9785E SS-SMII PQFP pin assignments.
208 ......... VCCIO
207 ......... GNDIO
206 ......... N/C
205 ......... RxData6
204 ......... TxSYNC1
203 ......... TxData7
202 ......... N/C
201 ......... TxCLK1
200 ......... N/C
199 ......... GNDIO
198 ......... N/C
197 ......... RxData7
196 .........VCCD
195 ......... GNDD
194 ......... LED7_3
193 ......... LED7_2
192 ......... LED7_1
191 ......... LED6_3
190 ......... LED6_2
189 ......... LED6_1
188 ......... GNDIO
187 ......... LED5_3
186 ......... LED5_2
185 ......... LED5_1
184 ......... VCCD
183 ......... GNDD
182 ......... LED4_3
181 ......... LED4_2
180 ......... LED4_1
179 ......... SGND
178 ......... ModeSel_1
177 ......... ModeSel_0
176 ......... Section
175 ......... RESET
174 ......... PWRDWN
173 ......... G_FX/TP
172 ......... N/C
171....... TRST
170 ......... TCK
169 ......... TMS
168 ......... TDO
167 ......... TDI
166 ......... SD7
165 ......... SD6
164 ......... VCCPECL
163 ......... GNDPECL
162 ......... SD5
161 ......... SD4
160 ......... N/C
159 ......... N/C
158 ......... VCCR7
157 ......... TPFIP7
Figure 4. Intel® LXT9785/LXT9785E SS-SMII 208-Pin PQFP Assignments
Part #
LOT #
FPO #
LXT9785/9785E XX
XXXXXX
XXXXXXXX
Rev #
156.........TPFIN7
155.........GNDR7
154......... TPFOP7
153.........TPFON7
152......... VCCT6/7
151.........TPFON6
150......... TPFOP6
149.........GNDR6
148......... GNDT6/7
147......... TPFIN6
146......... TPFIP6
145.........VCCR6
144.........VCCR5
143......... TPFIP5
142......... TPFIN5
141.........GNDR5
140......... TPFOP5
139.........TPFON5
138......... VCCT4/5
137.........TPFON4
136......... TPFOP4
135.........GNDR4
134......... GNDT4/5
133......... TPFIN4
132......... TPFIP4
131.........VCCR4
130.........VCCR3
129......... TPFIP3
128......... TPFIN3
127......... GNDT2/3
126.........GNDR3
125......... TPFOP3
124.........TPFON3
123......... VCCT2/3
122.........TPFON2
121......... TPFOP2
120.........GNDR2
119......... TPFIN2
118......... TPFIP2
117.........VCCR2
116.........VCCR1
115......... TPFIP1
114......... TPFIN1
113......... GNDT0/1
112.........GNDR1
111......... TPFOP1
110.........TPFON1
109......... VCCT0/1
108.........TPFON0
107......... TPFOP0
106.........GNDR0
105......... TPFIN0
N/C...... 53
RxData0...... 54
N/C...... 55
VCCIO...... 56
GNDIO...... 57
RxSYNC0...... 58
MDIX...... 59
RxCLK0...... 60
TxData0...... 61
N/C...... 62
MDC0...... 63
MDIO0...... 64
VCCD...... 65
GNDD...... 66
MDINT0...... 67
LED3_3...... 68
LED3_2...... 69
LED3_1...... 70
LED2_3...... 71
LED2_2...... 72
LED2_1...... 73
GNDIO...... 74
LED1_3...... 75
LED1_2...... 76
LED1_1...... 77
VCCD...... 78
GNDD...... 79
LED0_3...... 80
LED0_2...... 81
LED0_1...... 82
AMDIX_EN...... 83
MDDIS...... 84
CFG_3...... 85
CFG_2...... 86
CFG_1...... 87
ADD_4...... 88
ADD_3...... 89
ADD_2...... 90
ADD_1...... 91
ADD_0...... 92
TxSlew_1...... 93
TxSlew_0...... 94
SD_2P5V...... 95
SD0...... 96
SD1...... 97
VCCPECL...... 98
GNDPECL...... 99
SD2...... 100
SD3...... 101
N/C...... 102
VCCR0...... 103
TPFIP0...... 104
N/C ......1
N/CLINKHOLD ...... 2
N/C ......3
TxData6 ...... 4
N/C ......5
REFCLK1 ......6
RxData5 ......7
N/C ......8
GNDIO ......9
N/C ......10
FIFOSEL1 ...... 11
N/C ......12
TxData5 ......13
N/C ......14
RxData4 ......15
N/C ......16
RxSYNC1 ......17
VCCIO ......18
GNDIO ......19
FIFOSEL0 ...... 20
RxCLK1 ......21
TxData4 ......22
N/C ......23
MDC1 ......24
MDIO1 ...... 25
MDINT1 ......26
RxData3 ......27
N/C ......28
VCCIO ......29
GNDIO ......30
N/C ......31
TxCLK0 ......32
N/C ......33
TxData3 ......34
TxSYNC0 ......35
RxData2 ......36
N/C ......37
GNDIO ......38
N/C ......39
PREASEL ......40
N/C ......41
TxData2 ......42
N/C ......43
REFCLK0 ......44
RxData1 ......45
N/C ......46
VCCIO ......47
GNDIO ......48
N/C ......49
PAUSE ......50
N/C ......51
TxData1 ......52
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
31
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 4.
Intel® LXT9785/LXT9785 SS-SMII PQFP Pin List
Pin
32
Symbol
1
N/C
2
N/C
LINKHOLD
3
N/C
4
TxData6
5
Type1
–
Reference for Full
Description
Pin
Symbol
Table 16 (page 50)
33
N/C
34
TxData3
35
Table 13 (page 43)
Type1
Reference for Full
Description
–
Table 16 (page 50)
I, ID
Table 6 (page 39)
TxSYNC0
I, ID
Table 8 (page 40)
36
RxData2
O, TS,
ID
Table 8 (page 40)
–
Table 16 (page 50)
I, ID
Table 6 (page 39)
N/C
I
Table 16 (page 50)
37
N/C
–
Table 16 (page 50)
6
REFCLK1
I
Table 6 (page 39)
38
GNDIO
–
Table 15 (page 48)
7
RxData5
O, TS,
ID
Table 8 (page 40)
39
N/C
–
Table 16 (page 50)
40
PREASEL
I, ST
Table 13 (page 43)
8
N/C
–
Table 16 (page 50)
41
N/C
–
Table 16 (page 50)
9
GNDIO
–
Table 15 (page 48)
42
TxData2
I, ID
Table 6 (page 39)
10
N/C
–
Table 16 (page 50)
43
N/C
–
Table 16 (page 50)
11
FIFOSEL1
I, ID, ST
Table 13 (page 43)
44
REFCLK0
12
N/C
–
Table 16 (page 50)
13
TxData5
I, ID
Table 6 (page 39)
14
N/C
–
Table 16 (page 50)
15
RxData4
O, TS,
ID
Table 8 (page 40)
16
N/C
–
Table 16 (page 50)
17
RxSYNC1
O, TS,
ID
Table 8 (page 40)
18
VCCIO
–
19
GNDIO
20
FIFOSEL0
I
Table 6 (page 39)
O, TS,
ID
Table 8 (page 40)
45
RxData1
46
N/C
–
Table 16 (page 50)
47
VCCIO
–
Table 15 (page 48)
48
GNDIO
–
Table 15 (page 48)
49
N/C
50
PAUSE
Table 15 (page 48)
51
N/C
–
Table 15 (page 48)
52
TxData1
I, ID, ST
Table 13 (page 43)
53
N/C
–
Table 16 (page 50)
I, ID, ST
Table 13 (page 43)
–
Table 16 (page 50)
I, ID
Table 6 (page 39)
–
Table 16 (page 50)
O, TS,
ID
Table 8 (page 40)
21
RxCLK1
O, TS,
ID
Table 8 (page 40)
54
RxData0
22
TxData4
I, ID
Table 6 (page 39)
55
N/C
–
Table 16 (page 50)
23
N/C
–
Table 16 (page 50)
56
VCCIO
–
Table 15 (page 48)
24
MDC1
I, ST, ID
Table 9 (page 41)
57
GNDIO
–
Table 15 (page 48)
25
MDIO1
I/O, TS,
SL, IP
Table 9 (page 41)
58
RxSYNC0
O, TS,
ID
Table 8 (page 40)
26
MDINT1
OD, TS,
SL, IP
Table 9 (page 41)
59
MDIX
I, ID, ST
Table 13 (page 43)
60
RxCLK0
–
Table 8 (page 40)
27
RxData3
O, TS,
ID
Table 8 (page 40)
61
TxData0
I, ID
Table 6 (page 39)
28
N/C
–
Table 16 (page 50)
62
N/C
–
Table 16 (page 50)
29
VCCIO
–
Table 15 (page 48)
63
MDC0
I, ST, ID
Table 9 (page 41)
Table 9 (page 41)
30
GNDIO
31
N/C
32
TxCLK0
–
Table 15 (page 48)
64
MDIO0
I/O, TS,
SL, IP
–
Table 16 (page 50)
65
VCCD
–
Table 15 (page 48)
I, ID
Table 8 (page 40)
66
GNDD
–
Table 15 (page 48)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Pin
Symbol
Type1
Reference for Full
Description
67
MDINT0
OD, TS,
SL, IP
Table 9 (page 41)
68
LED3_3
OD, TS,
SO, IP
Table 14 (page 47)
69
LED3_2
OD, TS,
SL, IP
Table 14 (page 47)
70
LED3_1
OD, TS,
SL, IP
Table 14 (page 47)
71
LED2_3
OD, TS,
SL, IP
Table 14 (page 47)
72
LED2_2
OD, TS,
SL, IP
Table 14 (page 47)
73
LED2_1
OD, TS,
SL, IP
Table 14 (page 47)
74
GNDIO
–
Table 15 (page 48)
Type1
Reference for Full
Description
Pin
Symbol
97
SD1
I
Table 10 (page 42)
98
VCCPECL
–
Table 15 (page 48)
99
GNDPECL
–
Table 15 (page 48)
100
SD2
I
Table 10 (page 42)
101
SD3
I
Table 10 (page 42)
102
N/C
–
Table 16 (page 50)
103
VCCR0
–
Table 15 (page 48)
104
TPFIP0
AI/AO
Table 11 (page 42)
105
TPFIN0
AI/AO
Table 11 (page 42)
106
GNDR0
–
Table 15 (page 48)
107
TPFOP0
AO/AI
Table 11 (page 42)
108
TPFON0
AO/AI
Table 11 (page 42)
109
VCCT0/1
–
Table 15 (page 48)
110
TPFON1
AO/AI
Table 11 (page 42)
111
TPFOP1
AO/AI
Table 11 (page 42)
112
GNDR1
–
Table 15 (page 48)
113
GNDT0/1
–
Table 15 (page 48)
LED1_3
OD, TS,
SL, IP
Table 14 (page 47)
76
LED1_2
OD, TS,
SL, IP
Table 14 (page 47)
77
LED1_1
OD, TS,
SL, IP
Table 14 (page 47)
78
VCCD
–
Table 15 (page 48)
114
TPFIN1
AI/AO
Table 11 (page 42)
79
GNDD
–
Table 15 (page 48)
115
TPFIP1
AI/AO
Table 11 (page 42)
80
LED0_3
OD, TS,
SL, IP
Table 14 (page 47)
116
VCCR1
–
Table 15 (page 48)
117
VCCR2
–
Table 15 (page 48)
Table 14 (page 47)
118
TPFIP2
AI/AO
Table 11 (page 42)
119
TPFIN2
AI/AO
Table 11 (page 42)
75
81
LED0_2
OD, TS,
SL, IP
82
LED0_1
OD, TS,
SL, IP
Table 14 (page 47)
120
GNDR2
–
Table 15 (page 48)
83
AMDIX_EN
I, ST, IP
Table 13 (page 43)
121
TPFOP2
AO/AI
Table 11 (page 42)
84
MDDIS
I, ST, ID
Table 9 (page 41)
122
TPFON2
AO/AI
Table 11 (page 42)
85
CFG_3
I, ST, ID
Table 13 (page 43)
123
VCCT2/3
–
Table 15 (page 48)
86
CFG_2
I, ST, ID
Table 13 (page 43)
124
TPFON3
AO/AI
Table 11 (page 42)
87
CFG_1
I, ST, ID
Table 13 (page 43)
125
TPFOP3
AO/AI
Table 11 (page 42)
88
ADD_4
I, ST, ID
Table 13 (page 43)
126
GNDR3
–
Table 15 (page 48)
89
ADD_3
I, ST, ID
Table 13 (page 43)
127
GNDT2/3
–
Table 15 (page 48)
90
ADD_2
I, ST, ID
Table 13 (page 43)
128
TPFIN3
AI/AO
Table 11 (page 42)
91
ADD_1
I, ST, ID
Table 13 (page 43)
129
TPFIP3
AI/AO
Table 11 (page 42)
92
ADD_0
I, ST, ID
Table 13 (page 43)
130
VCCR3
–
Table 15 (page 48)
93
TxSLEW_1
I, ST, ID
Table 13 (page 43)
131
VCCR4
–
Table 15 (page 48)
94
TxSLEW_0
I, ST, ID
Table 13 (page 43)
132
TPFIP4
AI/AO
Table 11 (page 42)
95
SD_2P5V
I, ST, ID
Table 10 (page 42)
133
TPFIN4
AI/AO
Table 11 (page 42)
96
SD0
I
Table 10 (page 42)
134
GNDT4/5
–
Table 15 (page 48)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
33
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Reference for Full
Description
Pin
Symbol
Type1
Reference for Full
Description
–
Table 15 (page 48)
173
G_FX/TP
I, ST, ID
Table 13 (page 43)
TPFOP4
AO/AI
Table 11 (page 42)
174
PWRDWN
I, ST, ID
Table 13 (page 43)
137
TPFON4
AO/AI
Table 11 (page 42)
175
RESET
I, ST, IP
Table 13 (page 43)
138
VCCT4/5
–
Table 15 (page 48)
176
SECTION
I, ST, ID
Table 13 (page 43)
139
TPFON5
AO/AI
Table 11 (page 42)
177
ModeSel0
I, ST, ID
Table 13 (page 43)
140
TPFOP5
AO/AI
Table 11 (page 42)
178
ModeSel1
I, ST, ID
Table 13 (page 43)
141
GNDR5
–
Table 15 (page 48)
179
SGND
–
Table 15 (page 48)
142
TPFIN5
AI/AO
Table 11 (page 42)
180
LED4_1
TPFIP5
AI/AO
Table 11 (page 42)
OD, TS,
SL, IP
Table 14 (page 47)
143
144
VCCR5
–
Table 15 (page 48)
181
LED4_2
OD, TS,
SL, IP
Table 14 (page 47)
145
VCCR6
–
Table 15 (page 48)
146
TPFIP6
AI/AO
Table 11 (page 42)
182
LED4_3
OD, TS,
SL, IP
Table 14 (page 47)
147
TPFIN6
AI/AO
Table 11 (page 42)
183
GNDD
–
Table 15 (page 48)
VCCD
–
Table 15 (page 48)
Pin
Symbol
135
GNDR4
136
148
GNDT6/7
–
Table 15 (page 48)
184
149
GNDR6
–
Table 15 (page 48)
185
LED5_1
OD, TS,
SL, IP
Table 14 (page 47)
150
TPFOP6
AO/AI
Table 11 (page 42)
151
TPFON6
AO/AI
Table 11 (page 42)
186
LED5_2
OD, TS,
SL, IP
Table 14 (page 47)
152
VCCT6/7
–
Table 15 (page 48)
187
LED5_3
Table 14 (page 47)
153
TPFON7
AO/AI
Table 11 (page 42)
OD, TS,
SL, IP
154
TPFOP7
AO/AI
Table 11 (page 42)
188
GNDIO
–
Table 15 (page 48)
155
GNDR7
–
Table 15 (page 48)
189
LED6_1
OD, TS,
SL, IP
Table 14 (page 47)
156
TPFIN7
AI/AO
Table 11 (page 42)
157
TPFIP7
AI/AO
Table 11 (page 42)
190
LED6_2
OD, TS,
SL, IP
Table 14 (page 47)
158
VCCR7
–
Table 15 (page 48)
191
LED6_3
OD, TS,
SL, IP
Table 14 (page 47)
159
N/C
–
Table 16 (page 50)
160
N/C
–
Table 16 (page 50)
192
LED7_1
OD, TS,
SL, IP
Table 14 (page 47)
161
SD4
I
Table 10 (page 42)
193
LED7_2
Table 14 (page 47)
162
SD5
I
Table 10 (page 42)
OD, TS,
SL, IP
163
GNDPECL
–
Table 15 (page 48)
194
LED7_3
OD, TS,
SL, IP
Table 14 (page 47)
164
VCCPECL
–
Table 15 (page 48)
195
GNDD
–
Table 15 (page 48)
165
SD6
I
Table 10 (page 42)
196
VCCD
166
SD7
I
Table 10 (page 42)
167
TDI
I, ST, IP
Table 12 (page 43)
168
TDO
O, TS
169
TMS
170
171
172
34
Type1
–
Table 15 (page 48)
O, TS,
ID
Table 8 (page 40)
197
RxData7
Table 12 (page 43)
198
N/C
–
Table 16 (page 50)
I, ST, IP
Table 12 (page 43)
199
GNDIO
–
Table 15 (page 48)
TCK
I, ST, ID
Table 12 (page 43)
200
N/C
–
Table 16 (page 50)
TRST
I, ST, IP
Table 12 (page 43)
201
TxCLK1
I, ID
Table 8 (page 40)
Table 16 (page 50)
202
N/C
–
Table 16 (page 50)
N/C
–
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Reference for Full
Description
Pin
Symbol
Type1
203
TxData7
I, ID
Table 6 (page 39)
204
TxSYNC1
I, ID
Table 8 (page 40)
205
RxData6
O, TS,
ID
Table 8 (page 40)
206
N/C
–
Table 16 (page 50)
207
GNDIO
–
Table 15 (page 48)
208
VCCIO
–
Table 15 (page 48)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
35
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.2
PQFP Signal Descriptions
3.2.1
Signal Name Conventions
Signal names may contain either a port designation or a serial designation, or a combination of the
two designations. Signal naming conventions are as follows:
• Port Number Only. Individual signals that apply to a particular port are designated by the
Signal Mnemonic, immediately followed by the Port Designation. For example, Transmit
Enable signals would be identified as TxEN0, TxEN1, and TxEN2.
• Serial Number Only. A set of signals which are not tied to any specific port are designated by
the Signal Mnemonic, followed by an underscore and a serial designation. For example, a set
of three Global Configuration signals would be identified as CFG_1, CFG_2, and CFG_3.
• Port and Serial Number. In cases where each port is assigned a set of multiple signals, each
signal is designated in the following order: Signal Mnemonic, Port Designation, an
underscore, and the serial designation. For example, a set of three Port Configuration signals
would be identified as RxData0_0 and RxData0_1, RxData1_0 and RxData1_1, and
RxData2_0 and RxData2_1.
3.2.2
PQFP Signal Descriptions – RMII, SMII, and SS-SMII Configurations
Table 5 through Table 17, “Intel® LXT9785/LXT9785E Receive FIFO Depth Considerations” on
page 50 provide PQFP signal descriptions. Ball designations are included for cross-reference.
Table 5.
Intel® LXT9785/LXT9785E RMII Signal Descriptions – PQFP (Sheet 1 of 3)
Pin-Ball
Designation
PQFP
Symbol
Type1
Signal Description2,3
PBGA
Reference Clock.
44
6
E6,
E12
REFCLK0
REFCLK1
I
61
62
E2,
F4
TxData0_0
TxData0_1
I, ID
52
53
C3,
D4
TxData1_0
TxData1_1
I, ID
42
43
B5
A4
TxData2_0
TxData2_1
I, ID
50 MHz RMII reference clock is always required. RMII
inputs are sampled on the rising edge of REFCLK,
RMII outputs are sourced on the falling edge. See
“Clock/SYNC Requirements” on page 125 for detailed
CLK requirements.
Transmit Data - Port 0.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 0 are clocked in synchronously to REFCLK.
Transmit Data - Port 1.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 1 are clocked in synchronously to REFCLK
Transmit Data - Port 2.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 2 are clocked in synchronously to REFCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W
Power-Down modes and during H/W reset.
36
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 5.
Intel® LXT9785/LXT9785E RMII Signal Descriptions – PQFP (Sheet 2 of 3)
Pin-Ball
Designation
Symbol
Type1
PQFP
PBGA
34
35
D8,
A6
TxData3_0
TxData3_1
I, ID
22
23
A11,
C10
TxData4_0
TxData4_1
I, ID
13
14
B13,
D11
TxData5_0
TxData5_1
I, ID
4
5
D13,
A16
TxData6_0
TxData6_1
I, ID
203
204
E14,
C16
TxData7_0
TxData7_1
I, ID
60
51
41
33
21
12
3
202
E3,
B2,
C6,
A7,
B11,
A14,
C14,
D16
TxEN0
TxEN1
TxEN2
TxEN3
TxEN4
TxEN5
TxEN6
TxEN7
I, ID
55
54
C2,
B1
RxData0_0
RxData0_1
O, TS
O, TS, ID
46
45
A3,
B4
RxData1_0
RxData1_1
O, TS
O, TS, ID
37
36
B6,
C7
RxData2_0
RxData2_1
O, TS
O, TS, ID
28
27
D9,
B9
RxData3_0
RxData3_1
O, TS
O, TS, ID
16
15
A13,
C12
RxData4_0
RxData4_1
O, TS
O, TS, ID
8
7
B14,
B15
RxData5_0
RxData5_1
O, TS
O, TS, ID
Signal Description2,3
Transmit Data - Port 3.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 3 are clocked in synchronously to REFCLK.
Transmit Data - Port 4.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 4 are clocked in synchronously to REFCLK.
Transmit Data - Port 5.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 5 are clocked in synchronously to REFCLK.
Transmit Data - Port 6.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 6 are clocked in synchronously to REFCLK.
Transmit Data - Port 7.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 7 are clocked in synchronously to REFCLK.
Transmit Enable - Ports 0-7.
Active High input enables respective port transmitter.
This signal must be synchronous to the REFCLK.
Receive Data - Port 0.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 1.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 2.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 3.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 4.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 5.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W
Power-Down modes and during H/W reset.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
37
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 5.
Intel® LXT9785/LXT9785E RMII Signal Descriptions – PQFP (Sheet 3 of 3)
Pin-Ball
Designation
Symbol
Type1
PQFP
PBGA
206
205
C15,
B17
RxData6_0
RxData6_1
O, TS
O, TS, ID
198
197
E16,
F14
RxData7_0
RxData7_1
O, TS
O, TS, ID
58
49
39
31
17
10
1
200
E4,
C4,
A5,
B8,
B12,
D12,
B16,
E15
CRS_DV0
CRS_DV1
CRS_DV2
CRS_DV3
CRS_DV4
CRS_DV5
CRS_DV6
CRS_DV7
O, TS, SL,
ID
Signal Description2,3
Receive Data - Port 6.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 7.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Carrier Sense/Receive Data Valid - Ports 0-7.
On detection of valid carrier, these signals are
asserted asynchronously with respect to REFCLK.
CRS_DVn is de-asserted on loss of carrier,
synchronous to REFCLK.
Receive Error - Ports 0-7.
59
50
40
32
20
11
2
201
D2,
D5,
D7,
C8,
A12,
A15,
A17,
D17
RxER0
RxER1
RxER2
RxER3
RxER4
RxER5
RxER6
RxER7
These signals are synchronous to the respective
REFCLK. Active High indicates that received code
group is invalid, or that PLL is not locked.
O, TS, SL,
ID
The RxER signals have the following additional
function pins:
RxER0 (MDIX)
RxER1 (PAUSE)
RxER2 (PREASEL)
RxER4 (FIFOSEL0)
RxER5 (FIFOSEL1)
RxER6 (LINKHOLD)
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W
Power-Down modes and during H/W reset.
38
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 6.
Intel® LXT9785/LXT9785E SMII / SS-SMII Common Signal Descriptions – PQFP
Pin/Ball
Designation
PQFP
PBGA
61
52
42
34
22
13
4
203
E2,
C3,
B5,
D8,
A11,
B13,
D13,
E14
44
6
E6,
Symbol
Type1
TxData0
TxData1
TxData2
TxData3
TxData4
TxData5
TxData6
TxData7
I, ID
Signal Description2
Transmit Data - Ports 0-7.
These serial input streams provide data to be transmitted to
the network. The LXT9785/9785E clocks the data in
synchronously to REFCLK.
Reference Clock.
E12
REFCLK0
REFCLK1
I
The LXT9785/9785E always requires a 125 MHz reference
clock input. Refer to Functional Description for detailed clock
requirements. REFCLK0 and REFCLK1 are always
connected regardless of sectionalization mode.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode.
Table 7.
Intel® LXT9785/LXT9785E SMII Specific Signal Descriptions – PQFP
Pin/Ball
Designation
PQFP
Symbol
Type1
Signal Description2,3
PBGA
SMII Synchronization.
35
204
A6,
C16
SYNC0
SYNC1
55
46
37
28
16
8
206
198
C2,
A3,
B6,
D9,
A13,
B14,
C15,
E16
RxData0
RxData1
RxData2
RxData3
RxData4
RxData5
RxData6
RxData7
I, ID
The MAC must generate a SYNC pulse every 10 REFCLK
cycles to synchronize the SMII. SYNC0 is used when 1x8
port sectionalization is selected. SYNC0 and SYNC1 are
to be used when 2x4 port sectionalization is chosen.
Receive Data - Ports 0-7.
O, TS
These serial output streams provide data received from
the network. The LXT9785/9785E drives the data out
synchronously to REFCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode.
3. RxData[0:7] outputs are three-stated in Isolation and hardware power-down modes and during hardware
reset.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
39
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 8.
Intel® LXT9785/LXT9785E SS-SMII Specific Signal Descriptions – PQFP
Pin/Ball
Designation
PQFP
PBGA
35
204
A6,
C16
Symbol
Type1
TxSYNC0
TxSYNC1
I, ID
Signal Description2,3
SS-SMII Transmit Synchronization.
The MAC must generate a TxSYNC pulse every 10 TxCLK
cycles to mark the start of TxData segments. TxSYNC0 is
used when 1x8 port sectionalization is selected.
SS-SMII Receive Synchronization.
58
17
E4,
B12
RxSYNC0
RxSYNC1
O, TS,
ID
The LXT9785/9785E generates these pulses every 10
RxCLK cycles to mark the start of RxData segments for the
MAC. RxSYNC1 is used when 1x8 port sectionalization is
selected. RxSYNC0 may not be used. These outputs are
only enabled when SS-SMII mode is enabled.
SS-SMII Transmit Clock.
32
201
C8,
D17
TxCLK0
TxCLK1
I, ID
The MAC sources this 125 MHz clock as the timing
reference for TxData and TxSYNC. Only TxCLK0 is used
when 1x8 port sectionalization is selected. See “Clock/
SYNC Requirements” on page 125 for detailed clock
requirements.
SS-SMII Receive Clock.
60
21
E3,
B11
RxCLK0
RxCLK1
O, TS,
ID
54
45
36
27
15
7
205
197
B1,
B4,
C7,
B9,
C12,
B15,
B17,
F14
RxData0
RxData1
RxData2
RxData3
RxData4
RxData5
RxData6
RxData7
O, TS,
ID
The LXT9785/9785E generates these clocks, based on
REFCLK, to provide a timing reference for RxData and
RxSYNC to the MAC. RxCLK1 is used when 1x8 port
sectionalization is selected. RxCLK0 may not be used. See
“Clock/SYNC Requirements” on page 125 for detailed clock
requirements. These outputs are only enabled when SSSMII mode is enabled.
Receive Data - Ports 0-7.
These serial output streams provide data received from
the network. The LXT9785/9785E drives the data out
synchronously to REFCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. RxData[0:7], RxSYNC[0:1], and RxCLK[0:1] outputs are three-stated in Isolation and H/W Power-Down
modes and during H/W reset.
40
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 9.
Intel® LXT9785/LXT9785E MDIO Control Interface Signals – PQFP
Pin/Ball
Designation
PQFP
Symbol
Type1
Signal Description2,3,4
PBGA
Management Data Input/Output.
64
25
F3,
A10
MDIO0
MDIO1
I/O, TS, SL,
IP
Bidirectional serial data channel for communication
between the PHY and MAC or switch ASIC. Only
MDIO0 is used when 1x8 port sectionalization is
selected. In 2x4 port sectionalization mode, MDIO0
accesses ports 0-3 and MDIO1 accesses ports 4-7.
Refer to Figure 21 on page 140.
Management Data Interrupt.
67
26
F1,
C9
MDINT0
MDINT1
OD,TS, SL,
IP
When Register bit 18.1 = 1, an active Low output on this
Pin indicates status change. Only MDINT0 is used when
1x8 port sectionalization is selected. In 2x4 port
sectionalization mode, MDINT0 is associated with ports
0-3 and MDINT1 is associated with ports 4-7. Refer to
Figure 21 on page 140.
Management Data Clock.
63
24
E1,
B10
MDC0
MDC1
I, ST, ID
Clock for the MDIO serial data channel. Maximum
frequency is 20 MHz. Only MDC0 is used when 1x8 port
sectionalization is selected. In 2x4 port
sectionalization mode, MDC0 clocks ports 0-3 register
accesses and MDC1 clocks ports 4-7 register accesses.
Refer to Figure 21 on page 140.
Management Disable.
When MDDIS is tied High, the MDIO port is completely
disabled and the Hardware Control Interface pins set
their respective bits at power up and reset.
84
L1
MDDIS
I, ST, ID
When MDDIS is pulled Low at power up or reset, via the
internal pull-down resistor or by tieing it to ground, the
Hardware Control Interface Pins control only the initial
or “default” values of their respective register bits. After
the power-up/reset cycle is complete, bit control reverts
to the MDIO serial channel.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. MDIO[0:1] and MDINT[0:1] outputs are three-stated in H/W Power-Down mode and during H/W reset.
4. Supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
where X is the register number (0-32) and Y is the bit number (0-15).
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
41
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 10. Intel® LXT9785/LXT9785E Signal Detect – PQFP
Pin/Ball
Designation
PQFP
Symbol
Type1
Signal Description2,3
PBGA
Signal Detect 2.5 Volt Interface.
SD input threshold voltage select.
95
P1
SD_2P5V
I, ST, ID
Tie to VCCPECL = Select 2.5 V LVPECL input levels
Float or Tie to GNDPECL = Select 3.3 V LVPECL input
levels
96
97
100
101
161
162
165
166
P2,
N4,
P3,
N5,
P15,
P16,
P17,
N17
Signal Detect - Ports 0-7.
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
Signal Detect input from the fiber transceiver (these inputs
are only active for ports operating in fiber mode).
I
Logic High = Normal operation (the process of searching
for receive idles for the purpose of bringing link up is
initiated)
Logic Low = Link is declared lost
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode.
3. Tie SD[0:7] inputs to GNDPECL if unused.
Table 11. Intel® LXT9785/LXT9785E Network Interface Signal Descriptions – PQFP
Pin/Ball Designation
Symbol
PQFP
PBGA
107, 108
111, 110
121, 122
125, 124
136, 137
140, 139
150, 151
154, 153
T2, U1,
T3, R4,
T6, U5,
U7, T7,
T10, R10,
T11, U11,
T14,U15,
R14, T15
TPFOP0, TPFON0
TPFOP1, TPFON1
TPFOP2, TPFON2
TPFOP3, TPFON3
TPFOP4, TPFON4
TPFOP5, TPFON5
TPFOP6, TPFON6
TPFOP7, TPFON7
104, 105
115, 114
118, 119
129, 128
132, 133
143, 142
146, 147
157, 156
R2, T1,
U3, T4,
R6, T5,
T8, R8,
T9, U9,
U13, T12,
R12, T13,
R16, T16
TPFIP0, TPFIN0
TPFIP1, TPFIN1
TPFIP2, TPFIN2
TPFIP3, TPFIN3
TPFIP4, TPFIN4
TPFIP5, TPFIN5
TPFIP6, TPFIN6
TPFIP7, TPFIN7
Type1
Signal Description
Twisted-Pair/Fiber Outputs2, Positive &
Negative, Ports 0-7.
AO/AI
During 100BASE-TX or 10BASE-T operation,
TPFO pins drive 802.3 compliant pulses onto
the line.
During 100BASE-FX operation, TPFO pins
produce differential LVPECL outputs for fiber
transceivers.
Twisted-Pair/Fiber Inputs3, Positive &
Negative, Ports 0-7.
AI/AO
During 100BASE-TX or 10BASE-T operation,
TPFI pins receive differential 100BASE-TX or
10BASE-T signals from the line.
During 100BASE-FX operation, TPFI pins
receive differential LVPECL inputs from fiber
transceivers.
1. Type Column Coding: AI = Analog Input, AO = Analog Output.
2. Switched to Inputs (see TPFIP/N description) when not in fiber mode and MDIX is not active [that is,
twisted-pair, non-crossover MDI mode].
3. Switched to Outputs (see TPFOP/N description) when not in fiber mode and MDIX is not active [that is,
twisted-pair, non-crossover MDI mode].
42
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 12. Intel® LXT9785/LXT9785E JTAG Test Signal Descriptions – PQFP
Pin/Ball
Designation
Symbol
Type1
PQFP
PBGA
167
N14
TDI
I, ST, IP
168
N15
TDO
O, TS
169
N16
TMS
I, ST, IP
170
M16
TCK
I, ST, ID
171
M17
TRST
I, ST, IP
Signal Description2,3
Test Data Input.
Test data sampled with respect to the rising edge of TCK.
Test Data Output.
Test data driven with respect to the falling edge of TCK.
Test Mode Select.
Test Clock.
Clock input for JTAG test.
Test Reset.
Reset input for JTAG test.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain, TS = Three-State-able output, SMT =
Schmitt Triggered input, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. TDO output is three-stated in H/W Power-Down mode and during H/W reset.
Table 13. Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP (Sheet 1 of 4)
Pin/Ball
Designation
PQFP
Symbol
Type1
Signal Description2
PBGA
Tx Output Slew Controls 0 and 1 Defaults.
These pins are read at startup or reset. Their value at
that time is used to set the default state of Register bits
27.11:10 for all ports. These register bits can be read
and overwritten after startup / reset.
94
93
N3,
M4
TxSLEW_0
TxSLEW_1
These pins select the TX output slew rate for all ports
(rise and fall time) as follows:
I, ST, ID
TxSLEW_1
TxSLEW_0
Slew Rate (Rise and Fall
Time)
0
0
3.3 ns
0
1
3.6 ns
1
0
3.9 ns
1
1
4.2 ns
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
2. The IP/ID resistors are disabled during hardware power-down mode.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
43
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 13. Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP (Sheet 2 of 4)
Pin/Ball
Designation
PQFP
Symbol
Type1
Signal Description2
PBGA
Pause Default.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 4.10 for
all ports. This register bit can be read and overwritten
after startup / reset.
50
D5
PAUSE
I, ID, ST
When High, the LXT9785/9785E advertises Pause
capabilities on all ports during auto-negotiation.
This pin is shared with RMII-RxER1. An external pullup resistor (see applications section for value) can be
used to set Pause active while RxER1 is three-stated
during H/W reset. If no pull-up is used, the default
Pause state is set inactive via the internal pull-down
resistor.
Power-Down.
174
L14
PWRDWN
I, ST, ID
When High, forces the LXT9785/9785E into global
power-down mode.
Pin is not on JTAG chain.
Reset.
175
M15
RESET
I, ST, IP
This active low input is ORed with the control register
Reset Register bit 0.15. When held Low, all outputs are
forced to inactive state.
Pin is not on JTAG chain.
Address <4:0>.
88
89
90
91
92
L4,
M2,
M3,
N1,
N2
ADD_4
ADD_3
ADD_2
ADD_1
ADD_0
Sets base address. Each port adds its port number
(starting with 0) to this address to determine its PHY
address.
I, ST, ID
Port 0 Address = Base
Port 1 Address = Base + 1
Port 2 Address = Base + 2
Port 3 Address = Base + 3
Port 4 Address = Base + 4
Port 5 Address = Base + 5
Port 6 Address = Base + 6
Port 7 Address = Base + 7
Mode Select[1:0].
00 = RMII
178
177
L17,
L16
MODESEL_1
MODESEL_0
01 = SMII
I, ST, ID
10 = SS-SMII
11 = Reserved
All ports are configured the same. Interfaces cannot be
mixed and must be all RMII, SMII, or SS-SMII.
Sectionalization Select.
176
L15
SECTION
I, ST, ID
This pin selects sectionalization into separate ports.
0 = 1x8 ports,
1 = 2x4 ports
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
2. The IP/ID resistors are disabled during hardware power-down mode.
44
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 13. Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP (Sheet 3 of 4)
Pin/Ball
Designation
PQFP
Symbol
Type1
Signal Description2
PBGA
Auto MDIX Enable Default.
83
K1
AMDIX_EN
I, ST, IP
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 27.9 for
all ports. These register bits can be read and
overwritten after startup / reset. Refer to Table 40 on
page 119.
When active (High), automatic MDI crossover (MDIX)
(regardless of segmentation) is selected for all ports.
When inactive (Low) MDIX is selected according to the
MDIX pin.
MDIX Select Default.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 27.8 for
all ports. These register bits can be read and
overwritten after startup / reset. Refer to Table 40,
“Intel® LXT9785/LXT9785E MDIX Selection” on
page 119.
When AMDIX_EN is active this pin is ignored.
59
D2
MDIX
I, ID, ST
When AMDIX_EN is inactive, all ports are forced to the
MDI or the MDIX function regardless of segmentation.
If this pin is active (high), MDI crossover (MDIX) is
selected. If this pin is inactive, non-crossover MDI
mode is set.
This pin is shared with RMII-RxER0. An external pullup resistor (see applications section for value) can be
used to set MDIX active while RxER0 is three-stated
during H/W reset. If no pull-up is used, the default
MDIX state is set inactive via the internal pull-down
resistor. Do not tie this pin directly to VCCIO (vs. using
a pull-up) in non-RMII modes.
Global Port Configuration Defaults 1-3.
85
86
87
L2,
L3,
M1
CFG_3
CFG_2
CFG_1
I, ST, ID
These pins are read at startup or reset. Their value at
that time is used to set the default state of register bits
shown in Table 42, “Intel® LXT9785/9785E Global
Hardware Configuration Settings” on page 129 for all
ports. These register bits can be read and overwritten
after startup / reset.
When operating in Hardware Control Mode, these pins
provide configuration control options for all the ports
(refer to page 129 for details).
Global FX/TP Enable Default.
173
M14
G_FX/TP
I, ST, ID
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 16.0 for
all ports. These register bits can be read and
overwritten after startup / reset. Refer to Table 92, “Port
Configuration Register (Address 16, Hex 10)” on page 207.
This input selects whether all the ports are defaulted to
TP vs. FX mode.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
2. The IP/ID resistors are disabled during hardware power-down mode.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
45
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 13. Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP (Sheet 4 of 4)
Pin/Ball
Designation
PQFP
Symbol
Type1
Signal Description2
PBGA
FIFO Select <1:0>.
These pins are read at startup or reset. Their value at
that time is used to set the default state of Register bits
18.15:14 for all ports. These register bits can be read
and overwritten after startup/reset.
11
20
A15
A12
FIFOSEL1
FIFOSEL0
I, ID, ST
These pins are shared with RMII-RxER<5:4>. An
external pull-up resistor (see applications section for
value) can be used to set FIFO Select<1:0> to active
while RxER<5:4> are three-stated during hardware
reset. If no pull-up is used, the default FIFO select
state is set via the internal pull-down resistors.
See Table 17, “Intel® LXT9785/LXT9785E Receive
FIFO Depth Considerations” on page 50.
Preamble Select.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 16.5 for
all ports. This register bit can be read and overwritten
after startup/reset.
40
D7
PREASEL
I, ID, ST
This pin is shared with RMII-RxER2. An external pullup resistor (see applications section for value) can be
used to set Preamble Select to active while RxER2 is
three-stated during hardware reset. If no pull-up is
used, the default Preamble Select state is set via the
internal pull-down resistors.
Note: Preamble select has no effect in 100 Mbps
operation.
2
A17
LINKHOLD
ID
LINKHOLD Default. This pin is read at startup or
reset. Its value at that time is used to set the default
state of Register bit 0.11 for all ports. This register bit
can be read and overwritten after startup / reset. When
High, the LXT9785/9785E powers down all ports.
This pin is shared with RMII-RxER6. An external pullup resistor (see applications section for value) can be
used to set LINKHOLD active while RxER6 is tri-stated
during H/W reset. If no pull-up is used, the default
LINKHOLD state is set inactive via the internal pulldown resistor.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
2. The IP/ID resistors are disabled during hardware power-down mode.
46
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 14. Intel® LXT9785/LXT9785E LED Signal Descriptions – PQFP (Sheet 1 of 2)
Pin/Ball
Designation
PQFP
PBGA
82
81
80
K3,
K2,
J1
Symbol
Type1
Signal Description2,3
Port 0 LED Drivers 1-3.
LED0_1
LED0_2
LED0_3
OD, TS, SL,
IP
These pins drive LED indicators for Port 0. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to Table 96, “LED Configuration Register (Address
20, Hex 14)” on page 213 for details).
Port 1 LED Drivers 1-3.
77
76
75
J4,
J3,
H1
LED1_1
LED1_2
LED1_3
OD, TS, SL,
IP
These pins drive LED indicators for Port 1. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to Table 96, “LED Configuration Register (Address
20, Hex 14)” on page 213 for details).
Port 2 LED Drivers 1-3.
73
72
71
H2,
H3,
G1
LED2_1
LED2_2
LED2_3
OD, TS, SL,
IP
These pins drive LED indicators for Port 2. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to Table 96, “LED Configuration Register (Address
20, Hex 14)” on page 213 for details).
Port 3 LED Drivers 1-3.
70
69
68
F2,
G3,
G4
LED3_1
LED3_2
LED3_3
180
181
182
K16,
K17,
J17
LED4_1
LED4_2
LED4_3
OD, TS, SL,
IP
These pins drive LED indicators for Port 3. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to Table 96, “LED Configuration Register (Address
20, Hex 14)” on page 213 for details).
Port 4 LED Drivers 1-3.
OD, TS, SL,
IP
These pins drive LED indicators for Port 4. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to Table 96, “LED Configuration Register (Address
20, Hex 14)” on page 213 for details).
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. The LED outputs are three-stated in H/W Power-Down mode and during H/W reset.
4.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
47
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 14. Intel® LXT9785/LXT9785E LED Signal Descriptions – PQFP (Sheet 2 of 2)
Pin/Ball
Designation
Symbol
PQFP
PBGA
185
186
187
J15,
J16,
H17
Type1
Signal Description2,3
Port 5 LED Drivers 1-3.
LED5_1
LED5_2
LED5_3
OD, TS, SL,
IP
These pins drive LED indicators for Port 5. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to Table 96, “LED Configuration Register (Address
20, Hex 14)” on page 213 for details).
Port 6 LED Drivers 1-3.
189
190
191
H15,
H16,
G17
LED6_1
LED6_2
LED6_3
OD, TS, SL,
IP
These pins drive LED indicators for Port 6. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to Table 96, “LED Configuration Register (Address
20, Hex 14)” on page 213 for details).
Port 7 LED Drivers 1-3.
192
193
194
G15,
F17,
F16
LED7_1
LED7_2
LED7_3
OD, TS, SL,
IP
These pins drive LED indicators for Port 7. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to Table 96, “LED Configuration Register (Address
20, Hex 14)” on page 213 for details).
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. The LED outputs are three-stated in H/W Power-Down mode and during H/W reset.
4.
Table 15. Intel® LXT9785/LXT9785E Power Supply Signal Descriptions – PQFP (Sheet 1 of 2)
Pin/Ball Designation
PQFP
PBGA
65, 78, 184,
196
G13, J14,
F5, J5
Symbol
Type
VCCD
-
Signal Description
Digital Power Supply - Core.
+2.5 V supply for core digital circuits.
Digital Power Supply - I/O Ring.
18, 29, 47,
56, 208
A2, A8,
C1, C11,
D14
VCCIO
-
+2.5/3.3 V supply for digital I/O circuits. The digital
input circuits running off of this rail, having a TTL-level
threshold and over-voltage protection, may be
interfaced with 3.3/5.0 V, when the IO supply is 3.3 V,
and 2.5/3.3/5.0 V when 2.5 V.
Digital Power Supply - PECL Signal Detect Inputs.
98, 164
L13, L5
VCCPECL
-
103, 116,
117, 130,
131, 144,
145, 158
N13, P4,
P7, P8,
P9, P10,
P11, P12
VCCR
-
+2.5/3.3 V supply for PECL Signal Detect input
circuits. If Fiber Mode is not used, tie these pins to
GNDPECL to save power.
Analog Power Supply - Receive.
+2.5 V supply for all analog receive circuits.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
48
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 15. Intel® LXT9785/LXT9785E Power Supply Signal Descriptions – PQFP (Sheet 2 of 2)
Pin/Ball Designation
PQFP
PBGA
109, 123,
138, 152
N6, N7,
N9, N11,
N12
66, 79,
183, 195
A1, A9,
B3, B7,
C5, C13,
C17, D1,
D3, D6,
D10, D15,
E5, E7,
E9, E11,
E13, E17,
F13, H8,
H9, H10,
J8, J9,
J10, K8,
K9, K10
9, 19, 30,
38, 48, 57,
74, 188,
199, 207
Symbol
Type
VCCT
-
Signal Description
Analog Power Supply - Transmit.
+2.5 V supply for all analog transmit circuits.
Digital Ground.
GNDD
-
GNDIO
-
99, 163
M5, M13
GNDPECL
-
106, 112,
120, 126,
135, 141,
149, 155
P5, P6,
P13, R7,
R9, R11,
R13, U8
GNDR
-
113, 127,
134, 148
P14, R1,
R3, R5,
R15, R17,
T17, U2,
U4, U6,
U10, U12,
U14, U16,
U17
GNDT
-
179
K14
SGND
-
Ground return for core digital supplies (VCCD). All
ground pins can be tied together using a single ground
plane.
Digital GND - I/O Ring.
Ground return for digital I/O circuits (VCCIO).
Digital GND - PECL Signal Detect Inputs.
Ground return for PECL Signal Detect input circuits.
Analog Ground - Receive.
Ground return for receive analog supply. All ground
pins can be tied together using a single ground plane.
Analog Ground - Transmit.
Ground return for transmit analog supply. All ground
pins can be tied together using a single ground plane.
Substrate Ground.
Ground for chip substrate. All ground pins can be tied
together using a single ground plane.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
49
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 16. Intel® LXT9785/LXT9785E Unused/Reserved Pins – PQFP
Pin/Ball Designation
PQFP
PBGA
N/C
F15, G2,
G5, G14,
G16, H4,
H14, J2,
J13, K4,
K15
Symbol
Type1
N/C
–
Signal Description
No Connection.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2.
Table 17. Intel® LXT9785/LXT9785E Receive FIFO Depth Considerations
50
FIFOSEL1
FIFOSEL0
Register 18.15
Value
Register 18.14
Value
0
0
1
0
0
1
1
1
1
0
0
0
1
1
0
1
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.3
BGA23 Ball Assignments
The following sections provide BGA23 ball location and signal description information for RMII,
SMII, and SS-SMII:
•
•
•
•
Table 3.3.1 “RMII BGA23 Ball List” on page 52
Table 3.3.2 “SMII BGA23 Ball List” on page 62
Table 3.3.3 “SS-SMII BGA23 Ball List” on page 72
Table 3.4 “BGA23 Signal Descriptions” on page 82
Figure 5 illustrates the LXT9785/LXT9785E 241-ball BGA23 ball locations for RMII, SMII, and
SS-SMII.
Figure 5. Intel® LXT9785/LXT9785E 241-Ball BGA23 Assignments (Top View)
1
2
3
4
5
6
7
8
9
10
11
A
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 A12 A13 A14 A15
A16 A17
A
B
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11 B12 B13 B14 B15
B16 B17
B
C
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10 C11 C12 C13 C14 C15 C16 C17
C
D
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11 D12 D13 D14 D15 D16 D17
D
E
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11 E12 E13 E14 E15
E16 E17
E
F
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F16
F17
F
G
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10 G11 G12 G13 G14 G15 G16 G17
G
H
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10 H11 H12 H13 H14 H15 H16 H17
H
J
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J17
J
K
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10 K11 K12 K13 K14 K15 K16 K17
K
L
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L
M
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10 M11 M12 M13 M14 M15 M16 M17
M
N
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10 N11 N12 N13 N14 N15 N16 N17
N
P
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10 P11 P12 P13 P14 P15 P16 P17
P
R
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10 R11 R12 R13 R14 R15 R16 R17
R
T
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T17
T
U
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10 U11 U12 U13 U14 U15 U16 U17
U
1
2
3
4
5
6
7
8
9
10
J11
L11
T11
11
12
F12
J12
L12
T12
12
13
F13
J13
L13
T13
13
14
F14
J14
L14
T14
14
15
F15
J15
L15
T15
15
16
J16
L16
T16
16
17
L17
17
= No Ball
B1498-01
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
51
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.3.1
RMII BGA23 Ball List
The following tables provide the RMII BGA23 ball locations and signal names arranged in
alphanumeric order as follows:
• Table 18 “Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by
Signal Name”
• Table 19 “Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by
Ball Location” on page 57
Table 18. Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Signal
Name
52
Signal
Ball Type1
Reference for
Full Description
Signal
Ball Type1
Reference for
Full Description
ADD_0
N2
I, ST, ID
Table 32 (page 90)
GNDD
D10 –
Table 34 (page 95)
ADD_1
N1
I, ST, ID
Table 32 (page 90)
GNDD
D15 –
Table 34 (page 95)
ADD_2
M3
I, ST, ID
Table 32 (page 90)
GNDD
E5
–
Table 34 (page 95)
ADD_3
M2
I, ST, ID
Table 32 (page 90)
GNDD
E7
–
Table 34 (page 95)
ADD_4
L4
I, ST, ID
Table 32 (page 90)
GNDD
E9
–
Table 34 (page 95)
AMDIX_EN
K1
I, ST, IP
Table 32 (page 90)
GNDD
E11 –
Table 34 (page 95)
CFG_1
M1
I, ST, ID
Table 32 (page 90)
GNDD
E13 –
Table 34 (page 95)
CFG_2
L3
I, ST, ID
Table 32 (page 90)
GNDD
E17 –
Table 34 (page 95)
CFG_3
L2
I, ST, ID
Table 32 (page 90)
GNDD
F13 –
Table 34 (page 95)
CRS_DV0
E4
O, TS, SL
Table 24 (page 82)
GNDD
H8
–
Table 34 (page 95)
CRS_DV1
C4
O, TS, SL
Table 24 (page 82)
GNDD
H9
–
Table 34 (page 95)
CRS_DV2
A5
O, TS, SL
Table 24 (page 82)
GNDD
H10 –
Table 34 (page 95)
CRS_DV3
B8
O, TS, SL
Table 24 (page 82)
GNDD
J8
–
Table 34 (page 95)
CRS_DV4
B12 O, TS, SL
Table 24 (page 82)
GNDD
J9
–
Table 34 (page 95)
CRS_DV5
D12 O, TS, SL
Table 24 (page 82)
GNDD
J10
–
Table 34 (page 95)
CRS_DV6
B16 O, TS, SL
Table 24 (page 82)
GNDD
K8
–
Table 34 (page 95)
CRS_DV7
E15 O, TS, SL
Table 24 (page 82)
GNDD
K9
–
Table 34 (page 95)
G_FX/TP
M14 I, ST, ID
Table 32 (page 90)
GNDD
K10 –
Table 34 (page 95)
GNDD
A1
–
Table 34 (page 95)
GNDPECL
M5
–
Table 34 (page 95)
GNDD
A9
–
Table 34 (page 95)
GNDPECL
M13 –
Table 34 (page 95)
GNDD
B3
–
Table 34 (page 95)
GNDR
P5
–
Table 34 (page 95)
GNDD
B7
–
Table 34 (page 95)
GNDR
P6
–
Table 34 (page 95)
GNDD
C5
–
Table 34 (page 95)
GNDR
P13 –
Table 34 (page 95)
GNDD
C13 –
Table 34 (page 95)
GNDR
R7
–
Table 34 (page 95)
GNDD
C17 –
Table 34 (page 95)
GNDR
R9
–
Table 34 (page 95)
GNDD
D1
–
Table 34 (page 95)
GNDR
R11 –
Table 34 (page 95)
GNDD
D3
–
Table 34 (page 95)
GNDR
R13 –
Table 34 (page 95)
GNDD
D6
–
Table 34 (page 95)
GNDR
U8
Table 34 (page 95)
–
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal
Ball Type1
Reference for
Full Description
GNDT
P14 –
Table 34 (page 95)
GNDT
R1
–
Table 34 (page 95)
GNDT
R3
–
Table 34 (page 95)
GNDT
R5
–
Table 34 (page 95)
GNDT
R15 –
Table 34 (page 95)
GNDT
R17 –
Table 34 (page 95)
GNDT
T17 –
Table 34 (page 95)
GNDT
U2
–
Table 34 (page 95)
GNDT
U4
–
Table 34 (page 95)
GNDT
U6
–
Table 34 (page 95)
GNDT
U10 –
Table 34 (page 95)
GNDT
U12 –
Table 34 (page 95)
GNDT
U14 –
Table 34 (page 95)
GNDT
U16 –
Table 34 (page 95)
GNDT
U17 –
Table 34 (page 95)
K3
OD, TS,
SL, IP
Table 33 (page 94)
LED0_2
K2
OD, TS,
SL, IP
Table 33 (page 94)
LED0_3
J1
OD, TS,
SL, IP
Table 33 (page 94)
J4
OD, TS,
SL, IP
Table 33 (page 94)
J3
OD, TS,
SL, IP
Table 33 (page 94)
H1
OD, TS,
SL, IP
Table 33 (page 94)
H2
OD, TS,
SL, IP
Table 33 (page 94)
LED2_2
H3
OD, TS,
SL, IP
Table 33 (page 94)
LED2_3
G1
OD, TS,
SL, IP
Table 33 (page 94)
LED3_1
F2
OD, TS,
SL, IP
Table 33 (page 94)
Table 33 (page 94)
Table 33 (page 94)
LED0_1
LED1_1
LED1_2
LED1_3
LED2_1
LED3_2
G3
OD, TS,
SL, IP
LED3_3
G4
OD, TS,
SO, IP
LED4_1
OD, TS,
K16
SL, IP
Table 33 (page 94)
LED4_2
K17
OD, TS,
SL, IP
Table 33 (page 94)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Reference for
Full Description
Signal
Ball Type1
LED4_3
J17
OD, TS,
SL, IP
Table 33 (page 94)
LED5_1
J15
OD, TS,
SL, IP
Table 33 (page 94)
LED5_2
J16
OD, TS,
SL, IP
Table 33 (page 94)
LED5_3
H17
OD, TS,
SL, IP
Table 33 (page 94)
LED6_1
H15
OD, TS,
SL, IP
Table 33 (page 94)
LED6_2
H16
OD, TS,
SL, IP
Table 33 (page 94)
LED6_3
G17
OD, TS,
SL, IP
Table 33 (page 94)
LED7_1
G15
OD, TS,
SL, IP
Table 33 (page 94)
LED7_2
F17
OD, TS,
SL, IP
Table 33 (page 94)
LED7_3
F16
OD, TS,
SL, IP
Table 33 (page 94)
MDC0
E1
I, ST, ID
Table 28 (page 87)
MDC1
B10 I, ST, ID
Table 28 (page 87)
MDDIS
L1
I, ST, ID
Table 28 (page 87)
MDINT0
F1
OD, TS,
SL, IP
Table 28 (page 87)
MDINT1
C9
OD, TS,
SL, IP
Table 28 (page 87)
MDIO0
F3
I/O, TS,
SL, IP
Table 28 (page 87)
MDIO1
A10
I/O, TS,
SL, IP
Table 28 (page 87)
ModeSel0
L16 I, ST, ID
Table 32 (page 90)
ModeSel1
L17 I, ST, ID
Table 32 (page 90)
N/C
F15 –
Table 35 (page 97)
N/C
G2
–
Table 35 (page 97)
N/C
G5
–
Table 35 (page 97)
N/C
G14 –
Table 35 (page 97)
N/C
G16 –
Table 35 (page 97)
N/C
H4
–
Table 35 (page 97)
N/C
H14 –
Table 35 (page 97)
N/C
J2
–
Table 35 (page 97)
N/C
J13
–
Table 35 (page 97)
N/C
K4
–
Table 35 (page 97)
N/C
K15 –
Table 35 (page 97)
53
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal
Reference for
Full Description
Signal
Ball Type1
Reference for
Full Description
No ball
F6
–
–
No Ball
L11
–
–
No ball
F7
–
–
No Ball
M6
–
–
No ball
F8
–
–
No Ball
M7
–
–
No Ball
E8
–
–
No Ball
M8
–
–
No Ball
E10
No Ball
M9
–
–
No Ball
F9
–
–
No Ball
M10 –
–
No Ball
F10 –
–
No Ball
M11 –
–
No Ball
F11
–
–
No Ball
M12 –
–
No Ball
F12 –
–
No Ball
N8
–
–
No Ball
G6
–
–
No Ball
N10 –
–
No Ball
G7
–
–
PWRDWN
L14 I, ST, ID
Table 32 (page 90)
No Ball
G8
–
–
REFCLK0
E6
I
Table 24 (page 82)
No Ball
G9
–
–
REFCLK1
E12 I
Table 24 (page 82)
No Ball
G10 –
–
RESET
M15 I, ST, IP
Table 32 (page 90)
No Ball
G11 –
–
RxData0_0
No Ball
G12 –
C2
O, TS
Table 24 (page 82)
–
RxData0_1
B1
O, TS, ID
Table 24 (page 82)
No Ball
H5
–
–
RxData1_0
A3
O, TS
Table 24 (page 82)
No Ball
H6
–
–
RxData1_1
B4
O, TS, ID
Table 24 (page 82)
No Ball
H7
–
–
RxData2_0
B6
O, TS
Table 24 (page 82)
No Ball
H11 –
–
RxData2_1
C7
O, TS, ID
Table 24 (page 82)
No Ball
H12 –
–
RxData3_0
D9
O, TS
Table 24 (page 82)
No Ball
H13 –
–
RxData3_1
B9
O, TS, ID
Table 24 (page 82)
–
–
RxData4_0
A13 O, TS
Table 24 (page 82)
No Ball
54
Ball Type1
J6
No Ball
J7
–
–
RxData4_1
C12 O, TS,ID
Table 24 (page 82)
No Ball
J11
–
–
RxData5_0
B14 O, TS
Table 24 (page 82)
No Ball
J12
–
–
RxData5_1
B15 O, TS, ID
Table 24 (page 82)
No Ball
K5
–
–
RxData6_0
C15 O, TS
Table 24 (page 82)
No Ball
K6
–
–
RxData6_1
B17 O, TS, ID
Table 24 (page 82)
No Ball
K7
–
–
RxData7_0
E16 O, TS
Table 24 (page 82)
No Ball
K11 –
–
RxData7_1
F14 O, TS, ID
Table 24 (page 82)
No Ball
K12 –
–
D2
K13 –
–
O, TS, SL,
ID, I, ST
Table 32 (page 90)
No Ball
RxER0
(MDIX)
RxER1
(PAUSE)
D5
O, TS, SL,
ID, I, ST
Table 32 (page 90)
No Ball
L6
–
–
No Ball
L7
–
–
No Ball
L8
–
–
RxER2
(PREASEL)
D7
O, TS, SL,
ID, I, ST
Table 24 (page 82)
No Ball
L9
–
–
RxER3
C8
O, TS, SL,
ID
Table 24 (page 82)
No Ball
L10 –
–
No Ball
L11
–
RxER4
(FIFOSEL0)
A12
O, TS, SL,
ID, I, ST
Table 24 (page 82)
–
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Reference for
Full Description
Signal
Ball Type1
RxER5
(FIFOSEL1)
A15
O, TS, SL,
ID, I, ST
Table 24 (page 82)
RxER6LINK
HOLD
A17
O, TS, SL,
ID
Table 24 (page 82)
RxER7
D17
O, TS, SL,
ID
Table 24 (page 82)
Signal
Ball Type1
Reference for
Full Description
TPFON2
U5
AO/AI
Table 30 (page 88)
TPFON3
T7
AO/AI
Table 30 (page 88)
R10 AO/AI
Table 30 (page 88)
TPFON5
U11 AO/AI
Table 30 (page 88)
TPFON6
U15 AO/AI
Table 30 (page 88)
TPFON4
SD_2P5V
P1
I, ST, ID
Table 29 (page 88)
TPFON7
T15 AO/AI
Table 30 (page 88)
SD0
P2
I
Table 29 (page 88)
TPFOP0
T2
AO/AI
Table 30 (page 88)
SD1
N4
I
Table 29 (page 88)
TPFOP1
T3
AO/AI
Table 30 (page 88)
SD2
P3
I
Table 29 (page 88)
TPFOP2
T6
AO/AI
Table 30 (page 88)
SD3
N5
I
Table 29 (page 88)
TPFOP3
U7
AO/AI
Table 30 (page 88)
SD4
P15 I
Table 29 (page 88)
TPFOP4
T10 AO/AI
Table 30 (page 88)
SD5
P16 I
Table 29 (page 88)
TPFOP5
T11
AO/AI
Table 30 (page 88)
SD6
P17 I
Table 29 (page 88)
TPFOP6
T14 AO/AI
Table 30 (page 88)
SD7
N17 I
Table 29 (page 88)
TPFOP7
R14 AO/AI
Table 30 (page 88)
SECTION
L15 I, ST, ID
Table 32 (page 90)
TRST
M17 I, ST, IP
Table 31 (page 89)
SGND
K14 –
Table 34 (page 95)
TxData0_0
E2
I, ID
Table 24 (page 82)
TCK
M16 I, ST, ID
Table 31 (page 89)
TxData0_1
F4
I, ID
Table 24 (page 82)
TDI
N14 I, ST, IP
Table 31 (page 89)
TxData1_0
C3
I, ID
Table 24 (page 82)
TDO
N15 O, TS
Table 31 (page 89)
TxData1_1
D4
I, ID
Table 24 (page 82)
TMS
N16 I, ST, IP
Table 31 (page 89)
TxData2_0
B5
I, ID
Table 24 (page 82)
TPFIN0
T1
AO/AI
Table 30 (page 88)
TxData2_1
A4
I, ID
Table 24 (page 82)
TPFIN1
T4
AO/AI
Table 30 (page 88)
TxData3_0
D8
I, ID
Table 24 (page 82)
TPFIN2
T5
AO/AI
Table 30 (page 88)
TxData3_1
A6
I, ID
Table 24 (page 82)
TPFIN3
R8
AO/AI
Table 30 (page 88)
TxData4_0
A11 I, ID
Table 24 (page 82)
TPFIN4
U9
AO/AI
Table 30 (page 88)
TxData4_1
C10 I, ID
Table 24 (page 82)
TPFIN5
T12 AO/AI
Table 30 (page 88)
TxData5_0
B13 I, ID
Table 24 (page 82)
TPFIN6
T13 AO/AI
Table 30 (page 88)
TxData5_1
D11 I, ID
Table 24 (page 82)
TPFIN7
T16 AO/AI
Table 30 (page 88)
TxData6_0
D13 I, ID
Table 24 (page 82)
TPFIP0
R2
AO/AI
Table 30 (page 88)
TxData6_1
A16 I, ID
Table 24 (page 82)
TPFIP1
U3
AO/AI
Table 30 (page 88)
TxData7_0
E14 I, ID
Table 24 (page 82)
TPFIP2
R6
AO/AI
Table 30 (page 88)
TxData7_1
C16 I, ID
Table 24 (page 82)
TPFIP3
T8
AO/AI
Table 30 (page 88)
TxEN0
E3
I, ID
Table 24 (page 82)
TPFIP4
T9
AO/AI
Table 30 (page 88)
TxEN1
B2
I, ID
Table 24 (page 82)
TPFIP5
U13 AO/AI
Table 30 (page 88)
TxEN2
C6
I, ID
Table 24 (page 82)
TPFIP6
R12 AO/AI
Table 30 (page 88)
TxEN3
A7
I, ID
Table 24 (page 82)
TPFIP7
R16 AO/AI
Table 30 (page 88)
TxEN4
B11 I, ID
Table 24 (page 82)
TPFON0
U1
AO/AI
Table 30 (page 88)
TxEN5
A14 I, ID
Table 24 (page 82)
TPFON1
R4
AO/AI
Table 30 (page 88)
TxEN6
C14 I, ID
Table 24 (page 82)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
55
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal
Ball Type1
Reference for
Full Description
TxEN7
D16 I, ID
Table 24 (page 82)
TxSLEW_0
N3
I, ST, ID
Table 32 (page 90)
TxSLEW_1
M4
I, ST, ID
Table 32 (page 90)
F5
–
Table 34 (page 95)
G13 –
Table 34 (page 95)
VCCD
VCCD
56
VCCD
J5
–
Table 34 (page 95)
VCCD
J14
–
Table 34 (page 95)
VCCIO
A2
–
Table 34 (page 95)
VCCIO
A8
–
Table 34 (page 95)
VCCIO
C1
–
Table 34 (page 95)
VCCIO
C11 –
Table 34 (page 95)
VCCIO
D14 –
Table 34 (page 95)
VCCPECL
L5
–
Table 34 (page 95)
VCCPECL
L13 –
Table 34 (page 95)
VCCR
N13 –
Table 34 (page 95)
VCCR
P4
–
Table 34 (page 95)
VCCR
P7
–
Table 34 (page 95)
VCCR
P8
–
Table 34 (page 95)
VCCR
P9
–
Table 34 (page 95)
VCCR
P10 –
Table 34 (page 95)
VCCR
P11 –
Table 34 (page 95)
VCCR
P12 –
Table 34 (page 95)
VCCT
N6
–
Table 34 (page 95)
VCCT
N7
–
Table 34 (page 95)
VCCT
N9
–
Table 34 (page 95)
VCCT
N11 –
Table 34 (page 95)
VCCT
N12 –
Table 34 (page 95)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 19. Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Ball
Location
Ball
Signal
Type1
Reference for
Full Description
Ball
Signal
Type1
Reference for
Full Description
A1
GNDD
–
Table 34 (page 95)
B17
RxData6_1
O, TS, ID
Table 24 (page 82)
A2
VCCIO
–
Table 34 (page 95)
C1
VCCIO
–
Table 34 (page 95)
A3
RxData1_0
O, TS
Table 24 (page 82)
C2
RxData0_0
O, TS
Table 24 (page 82)
A4
TxData2_1
I, ID
Table 24 (page 82)
C3
TxData1_0
I, ID
Table 24 (page 82)
A5
CRS_DV2
O, TS, SL
Table 24 (page 82)
C4
CRS_DV1
O, TS, SL
Table 24 (page 82)
A6
TxData3_1
I, ID
Table 24 (page 82)
C5
GNDD
–
Table 34 (page 95)
A7
TxEN3
I, ID
Table 24 (page 82)
C6
TxEN2
I, ID
Table 24 (page 82)
A8
VCCIO
–
Table 34 (page 95)
C7
RxData2_1
O, TS, ID
Table 24 (page 82)
A9
GNDD
–
Table 34 (page 95)
C8
RxER3
O, TS, SL,
Table 24 (page 82)
ID
A10
MDIO1
I/O, TS,
SL, IP
Table 28 (page 87)
C9
MDINT1
TxData4_0
I, ID
Table 24 (page 82)
OD, TS,
SL, IP
Table 28 (page 87)
A11
RxER4
(FIFOSEL0)
O, TS, SL,
Table 24 (page 82)
ID, I, ST
C10
TxData4_1
I, ID
Table 24 (page 82)
A12
C11
VCCIO
–
Table 34 (page 95)
A13
RxData4_0
O, TS
Table 24 (page 82)
C12
RxData4_1
O, TS,ID
Table 24 (page 82)
A14
TxEN5
I, ID
Table 24 (page 82)
C13
GNDD
–
Table 34 (page 95)
A15
RxER5
(FIFOSEL1)
O, TS, SL,
Table 24 (page 82)
ID, I, ST
C14
TxEN6
I, ID
Table 24 (page 82)
C15
RxData6_0
O, TS
Table 24 (page 82)
A16
TxData6_1
I, ID
C16
TxData7_1
I, ID
Table 24 (page 82)
A17
RxER6LINK
HOLD
O, TS, SL,
Table 24 (page 82)
ID
C17
GNDD
–
Table 34 (page 95)
B1
RxData0_1
O, TS, ID
D1
GNDD
–
Table 34 (page 95)
D2
RxER0
(MDIX)
O, TS, SL,
Table 32 (page 90)
ID, I, ST
D3
GNDD
–
Table 34 (page 95)
D4
TxData1_1
I, ID
Table 24 (page 82)
D5
RxER1
(PAUSE)
O, TS, SL,
Table 32 (page 90)
ID, I, ST
D6
GNDD
–
D7
RxER2
(PREASEL)
O, TS, SL,
Table 24 (page 82)
ID, I, ST
Table 24 (page 82)
Table 24 (page 82)
B2
TxEN1
I, ID
Table 24 (page 82)
B3
GNDD
–
Table 34 (page 95)
B4
RxData1_1
O, TS, ID
Table 24 (page 82)
B5
TxData2_0
I, ID
Table 24 (page 82)
B6
RxData2_0
O, TS
Table 24 (page 82)
B7
GNDD
–
Table 34 (page 95)
B8
CRS_DV3
O, TS, SL
Table 24 (page 82)
B9
RxData3_1
O, TS, ID
Table 24 (page 82)
B10
MDC1
I, ST, ID
Table 28 (page 87)
B11
TxEN4
I, ID
Table 24 (page 82)
B12
CRS_DV4
O, TS, SL
Table 24 (page 82)
B13
TxData5_0
I, ID
Table 24 (page 82)
B14
RxData5_0
O, TS
Table 24 (page 82)
B15
RxData5_1
O, TS, ID
Table 24 (page 82)
B16
CRS_DV6
O, TS, SL
Table 24 (page 82)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Table 34 (page 95)
D8
TxData3_0
I, ID
Table 24 (page 82)
D9
RxData3_0
O, TS
Table 24 (page 82)
D10
GNDD
–
Table 34 (page 95)
D11
TxData5_1
I, ID
Table 24 (page 82)
D12
CRS_DV5
O, TS, SL
Table 24 (page 82)
D13
TxData6_0
I, ID
Table 24 (page 82)
D14
VCCIO
–
Table 34 (page 95)
D15
GNDD
–
Table 34 (page 95)
57
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball
Signal
Type1
Reference for
Full Description
D16
TxEN7
I, ID
Table 24 (page 82)
RxER7
O, TS, SL,
Table 24 (page 82)
ID
D17
58
Ball
Signal
Type1
Reference for
Full Description
F17
LED7_2
OD, TS,
SL, IP
Table 33 (page 94)
G1
LED2_3
OD, TS,
SL, IP
Table 33 (page 94)
G2
N/C
–
Table 35 (page 97)
G3
LED3_2
OD, TS,
SL, IP
Table 33 (page 94)
G4
LED3_3
OD, TS,
SO, IP
Table 33 (page 94)
E1
MDC0
I, ST, ID
Table 28 (page 87)
E2
TxData0_0
I, ID
Table 24 (page 82)
E3
TxEN0
I, ID
Table 24 (page 82)
E4
CRS_DV0
O, TS, SL
Table 24 (page 82)
E5
GNDD
–
Table 34 (page 95)
E6
REFCLK0
I
Table 24 (page 82)
G5
N/C
–
Table 35 (page 97)
E7
GNDD
–
Table 34 (page 95)
G6
No Ball
–
–
E8
No Ball
–
–
G7
No Ball
–
–
Table 34 (page 95)
G8
No Ball
–
–
G9
No Ball
–
–
G10
No Ball
–
–
E9
GNDD
–
E10
No Ball
E11
GNDD
–
Table 34 (page 95)
E12
REFCLK1
I
Table 24 (page 82)
G11
No Ball
–
–
No Ball
–
–
E13
GNDD
–
Table 34 (page 95)
G12
E14
TxData7_0
I, ID
Table 24 (page 82)
G13
VCCD
–
Table 34 (page 95)
E15
CRS_DV7
O, TS, SL
Table 24 (page 82)
G14
N/C
–
Table 35 (page 97)
E16
RxData7_0
O, TS
Table 24 (page 82)
G15
LED7_1
OD, TS,
SL, IP
Table 33 (page 94)
E17
GNDD
–
Table 34 (page 95)
G16
N/C
–
Table 35 (page 97)
F1
MDINT0
OD, TS,
SL, IP
Table 28 (page 87)
G17
LED6_3
OD, TS,
SL, IP
Table 33 (page 94)
F2
LED3_1
OD, TS,
SL, IP
Table 33 (page 94)
H1
LED1_3
OD, TS,
SL, IP
Table 33 (page 94)
F3
MDIO0
I/O, TS,
SL, IP
Table 28 (page 87)
H2
LED2_1
OD, TS,
SL, IP
Table 33 (page 94)
F4
TxData0_1
I, ID
Table 24 (page 82)
F5
VCCD
–
Table 34 (page 95)
H3
LED2_2
OD, TS,
SL, IP
Table 33 (page 94)
F6
No ball
–
–
H4
N/C
–
Table 35 (page 97)
F7
No ball
–
–
H5
No Ball
–
–
F8
No ball
–
–
H6
No Ball
–
–
F9
No Ball
–
–
H7
No Ball
–
–
F10
No Ball
–
–
H8
GNDD
–
Table 34 (page 95)
F11
No Ball
–
–
H9
GNDD
–
Table 34 (page 95)
F12
No Ball
–
–
H10
GNDD
–
Table 34 (page 95)
F13
GNDD
–
Table 34 (page 95)
H11
No Ball
–
–
F14
RxData7_1
O, TS, ID
Table 24 (page 82)
H12
No Ball
–
–
F15
N/C
–
Table 35 (page 97)
H13
No Ball
–
–
F16
LED7_3
OD, TS,
SL, IP
Table 33 (page 94)
H14
N/C
–
Table 35 (page 97)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball
Signal
Type1
Reference for
Full Description
H15
LED6_1
OD, TS,
SL, IP
Table 33 (page 94)
H16
LED6_2
OD, TS,
SL, IP
Table 33 (page 94)
H17
LED5_3
OD, TS,
SL, IP
Table 33 (page 94)
J1
LED0_3
OD, TS,
SL, IP
Table 33 (page 94)
J2
N/C
–
Table 35 (page 97)
J3
LED1_2
OD, TS,
SL, IP
Table 33 (page 94)
J4
LED1_1
OD, TS,
SL, IP
Table 33 (page 94)
J5
VCCD
–
Table 34 (page 95)
J6
No Ball
–
–
J7
No Ball
–
–
J8
GNDD
–
Table 34 (page 95)
J9
GNDD
–
Table 34 (page 95)
J10
GNDD
–
Table 34 (page 95)
J11
No Ball
–
–
J12
No Ball
–
–
J13
N/C
–
Table 35 (page 97)
Ball
Signal
Type1
Reference for
Full Description
K12
No Ball
–
–
K13
No Ball
–
–
K14
SGND
–
Table 34 (page 95)
K15
N/C
–
Table 35 (page 97)
K16
LED4_1
OD, TS,
SL, IP
Table 33 (page 94)
K17
LED4_2
OD, TS,
SL, IP
Table 33 (page 94)
L1
MDDIS
I, ST, ID
Table 28 (page 87)
L2
CFG_3
I, ST, ID
Table 32 (page 90)
L3
CFG_2
I, ST, ID
Table 32 (page 90)
L4
ADD_4
I, ST, ID
Table 32 (page 90)
L5
VCCPECL
–
Table 34 (page 95)
L6
No Ball
–
–
L7
No Ball
–
–
L8
No Ball
–
–
L9
No Ball
–
–
L10
No Ball
–
–
L11
No Ball
–
–
L11
No Ball
–
–
L13
VCCPECL
–
Table 34 (page 95)
L14
PWRDWN
I, ST, ID
Table 32 (page 90)
L15
SECTION
I, ST, ID
Table 32 (page 90)
L16
ModeSel0
I, ST, ID
Table 32 (page 90)
L17
ModeSel1
I, ST, ID
Table 32 (page 90)
J14
VCCD
–
Table 34 (page 95)
J15
LED5_1
OD, TS,
SL, IP
Table 33 (page 94)
J16
LED5_2
OD, TS,
SL, IP
Table 33 (page 94)
Table 33 (page 94)
M1
CFG_1
I, ST, ID
Table 32 (page 90)
M2
ADD_3
I, ST, ID
Table 32 (page 90)
M3
ADD_2
I, ST, ID
Table 32 (page 90)
M4
TxSLEW_1
I, ST, ID
Table 32 (page 90)
M5
GNDPECL
–
Table 34 (page 95)
M6
No Ball
–
–
M7
No Ball
–
–
M8
No Ball
–
–
M9
No Ball
–
–
M10
No Ball
–
–
J17
LED4_3
OD, TS,
SL, IP
K1
AMDIX_EN
I, ST, IP
Table 32 (page 90)
K2
LED0_2
OD, TS,
SL, IP
Table 33 (page 94)
K3
LED0_1
OD, TS,
SL, IP
Table 33 (page 94)
K4
N/C
–
Table 35 (page 97)
K5
No Ball
–
–
K6
No Ball
–
–
K7
No Ball
–
–
K8
GNDD
–
Table 34 (page 95)
K9
GNDD
–
Table 34 (page 95)
K10
GNDD
–
Table 34 (page 95)
K11
No Ball
–
–
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
M11
No Ball
–
–
M12
No Ball
–
–
M13
GNDPECL
–
Table 34 (page 95)
M14
G_FX/TP
I, ST, ID
Table 32 (page 90)
59
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball
Signal
Type1
Reference for
Full Description
Ball
Signal
Type1
Reference for
Full Description
M15
RESET
I, ST, IP
Table 32 (page 90)
R2
TPFIP0
AO/AI
Table 30 (page 88)
M16
TCK
I, ST, ID
Table 31 (page 89)
R3
GNDT
–
Table 34 (page 95)
M17
TRST
I, ST, IP
Table 31 (page 89)
R4
TPFON1
AO/AI
Table 30 (page 88)
N1
ADD_1
I, ST, ID
Table 32 (page 90)
R5
GNDT
–
Table 34 (page 95)
N2
ADD_0
I, ST, ID
Table 32 (page 90)
R6
TPFIP2
AO/AI
Table 30 (page 88)
N3
TxSLEW_0
I, ST, ID
Table 32 (page 90)
R7
GNDR
–
Table 34 (page 95)
N4
SD1
I
Table 29 (page 88)
R8
TPFIN3
AO/AI
Table 30 (page 88)
N5
SD3
I
Table 29 (page 88)
R9
GNDR
–
Table 34 (page 95)
N6
VCCT
–
Table 34 (page 95)
R10
TPFON4
AO/AI
Table 30 (page 88)
N7
VCCT
–
Table 34 (page 95)
R11
GNDR
–
Table 34 (page 95)
N8
No Ball
–
–
R12
TPFIP6
AO/AI
Table 30 (page 88)
N9
VCCT
–
Table 34 (page 95)
R13
GNDR
–
Table 34 (page 95)
N10
No Ball
–
–
R14
TPFOP7
AO/AI
Table 30 (page 88)
N11
VCCT
–
Table 34 (page 95)
R15
GNDT
–
Table 34 (page 95)
N12
VCCT
–
Table 34 (page 95)
R16
TPFIP7
AO/AI
Table 30 (page 88)
N13
VCCR
–
Table 34 (page 95)
R17
GNDT
–
Table 34 (page 95)
N14
TDI
I, ST, IP
Table 31 (page 89)
T1
TPFIN0
AO/AI
Table 30 (page 88)
N15
TDO
O, TS
Table 31 (page 89)
T2
TPFOP0
AO/AI
Table 30 (page 88)
N16
TMS
I, ST, IP
Table 31 (page 89)
T3
TPFOP1
AO/AI
Table 30 (page 88)
SD7
I
Table 29 (page 88)
T4
TPFIN1
AO/AI
Table 30 (page 88)
P1
SD_2P5V
I, ST, ID
Table 29 (page 88)
T5
TPFIN2
AO/AI
Table 30 (page 88)
P2
SD0
I
Table 29 (page 88)
T6
TPFOP2
AO/AI
Table 30 (page 88)
P3
SD2
I
Table 29 (page 88)
T7
TPFON3
AO/AI
Table 30 (page 88)
P4
VCCR
–
Table 34 (page 95)
T8
TPFIP3
AO/AI
Table 30 (page 88)
P5
GNDR
–
Table 34 (page 95)
T9
TPFIP4
AO/AI
Table 30 (page 88)
P6
GNDR
–
Table 34 (page 95)
T10
TPFOP4
AO/AI
Table 30 (page 88)
P7
VCCR
–
Table 34 (page 95)
T11
TPFOP5
AO/AI
Table 30 (page 88)
P8
VCCR
–
Table 34 (page 95)
T12
TPFIN5
AO/AI
Table 30 (page 88)
P9
VCCR
–
Table 34 (page 95)
T13
TPFIN6
AO/AI
Table 30 (page 88)
P10
VCCR
–
Table 34 (page 95)
T14
TPFOP6
AO/AI
Table 30 (page 88)
P11
VCCR
–
Table 34 (page 95)
T15
TPFON7
AO/AI
Table 30 (page 88)
P12
VCCR
–
Table 34 (page 95)
T16
TPFIN7
AO/AI
Table 30 (page 88)
P13
GNDR
–
Table 34 (page 95)
T17
GNDT
–
Table 34 (page 95)
P14
GNDT
–
Table 34 (page 95)
U1
TPFON0
AO/AI
Table 30 (page 88)
P15
SD4
I
Table 29 (page 88)
U2
GNDT
–
Table 34 (page 95)
P16
SD5
I
Table 29 (page 88)
U3
TPFIP1
AO/AI
Table 30 (page 88)
P17
SD6
I
Table 29 (page 88)
U4
GNDT
–
Table 34 (page 95)
R1
GNDT
–
Table 34 (page 95)
U5
TPFON2
AO/AI
Table 30 (page 88)
N17
60
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball
Signal
Type1
Reference for
Full Description
U6
GNDT
–
Table 34 (page 95)
U7
TPFOP3
AO/AI
Table 30 (page 88)
U8
GNDR
–
Table 34 (page 95)
U9
TPFIN4
AO/AI
Table 30 (page 88)
U10
GNDT
–
Table 34 (page 95)
U11
TPFON5
AO/AI
Table 30 (page 88)
U12
GNDT
–
Table 34 (page 95)
U13
TPFIP5
AO/AI
Table 30 (page 88)
U14
GNDT
–
Table 34 (page 95)
U15
TPFON6
AO/AI
Table 30 (page 88)
U16
GNDT
–
Table 34 (page 95)
U17
GNDT
–
Table 34 (page 95)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
61
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.3.2
SMII BGA23 Ball List
The following tables provide the SMII ball locations and signal names arranged in alphanumeric
order as follows:
• Table 20 “Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by
Signal Name”
• Table 21 “Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball
Location” on page 67
Table 20. Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Signal
Name
62
Signal
Ball Type1
Reference for
Full Description
Signal
Ball Type1
Reference for
Full Description
ADD_0
N2
I, ST, ID
Table 32 (page 90)
GNDD
D1
–
Table 34 (page 95)
ADD_1
N1
I, ST, ID
Table 32 (page 90)
GNDD
D3
–
Table 34 (page 95)
ADD_2
M3
I, ST, ID
Table 32 (page 90)
GNDD
D6
–
Table 34 (page 95)
ADD_3
M2
I, ST, ID
Table 32 (page 90)
GNDD
D10 –
Table 34 (page 95)
D15 –
Table 34 (page 95)
ADD_4
L4
I, ST, ID
Table 32 (page 90)
GNDD
AMDIX_EN
K1
I, ST, IP
Table 32 (page 90)
GNDD
E5
–
Table 34 (page 95)
CFG_1
M1
I, ST, ID
Table 32 (page 90)
GNDD
E7
–
Table 34 (page 95)
CFG_2
L3
I, ST, ID
Table 32 (page 90)
GNDD
E9
–
Table 34 (page 95)
CFG_3
L2
I, ST, ID
Table 32 (page 90)
GNDD
E11 –
Table 34 (page 95)
CRS_DV0
E4
O, TS, SL
Table 24 (page 82)
GNDD
E13 –
Table 34 (page 95)
CRS_DV1
C4
O, TS, SL
Table 24 (page 82)
GNDD
E17 –
Table 34 (page 95)
CRS_DV2
A5
O, TS, SL
Table 24 (page 82)
GNDD
F13 –
Table 34 (page 95)
CRS_DV3
B8
O, TS, SL
Table 24 (page 82)
GNDD
H8
–
Table 34 (page 95)
CRS_DV4
B12 O, TS, SL
Table 24 (page 82)
GNDD
H9
–
Table 34 (page 95)
CRS_DV5
D12 O, TS, SL
Table 24 (page 82)
GNDD
H10 –
Table 34 (page 95)
CRS_DV6
B16 O, TS, SL
Table 24 (page 82)
GNDD
CRS_DV7
E15 O, TS, SL
Table 24 (page 82)
GNDD
FIFOSEL0
O, TS, SL,
A12
Table 24 (page 82)
ID, I, ST
GNDD
GNDD
FIFOSEL1
A15
G_FX/TP
M14 I, ST, ID
–
Table 34 (page 95)
J9
–
Table 34 (page 95)
J10
–
Table 34 (page 95)
K8
–
Table 34 (page 95)
GNDD
K9
–
Table 34 (page 95)
Table 32 (page 90)
GNDD
K10 –
Table 34 (page 95)
M5
–
Table 34 (page 95)
M13 –
Table 34 (page 95)
O, TS, SL,
Table 24 (page 82)
ID, I, ST
GNDD
A1
–
Table 34 (page 95)
GNDPECL
GNDD
A9
–
Table 34 (page 95)
GNDPECL
GNDD
B3
–
Table 34 (page 95)
GNDR
GNDD
B7
–
Table 34 (page 95)
J8
P5
–
Table 34 (page 95)
GNDR
P6
–
Table 34 (page 95)
P13 –
Table 34 (page 95)
GNDD
C5
–
Table 34 (page 95)
GNDR
GNDD
C13 –
Table 34 (page 95)
GNDR
R7
–
Table 34 (page 95)
GNDD
C17 –
Table 34 (page 95)
GNDR
R9
–
Table 34 (page 95)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal
Ball Type1
Reference for
Full Description
GNDR
R11 –
Table 34 (page 95)
GNDR
R13 –
Table 34 (page 95)
GNDR
U8
–
Table 34 (page 95)
GNDT
P14 –
Table 34 (page 95)
GNDT
R1
–
Table 34 (page 95)
GNDT
R3
–
Table 34 (page 95)
GNDT
R5
–
Table 34 (page 95)
GNDT
R15 –
Table 34 (page 95)
GNDT
R17 –
Table 34 (page 95)
GNDT
T17 –
Table 34 (page 95)
GNDT
U2
–
Table 34 (page 95)
GNDT
U4
–
Table 34 (page 95)
GNDT
U6
–
Table 34 (page 95)
GNDT
U10 –
Table 34 (page 95)
GNDT
U12 –
Table 34 (page 95)
GNDT
U14 –
Table 34 (page 95)
GNDT
U16 –
Table 34 (page 95)
GNDT
U17 –
Table 34 (page 95)
LED0_1
K3
OD, TS,
SL, IP
Table 33 (page 94)
LED0_2
K2
OD, TS,
SL, IP
Table 33 (page 94)
LED0_3
J1
OD, TS,
SL, IP
Table 33 (page 94)
LED1_1
J4
OD, TS,
SL, IP
Table 33 (page 94)
LED1_2
J3
OD, TS,
SL, IP
Table 33 (page 94)
LED1_3
H1
OD, TS,
SL, IP
Table 33 (page 94)
LED2_1
H2
OD, TS,
SL, IP
Table 33 (page 94)
LED2_2
H3
OD, TS,
SL, IP
Table 33 (page 94)
LED2_3
G1
OD, TS,
SL, IP
Table 33 (page 94)
LED3_1
F2
OD, TS,
SL, IP
Table 33 (page 94)
LED3_2
G3
OD, TS,
SL, IP
Table 33 (page 94)
G4
OD, TS,
SO, IP
Table 33 (page 94)
LED3_3
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Reference for
Full Description
Signal
Ball Type1
LED4_1
K16
OD, TS,
SL, IP
Table 33 (page 94)
LED4_2
K17
OD, TS,
SL, IP
Table 33 (page 94)
LED4_3
J17
OD, TS,
SL, IP
Table 33 (page 94)
LED5_1
J15
OD, TS,
SL, IP
Table 33 (page 94)
LED5_2
J16
OD, TS,
SL, IP
Table 33 (page 94)
LED5_3
H17
OD, TS,
SL, IP
Table 33 (page 94)
LED6_1
H15
OD, TS,
SL, IP
Table 33 (page 94)
LED6_2
H16
OD, TS,
SL, IP
Table 33 (page 94)
LED6_3
G17
OD, TS,
SL, IP
Table 33 (page 94)
LED7_1
G15
OD, TS,
SL, IP
Table 33 (page 94)
LED7_2
F17
OD, TS,
SL, IP
Table 33 (page 94)
LED7_3
F16
OD, TS,
SL, IP
Table 33 (page 94)
LINKHOLD
A17
O, TS, SL,
Table 24 (page 82)
ID, I, ST
MDC0
E1
I, ST, ID
Table 28 (page 87)
MDC1
B10 I, ST, ID
Table 28 (page 87)
MDDIS
L1
I, ST, ID
Table 28 (page 87)
MDINT0
F1
OD, TS,
SL, IP
Table 28 (page 87)
MDINT1
C9
OD, TS,
SL, IP
Table 28 (page 87)
MDIO0
F3
I/O, TS,
SL, IP
Table 28 (page 87)
MDIO1
A10
I/O, TS,
SL, IP
Table 28 (page 87)
MDIX
D2
O, TS, SL,
Table 32 (page 90)
ID, I, ST
ModeSel0
L16 I, ST, ID
Table 32 (page 90)
ModeSel1
L17 I, ST, ID
Table 32 (page 90)
N/C
A4
I, ID
Table 24 (page 82)
N/C
A7
I, ID
Table 24 (page 82)
N/C
A14 I, ID
Table 24 (page 82)
N/C
A16 I, ID
Table 24 (page 82)
63
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal
64
Ball Type1
Reference for
Full Description
Signal
Ball Type1
Reference for
Full Description
N/C
B1
O, TS, ID
Table 24 (page 82)
No Ball
F10 –
–
N/C
B2
I, ID
Table 24 (page 82)
No Ball
F11
–
–
N/C
B4
O, TS, ID
Table 24 (page 82)
No Ball
F12 –
–
N/C
B9
O, TS, ID
Table 24 (page 82)
No Ball
G6
–
–
N/C
B11 I, ID
Table 24 (page 82)
No Ball
G7
–
–
N/C
B15 O, TS, ID
Table 24 (page 82)
No Ball
G8
–
–
N/C
B17 O, TS, ID
Table 24 (page 82)
No Ball
G9
–
–
N/C
C6
I, ID
Table 24 (page 82)
No Ball
G10 –
–
N/C
C7
O, TS, ID
Table 24 (page 82)
No Ball
G11 –
–
N/C
C8
O, TS, SL,
Table 24 (page 82)
ID
No Ball
G12 –
–
N/C
C10 I, ID
Table 24 (page 82)
N/C
C12 O, TS,ID
Table 24 (page 82)
N/C
C14 I, ID
Table 24 (page 82)
N/C
D4
I, ID
Table 24 (page 82)
N/C
D11 I, ID
Table 24 (page 82)
N/C
D16 I, ID
Table 24 (page 82)
N/C
O, TS, SL,
D17
Table 24 (page 82)
ID
No Ball
H5
–
–
No Ball
H6
–
–
No Ball
H7
–
–
No Ball
H11 –
–
No Ball
H12 –
–
No Ball
H13 –
–
No Ball
J6
–
–
No Ball
J7
–
–
–
–
N/C
E3
I, ID
Table 24 (page 82)
No Ball
J11
N/C
F4
I, ID
Table 24 (page 82)
No Ball
J12
–
–
K5
–
–
N/C
F14 O, TS, ID
Table 24 (page 82)
No Ball
N/C
F15 –
Table 35 (page 97)
No Ball
K6
–
–
N/C
G2
–
Table 35 (page 97)
No Ball
K7
–
–
N/C
G5
–
Table 35 (page 97)
No Ball
K11 –
–
K12 –
–
K13 –
–
N/C
G14 –
Table 35 (page 97)
No Ball
N/C
G16 –
Table 35 (page 97)
No Ball
N/C
H4
–
Table 35 (page 97)
No Ball
L6
–
–
N/C
H14 –
Table 35 (page 97)
No Ball
L7
–
–
L8
–
–
N/C
J2
–
Table 35 (page 97)
No Ball
N/C
J13
–
Table 35 (page 97)
No Ball
L9
–
–
N/C
K4
–
Table 35 (page 97)
No Ball
L10 –
–
N/C
K15 –
Table 35 (page 97)
No Ball
L11
–
–
L11
–
–
No ball
F6
–
–
No Ball
No ball
F7
–
–
No Ball
M6
–
–
No ball
F8
–
–
No Ball
M7
–
–
No Ball
E8
–
–
No Ball
M8
–
–
No Ball
M9
–
–
No Ball
M10 –
–
No Ball
E10
No Ball
F9
–
–
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal
Ball Type1
Reference for
Full Description
Signal
No Ball
M11 –
–
TPFIN2
T5
AO/AI
Table 30 (page 88)
No Ball
M12 –
–
TPFIN3
R8
AO/AI
Table 30 (page 88)
Ball Type1
Reference for
Full Description
No Ball
N8
–
–
TPFIN4
U9
AO/AI
Table 30 (page 88)
No Ball
N10 –
–
TPFIN5
T12 AO/AI
Table 30 (page 88)
TPFIN6
T13 AO/AI
Table 30 (page 88)
TPFIN7
T16 AO/AI
Table 30 (page 88)
TPFIP0
R2
AO/AI
Table 30 (page 88)
Table 32 (page 90)
TPFIP1
U3
AO/AI
Table 30 (page 88)
R6
AO/AI
Table 30 (page 88)
PAUSE
D5
O, TS, SL,
Table 32 (page 90)
ID, I, ST
PREASEL
D7
O, TS, SL,
Table 24 (page 82)
ID, I, ST
PWRDWN
L14 I, ST, ID
REFCLK0
E6
I
Table 24 (page 82)
TPFIP2
REFCLK1
E12 I
Table 24 (page 82)
TPFIP3
T8
AO/AI
Table 30 (page 88)
RESET
M15 I, ST, IP
Table 32 (page 90)
TPFIP4
T9
AO/AI
Table 30 (page 88)
Table 24 (page 82)
TPFIP5
U13 AO/AI
Table 30 (page 88)
R12 AO/AI
Table 30 (page 88)
RxData0
C2
O, TS
RxData1
A3
O, TS
Table 24 (page 82)
TPFIP6
RxData2
B6
O, TS
Table 24 (page 82)
TPFIP7
R16 AO/AI
Table 30 (page 88)
RxData3
D9
O, TS
Table 24 (page 82)
TPFON0
U1
AO/AI
Table 30 (page 88)
RxData4
A13 O, TS
Table 24 (page 82)
TPFON1
R4
AO/AI
Table 30 (page 88)
U5
AO/AI
Table 30 (page 88)
T7
AO/AI
Table 30 (page 88)
R10 AO/AI
Table 30 (page 88)
RxData5
B14 O, TS
Table 24 (page 82)
TPFON2
RxData6
C15 O, TS
Table 24 (page 82)
TPFON3
RxData7
E16 O, TS
Table 24 (page 82)
TPFON4
SD_2P5V
P1
Table 29 (page 88)
TPFON5
U11 AO/AI
Table 30 (page 88)
U15 AO/AI
Table 30 (page 88)
I, ST, ID
SD0
P2
I
Table 29 (page 88)
TPFON6
SD1
N4
I
Table 29 (page 88)
TPFON7
T15 AO/AI
Table 30 (page 88)
SD2
P3
I
Table 29 (page 88)
TPFOP0
T2
AO/AI
Table 30 (page 88)
SD3
N5
I
Table 29 (page 88)
TPFOP1
T3
AO/AI
Table 30 (page 88)
T6
AO/AI
Table 30 (page 88)
SD4
P15 I
Table 29 (page 88)
TPFOP2
SD5
P16 I
Table 29 (page 88)
TPFOP3
U7
AO/AI
Table 30 (page 88)
SD6
P17 I
Table 29 (page 88)
TPFOP4
T10 AO/AI
Table 30 (page 88)
SD7
N17 I
Table 29 (page 88)
TPFOP5
T11
AO/AI
Table 30 (page 88)
T14 AO/AI
Table 30 (page 88)
SECTION
L15 I, ST, ID
Table 32 (page 90)
TPFOP6
SGND
K14 –
Table 34 (page 95)
TPFOP7
R14 AO/AI
Table 30 (page 88)
SYNC0
A6
I, ID
Table 24 (page 82)
TRST
M17 I, ST, IP
Table 31 (page 89)
SYNC1
C16 I, ID
Table 24 (page 82)
TxData0
E2
I, ID
Table 24 (page 82)
C3
I, ID
Table 24 (page 82)
TCK
M16 I, ST, ID
Table 31 (page 89)
TxData1
TDI
N14 I, ST, IP
Table 31 (page 89)
TxData2
B5
I, ID
Table 24 (page 82)
TDO
N15 O, TS
Table 31 (page 89)
TxData3
D8
I, ID
Table 24 (page 82)
TMS
N16 I, ST, IP
Table 31 (page 89)
TxData4
A11 I, ID
Table 24 (page 82)
B13 I, ID
Table 24 (page 82)
D13 I, ID
Table 24 (page 82)
TPFIN0
T1
AO/AI
Table 30 (page 88)
TxData5
TPFIN1
T4
AO/AI
Table 30 (page 88)
TxData6
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
65
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal
Ball Type1
Reference for
Full Description
TxData7
E14 I, ID
Table 24 (page 82)
TxSLEW_0
N3
I, ST, ID
Table 32 (page 90)
TxSLEW_1
M4
I, ST, ID
Table 32 (page 90)
F5
–
Table 34 (page 95)
G13 –
Table 34 (page 95)
VCCD
VCCD
66
VCCD
J5
–
Table 34 (page 95)
VCCD
J14
–
Table 34 (page 95)
VCCIO
A2
–
Table 34 (page 95)
VCCIO
A8
–
Table 34 (page 95)
VCCIO
C1
–
Table 34 (page 95)
VCCIO
C11 –
Table 34 (page 95)
VCCIO
D14 –
Table 34 (page 95)
VCCPECL
L5
–
Table 34 (page 95)
VCCPECL
L13 –
Table 34 (page 95)
VCCR
N13 –
Table 34 (page 95)
VCCR
P4
–
Table 34 (page 95)
VCCR
P7
–
Table 34 (page 95)
VCCR
P8
–
Table 34 (page 95)
VCCR
P9
–
Table 34 (page 95)
VCCR
P10 –
Table 34 (page 95)
VCCR
P11 –
Table 34 (page 95)
VCCR
P12 –
Table 34 (page 95)
VCCT
N6
–
Table 34 (page 95)
VCCT
N7
–
Table 34 (page 95)
VCCT
N9
–
Table 34 (page 95)
VCCT
N11 –
Table 34 (page 95)
VCCT
N12 –
Table 34 (page 95)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 21. Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball
Location
Ball Signal
Type1
Reference for
Full Description
Ball Signal
Type1
Reference for
Full Description
A1
GNDD
–
Table 34 (page 95)
B17 N/C
O, TS, ID
Table 24 (page 82)
A2
VCCIO
–
Table 34 (page 95)
C1
VCCIO
–
Table 34 (page 95)
A3
RxData1
O, TS
Table 24 (page 82)
C2
RxData0
O, TS
Table 24 (page 82)
A4
N/C
I, ID
Table 24 (page 82)
C3
TxData1
I, ID
Table 24 (page 82)
A5
CRS_DV2
O, TS, SL
Table 24 (page 82)
C4
CRS_DV1
O, TS, SL
Table 24 (page 82)
A6
SYNC0
I, ID
Table 24 (page 82)
C5
GNDD
–
Table 34 (page 95)
A7
N/C
I, ID
Table 24 (page 82)
C6
N/C
I, ID
Table 24 (page 82)
A8
VCCIO
–
Table 34 (page 95)
C7
N/C
O, TS, ID
Table 24 (page 82)
A9
GNDD
–
Table 34 (page 95)
C8
N/C
O, TS, SL,
ID
Table 24 (page 82)
C9
MDINT1
OD, TS, SL,
Table 28 (page 87)
IP
A10 MDIO1
I/O, TS, SL,
Table 28 (page 87)
IP
A11 TxData4
I, ID
Table 24 (page 82)
A12 FIFOSEL0
O, TS, SL,
ID, I, ST
Table 24 (page 82)
A13 RxData4
O, TS
A14 N/C
A15 FIFOSEL1
C10 N/C
I, ID
Table 24 (page 82)
C11 VCCIO
–
Table 34 (page 95)
Table 24 (page 82)
C12 N/C
O, TS,ID
Table 24 (page 82)
I, ID
Table 24 (page 82)
C13 GNDD
–
Table 34 (page 95)
O, TS, SL,
ID, I, ST
Table 24 (page 82)
C14 N/C
I, ID
Table 24 (page 82)
C15 RxData6
O, TS
Table 24 (page 82)
A16 N/C
I, ID
Table 24 (page 82)
C16 SYNC1
I, ID
Table 24 (page 82)
A17 LINKHOLD
O, TS, SL,
ID
Table 24 (page 82)
C17 GNDD
–
Table 34 (page 95)
B1
O, TS
Table 24 (page 82)
D1
GNDD
–
Table 34 (page 95)
D2
MDIX
O, TS, SL,
ID, I, ST
Table 32 (page 90)
D3
GNDD
–
Table 34 (page 95)
D4
N/C
I, ID
Table 24 (page 82)
D5
PAUSE
O, TS, SL,
ID, I, ST
Table 32 (page 90)
D6
GNDD
–
Table 34 (page 95)
D7
PREASEL
O, TS, SL,
ID, I, ST
Table 24 (page 82)
N/C
B2
N/C
–
Table 24 (page 82)
B3
GNDD
–
Table 34 (page 95)
B4
N/C
O, TS, ID
Table 24 (page 82)
B5
TxData2
I, ID
Table 24 (page 82)
B6
RxData2
O, TS
Table 24 (page 82)
B7
GNDD
–
Table 34 (page 95)
B8
CRS_DV3
O, TS, SL
Table 24 (page 82)
B9
N/C
O, TS, ID
Table 24 (page 82)
I, ST, ID
Table 28 (page 87)
B10 MDC1
B11 N/C
I, ID
Table 24 (page 82)
B12 CRS_DV4
O, TS, SL
Table 24 (page 82)
B13 TxData5
I, ID
Table 24 (page 82)
B14 RxData5
O, TS
Table 24 (page 82)
B15 N/C
O, TS, ID
Table 24 (page 82)
B16 CRS_DV6
O, TS, SL
Table 24 (page 82)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
D8
TxData3
I, ID
Table 24 (page 82)
D9
RxData3
O, TS
Table 24 (page 82)
D10 GNDD
–
Table 34 (page 95)
D11 N/C
I, ID
Table 24 (page 82)
D12 CRS_DV5
O, TS, SL
Table 24 (page 82)
D13 TxData6
I, ID
Table 24 (page 82)
D14 VCCIO
–
Table 34 (page 95)
D15 GNDD
–
Table 34 (page 95)
67
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball Signal
Type1
Reference for
Full Description
D16 N/C
I, ID
Table 24 (page 82)
D17 N/C
O, TS, SL,
ID
Table 24 (page 82)
Type1
F17 LED7_2
OD, TS, SL,
Table 33 (page 94)
IP
G1
LED2_3
OD, TS, SL,
Table 33 (page 94)
IP
G2
N/C
–
G3
LED3_2
OD, TS, SL,
Table 33 (page 94)
IP
G4
LED3_3
OD, TS,
SO, IP
Table 33 (page 94)
E1
MDC0
I, ST, ID
Table 28 (page 87)
E2
TxData0
I, ID
Table 24 (page 82)
E3
N/C
I, ID
Table 24 (page 82)
E4
CRS_DV0
O, TS, SL
Table 24 (page 82)
E5
GNDD
–
Table 34 (page 95)
E6
REFCLK0
I
Table 24 (page 82)
G5
N/C
–
Table 35 (page 97)
E7
GNDD
–
Table 34 (page 95)
G6
No Ball
–
–
E8
No Ball
–
–
G7
No Ball
–
–
Table 34 (page 95)
G8
No Ball
–
–
G9
No Ball
–
–
G10 No Ball
–
–
E9
GNDD
–
E10 No Ball
68
Reference for
Full Description
Ball Signal
Table 35 (page 97)
E11 GNDD
–
Table 34 (page 95)
E12 REFCLK1
I
Table 24 (page 82)
G11 No Ball
–
–
–
–
E13 GNDD
–
Table 34 (page 95)
G12 No Ball
E14 TxData7
I, ID
Table 24 (page 82)
G13 VCCD
–
Table 34 (page 95)
E15 CRS_DV7
O, TS, SL
Table 24 (page 82)
G14 N/C
–
Table 35 (page 97)
E16 RxData7
O, TS
Table 24 (page 82)
G15 LED7_1
OD, TS, SL,
Table 33 (page 94)
IP
E17 GNDD
–
Table 34 (page 95)
G16 N/C
–
G17 LED6_3
OD, TS, SL,
Table 33 (page 94)
IP
Table 35 (page 97)
F1
MDINT0
OD, TS, SL,
Table 28 (page 87)
IP
F2
LED3_1
OD, TS, SL,
Table 33 (page 94)
IP
H1
LED1_3
OD, TS, SL,
Table 33 (page 94)
IP
F3
MDIO0
I/O, TS, SL,
Table 28 (page 87)
IP
H2
LED2_1
OD, TS, SL,
Table 33 (page 94)
IP
F4
N/C
I, ID
Table 24 (page 82)
F5
VCCD
–
Table 34 (page 95)
H3
LED2_2
OD, TS, SL,
Table 33 (page 94)
IP
F6
No ball
–
–
H4
N/C
–
Table 35 (page 97)
F7
No ball
–
–
H5
No Ball
–
–
F8
No ball
–
–
H6
No Ball
–
–
F9
No Ball
–
–
H7
No Ball
–
–
F10 No Ball
–
–
H8
GNDD
–
Table 34 (page 95)
F11
No Ball
–
–
H9
GNDD
–
Table 34 (page 95)
F12 No Ball
–
–
H10 GNDD
–
Table 34 (page 95)
F13 GNDD
–
Table 34 (page 95)
H11 No Ball
–
–
F14 N/C
O, TS, ID
Table 24 (page 82)
H12 No Ball
–
–
F15 N/C
–
Table 35 (page 97)
H13 No Ball
–
–
F16 LED7_3
OD, TS, SL,
Table 33 (page 94)
IP
H14 N/C
–
Table 35 (page 97)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Reference for
Full Description
Ball Signal
Type1
H15 LED6_1
OD, TS, SL,
Table 33 (page 94)
IP
H16 LED6_2
OD, TS, SL,
Table 33 (page 94)
IP
H17 LED5_3
OD, TS, SL,
Table 33 (page 94)
IP
Ball Signal
Type1
Reference for
Full Description
K12 No Ball
–
–
K13 No Ball
–
–
K14 SGND
–
Table 34 (page 95)
K15 N/C
–
Table 35 (page 97)
K16 LED4_1
OD, TS, SL,
Table 33 (page 94)
IP
K17 LED4_2
OD, TS, SL,
Table 33 (page 94)
IP
J1
LED0_3
OD, TS, SL,
Table 33 (page 94)
IP
J2
N/C
–
J3
LED1_2
OD, TS, SL,
Table 33 (page 94)
IP
L1
MDDIS
I, ST, ID
Table 28 (page 87)
L2
CFG_3
I, ST, ID
Table 32 (page 90)
J4
LED1_1
OD, TS, SL,
Table 33 (page 94)
IP
L3
CFG_2
I, ST, ID
Table 32 (page 90)
J5
VCCD
–
L4
ADD_4
I, ST, ID
Table 32 (page 90)
L5
VCCPECL
–
Table 34 (page 95)
L6
No Ball
–
–
L7
No Ball
–
–
L8
No Ball
–
–
L9
No Ball
–
–
L10 No Ball
–
–
L11
No Ball
–
–
L11
No Ball
Table 35 (page 97)
Table 34 (page 95)
J6
No Ball
–
–
J7
No Ball
–
–
J8
GNDD
–
Table 34 (page 95)
J9
GNDD
–
Table 34 (page 95)
J10
GNDD
–
Table 34 (page 95)
J11
No Ball
–
–
J12
No Ball
–
–
J13
N/C
–
Table 35 (page 97)
J14
VCCD
–
Table 34 (page 95)
J15
LED5_1
OD, TS, SL,
Table 33 (page 94)
IP
J16
LED5_2
OD, TS, SL,
Table 33 (page 94)
IP
–
–
L13 VCCPECL
–
Table 34 (page 95)
L14 PWRDWN
I, ST, ID
Table 32 (page 90)
L15 SECTION
I, ST, ID
Table 32 (page 90)
L16 ModeSel0
I, ST, ID
Table 32 (page 90)
L17 ModeSel1
I, ST, ID
Table 32 (page 90)
M1
CFG_1
I, ST, ID
Table 32 (page 90)
I, ST, ID
Table 32 (page 90)
J17
LED4_3
OD, TS, SL,
Table 33 (page 94)
IP
K1
AMDIX_EN
I, ST, IP
Table 32 (page 90)
M2
ADD_3
K2
LED0_2
OD, TS, SL,
Table 33 (page 94)
IP
M3
ADD_2
I, ST, ID
Table 32 (page 90)
M4
TxSLEW_1
I, ST, ID
Table 32 (page 90)
K3
LED0_1
OD, TS, SL,
Table 33 (page 94)
IP
M5
GNDPECL
–
Table 34 (page 95)
K4
N/C
–
Table 35 (page 97)
M6
No Ball
–
–
K5
No Ball
–
–
M7
No Ball
–
–
M8
No Ball
–
–
M9
No Ball
–
–
M10 No Ball
–
–
K6
No Ball
–
–
K7
No Ball
–
–
K8
GNDD
–
Table 34 (page 95)
K9
GNDD
–
Table 34 (page 95)
K10 GNDD
–
Table 34 (page 95)
K11 No Ball
–
–
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
M11 No Ball
–
–
M12 No Ball
–
–
M13 GNDPECL
–
Table 34 (page 95)
M14 G_FX/TP
I, ST, ID
Table 32 (page 90)
69
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
70
Ball Signal
Type1
Reference for
Full Description
Ball Signal
Type1
Reference for
Full Description
M15 RESET
I, ST, IP
Table 32 (page 90)
R2
TPFIP0
AO/AI
Table 30 (page 88)
M16 TCK
I, ST, ID
Table 31 (page 89)
R3
GNDT
–
Table 34 (page 95)
M17 TRST
I, ST, IP
Table 31 (page 89)
R4
TPFON1
AO/AI
Table 30 (page 88)
N1
ADD_1
I, ST, ID
Table 32 (page 90)
R5
GNDT
–
Table 34 (page 95)
N2
ADD_0
I, ST, ID
Table 32 (page 90)
R6
TPFIP2
AO/AI
Table 30 (page 88)
N3
TxSLEW_0
I, ST, ID
Table 32 (page 90)
R7
GNDR
–
Table 34 (page 95)
N4
SD1
I
Table 29 (page 88)
R8
TPFIN3
AO/AI
Table 30 (page 88)
GNDR
N5
SD3
I
Table 29 (page 88)
R9
–
Table 34 (page 95)
N6
VCCT
–
Table 34 (page 95)
R10 TPFON4
AO/AI
Table 30 (page 88)
N7
VCCT
–
Table 34 (page 95)
R11 GNDR
–
Table 34 (page 95)
N8
No Ball
–
–
R12 TPFIP6
AO/AI
Table 30 (page 88)
N9
VCCT
–
Table 34 (page 95)
R13 GNDR
–
Table 34 (page 95)
N10 No Ball
–
–
R14 TPFOP7
AO/AI
Table 30 (page 88)
N11 VCCT
–
Table 34 (page 95)
R15 GNDT
–
Table 34 (page 95)
N12 VCCT
–
Table 34 (page 95)
R16 TPFIP7
AO/AI
Table 30 (page 88)
N13 VCCR
–
Table 34 (page 95)
R17 GNDT
–
Table 34 (page 95)
N14 TDI
I, ST, IP
Table 31 (page 89)
T1
TPFIN0
AO/AI
Table 30 (page 88)
N15 TDO
O, TS
Table 31 (page 89)
T2
TPFOP0
AO/AI
Table 30 (page 88)
N16 TMS
I, ST, IP
Table 31 (page 89)
T3
TPFOP1
AO/AI
Table 30 (page 88)
N17 SD7
I
Table 29 (page 88)
T4
TPFIN1
AO/AI
Table 30 (page 88)
P1
SD_2P5V
I, ST, ID
Table 29 (page 88)
T5
TPFIN2
AO/AI
Table 30 (page 88)
P2
SD0
I
Table 29 (page 88)
T6
TPFOP2
AO/AI
Table 30 (page 88)
P3
SD2
I
Table 29 (page 88)
T7
TPFON3
AO/AI
Table 30 (page 88)
P4
VCCR
–
Table 34 (page 95)
T8
TPFIP3
AO/AI
Table 30 (page 88)
P5
GNDR
–
Table 34 (page 95)
T9
TPFIP4
AO/AI
Table 30 (page 88)
P6
GNDR
–
Table 34 (page 95)
T10 TPFOP4
AO/AI
Table 30 (page 88)
P7
VCCR
–
Table 34 (page 95)
T11
AO/AI
Table 30 (page 88)
P8
VCCR
–
Table 34 (page 95)
T12 TPFIN5
AO/AI
Table 30 (page 88)
P9
VCCR
–
Table 34 (page 95)
T13 TPFIN6
AO/AI
Table 30 (page 88)
P10 VCCR
–
Table 34 (page 95)
T14 TPFOP6
AO/AI
Table 30 (page 88)
P11 VCCR
–
Table 34 (page 95)
T15 TPFON7
AO/AI
Table 30 (page 88)
P12 VCCR
–
Table 34 (page 95)
T16 TPFIN7
AO/AI
Table 30 (page 88)
P13 GNDR
–
Table 34 (page 95)
T17 GNDT
–
Table 34 (page 95)
P14 GNDT
–
Table 34 (page 95)
U1
TPFON0
AO/AI
Table 30 (page 88)
P15 SD4
I
Table 29 (page 88)
U2
GNDT
–
Table 34 (page 95)
P16 SD5
I
Table 29 (page 88)
U3
TPFIP1
AO/AI
Table 30 (page 88)
P17 SD6
I
Table 29 (page 88)
U4
GNDT
–
Table 34 (page 95)
R1
–
Table 34 (page 95)
U5
TPFON2
AO/AI
Table 30 (page 88)
GNDT
TPFOP5
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball Signal
Type1
Reference for
Full Description
U6
GNDT
–
Table 34 (page 95)
U7
TPFOP3
AO/AI
Table 30 (page 88)
U8
GNDR
–
Table 34 (page 95)
U9
TPFIN4
AO/AI
Table 30 (page 88)
U10 GNDT
–
Table 34 (page 95)
U11 TPFON5
AO/AI
Table 30 (page 88)
U12 GNDT
–
Table 34 (page 95)
U13 TPFIP5
AO/AI
Table 30 (page 88)
U14 GNDT
–
Table 34 (page 95)
U15 TPFON6
AO/AI
Table 30 (page 88)
U16 GNDT
–
Table 34 (page 95)
U17 GNDT
–
Table 34 (page 95)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
71
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.3.3
SS-SMII BGA23 Ball List
The following tables provide the SS-SMII ball locations and signal names arranged in
alphanumeric order as follows:
• Table 22 “Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by
Signal Name”
• Table 23 “Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by
Ball Location” on page 77
Table 22. Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by
Signal Name
Ball Type1
Reference for
Full Description
Signal
Ball Type1
Reference for
Full Description
ADD_0
N2
I
Table 29 (page 88)
GNDD
C17 –
Table 34 (page 95)
ADD_1
N1
I, ST, ID
Table 29 (page 88)
GNDD
D1
–
Table 34 (page 95)
ADD_2
M3
–
–
GNDD
D3
–
Table 34 (page 95)
ADD_3
M2
–
–
GNDD
D6
–
Table 34 (page 95)
ADD_4
L4
–
–
GNDD
D10 –
Table 34 (page 95)
AMDIX_EN
K1
–
–
GNDD
D15 –
Table 34 (page 95)
CFG_1
M1
–
–
CFG_2
L3
–
–
CFG_3
L2
–
CRS_DV0
E4
CRS_DV1
Signal
72
GNDD
E5
OD, TS,
SL, IP
Table 33 (page 94)
–
GNDD
E7
OD, TS,
SL, IP
Table 33 (page 94)
OD, TS,
SL, IP
Table 33 (page 94)
GNDD
E9
OD, TS,
SL, IP
Table 33 (page 94)
C4
–
Table 34 (page 95)
CRS_DV2
A5
I, ST, ID
Table 32 (page 90)
GNDD
E11
OD, TS,
SL, IP
Table 33 (page 94)
CRS_DV3
B8
–
Table 34 (page 95)
GNDD
E13
OD, TS,
SL, IP
Table 33 (page 94)
CRS_DV4
B12 –
Table 34 (page 95)
CRS_DV5
D12 –
Table 34 (page 95)
GNDD
E17
OD, TS,
SL, IP
Table 33 (page 94)
CRS_DV6
B16 –
Table 34 (page 95)
GNDD
F13 I, ST, ID
Table 28 (page 87)
CRS_DV7
E15
OD, TS,
SO, IP
Table 33 (page 94)
GNDD
H8
–
Table 24 (page 82)
GNDD
H9
I, ID
Table 24 (page 82)
FIFOSEL0
A12
O, TS, SL,
I, ST
Table 24 (page 82)
GNDD
H10 I, ID
Table 24 (page 82)
FIFOSEL1
A15
O, TS, SL,
I, ST
Table 24 (page 82)
G_FX/TP
M14 O, TS
GNDD
J8
–
–
GNDD
J9
–
–
Table 24 (page 82)
GNDD
J10
–
–
GNDD
A1
I, ST, ID
Table 32 (page 90)
GNDD
K8
–
–
GNDD
A9
I, ST, ID
Table 32 (page 90)
GNDD
K9
–
–
GNDD
B3
–
Table 34 (page 95)
GNDD
K10 –
–
GNDD
B7
–
Table 34 (page 95)
GNDPECL
M5
Table 32 (page 90)
GNDD
C5
–
Table 34 (page 95)
GNDPECL
M13 O, TS
GNDD
C13 –
Table 34 (page 95)
GNDR
P5
I, ST, ID
AO/AI
Table 24 (page 82)
Table 30 (page 88)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal
Ball Type1
Reference for
Full Description
Signal
Ball Type1
Reference for
Full Description
GNDR
P6
AO/AI
Table 30 (page 88)
LED4_3
J17
–
–
GNDR
P13 AO/AI
Table 30 (page 88)
LED5_1
J15
–
–
GNDR
R7
AO/AI
Table 30 (page 88)
LED5_2
J16
–
–
GNDR
R9
AO/AI
Table 30 (page 88)
LED5_3
H17 –
Table 35 (page 97)
GNDR
R11 AO/AI
Table 30 (page 88)
LED6_1
H15 –
Table 35 (page 97)
GNDR
R13 AO/AI
Table 30 (page 88)
LED6_2
H16 –
Table 35 (page 97)
GNDR
U8
Table 34 (page 95)
LED6_3
G17 –
Table 24 (page 82)
GNDT
P14 AO/AI
Table 30 (page 88)
LED7_1
G15 I, ID
Table 24 (page 82)
GNDT
R1
AO/AI
Table 30 (page 88)
LED7_2
Table 28 (page 87)
GNDT
R3
AO/AI
Table 30 (page 88)
I/O, TS,
F17
SL, IP
GNDT
R5
AO/AI
Table 30 (page 88)
LED7_3
F16
I/O, TS,
SL, IP
Table 28 (page 87)
GNDT
R15
O, TS, SL,
Table 24 (page 82)
ID
LINKHOLD
A17 O, TS, SL
Table 24 (page 82)
GNDT
R17 I, ID
Table 24 (page 82)
MDC0
E1
–
Table 34 (page 95)
GNDT
T17 –
Table 34 (page 95)
MDC1
B10 –
Table 34 (page 95)
GNDT
U2
Table 34 (page 95)
–
–
MDDIS
L1
–
–
Table 33 (page 94)
U4
–
Table 34 (page 95)
MDINT0
F1
OD, TS,
SL, IP
GNDT
U6
–
Table 34 (page 95)
MDINT1
C9
–
Table 34 (page 95)
GNDT
U10 –
Table 34 (page 95)
GNDT
U12 –
Table 34 (page 95)
MDIO0
F3
OD, TS,
SL, IP
Table 33 (page 94)
GNDT
U14 –
Table 34 (page 95)
MDIO1
A10 O, TS, SL
Table 24 (page 82)
GNDT
U16 –
Table 34 (page 95)
MDIX
D2
Table 34 (page 95)
GNDT
U17 –
Table 34 (page 95)
ModeSel0
L16 –
–
L17 –
–
GNDT
I, ST
LED0_1
K3
–
–
ModeSel1
LED0_2
K2
–
–
N/C
A3
I, ST, ID
Table 32 (page 90)
LED0_3
J1
–
Table 35 (page 97)
N/C
A4
I, ST, ID
Table 32 (page 90)
LED1_1
J4
–
Table 35 (page 97)
N/C
A7
I, ST, ID
Table 32 (page 90)
A13 O, TS, SL
Table 24 (page 82)
LED1_2
J3
–
Table 35 (page 97)
N/C
LED1_3
H1
I, ID
Table 24 (page 82)
N/C
A14 O, TS, SL
Table 24 (page 82)
LED2_1
H2
O, TS, SL,
Table 24 (page 82)
ID
N/C
A16 O, TS, SL
Table 24 (page 82)
N/C
B2
–
Table 34 (page 95)
LED2_2
H3
I, ID
Table 24 (page 82)
N/C
B6
–
Table 34 (page 95)
LED2_3
G1
O, TS, SL,
Table 32 (page 90)
ID
N/C
B11 –
Table 34 (page 95)
B14 –
Table 34 (page 95)
F2
OD, TS,
SL, IP
N/C
LED3_1
Table 33 (page 94)
N/C
C2
–
Table 34 (page 95)
LED3_2
G3
I, ST, ID
Table 32 (page 90)
N/C
C6
–
Table 34 (page 95)
LED3_3
G4
–
Table 24 (page 82)
N/C
C8
–
Table 34 (page 95)
LED4_1
K16 –
–
N/C
C10 –
Table 34 (page 95)
LED4_2
K17 –
–
N/C
C14 –
Table 34 (page 95)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
73
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal
Ball Type1
Reference for
Full Description
N/C
C15 –
Table 34 (page 95)
N/C
D4
–
Table 34 (page 95)
N/C
D9
–
Table 34 (page 95)
N/C
D11 –
N/C
N/C
Ball Type1
No Ball
G10
No Ball
G11 I, ID
Table 34 (page 95)
No Ball
G12
D16 –
Table 34 (page 95)
No Ball
H5
–
Table 24 (page 82)
OD, TS,
E16
SL, IP
Table 33 (page 94)
No Ball
H6
I, ID
Table 24 (page 82)
No Ball
H7
O, TS, SL,
Table 24 (page 82)
ID
N/C
F4
OD, TS,
SL, IP
Table 33 (page 94)
N/C
F15
OD, TS,
SL, IP
Table 28 (page 87)
N/C
G2
I, ST, ID
N/C
G5
I, ID
N/C
N/C
O, TS, SL,
Table 24 (page 82)
ID
Table 24 (page 82)
O, TS, SL,
Table 24 (page 82)
ID
No Ball
H11 –
Table 24 (page 82)
No Ball
H12 I, ID
Table 24 (page 82)
Table 32 (page 90)
No Ball
H13 –
Table 35 (page 97)
Table 24 (page 82)
No Ball
G14 –
Table 24 (page 82)
G16 –
Table 24 (page 82)
N/C
H4
N/C
H14 –
I, ID
J6
–
Table 35 (page 97)
No Ball
J7
–
–
No Ball
J11
Table 24 (page 82)
No Ball
J12
–
–
Table 35 (page 97)
No Ball
K5
–
–
N/C
J2
–
Table 35 (page 97)
No Ball
K6
–
–
N/C
J13
–
–
No Ball
K7
–
–
N/C
K4
–
–
No Ball
K11 –
–
N/C
K15 –
–
No Ball
K12 –
–
No Ball
K13 –
–
No ball
74
Reference for
Full Description
Signal
F6
OD, TS,
SL, IP
Table 33 (page 94)
Table 33 (page 94)
Table 33 (page 94)
No Ball
L6
–
–
No Ball
L7
–
–
No Ball
L8
–
–
No Ball
L9
–
–
No Ball
L10 –
–
No Ball
L11
–
–
No Ball
L11
–
–
No Ball
M6
I
Table 24 (page 82)
No Ball
M7
I
Table 24 (page 82)
No ball
F7
OD, TS,
SL, IP
No ball
F8
OD, TS,
SL, IP
No Ball
E8
OD, TS,
SL, IP
Table 33 (page 94)
No Ball
E10
OD, TS,
SL, IP
Table 33 (page 94)
No Ball
F9
OD, TS,
SL, IP
Table 33 (page 94)
No Ball
OD, TS,
F10
SL, IP
Table 33 (page 94)
No Ball
M8
I, ST, IP
Table 32 (page 90)
No Ball
F11
I, ST, ID
Table 28 (page 87)
No Ball
M9
I, ID
Table 24 (page 82)
No Ball
F12 I, ST, ID
Table 28 (page 87)
No Ball
M10 O, TS
Table 24 (page 82)
No Ball
M11 O, TS
Table 24 (page 82)
No Ball
M12 O, TS
Table 24 (page 82)
No Ball
G6
I, ID
Table 24 (page 82)
No Ball
G7
O, TS, SL,
ID
Table 24 (page 82)
No Ball
N8
I
Table 29 (page 88)
No Ball
G8
–
Table 24 (page 82)
No Ball
N10 I, ST, ID
Table 32 (page 90)
No Ball
G9
I, ID
Table 24 (page 82)
PAUSE
D5
Table 34 (page 95)
I, ST
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal
Ball Type1
Reference for
Full Description
Signal
Ball Type1
Reference for
Full Description
PREASEL
D7
Table 34 (page 95)
TPFIN7
T16 –
Table 34 (page 95)
PWRDWN
L14 –
–
TPFIP0
R2
AO/AI
Table 30 (page 88)
REFCLK0
E6
OD, TS,
SL, IP
Table 33 (page 94)
TPFIP1
U3
–
Table 34 (page 95)
TPFIP2
R6
AO/AI
Table 30 (page 88)
REFCLK1
E12
OD, TS,
SL, IP
Table 33 (page 94)
TPFIP3
T8
I, ST, ID
Table 32 (page 90)
RESET
M15 O, TS, ID
Table 24 (page 82)
TPFIP4
T9
I, ID
Table 24 (page 82)
I, ST
RxCLK0
E3
–
Table 34 (page 95)
TPFIP5
U13 –
Table 34 (page 95)
RxData0
B1
I, ST, ID
Table 32 (page 90)
TPFIP6
R12 AO/AI
Table 30 (page 88)
R16 I, ID
Table 24 (page 82)
RxData1
B4
–
Table 34 (page 95)
TPFIP7
RxData2
C7
–
Table 34 (page 95)
TPFON0
U1
–
Table 34 (page 95)
RxData3
B9
–
Table 34 (page 95)
TPFON1
R4
AO/AI
Table 30 (page 88)
C12 –
Table 34 (page 95)
TPFON2
U5
–
Table 34 (page 95)
T7
I, ST, ID
Table 32 (page 90)
RxData4
RxData5
B15 –
Table 34 (page 95)
TPFON3
RxData6
B17 –
Table 34 (page 95)
TPFON4
R10 AO/AI
Table 30 (page 88)
RxData7
F14
OD, TS,
SL, IP
Table 28 (page 87)
TPFON5
U11 –
Table 34 (page 95)
TPFON6
U15 –
Table 34 (page 95)
SD_2P5V
P1
AO/AI
Table 30 (page 88)
TPFON7
T15 –
Table 34 (page 95)
SD0
P2
AO/AI
Table 30 (page 88)
TPFOP0
T2
I, ID
Table 24 (page 82)
SD1
N4
I
Table 29 (page 88)
TPFOP1
T3
I, ID
Table 24 (page 82)
SD2
P3
AO/AI
Table 30 (page 88)
TPFOP2
T6
I, ID
Table 24 (page 82)
SD3
N5
I
Table 29 (page 88)
TPFOP3
U7
–
Table 34 (page 95)
SD4
P15 AO/AI
Table 30 (page 88)
TPFOP4
T10 I, ID
Table 24 (page 82)
SD5
P16 AO/AI
Table 30 (page 88)
TPFOP5
T11
–
Table 34 (page 95)
SD6
P17 AO/AI
Table 30 (page 88)
TPFOP6
T14 –
Table 34 (page 95)
SD7
N17 AO/AI
Table 30 (page 88)
TPFOP7
R14 I, ST, IP
Table 31 (page 89)
SECTION
L15 –
–
TRST
M17 O, TS, ID
Table 24 (page 82)
SGND
K14 –
–
TxCLK1
D17 –
Table 34 (page 95)
TCK
M16 O, TS, ID
Table 24 (page 82)
TxData0
E2
–
Table 34 (page 95)
TDI
N14 O, TS
Table 31 (page 89)
TxData1
C3
–
Table 34 (page 95)
TDO
N15 I, ST, IP
Table 31 (page 89)
TxData2
B5
–
Table 34 (page 95)
TMS
N16 AO/AI
Table 30 (page 88)
TxData3
D8
–
Table 34 (page 95)
TPFIN0
T1
I, ID
Table 24 (page 82)
TxData4
A11 O, TS, SL
Table 24 (page 82)
TPFIN1
T4
I, ID
Table 24 (page 82)
TxData5
B13 –
Table 34 (page 95)
TPFIN2
T5
I, ID
Table 24 (page 82)
TxData6
D13 –
Table 34 (page 95)
TPFIN3
R8
AO/AI
Table 30 (page 88)
TPFIN4
U9
–
Table 34 (page 95)
TxData7
E14
OD, TS,
SL, IP
Table 33 (page 94)
TPFIN5
T12 –
Table 34 (page 95)
TxSLEW_0
N3
I
Table 29 (page 88)
TPFIN6
T13 –
Table 34 (page 95)
TxSLEW_1
M4
O, TS, SL,
Table 32 (page 90)
ID
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
75
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal
TxSYNC0
TxSYNC1
VCCD
VCCD
A6
I, ST, IP
C16 –
F5
OD, TS,
SL, IP
G13 I, ID
Reference for
Full Description
Table 32 (page 90)
Table 34 (page 95)
Table 33 (page 94)
Table 24 (page 82)
VCCD
J5
–
Table 35 (page 97)
VCCD
J14
–
–
VCCIO
A2
I, ST, ID
Table 32 (page 90)
VCCIO
A8
I, ST, ID
Table 32 (page 90)
VCCIO
C1
–
Table 34 (page 95)
VCCIO
C11 –
Table 34 (page 95)
VCCIO
D14 –
Table 34 (page 95)
VCCPECL
76
Ball Type1
L5
–
–
VCCPECL
L13 –
–
VCCR
N13 I, ST, IP
Table 31 (page 89)
VCCR
P4
AO/AI
Table 30 (page 88)
VCCR
P7
AO/AI
Table 30 (page 88)
VCCR
P8
AO/AI
Table 30 (page 88)
VCCR
P9
AO/AI
Table 30 (page 88)
VCCR
P10 AO/AI
Table 30 (page 88)
VCCR
P11 AO/AI
Table 30 (page 88)
VCCR
P12 AO/AI
Table 30 (page 88)
VCCT
N6
I
Table 29 (page 88)
VCCT
N7
I
Table 29 (page 88)
VCCT
N9
I
Table 29 (page 88)
VCCT
N11 –
Table 34 (page 95)
VCCT
N12 I, ST, ID
Table 31 (page 89)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 23. Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball
Location
Ball Symbol
Type1
Reference for
Full Description
Ball Symbol
Type1
Reference for
Full Description
A1
GNDD
–
Table 34 (page 95)
B17 RxData6
O, TS, ID
Table 24 (page 82)
A2
VCCIO
–
Table 34 (page 95)
C1
VCCIO
–
Table 34 (page 95)
A3
N/C
O, TS
Table 24 (page 82)
C2
N/C
–
Table 24 (page 82)
A4
N/C
I, ID
Table 24 (page 82)
C3
TxData1
I, ID
Table 24 (page 82)
A5
CRS_DV2
O, TS, SL
Table 24 (page 82)
C4
CRS_DV1
O, TS, SL
Table 24 (page 82)
A6
TxSYNC0
I, ID
Table 24 (page 82)
C5
GNDD
–
Table 34 (page 95)
A7
N/C
I, ID
Table 24 (page 82)
C6
N/C
I, ID
Table 24 (page 82)
A8
VCCIO
–
Table 34 (page 95)
C7
RxData2
O, TS, ID
Table 24 (page 82)
A9
GNDD
–
Table 34 (page 95)
C8
N/C
O, TS, SL,
Table 24 (page 82)
ID
A10 MDIO1
I/O, TS,
SL, IP
Table 28 (page 87)
C9
MDINT1
I, ID
Table 24 (page 82)
OD, TS,
SL, IP
Table 28 (page 87)
A11 TxData4
O, TS, SL,
Table 24 (page 82)
ID, I, ST
C10 N/C
I, ID
Table 24 (page 82)
A12 FIFOSEL0
C11 VCCIO
–
Table 34 (page 95)
A13 N/C
O, TS
Table 24 (page 82)
C12 RxData4
O, TS,ID
Table 24 (page 82)
A14 N/C
I, ID
Table 24 (page 82)
C13 GNDD
–
Table 34 (page 95)
A15 FIFOSEL1
O, TS, SL,
Table 24 (page 82)
ID, I, ST
C14 N/C
I, ID
Table 24 (page 82)
C15 N/C
O, TS
Table 24 (page 82)
A16 N/C
I, ID
C16 TxSYNC1
I, ID
Table 24 (page 82)
A17 LINKHOLD
O, TS, SL,
Table 24 (page 82)
ID, I, ST
C17 GNDD
–
Table 34 (page 95)
B1
O, TS
D1
GNDD
–
Table 34 (page 95)
D2
MDIX
O, TS, SL,
Table 32 (page 90)
ID, I, ST
D3
GNDD
–
Table 34 (page 95)
D4
N/C
I, ID
Table 24 (page 82)
D5
PAUSE
O, TS, SL,
Table 32 (page 90)
ID, I, ST
D6
GNDD
–
D7
PREASEL
O, TS, SL,
Table 24 (page 82)
ID, I, ST
RxData0
Table 24 (page 82)
Table 24 (page 82)
B2
N/C
I, ID
Table 24 (page 82)
B3
GNDD
–
Table 34 (page 95)
B4
RxData1
O, TS, ID
Table 24 (page 82)
B5
TxData2
I, ID
Table 24 (page 82)
B6
N/C
O, TS
Table 24 (page 82)
B7
GNDD
–
Table 34 (page 95)
B8
CRS_DV3
O, TS, SL
Table 24 (page 82)
B9
RxData3
O, TS, ID
Table 24 (page 82)
I, ST, ID
Table 28 (page 87)
B10 MDC1
B11 N/C
I, ID
Table 24 (page 82)
B12 CRS_DV4
O, TS, SL
Table 24 (page 82)
B13 TxData5
I, ID
Table 24 (page 82)
B14 N/C
O, TS
Table 24 (page 82)
B15 RxData5
O, TS, ID
Table 24 (page 82)
B16 CRS_DV6
O, TS, SL
Table 24 (page 82)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Table 34 (page 95)
D8
TxData3
I, ID
Table 24 (page 82)
D9
N/C
O, TS
Table 24 (page 82)
D10 GNDD
–
Table 34 (page 95)
D11 N/C
I, ID
Table 24 (page 82)
D12 CRS_DV5
O, TS, SL
Table 24 (page 82)
D13 TxData6
I, ID
Table 24 (page 82)
D14 VCCIO
–
Table 34 (page 95)
D15 GNDD
–
Table 34 (page 95)
77
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball Symbol
Type1
Reference for
Full Description
D16 N/C
I, ID
Table 24 (page 82)
D17 TxCLK1
O, TS, SL,
ID
Table 24 (page 82)
Type1
Reference for
Full Description
F17 LED7_2
OD, TS,
SL, IP
Table 33 (page 94)
G1
LED2_3
OD, TS,
SL, IP
Table 33 (page 94)
G2
N/C
–
Table 35 (page 97)
G3
LED3_2
OD, TS,
SL, IP
Table 33 (page 94)
G4
LED3_3
OD, TS,
SO, IP
Table 33 (page 94)
E1
MDC0
I, ST, ID
Table 28 (page 87)
E2
TxData0
I, ID
Table 24 (page 82)
E3
RxCLK0
I, ID
Table 24 (page 82)
E4
CRS_DV0
O, TS, SL
Table 24 (page 82)
E5
GNDD
–
Table 34 (page 95)
E6
REFCLK0
I
Table 24 (page 82)
G5
N/C
–
Table 35 (page 97)
E7
GNDD
–
Table 34 (page 95)
G6
No Ball
–
–
E8
No Ball
–
–
G7
No Ball
–
–
Table 34 (page 95)
G8
No Ball
–
–
G9
No Ball
–
–
G10 No Ball
–
–
E9
GNDD
–
E10 No Ball
78
Ball Symbol
E11 GNDD
–
Table 34 (page 95)
E12 REFCLK1
I
Table 24 (page 82)
G11 No Ball
–
–
–
–
E13 GNDD
–
Table 34 (page 95)
G12 No Ball
E14 TxData7
I, ID
Table 24 (page 82)
G13 VCCD
–
Table 34 (page 95)
E15 CRS_DV7
O, TS, SL
Table 24 (page 82)
G14 N/C
–
Table 35 (page 97)
E16 N/C
O, TS
Table 24 (page 82)
G15 LED7_1
OD, TS,
SL, IP
Table 33 (page 94)
E17 GNDD
–
Table 34 (page 95)
G16 N/C
–
Table 35 (page 97)
G17 LED6_3
OD, TS,
SL, IP
Table 33 (page 94)
F1
MDINT0
OD, TS,
SL, IP
Table 28 (page 87)
F2
LED3_1
OD, TS,
SL, IP
Table 33 (page 94)
F3
MDIO0
I/O, TS,
SL, IP
Table 28 (page 87)
F4
N/C
I, ID
Table 24 (page 82)
F5
VCCD
–
Table 34 (page 95)
F6
No ball
–
F7
No ball
F8
No ball
F9
H1
LED1_3
OD, TS,
SL, IP
Table 33 (page 94)
H2
LED2_1
OD, TS,
SL, IP
Table 33 (page 94)
H3
LED2_2
OD, TS,
SL, IP
Table 33 (page 94)
–
H4
N/C
–
Table 35 (page 97)
–
–
H5
No Ball
–
–
–
–
H6
No Ball
–
–
No Ball
–
–
H7
No Ball
–
–
F10 No Ball
–
–
H8
GNDD
–
Table 34 (page 95)
F11
No Ball
–
–
H9
GNDD
–
Table 34 (page 95)
F12 No Ball
–
–
H10 GNDD
–
Table 34 (page 95)
F13 GNDD
–
Table 34 (page 95)
H11 No Ball
–
–
F14 RxData7
O, TS, ID
Table 24 (page 82)
H12 No Ball
–
–
F15 N/C
–
Table 35 (page 97)
H13 No Ball
–
–
F16 LED7_3
OD, TS,
SL, IP
Table 33 (page 94)
H14 N/C
–
Table 35 (page 97)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball Symbol
Type1
Reference for
Full Description
H15 LED6_1
OD, TS,
SL, IP
Table 33 (page 94)
H16 LED6_2
OD, TS,
SL, IP
Table 33 (page 94)
H17 LED5_3
OD, TS,
SL, IP
Table 33 (page 94)
J1
LED0_3
OD, TS,
SL, IP
Table 33 (page 94)
J2
N/C
–
Table 35 (page 97)
J3
LED1_2
OD, TS,
SL, IP
Table 33 (page 94)
J4
LED1_1
OD, TS,
SL, IP
Table 33 (page 94)
J5
VCCD
–
Table 34 (page 95)
J6
No Ball
–
–
J7
No Ball
–
–
J8
GNDD
–
Table 34 (page 95)
J9
GNDD
–
Table 34 (page 95)
J10
GNDD
–
Table 34 (page 95)
J11
No Ball
–
–
J12
No Ball
–
–
J13
N/C
–
Table 35 (page 97)
Ball Symbol
Type1
Reference for
Full Description
K12 No Ball
–
–
K13 No Ball
–
–
K14 SGND
–
Table 34 (page 95)
K15 N/C
–
Table 35 (page 97)
K16 LED4_1
OD, TS,
SL, IP
Table 33 (page 94)
K17 LED4_2
OD, TS,
SL, IP
Table 33 (page 94)
L1
MDDIS
I, ST, ID
Table 28 (page 87)
L2
CFG_3
I, ST, ID
Table 32 (page 90)
L3
CFG_2
I, ST, ID
Table 32 (page 90)
L4
ADD_4
I, ST, ID
Table 32 (page 90)
L5
VCCPECL
–
Table 34 (page 95)
L6
No Ball
–
–
L7
No Ball
–
–
L8
No Ball
–
–
L9
No Ball
–
–
L10 No Ball
–
–
L11
No Ball
–
–
L11
No Ball
–
–
L13 VCCPECL
–
Table 34 (page 95)
L14 PWRDWN
I, ST, ID
Table 32 (page 90)
L15 SECTION
I, ST, ID
Table 32 (page 90)
L16 ModeSel0
I, ST, ID
Table 32 (page 90)
L17 ModeSel1
I, ST, ID
Table 32 (page 90)
J14
VCCD
–
Table 34 (page 95)
J15
LED5_1
OD, TS,
SL, IP
Table 33 (page 94)
J16
LED5_2
OD, TS,
SL, IP
Table 33 (page 94)
Table 33 (page 94)
M1
CFG_1
I, ST, ID
Table 32 (page 90)
M2
ADD_3
I, ST, ID
Table 32 (page 90)
M3
ADD_2
I, ST, ID
Table 32 (page 90)
M4
TxSLEW_1
I, ST, ID
Table 32 (page 90)
M5
GNDPECL
–
Table 34 (page 95)
M6
No Ball
–
–
M7
No Ball
–
–
M8
No Ball
–
–
M9
No Ball
–
–
M10 No Ball
–
–
J17
LED4_3
OD, TS,
SL, IP
K1
AMDIX_EN
I, ST, IP
Table 32 (page 90)
K2
LED0_2
OD, TS,
SL, IP
Table 33 (page 94)
K3
LED0_1
OD, TS,
SL, IP
Table 33 (page 94)
K4
N/C
–
Table 35 (page 97)
K5
No Ball
–
–
K6
No Ball
–
–
K7
No Ball
–
–
K8
GNDD
–
Table 34 (page 95)
K9
GNDD
–
Table 34 (page 95)
K10 GNDD
–
Table 34 (page 95)
K11 No Ball
–
–
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
M11 No Ball
–
–
M12 No Ball
–
–
M13 GNDPECL
–
Table 34 (page 95)
M14 G_FX/TP
I, ST, ID
Table 32 (page 90)
79
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
80
Ball Symbol
Type1
Reference for
Full Description
Ball Symbol
Type1
Reference for
Full Description
M15 RESET
I, ST, IP
Table 32 (page 90)
R2
TPFIP0
AO/AI
Table 30 (page 88)
M16 TCK
I, ST, ID
Table 31 (page 89)
R3
GNDT
–
Table 34 (page 95)
M17 TRST
I, ST, IP
Table 31 (page 89)
R4
TPFON1
AO/AI
Table 30 (page 88)
N1
ADD_1
I, ST, ID
Table 32 (page 90)
R5
GNDT
–
Table 34 (page 95)
N2
ADD_0
I, ST, ID
Table 32 (page 90)
R6
TPFIP2
AO/AI
Table 30 (page 88)
N3
TxSLEW_0
I, ST, ID
Table 32 (page 90)
R7
GNDR
–
Table 34 (page 95)
N4
SD1
I
Table 29 (page 88)
R8
TPFIN3
AO/AI
Table 30 (page 88)
GNDR
N5
SD3
I
Table 29 (page 88)
R9
–
Table 34 (page 95)
N6
VCCT
–
Table 34 (page 95)
R10 TPFON4
AO/AI
Table 30 (page 88)
N7
VCCT
–
Table 34 (page 95)
R11 GNDR
–
Table 34 (page 95)
N8
No Ball
–
–
R12 TPFIP6
AO/AI
Table 30 (page 88)
N9
VCCT
–
Table 34 (page 95)
R13 GNDR
–
Table 34 (page 95)
N10 No Ball
–
–
R14 TPFOP7
AO/AI
Table 30 (page 88)
N11 VCCT
–
Table 34 (page 95)
R15 GNDT
–
Table 34 (page 95)
N12 VCCT
–
Table 34 (page 95)
R16 TPFIP7
AO/AI
Table 30 (page 88)
N13 VCCR
–
Table 34 (page 95)
R17 GNDT
–
Table 34 (page 95)
N14 TDI
I, ST, IP
Table 31 (page 89)
T1
TPFIN0
AO/AI
Table 30 (page 88)
N15 TDO
O, TS
Table 31 (page 89)
T2
TPFOP0
AO/AI
Table 30 (page 88)
N16 TMS
I, ST, IP
Table 31 (page 89)
T3
TPFOP1
AO/AI
Table 30 (page 88)
N17 SD7
I
Table 29 (page 88)
T4
TPFIN1
AO/AI
Table 30 (page 88)
P1
SD_2P5V
I, ST, ID
Table 29 (page 88)
T5
TPFIN2
AO/AI
Table 30 (page 88)
P2
SD0
I
Table 29 (page 88)
T6
TPFOP2
AO/AI
Table 30 (page 88)
P3
SD2
I
Table 29 (page 88)
T7
TPFON3
AO/AI
Table 30 (page 88)
P4
VCCR
–
Table 34 (page 95)
T8
TPFIP3
AO/AI
Table 30 (page 88)
P5
GNDR
–
Table 34 (page 95)
T9
TPFIP4
AO/AI
Table 30 (page 88)
P6
GNDR
–
Table 34 (page 95)
T10 TPFOP4
AO/AI
Table 30 (page 88)
P7
VCCR
–
Table 34 (page 95)
T11
AO/AI
Table 30 (page 88)
P8
VCCR
–
Table 34 (page 95)
T12 TPFIN5
AO/AI
Table 30 (page 88)
P9
VCCR
–
Table 34 (page 95)
T13 TPFIN6
AO/AI
Table 30 (page 88)
P10 VCCR
–
Table 34 (page 95)
T14 TPFOP6
AO/AI
Table 30 (page 88)
P11 VCCR
–
Table 34 (page 95)
T15 TPFON7
AO/AI
Table 30 (page 88)
P12 VCCR
–
Table 34 (page 95)
T16 TPFIN7
AO/AI
Table 30 (page 88)
P13 GNDR
–
Table 34 (page 95)
T17 GNDT
–
Table 34 (page 95)
P14 GNDT
–
Table 34 (page 95)
U1
TPFON0
AO/AI
Table 30 (page 88)
P15 SD4
I
Table 29 (page 88)
U2
GNDT
–
Table 34 (page 95)
P16 SD5
I
Table 29 (page 88)
U3
TPFIP1
AO/AI
Table 30 (page 88)
P17 SD6
I
Table 29 (page 88)
U4
GNDT
–
Table 34 (page 95)
R1
–
Table 34 (page 95)
U5
TPFON2
AO/AI
Table 30 (page 88)
GNDT
TPFOP5
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball Symbol
Type1
Reference for
Full Description
U6
GNDT
–
Table 34 (page 95)
U7
TPFOP3
AO/AI
Table 30 (page 88)
U8
GNDR
–
Table 34 (page 95)
U9
TPFIN4
AO/AI
Table 30 (page 88)
U10 GNDT
–
Table 34 (page 95)
U11 TPFON5
AO/AI
Table 30 (page 88)
U12 GNDT
–
Table 34 (page 95)
U13 TPFIP5
AO/AI
Table 30 (page 88)
U14 GNDT
–
Table 34 (page 95)
U15 TPFON6
AO/AI
Table 30 (page 88)
U16 GNDT
–
Table 34 (page 95)
U17 GNDT
–
Table 34 (page 95)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
81
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.4
BGA23 Signal Descriptions
3.4.1
Signal Name Conventions
Signal names may contain either a port designation or a serial designation, or a combination of the
two designations. Signal naming conventions are as follows:
• Port Number Only. Individual signals that apply to a particular port are designated by the
Signal Mnemonic, immediately followed by the Port Designation. For example, Transmit
Enable signals would be identified as TxEN0, TxEN1, and TxEN2.
• Serial Number Only. A set of signals which are not tied to any specific port are designated by
the Signal Mnemonic, followed by an underscore and a serial designation. For example, a set
of three Global Configuration signals would be identified as CFG_1, CFG_2, and CFG_3.
• Port and Serial Number. In cases where each port is assigned a set of multiple signals, each
signal is designated in the following order: Signal Mnemonic, Port Designation, an
underscore, and the serial designation. For example, a set of three Port Configuration signals
would be identified as RxData0_0 and RxData0_1, RxData1_0 and RxData1_1, and
RxData2_0 and RxData2_1.
3.4.2
Signal Descriptions – RMII, SMII, and SS-SMII Configurations
Table 24. Intel® LXT9785/LXT9785E RMII Signal Descriptions – BGA23 (Sheet 1 of 3)
Ball/Pin
Designation
BGA23
Symbol
Type1
Signal Description2,3
PQFP
Reference Clock.
E6,
E12
44
6
REFCLK0
REFCLK1
I
E2,
F4
61
62
TxData0_0
TxData0_1
I, ID
C3,
D4
52
53
TxData1_0
TxData1_1
I, ID
B5
A4
42
43
TxData2_0
TxData2_1
I, ID
50 MHz RMII reference clock is always required. RMII
inputs are sampled on the rising edge of REFCLK,
RMII outputs are sourced on the falling edge. See
“Clock/SYNC Requirements” on page 125. for detailed
CLK requirements.
Transmit Data - Port 0.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 0 are clocked in synchronously to REFCLK.
Transmit Data - Port 1.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 1 are clocked in synchronously to REFCLK
Transmit Data - Port 2.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 2 are clocked in synchronously to REFCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W
Power-Down modes and during H/W reset.
82
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 24. Intel® LXT9785/LXT9785E RMII Signal Descriptions – BGA23 (Sheet 2 of 3)
Ball/Pin
Designation
Symbol
Type1
BGA23
PQFP
D8,
A6
34
35
TxData3_0
TxData3_1
I, ID
A11,
C10
22
23
TxData4_0
TxData4_1
I, ID
B13,
D11
13
14
TxData5_0
TxData5_1
I, ID
D13,
A16
4
5
TxData6_0
TxData6_1
I, ID
E14,
C16
203
204
TxData7_0
TxData7_1
I, ID
E3,
B2,
C6,
A7,
B11,
A14,
C14,
D16
60
51
41
33
21
12
3
202
TxEN0
TxEN1
TxEN2
TxEN3
TxEN4
TxEN5
TxEN6
TxEN7
I, ID
C2,
B1
55
54
RxData0_0
RxData0_1
O, TS
O, TS, ID
A3,
B4
46
45
RxData1_0
RxData1_1
O, TS
O, TS, ID
B6,
C7
37
36
RxData2_0
RxData2_1
O, TS
O, TS, ID
D9,
B9
28
27
RxData3_0
RxData3_1
O, TS
O, TS, ID
A13,
C12
16
15
RxData4_0
RxData4_1
O, TS
O, TS, ID
B14,
B15
8
7
RxData5_0
RxData5_1
O, TS
O, TS, ID
Signal Description2,3
Transmit Data - Port 3.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 3 are clocked in synchronously to REFCLK.
Transmit Data - Port 4.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 4 are clocked in synchronously to REFCLK.
Transmit Data - Port 5.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 5 are clocked in synchronously to REFCLK.
Transmit Data - Port 6.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 6 are clocked in synchronously to REFCLK.
Transmit Data - Port 7.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 7 are clocked in synchronously to REFCLK.
Transmit Enable - Ports 0-7.
Active High input enables respective port transmitter.
This signal must be synchronous to the REFCLK.
Receive Data - Port 0.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 1.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 2.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 3.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 4.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 5.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W
Power-Down modes and during H/W reset.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
83
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 24. Intel® LXT9785/LXT9785E RMII Signal Descriptions – BGA23 (Sheet 3 of 3)
Ball/Pin
Designation
Symbol
Type1
BGA23
PQFP
C15,
B17
206
205
RxData6_0
RxData6_1
O, TS
O, TS, ID
E16,
F14
198
197
RxData7_0
RxData7_1
O, TS
O, TS, ID
E4,
C4,
A5,
B8,
B12,
D12,
B16,
E15
58
49
39
31
17
10
1
200
CRS_DV0
CRS_DV1
CRS_DV2
CRS_DV3
CRS_DV4
CRS_DV5
CRS_DV6
CRS_DV7
O, TS, SL,
ID
Signal Description2,3
Receive Data - Port 6.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 7.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Carrier Sense/Receive Data Valid - Ports 0-7.
On detection of valid carrier, these signals are
asserted asynchronously with respect to REFCLK.
CRS_DVn is de-asserted on loss of carrier,
synchronous to REFCLK.
Receive Error - Ports 0-7.
D2,
D5,
D7,
C8,
A12,
A15,
A17,
D17
59
50
40
32
20
11
2
201
RxER0
RxER1
RxER2
RxER3
RxER4
RxER5
RxER6
RxER7
These signals are synchronous to the respective
REFCLK. Active High indicates that received code
group is invalid, or that PLL is not locked.
O, TS, SL,
ID, I, ST
The RxER signals have the following additional
function pins:
RxER0 (MDIX)
RxER1 (PAUSE)
RxER2 (PREASEL)
RxER4 (FIFOSEL0)
RxER5 (FIFOSEL1)
RxER6 {LINKHOLD)
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W
Power-Down modes and during H/W reset.
84
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 25. Intel® LXT9785/LXT9785E SMII / SS-SMII Common Signal Descriptions – BGA23
Ball/Pin
Designation
BGA23
PQFP
E2,
C3,
B5,
D8,
A11,
B13,
D13,
E14
61
52
42
34
22
13
4
203
Symbol
Type1
TxData0
TxData1
TxData2
TxData3
TxData4
TxData5
TxData6
TxData7
I, ID
Signal Description2
Transmit Data - Ports 0-7.
These serial input streams provide data to be transmitted to
the network. The LXT9785/9785E clocks the data in
synchronously to REFCLK.
Reference Clock.
E6,
E12
44
6
REFCLK0
REFCLK1
I
The LXT9785/9785E always requires a 125 MHz reference
clock input. Refer to Functional Description for detailed clock
requirements. REFCLK0 and REFCLK1 are always
connected regardless of sectionalization mode.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode.
Table 26. Intel® LXT9785/LXT9785E SMII Specific Signal Descriptions – BGA23
Pin/Ball
Designation
BGA23
Symbol
Type1
Signal Description2,3
PQFP
SMII Synchronization.
A6,
C16
35
204
SYNC0
SYNC1
C2,
A3,
B6,
D9,
A13,
B14,
C15,
E16
55
46
37
28
16
8
206
198
RxData0
RxData1
RxData2
RxData3
RxData4
RxData5
RxData6
RxData7
I, ID
The MAC must generate a SYNC pulse every 10 REFCLK
cycles to synchronize the SMII. SYNC0 is used when 1x8
port sectionalization is selected. SYNC0 and SYNC1 are
to be used when 2x4 port sectionalization is chosen.
Receive Data - Ports 0-7.
O, TS
These serial output streams provide data received from
the network. The LXT9785/9785E drives the data out
synchronously to RXCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode.
3. RxData[0:7] outputs are three-stated in Isolation and hardware power-down modes and during hardware
reset.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
85
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 27. Intel® LXT9785/LXT9785E SS-SMII Specific Signal Descriptions – BGA23
Ball/Pin
Designation
BGA23
PQFP
A6,
C16
35
204
Symbol
Type1
TxSYNC0
TxSYNC1
I, ID
Signal Description2,3
SS-SMII Transmit Synchronization.
The MAC must generate a TxSYNC pulse every 10 TxCLK
cycles to mark the start of TxData segments. TxSYNC0 is
used when 1x8 port sectionalization is selected.
SS-SMII Receive Synchronization.
E4,
B12
58
17
RxSYNC0
RxSYNC1
O, TS,
ID
The LXT9785/9785E generates these pulses every 10
RxCLK cycles to mark the start of RxData segments for the
MAC. RxSYNC1 is used when 1x8 port sectionalization is
selected. RxSYNC0 may not be used. These outputs are
only enabled when SS-SMII mode is enabled.
SS-SMII Transmit Clock.
C8,
D17
32
201
TxCLK0
TxCLK1
I, ID
The MAC sources this 125 MHz clock as the timing
reference for TxData and TxSYNC. Only TxCLK0 is used
when 1x8 port sectionalization is selected. See “Clock/
SYNC Requirements” on page 125. for detailed clock
requirements.
SS-SMII Receive Clock.
E3,
B11
60
21
RxCLK0
RxCLK1
O, TS,
ID
B1,
B4,
C7,
B9,
C12,
B15,
B17,
F14
54
45
36
27
15
7
205
197
RxData0
RxData1
RxData2
RxData3
RxData4
RxData5
RxData6
RxData7
O, TS,
ID
The LXT9785/9785E generates these clocks, based on
REFCLK, to provide a timing reference for RxData and
RxSYNC to the MAC. RxCLK1 is used when 1x8 port
sectionalization is selected. RxCLK0 may not be used. See
“Clock/SYNC Requirements” on page 125. for detailed clock
requirements. These outputs are only enabled when SSSMII mode is enabled.
Receive Data - Ports 0-7.
These serial output streams provide data received from
the network. The LXT9785/9785E drives the data out
synchronously to REFCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. RxData[0:7], RxSYNC[0:1], and RxCLK[0:1] outputs are three-stated in Isolation and H/W Power-Down
modes and during H/W reset.
86
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 28. Intel® LXT9785/LXT9785E MDIO Control Interface Signals – BGA23
Ball/Pin
Designation
BGA23
Symbol
Type1
Signal Description2,3,4
PQFP
Management Data Input/Output.
F3,
A10
64
25
MDIO0
MDIO1
I/O, TS, SL,
IP
Bidirectional serial data channel for communication
between the PHY and MAC or switch ASIC. Only
MDIO0 is used when 1x8 port sectionalization is
selected. In 2x4 port sectionalization mode, MDIO0
accesses ports 0-3 and MDIO1 accesses ports 4-7.
Refer to Figure 21 “Intel® LXT9785/LXT9785E Typical
SS-SMII Quad Sectionalization Diagram” on page 140.
Management Data Interrupt.
F1,
C9
67
26
MDINT0
MDINT1
OD, TS, SL,
IP
When Register bit 18.1 = 1, an active Low output on this
Pin indicates status change. Only MDINT0 is used when
1x8 port sectionalization is selected. In 2x4 port
sectionalization mode, MDINT0 is associated with ports
0-3 and MDINT1 is associated with ports 4-7. Refer to
Figure 21 “Intel® LXT9785/LXT9785E Typical SS-SMII
Quad Sectionalization Diagram” on page 140.
Management Data Clock.
E1,
B10
63
24
MDC0
MDC1
I, ST, ID
Clock for the MDIO serial data channel. Maximum
frequency is 20 MHz. Only MDC0 is used when 1x8 port
sectionalization is selected. In 2x4 port
sectionalization mode, MDC0 clocks ports 0-3 register
accesses and MDC1 clocks ports 4-7 register accesses.
Refer to Figure 21 “Intel® LXT9785/LXT9785E Typical
SS-SMII Quad Sectionalization Diagram” on page 140.
Management Disable.
When MDDIS is tied High, the MDIO port is completely
disabled and the Hardware Control Interface pins set
their respective bits at power up and reset.
L1
84
MDDIS
I, ST, ID
When MDDIS is pulled Low at power up or reset, via the
internal pull-down resistor or by tieing it to ground, the
Hardware Control Interface Pins control only the initial
or “default” values of their respective register bits. After
the power-up/reset cycle is complete, bit control reverts
to the MDIO serial channel.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. MDIO[0:1] and MDINT[0:1] outputs are three-stated in H/W Power-Down mode and during H/W reset.
4. Supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
where X is the register number (0-32) and Y is the bit number (0-15).
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
87
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 29. Intel® LXT9785/LXT9785E Signal Detect – BGA23
Ball/Pin
Designation
BGA23
Symbol
Type1
Signal Description2,3
PQFP
Signal Detect 2.5 Volt Interface.
SD input threshold voltage select.
P1
95
SD_2P5V
I, ST, ID
Tie to VCCPECL = Select 2.5 V LVPECL input levels
Float or Tie to GNDPECL = Select 3.3 V LVPECL input
levels
P2,
N4,
P3,
N5,
P15,
P16,
P17,
N17
96
97
100
101
161
162
165
166
Signal Detect - Ports 0-7.
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
Signal Detect input from the fiber transceiver (these inputs
are only active for ports operating in fiber mode).
I
Logic High = Normal operation (the process of searching
for receive idles for the purpose of bringing link up is
initiated)
Logic Low = Link is declared lost
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode.
3. Tie SD[0:7] inputs to GNDPECL if unused.
Table 30. Intel® LXT9785/LXT9785E Network Interface Signal Descriptions – BGA23
Ball/Pin Designation
Symbol
BGA23
PQFP
T2, U1,
T3, R4,
T6, U5,
U7, T7,
T10, R10,
T11, U11,
T14,U15,
R14, T15
107, 108
111, 110
121, 122
125, 124
136, 137
140, 139
150, 151
154, 153
TPFOP0, TPFON0
TPFOP1, TPFON1
TPFOP2, TPFON2
TPFOP3, TPFON3
TPFOP4, TPFON4
TPFOP5, TPFON5
TPFOP6, TPFON6
TPFOP7, TPFON7
R2, T1,
U3, T4,
R6, T5,
T8, R8,
T9, U9,
U13, T12,
R12, T13,
R16, T16
104, 105
115, 114
118, 119
129, 128
132, 133
143, 142
146, 147
157, 156
TPFIP0, TPFIN0
TPFIP1, TPFIN1
TPFIP2, TPFIN2
TPFIP3, TPFIN3
TPFIP4, TPFIN4
TPFIP5, TPFIN5
TPFIP6, TPFIN6
TPFIP7, TPFIN7
Type1
Signal Description
Twisted-Pair/Fiber Outputs2, Positive &
Negative, Ports 0-7.
AO/AI
During 100BASE-TX or 10BASE-T operation,
TPFO pins drive 802.3 compliant pulses onto
the line.
During 100BASE-FX operation, TPFO pins
produce differential LVPECL outputs for fiber
transceivers.
Twisted-Pair/Fiber Inputs3, Positive &
Negative, Ports 0-7.
AI/AO
During 100BASE-TX or 10BASE-T operation,
TPFI pins receive differential 100BASE-TX or
10BASE-T signals from the line.
During 100BASE-FX operation, TPFI pins
receive differential LVPECL inputs from fiber
transceivers.
1. Type Column Coding: AI = Analog Input, AO = Analog Output.
2. Switched to Inputs (see TPFIP/N description) when not in fiber mode and MDIX is not active [that is,
twisted-pair, non-crossover MDI mode].
3. Switched to Outputs (see TPFOP/N description) when not in fiber mode and MDIX is not active [that is,
twisted-pair, non-crossover MDI mode].
88
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 31. Intel® LXT9785/LXT9785E JTAG Test Signal Descriptions – BGA23
Ball/Pin
Designation
Symbol
Type1
BGA23
PQFP
N14
167
TDI
I, ST, IP
N15
168
TDO
O, TS
N16
169
TMS
I, ST, IP
M16
170
TCK
I, ST, ID
M17
171
TRST
I, ST, IP
Signal Description2,3
Test Data Input.
Test data sampled with respect to the rising edge of TCK.
Test Data Output.
Test data driven with respect to the falling edge of TCK.
Test Mode Select.
Test Clock.
Clock input for JTAG test.
Test Reset.
Reset input for JTAG test.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain, TS = Three-State-able output, SMT =
Schmitt Triggered input, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. TDO output is three-stated in H/W Power-Down mode and during H/W reset.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
89
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 32. Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 (Sheet 1 of 4)
Ball/Pin
Designation
BGA23
Symbol
Type1
Signal Description2
PQFP
Tx Output Slew Controls 0 and 1 Defaults.
These pins are read at startup or reset. Their value at
that time is used to set the default state of Register bits
27.11:10 for all ports. These register bits can be read
and overwritten after startup / reset.
N3,
M4
94
93
TxSLEW_0
TxSLEW_1
These pins select the TX output slew rate for all ports
(rise and fall time) as follows:
I, ST, ID
TxSLEW_1
TxSLEW_0
Slew Rate (Rise and Fall
Time)
0
0
3.3 ns
0
1
3.6 ns
1
0
3.9 ns
1
1
4.2 ns
Pause Default.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 4.10 for
all ports. This register bit can be read and overwritten
after startup / reset.
D5
50
PAUSE
ID, I, ST
When High, the LXT9785/9785E advertises Pause
capabilities on all ports during auto-negotiation.
This pin is shared with RMII-RxER1. An external pullup resistor (see applications section for value) can be
used to set Pause active while RxER1 is three-stated
during H/W reset. If no pull-up is used, the default
Pause state is set inactive via the internal pull-down
resistor.
Power-Down.
L14
174
PWRDWN
I, ST, ID
When High, forces the LXT9785/9785E into global
power-down mode.
Pin is not on JTAG chain.
Reset.
M15
175
RESET
I, ST, IP
This active low input is ORed with the control register
Reset Register bit 0.15. When held Low, all outputs are
forced to inactive state.
Pin is not on JTAG chain.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
2. The IP/ID resistors are disabled during hardware power-down mode.
90
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 32. Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 (Sheet 2 of 4)
Ball/Pin
Designation
BGA23
Symbol
Type1
Signal Description2
PQFP
Address <4:0>.
L4,
M2,
M3,
N1,
N2
88
89
90
91
92
ADD_4
ADD_3
ADD_2
ADD_1
ADD_0
Sets base address. Each port adds its port number
(starting with 0) to this address to determine its PHY
address.
I, ST, ID
Port 0 Address = Base
Port 1 Address = Base + 1
Port 2 Address = Base + 2
Port 3 Address = Base + 3
Port 4 Address = Base + 4
Port 5 Address = Base + 5
Port 6 Address = Base + 6
Port 7 Address = Base + 7
Mode Select[1:0].
00 = RMII
L17,
L16
178
177
MODESEL_1
MODESEL_0
01 = SMII
I, ST, ID
10 = SS-SMII
11 = Reserved
All ports are configured the same. Interfaces cannot be
mixed and must be all RMII, SMII, or SS-SMII.
Sectionalization Select.
L15
176
SECTION
I, ST, ID
This pin selects sectionalization into separate ports.
0 = 1x8 ports,
1 = 2x4 ports
Auto MDI/MDIX Enable Default.
K1
83
AMDIX_EN
I, ST, IP
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 27.9 for
all ports. These register bits can be read and
overwritten after startup / reset. Refer to Table 40
“Intel® LXT9785/LXT9785E MDIX Selection” on
page 119.
When active (High), automatic MDI crossover (MDIX)
(regardless of segmentation) is selected for all ports.
When inactive (Low) MDIX is selected according to the
MDIX pin.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
2. The IP/ID resistors are disabled during hardware power-down mode.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
91
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 32. Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 (Sheet 3 of 4)
Ball/Pin
Designation
BGA23
Symbol
Type1
Signal Description2
PQFP
MDIX Select Default.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 27.8 for
all ports. These register bits can be read and
overwritten after startup / reset. Refer to Table 40
“Intel® LXT9785/LXT9785E MDIX Selection” on
page 119.
When AMDIX_EN is active this pin is ignored.
D2
59
MDIX
I, ID, ST
When AMDIX_EN is inactive, all ports are forced to the
MDI or the MDIX function regardless of segmentation.
If this pin is active (high), MDI crossover (MDIX) is
selected. If this pin is inactive, non-crossover MDI
mode is set.
This pin is shared with RMII-RxER0. An external pullup resistor (see applications section for value) can be
used to set MDIX active while RxER0 is three-stated
during H/W reset. If no pull-up is used, the default
MDIX state is set inactive via the internal pull-down
resistor. Do not tie this pin directly to VCCIO (vs. using
a pull-up) in non-RMII modes.
Global Port Configuration Defaults 1-3.
L2,
L3,
M1
85
86
87
CFG_3
CFG_2
CFG_1
I, ST, ID
These pins are read at startup or reset. Their value at
that time is used to set the default state of register bits
shown in Table 42 “Intel® LXT9785/9785E Global
Hardware Configuration Settings” on page 129 for all
ports. These register bits can be read and overwritten
after startup / reset.
When operating in Hardware Control Mode, these pins
provide configuration control options for all the ports
(refer to Table 42 “Intel® LXT9785/9785E Global
Hardware Configuration Settings” on page 129 for
details).
Global FX/TP Enable Default.
M14
173
G_FX/TP
I, ST, ID
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 16.0 for
all ports. These register bits can be read and
overwritten after startup / reset. Refer to Table 92 “Port
Configuration Register (Address 16, Hex 10)” on page 207.
This input selects whether all the ports are defaulted to
TP vs. FX mode.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
2. The IP/ID resistors are disabled during hardware power-down mode.
92
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 32. Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 (Sheet 4 of 4)
Ball/Pin
Designation
BGA23
Symbol
Type1
Signal Description2
PQFP
FIFO Select <1:0>.
These pins are read at startup or reset. Their value at
that time is used to set the default state of Register bits
18.15:14 for all ports. These register bits can be read
and overwritten after startup/reset.
A15
A12
11
20
FIFOSEL1
FIFOSEL0
I, ID, ST
These pins are shared with RMII-RxER<5:4>. An
external pull-up resistor (see applications section for
value) can be used to set FIFO Select<1:0> to active
while RxER<5:4> are three-stated during hardware
reset. If no pull-up is used, the default FIFO select
state is set via the internal pull-down resistors.
See Table 36 “Intel® LXT9785/LXT9785E Receive
FIFO Depth Configurations” on page 97.
Preamble Select.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 16.5 for
all ports. This register bit can be read and overwritten
after startup/reset.
D7
40
PREASEL
I, ID, ST
This pin is shared with RMII-RxER2. An external pullup resistor (see applications section for value) can be
used to set Preamble Select to active while RxER2 is
three-stated during hardware reset. If no pull-up is
used, the default Preamble Select state is set via the
internal pull-down resistors.
Note: Preamble select has no effect in 100 Mbps
operation.
A17
2
LINKHOLD
I, ID, ST
LINKHOLD Default. This pin is read at startup or
reset. Its value at that time is used to set the default
state of Register bit 0.11 for all ports. This register bit
can be read and overwritten after startup / reset. When
High, the LXT9785/9785E powers down all ports.
This pin is shared with RMII-RxER6. An external pullup resistor (see applications section for value) can be
used to set LINKHOLD active while RxER6 is tri-stated
during H/W reset. If no pull-up is used, the default
LINKHOLD state is set inactive via the internal pulldown resistor.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
2. The IP/ID resistors are disabled during hardware power-down mode.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
93
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 33. Intel® LXT9785/LXT9785E LED Signal Descriptions – BGA23 (Sheet 1 of 2)
Ball/Pin
Designation
BGA23
PQFP
K3,
K2,
J1
82
81
80
Symbol
Type1
Signal Description2,3
Port 0 LED Drivers 1-3.
LED0_1
LED0_2
LED0_3
OD, TS, SL,
IP
These pins drive LED indicators for Port 0. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to Table 96 “LED Configuration Register (Address 20,
Hex 14)” on page 213 for details).
Port 1 LED Drivers 1-3.
J4,
J3,
H1
77
76
75
LED1_1
LED1_2
LED1_3
OD, TS, SL,
IP
These pins drive LED indicators for Port 1. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to Table 96 “LED Configuration Register (Address 20,
Hex 14)” on page 213 for details).
Port 2 LED Drivers 1-3.
H2,
H3,
G1
73
72
71
LED2_1
LED2_2
LED2_3
OD, TS, SL,
IP
These pins drive LED indicators for Port 2. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to Table 96 “LED Configuration Register (Address 20,
Hex 14)” on page 213 for details).
Port 3 LED Drivers 1-3.
F2,
G3,
G4
70
69
68
LED3_1
LED3_2
LED3_3
K16,
K17,
J17
180
181
182
LED4_1
LED4_2
LED4_3
OD, TS, SL,
IP
These pins drive LED indicators for Port 3. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to Table 96 “LED Configuration Register (Address 20,
Hex 14)” on page 213 for details).
Port 4 LED Drivers 1-3.
OD, TS, SL,
IP
These pins drive LED indicators for Port 4. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to Table 96 “LED Configuration Register (Address 20,
Hex 14)” on page 213 for details).
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. The LED outputs are three-stated in H/W Power-Down mode and during H/W reset.
4.
94
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 33. Intel® LXT9785/LXT9785E LED Signal Descriptions – BGA23 (Sheet 2 of 2)
Ball/Pin
Designation
Symbol
BGA23
PQFP
J15,
J16,
H17
185
186
187
Type1
Signal Description2,3
Port 5 LED Drivers 1-3.
LED5_1
LED5_2
LED5_3
OD, TS, SL,
IP
These pins drive LED indicators for Port 5. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to Table 96 “LED Configuration Register (Address 20,
Hex 14)” on page 213 for details).
Port 6 LED Drivers 1-3.
H15,
H16,
G17
189
190
191
LED6_1
LED6_2
LED6_3
OD, TS, SL,
IP
These pins drive LED indicators for Port 6. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to Table 96 “LED Configuration Register (Address 20,
Hex 14)” on page 213 for details).
Port 7 LED Drivers 1-3.
G15,
F17,
F16
192
193
194
LED7_1
LED7_2
LED7_3
OD, TS, SL,
IP
These pins drive LED indicators for Port 7. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to Table 96 “LED Configuration Register (Address 20,
Hex 14)” on page 213 for details).
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID
resistors are also disabled when the output is enabled.
3. The LED outputs are three-stated in H/W Power-Down mode and during H/W reset.
4.
Table 34. Intel® LXT9785/LXT9785E Power Supply Signal Descriptions – BGA23 (Sheet 1 of 2)
Ball/Pin Designation
BGA23
PQFP
G13, J14,
F5, J5
65, 78, 184,
196
Symbol
Type
VCCD
-
Signal Description
Digital Power Supply - Core.
+2.5 V supply for core digital circuits.
Digital Power Supply - I/O Ring.
A2, A8,
C1, C11,
D14
18, 29, 47,
56, 208
VCCIO
-
+2.5/3.3 V supply for digital I/O circuits. The digital
input circuits running off of this rail, having a TTL-level
threshold and over-voltage protection, may be
interfaced with 3.3/5.0 V, when the IO supply is 3.3 V,
and 2.5/3.3/5.0 V when 2.5 V.
Digital Power Supply - PECL Signal Detect Inputs.
L13, L5
98, 164
VCCPECL
-
N13, P4,
P7, P8,
P9, P10,
P11, P12
103, 116,
117, 130,
131, 144,
145, 158
VCCR
-
+2.5/3.3 V supply for PECL Signal Detect input
circuits. If Fiber Mode is not used, tie these pins to
GNDPECL to save power.
Analog Power Supply - Receive.
+2.5 V supply for all analog receive circuits.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
95
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 34. Intel® LXT9785/LXT9785E Power Supply Signal Descriptions – BGA23 (Sheet 2 of 2)
Ball/Pin Designation
Symbol
Type
VCCT
-
BGA23
PQFP
N6, N7,
N9, N11,
N12
109, 123,
138, 152
A1, A9,
B3, B7,
C5, C13,
C17, D1,
D3, D6,
D10, D15,
E5, E7,
E9, E11,
E13, E17,
F13, H8,
H9, H10,
J8, J9,
J10, K8,
K9, K10
66, 79,
183, 195
GNDD
-
9, 19, 30,
38, 48, 57,
74, 188,
199, 207
GNDIO
-
M5, M13
99, 163
GNDPECL
-
P5, P6,
P13, R7,
R9, R11,
R13, U8
106, 112,
120, 126,
135, 141,
149, 155
GNDR
-
P14, R1,
R3, R5,
R15, R17,
T17, U2,
U4, U6,
U10, U12,
U14, U16,
U17
113, 127,
134, 148
GNDT
-
K14
179
SGND
-
Signal Description
Analog Power Supply - Transmit.
+2.5 V supply for all analog transmit circuits.
Digital Ground.
Ground return for core digital supplies (VCCD). All
ground pins can be tied together using a single ground
plane.
Digital GND - I/O Ring.
Ground return for digital I/O circuits (VCCIO).
Digital GND - PECL Signal Detect Inputs.
Ground return for PECL Signal Detect input circuits.
Analog Ground - Receive.
Ground return for receive analog supply. All ground
pins can be tied together using a single ground plane.
Analog Ground - Transmit.
Ground return for transmit analog supply. All ground
pins can be tied together using a single ground plane.
Substrate Ground.
Ground for chip substrate. All ground pins can be tied
together using a single ground plane.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
96
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 35. Intel® LXT9785/LXT9785E Unused/Reserved Pins – BGA23
Pin/Ball Designation
BGA23
PQFP
F15, G2,
G5, G14,
G16, H4,
H14, J2,
J13, K4,
K15
N/C
Symbol
Type1
N/C
–
Signal Description
No Connection.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown
2.
Table 36. Intel® LXT9785/LXT9785E Receive FIFO Depth Configurations
FIFOSEL1
FIFOSEL0
Register 18.15 Value
Register 18.14 Value
0
0
1
0
0
1
1
1
1
0
0
0
1
1
0
1
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
97
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.5
BGA15 Ball Assignments
The following figure and tables provide the BGA15 ball locations and signal names arranged in
alphanumeric order as follows:
• Figure 6 “Intel® LXT9785MBC 196-Ball BGA15 Assignments (Top View)”
• Table 37, “Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name”
on page 99
• Table 38, “Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location
(SMII/SS-SMII)” on page 103
Figure 6. Intel® LXT9785MBC 196-Ball BGA15 Assignments (Top View)
1
2
3
4
5
6
7
8
9
10
11
A
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 A12 A13 A14
A
B
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11 B12 B13 B14
B
C
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10 C11 C12 C13 C14
C
D
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11 D12 D13 D14
D
E
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11 E12 E13 E14
E
F
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F14
F
G
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10 G11 G12 G13 G14
G
H
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10 H11 H12 H13 H14
H
J
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J14
J
K
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10 K11 K12 K13 K14
K
L
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L
M
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10 M11 M12 M13 M14
M
N
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10 N11 N12 N13 N14
N
P
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10 P11 P12 P13 P14
P
1
2
3
4
5
6
7
8
9
10
J11
L11
11
12
F12
J12
L12
12
13
F13
J13
L13
13
14
L14
14
B1532-01
98
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.5.1
BGA15 Ball List
The following tables provide the RMII BGA23 ball locations and signal names arranged in
alphanumeric order as follows:
Table 37 “Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name”
Table 38 “Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location (SMII/
SS-SMII)”
Table 37. Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name
Signal
Name
Ball
Type
Reference for Full
Description
Signal
Name
Ball
Type
Reference for Full
Description
ADD_3
P10
I, ST,
ID
Table 39 on page 109
CFG_2
L9
I, ST,
ID
Table 39 on page 109
ADD_4
N10
I, ST,
ID
Table 39 on page 109
CFG_3
M9
I, ST,
ID
Table 39 on page 109
AMDIX_EN
K8
I, ST,
IP
Table 39 on page 109
FIFOSEL0
F1
I, ID
Table 39 on page 109
FIFOSEL1
C1
I, ID
Table 39 on page 109
AVCC
D12
–
Table 39 on page 109
GNDD
A1
–
Table 39 on page 109
AVCC
E12
–
Table 39 on page 109
GNDD
A2
–
Table 39 on page 109
AVCC
F12
–
Table 39 on page 109
GNDD
A3
–
Table 39 on page 109
AVCC
G12
–
Table 39 on page 109
GNDD
B1
–
Table 39 on page 109
AVCC
H12
–
Table 39 on page 109
GNDD
B2
–
Table 39 on page 109
AVCC
J12
–
Table 39 on page 109
AVCC
K12
–
Table 39 on page 109
AVCC
L12
–
Table 39 on page 109
AVSS
E11
–
Table 39 on page 109
AVSS
F9
–
Table 39 on page 109
AVSS
F10
–
Table 39 on page 109
AVSS
F11
–
Table 39 on page 109
AVSS
G9
–
Table 39 on page 109
AVSS
G10
–
Table 39 on page 109
AVSS
G11
–
Table 39 on page 109
AVSS
H9
–
Table 39 on page 109
AVSS
H10
–
Table 39 on page 109
AVSS
H11
–
Table 39 on page 109
AVSS
J9
–
Table 39 on page 109
AVSS
J10
–
Table 39 on page 109
AVSS
J11
–
Table 39 on page 109
AVSS
K11
–
Table 39 on page 109
AVSS
L11
–
Table 39 on page 109
M10
I, ST,
ID
Table 39 on page 109
CFG_1
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
GNDD
B5
–
Table 39 on page 109
GNDD
B10
–
Table 39 on page 109
GNDD
D9
–
Table 39 on page 109
GNDD
D11
–
Table 39 on page 109
GNDD
E5
–
Table 39 on page 109
GNDD
E6
–
Table 39 on page 109
GNDD
E9
–
Table 39 on page 109
GNDD
E10
–
Table 39 on page 109
GNDD
F5
–
Table 39 on page 109
GNDD
F6
–
Table 39 on page 109
GNDD
F7
–
Table 39 on page 109
GNDD
F8
–
Table 39 on page 109
GNDD
G4
–
Table 39 on page 109
GNDD
G6
–
Table 39 on page 109
GNDD
G7
–
Table 39 on page 109
GNDD
G8
–
Table 39 on page 109
GNDD
H6
–
Table 39 on page 109
GNDD
H7
–
Table 39 on page 109
GNDD
H8
–
Table 39 on page 109
GNDD
J5
–
Table 39 on page 109
99
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal
Name
Ball
Type
Reference for Full
Description
GNDD
J6
–
Table 39 on page 109
Ball
Type
Reference for Full
Description
LED6_1
A7
OD,
TS,
SL, IP
Table 39 on page 109
LED6_2
B7
OD,
TS,
SL, IP
Table 39 on page 109
LED7_1
B6
OD,
TS,
SL, IP
Table 39 on page 109
LED7_2
A6
OD,
TS,
SL, IP
Table 39 on page 109
GNDD
J7
–
Table 39 on page 109
GNDD
J8
–
Table 39 on page 109
GNDD
K5
–
Table 39 on page 109
GNDD
K6
–
Table 39 on page 109
GNDD
K9
–
Table 39 on page 109
GNDD
K10
–
Table 39 on page 109
GNDD
L2
–
Table 39 on page 109
GNDD
N1
–
Table 39 on page 109
GNDD
N11
–
Table 39 on page 109
LINKHOLD
B3
ID
Table 39 on page 109
GNDD
P1
–
Table 39 on page 109
MDC
P4
I, ST,
ID
Table 39 on page 109
GNDD
P11
–
Table 39 on page 109
MDINT
P5
OD,
TS,
SL, IP
Table 39 on page 109
N9
OD,
TS,
SL, IP
MDIO
N5
IO, TS,
SL, IP
Table 39 on page 109
P9
OD,
TS,
SL, IP
Table 39 on page 109
ModeSel_0
C9
I, ST,
ID
Table 39 on page 109
ModeSel_1
E8
I, ST,
ID
Table 39 on page 109
N/C
C4
–
Table 39 on page 109
N/C
C7
–
Table 39 on page 109
N/C
D1
–
Table 39 on page 109
N/C
D2
–
Table 39 on page 109
N/C
D5
–
Table 39 on page 109
N/C
D6
–
Table 39 on page 109
N/C
D8
–
Table 39 on page 109
N/C
D10
–
Table 39 on page 109
N/C
E4
–
Table 39 on page 109
N/C
E7
–
Table 39 on page 109
N/C
G2
–
Table 39 on page 109
N/C
G5
–
Table 39 on page 109
N/C
H1
–
Table 39 on page 109
N/C
H5
–
Table 39 on page 109
N/C
J4
–
Table 39 on page 109
N/C
K4
–
Table 39 on page 109
N/C
K7
–
Table 39 on page 109
N/C
L1
–
Table 39 on page 109
N/C
L6
–
Table 39 on page 109
N/C
L8
–
Table 39 on page 109
LED0_1
LED0_2
Table 39 on page 109
LED1_1
N8
OD,
TS,
SL, IP
Table 39 on page 109
LED1_2
P8
OD,
TS,
SL, IP
Table 39 on page 109
P7
OD,
TS,
SL, IP
Table 39 on page 109
N7
OD,
TS,
SL, IP
Table 39 on page 109
P6
OD,
TS,
SL, IP
Table 39 on page 109
LED2_1
LED2_2
LED3_1
LED3_2
N6
OD,
TS,
SL, IP
Table 39 on page 109
LED4_1
B9
OD,
TS,
SL, IP
Table 39 on page 109
A9
OD,
TS,
SL, IP
B8
OD,
TS,
SL, IP
Table 39 on page 109
A8
OD,
TS,
SL, IP
Table 39 on page 109
LED4_2
LED5_1
LED5_2
100
Signal
Name
Table 39 on page 109
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal
Name
Ball
Type
Reference for Full
Description
N/C
L10
–
Table 39 on page 109
N/C
M4
–
Table 39 on page 109
N/C
M5
–
N/C
M6
N/C
M7
N/C
Signal
Name
Ball
Type
Reference for Full
Description
TCK
A11
I, ST,
ID
Table 39 on page 109
Table 39 on page 109
TDI
C12
I, ST,
IP
Table 39 on page 109
–
Table 39 on page 109
TDO
C11
O, TS
Table 39 on page 109
–
Table 39 on page 109
M8
–
Table 39 on page 109
TMS
B11
I, ST,
IP
Table 39 on page 109
N/C
P2
–
Table 39 on page 109
TPIN0
N12
AI/AO
Table 39 on page 109
N/C
P3
–
Table 39 on page 109
TPIN1
M13
AI/AO
Table 39 on page 109
REFCLK0
L4
I
Table 39 on page 109
TPIN2
L14
AI/AO
Table 39 on page 109
TPIN3
H13
AI/AO
Table 39 on page 109
TPIN4
G13
AI/AO
Table 39 on page 109
TPIN5
D14
AI/AO
Table 39 on page 109
TPIN6
C13
AI/AO
Table 39 on page 109
TPIN7
B12
AI/AO
Table 39 on page 109
TPIP0
P12
AI/AO
Table 39 on page 109
TPIP1
M14
AI/AO
Table 39 on page 109
REFCLK1
C3
I
Table 39 on page 109
RESET
C10
I, ST,
IP
Table 39 on page 109
G1
O, TS,
ID
Table 39 on page 109
RXCLK
RxData0_S
N3
O, TS
Table 39 on page 109
RxData0_SS
M3
O, TS,
ID
Table 39 on page 109
RxData1_S
M2
O, TS
Table 39 on page 109
RxData1_SS
M1
O, TS,
ID
Table 39 on page 109
RxData2_S
K2
O, TS
Table 39 on page 109
RxData2_SS
J2
O, TS,
ID
Table 39 on page 109
TPIP2
L13
AI/AO
Table 39 on page 109
TPIP3
H14
AI/AO
Table 39 on page 109
TPIP4
G14
AI/AO
Table 39 on page 109
TPIP5
D13
AI/AO
Table 39 on page 109
TPIP6
C14
AI/AO
Table 39 on page 109
TPIP7
A12
AI/AO
Table 39 on page 109
TPON0
N13
AO/AI
Table 39 on page 109
AO/AI
Table 39 on page 109
RxData3_S
H3
O, TS
Table 39 on page 109
RxData3_SS
H2
O, TS,
ID
Table 39 on page 109
TPON1
P14
RxData4_S
F2
O, TS
Table 39 on page 109
TPON2
K14
AO/AI
Table 39 on page 109
RxData4_SS
F3
O, TS,
ID
Table 39 on page 109
TPON3
J13
AO/AI
Table 39 on page 109
RxData5_S
E3
O, TS
Table 39 on page 109
TPON4
F13
AO/AI
Table 39 on page 109
RxData5_SS
C2
O, TS
Table 39 on page 109
TPON5
E14
AO/AI
Table 39 on page 109
RxData6_S
B4
O, TS
Table 39 on page 109
TPON6
A14
AO/AI
Table 39 on page 109
TPON7
B13
AO/AI
Table 39 on page 109
TPOP0
P13
AO/AI
Table 39 on page 109
TPOP1
N14
AO/AI
Table 39 on page 109
TPOP2
K13
AO/AI
Table 39 on page 109
TPOP3
J14
AO/AI
Table 39 on page 109
RxData6_SS
A4
O, TS,
ID
Table 39 on page 109
RxData7_S
C5
O, TS
Table 39 on page 109
RxData7_SS
C6
O, TS,
ID
Table 39 on page 109
Table 39 on page 109
TPOP4
F14
AO, AI Table 39 on page 109
TPOP5
E13
AO/AI
Table 39 on page 109
TPOP6
B14
AO/AI
Table 39 on page 109
TPOP7
A13
AO/AI
Table 39 on page 109
RxSYNC
E1
O, TS,
ID
SGND
C8
–
Table 39 on page 109
SYNC/
TXSYNC
K1
I, ID
Table 39 on page 109
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
101
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
102
Signal
Name
Ball
Type
Reference for Full
Description
TRST
A10
I, ST,
IP
Table 39 on page 109
TXCLK
J3
I, ID
Table 39 on page 109
TxData0
N4
I, ID
Table 39 on page 109
TxData1
N2
I, ID
Table 39 on page 109
TxData2
K3
I, ID
Table 39 on page 109
TxData3
J1
I, ID
Table 39 on page 109
TxData4
G3
I, ID
Table 39 on page 109
TxData5
E2
I, ID
Table 39 on page 109
TxData6
D3
I, ID
Table 39 on page 109
TxData7
A5
I, ID
Table 39 on page 109
TXSLEW_0
M11
I, ST,
ID
Table 39 on page 109
TXSLEW_1
M12
I,ST,
ID
Table 39 on page 109
VCCD
D7
–
Table 39 on page 109
VCCD
L7
–
Table 39 on page 109
VCCIO
D4
–
Table 39 on page 109
VCCIO
F4
–
Table 39 on page 109
VCCIO
H4
–
Table 39 on page 109
VCCIO
L3
–
Table 39 on page 109
VCCIO
L5
–
Table 39 on page 109
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 38 shows the ball locations and signal names arranged in order by ball location.
Table 38. Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location (SMII/
SS-SMII)
Ball
Signal Name
Type
Reference for Full
Description
A1
GNDD
–
Table 39 on
page 109
A2
GNDD
–
Table 39 on
page 109
Ball
Signal Name
Type
Reference for Full
Description
B7
LED6_2
OD,
TS,
SL, IP
Table 39 on
page 109
B8
LED5_1
OD,
TS,
SL, IP
Table 39 on
page 109
A3
GNDD
–
Table 39 on
page 109
A4
RxData6_SS
O, TS,
ID
Table 39 on
page 109
B9
LED4_1
OD,
TS,
SL, IP
Table 39 on
page 109
A5
TxData7
I, ID
Table 39 on
page 109
B10
GNDD
–
Table 39 on
page 109
A6
LED7_2
OD,
TS,
SL, IP
Table 39 on
page 109
B11
TMS
I, ST,
IP
Table 39 on
page 109
Table 39 on
page 109
B12
TPIN7
AI/AO
LED6_1
OD,
TS,
SL, IP
Table 39 on
page 109
B13
TPON7
AO/AI
Table 39 on
page 109
B14
TPOP6
AO/AI
Table 39 on
page 109
C1
FIFOSEL1
I, ID
Table 39 on
page 109
C2
RxData5_SS
O, TS,
ID
Table 39 on
page 109
C3
REFCLK1
I
Table 39 on
page 109
C4
N/C
–
Table 39 on
page 109
C5
RxData7_S
O, TS
Table 39 on
page 109
C6
RxData7_SS
O, TS,
ID
Table 39 on
page 109
C7
N/C
–
Table 39 on
page 109
C8
SGND
–
Table 39 on
page 109
C9
ModeSel_0
I, ST,
ID
Table 39 on
page 109
C10
RESET
I, ST,
IP
Table 39 on
page 109
C11
TDO
O, TS
Table 39 on
page 109
C12
TDI
I, ST,
IP
Table 39 on
page 109
C13
TPIN6
AI/AO
Table 39 on
page 109
A7
A8
LED5_2
OD,
TS,
SL, IP
Table 39 on
page 109
A9
LED4_2
OD,
TS,
SL, IP
Table 39 on
page 109
A10
TRST
I, ST,
IP
Table 39 on
page 109
A11
TCK
I, ST,
ID
Table 39 on
page 109
A12
TPIP7
AI/AO
Table 39 on
page 109
A13
TPOP7
AO/AI
Table 39 on
page 109
A14
TPON6
AO/AI
Table 39 on
page 109
B1
GNDD
–
Table 39 on
page 109
B2
GNDD
–
Table 39 on
page 109
B3
LINKHOLD
ID
Table 39 on
page 109
B4
RxData6_S
O, TS
Table 39 on
page 109
B5
GNDD
–
Table 39 on
page 109
LED7_1
OD,
TS,
SL, IP
Table 39 on
page 109
B6
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
103
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
104
Ball
Signal Name
Type
Reference for Full
Description
Ball
Signal Name
Type
Reference for Full
Description
C14
TPIP6
AI/AO
Table 39 on
page 109
E10
GNDD
–
Table 39 on
page 109
D1
N/C
–
Table 39 on
page 109
E11
AVSS
–
Table 39 on
page 109
D2
N/C
–
Table 39 on
page 109
E12
AVCC
–
Table 39 on
page 109
D3
TxData6
I, ID
Table 39 on
page 109
E13
TPOP5
AO/AI
Table 39 on
page 109
D4
VCCIO
–
Table 39 on
page 109
E14
TPON5
AO/AI
Table 39 on
page 109
D5
N/C
–
Table 39 on
page 109
F1
FIFOSEL0
I, ID
Table 39 on
page 109
D6
N/C
–
Table 39 on
page 109
F2
RxData4_S
O, TS
Table 39 on
page 109
D7
VCCD
–
Table 39 on
page 109
F3
RxData4_SS
O, TS,
ID
Table 39 on
page 109
D8
N/C
–
Table 39 on
page 109
F4
VCCIO
–
Table 39 on
page 109
D9
GNDD
–
Table 39 on
page 109
F5
GNDD
–
Table 39 on
page 109
D10
N/C
–
Table 39 on
page 109
F6
GNDD
–
Table 39 on
page 109
D11
GNDD
–
Table 39 on
page 109
F7
GNDD
–
Table 39 on
page 109
D12
AVCC
–
Table 39 on
page 109
F8
GNDD
–
Table 39 on
page 109
D13
TPIP5
AI/AO
Table 39 on
page 109
F9
AVSS
–
Table 39 on
page 109
D14
TPIN5
AI/AO
Table 39 on
page 109
F10
AVSS
–
Table 39 on
page 109
E1
RxSYNC
O, TS,
ID
Table 39 on
page 109
F11
AVSS
–
Table 39 on
page 109
E2
TxData5
I, ID
Table 39 on
page 109
F12
AVCC
–
Table 39 on
page 109
E3
RxData5_S
O, TS
Table 39 on
page 109
F13
TPON4
AO/AI
Table 39 on
page 109
E4
N/C
–
Table 39 on
page 109
F14
TPOP4
AO, AI
Table 39 on
page 109
E5
GNDD
–
Table 39 on
page 109
G1
RXCLK
O, TS,
ID
Table 39 on
page 109
E6
GNDD
–
Table 39 on
page 109
G2
N/C
–
Table 39 on
page 109
E7
N/C
–
Table 39 on
page 109
G3
TxData4
I, ID
Table 39 on
page 109
E8
ModeSel_1
I, ST,
ID
Table 39 on
page 109
G4
GNDD
–
Table 39 on
page 109
E9
GNDD
–
Table 39 on
page 109
G5
N/C
–
Table 39 on
page 109
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball
Signal Name
Type
Reference for Full
Description
Ball
Signal Name
Type
Reference for Full
Description
G6
GNDD
–
Table 39 on
page 109
J2
RxData2_SS
O, TS,
ID
Table 39 on
page 109
G7
GNDD
–
Table 39 on
page 109
J3
TXCLK
I, ID
Table 39 on
page 109
G8
GNDD
–
Table 39 on
page 109
J4
N/C
–
Table 39 on
page 109
G9
AVSS
–
Table 39 on
page 109
J5
GNDD
–
Table 39 on
page 109
G10
AVSS
–
Table 39 on
page 109
J6
GNDD
–
Table 39 on
page 109
G11
AVSS
–
Table 39 on
page 109
J7
GNDD
–
Table 39 on
page 109
G12
AVCC
–
Table 39 on
page 109
J8
GNDD
–
Table 39 on
page 109
G13
TPIN4
AI/AO
Table 39 on
page 109
J9
AVSS
–
Table 39 on
page 109
G14
TPIP4
AI/AO
Table 39 on
page 109
J10
AVSS
–
Table 39 on
page 109
H1
N/C
–
Table 39 on
page 109
J11
AVSS
–
Table 39 on
page 109
H2
RxData3_SS
O, TS,
ID
Table 39 on
page 109
J12
AVCC
–
Table 39 on
page 109
H3
RxData3_S
O, TS
Table 39 on
page 109
J13
TPON3
AO/AI
Table 39 on
page 109
H4
VCCIO
–
Table 39 on
page 109
J14
TPOP3
AO/AI
Table 39 on
page 109
H5
N/C
–
Table 39 on
page 109
K1
SYNC/
TXSYNC
I, ID
Table 39 on
page 109
H6
GNDD
–
Table 39 on
page 109
K2
RxData2_S
O, TS
Table 39 on
page 109
H7
GNDD
–
Table 39 on
page 109
K3
TxData2
I, ID
Table 39 on
page 109
H8
GNDD
–
Table 39 on
page 109
K4
N/C
–
Table 39 on
page 109
H9
AVSS
–
Table 39 on
page 109
K5
GNDD
–
Table 39 on
page 109
H10
AVSS
–
Table 39 on
page 109
K6
GNDD
–
Table 39 on
page 109
H11
AVSS
–
Table 39 on
page 109
K7
N/C
–
Table 39 on
page 109
H12
AVCC
–
Table 39 on
page 109
K8
AMDIX_EN
I, ST,
IP
Table 39 on
page 109
H13
TPIN3
AI/AO
Table 39 on
page 109
K9
GNDD
–
Table 39 on
page 109
H14
TPIP3
AI/AO
Table 39 on
page 109
K10
GNDD
–
Table 39 on
page 109
J1
TxData3
I, ID
Table 39 on
page 109
K11
AVSS
–
Table 39 on
page 109
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
105
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
106
Ball
Signal Name
Type
Reference for Full
Description
Ball
Signal Name
Type
Reference for Full
Description
K12
AVCC
–
Table 39 on
page 109
M8
N/C
–
Table 39 on
page 109
K13
TPOP2
AO/AI
Table 39 on
page 109
M9
CFG_3
I, ST,
ID
Table 39 on
page 109
K14
TPON2
AO/AI
Table 39 on
page 109
M10
CFG_1
I, ST,
ID
Table 39 on
page 109
L1
N/C
–
Table 39 on
page 109
M11
TXSLEW_0
I, ST,
ID
Table 39 on
page 109
L2
GNDD
–
Table 39 on
page 109
M12
TXSLEW_1
I,ST,
ID
Table 39 on
page 109
L3
VCCIO
–
Table 39 on
page 109
M13
TPIN1
AI/AO
Table 39 on
page 109
L4
REFCLK0
I
Table 39 on
page 109
M14
TPIP1
AI/AO
Table 39 on
page 109
L5
VCCIO
–
Table 39 on
page 109
N1
GNDD
–
Table 39 on
page 109
L6
N/C
–
Table 39 on
page 109
N2
TxData1
I, ID
Table 39 on
page 109
L7
VCCD
–
Table 39 on
page 109
N3
RxData0_S
O, TS
Table 39 on
page 109
L8
N/C
–
Table 39 on
page 109
N4
TxData0
I, ID
Table 39 on
page 109
L9
CFG_2
I, ST,
ID
Table 39 on
page 109
N5
MDIO
Table 39 on
page 109
L10
N/C
–
Table 39 on
page 109
IO,
TS,
SL, IP
N6
LED3_2
OD,
TS,
SL, IP
Table 39 on
page 109
N7
LED2_2
OD,
TS,
SL, IP
Table 39 on
page 109
N8
LED1_1
OD,
TS,
SL, IP
Table 39 on
page 109
L11
AVSS
–
Table 39 on
page 109
L12
AVCC
–
Table 39 on
page 109
L13
TPIP2
AI/AO
Table 39 on
page 109
L14
TPIN2
AI/AO
Table 39 on
page 109
M1
RxData1_SS
O, TS,
ID
Table 39 on
page 109
N9
LED0_1
OD,
TS,
SL, IP
Table 39 on
page 109
M2
RxData1_S
O, TS
Table 39 on
page 109
N10
ADD_4
I, ST,
ID
Table 39 on
page 109
M3
RxData0_SS
O, TS,
ID
Table 39 on
page 109
N11
GNDD
–
Table 39 on
page 109
M4
N/C
–
Table 39 on
page 109
N12
TPIN0
AI/AO
Table 39 on
page 109
M5
N/C
–
Table 39 on
page 109
N13
TPON0
AO/AI
Table 39 on
page 109
M6
N/C
–
Table 39 on
page 109
N14
TPOP1
AO/AI
Table 39 on
page 109
M7
N/C
–
Table 39 on
page 109
P1
GNDD
–
Table 39 on
page 109
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball
Signal Name
Type
Reference for Full
Description
P2
N/C
–
Table 39 on
page 109
P3
N/C
–
Table 39 on
page 109
P4
MDC
I, ST,
ID
Table 39 on
page 109
P5
MDINT
OD,
TS,
SL, IP
Table 39 on
page 109
P6
LED3_1
OD,
TS,
SL, IP
Table 39 on
page 109
P7
LED2_1
OD,
TS,
SL, IP
Table 39 on
page 109
P8
LED1_2
OD,
TS,
SL, IP
Table 39 on
page 109
P9
LED0_2
OD,
TS,
SL, IP
Table 39 on
page 109
P10
ADD_3
I, ST,
ID
Table 39 on
page 109
P11
GNDD
–
Table 39 on
page 109
P12
TPIP0
AI/AO
Table 39 on
page 109
P13
TPOP0
AO/AI
Table 39 on
page 109
P14
TPON1
AO/AI
Table 39 on
page 109
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
107
Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
108
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.6
BGA15 Signal Descriptions
3.6.1
Signal Name Conventions
Signal names may contain either a port designation or a serial designation, or a combination of the
two designations. Signal naming conventions are as follows:
• Port Number Only. Individual signals that apply to a particular port are designated by the
Signal Mnemonic, immediately followed by the Port Designation. For example, Transmit
Enable signals would be identified as TxEN0, TxEN1, and TxEN2.
• Serial Number Only. A set of signals which are not tied to any specific port are designated by
the Signal Mnemonic, followed by an underscore and a serial designation. For example, a set
of three Global Configuration signals would be identified as CFG_1, CFG_2, and CFG_3.
• Port and Serial Number. In cases where each port is assigned a set of multiple signals, each
signal is designated in the following order: Signal Mnemonic, Port Designation, an
underscore, and the serial designation. For example, a set of three Port Configuration signals
would be identified as RxData0_0 and RxData0_1, RxData1_0 and RxData1_1, and
RxData2_0 and RxData2_1.
3.6.2
Signal Descriptions – SMII and SS-SMII Configurations
Table 39 provides the BGA15 signal descriptions.
Table 39. Intel® LXT9785 BGA15 Signal Descriptions (Sheet 1 of 7)
BGA15 Ball
Designation
Symbol
Type
Signal Description
SMII/SS-SMII Common Signal Descriptions
N4,
N2,
K3,
J1,
G3,
E2,
D3,
A5
TxData0
TxData1
TxData2
TxData3
TxData4
TxData5
TxData6
TxData7
C3
L4
REFCLK1
Transmit Data - Ports 0-7.
I, ID
These serial input streams provide data to be transmitted to
the network. The LXT9785/9785E clocks the data in
synchronously to REFCLK.
Reference Clock.
REFCLK0
I
The LXT9785/9785E always requires a 125 MHz reference
clock input. Refer to Section 4.4.2, “Clock/SYNC
Requirements” on page 125 for detailed clock
requirements.
SMII Specific Signal Descriptions
SMII Synchronization.
K1
SYNC
I, ID
The MAC must generate a SYNC pulse every 10 REFCLK
cycles to synchronize the SMII.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
109
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 39. Intel® LXT9785 BGA15 Signal Descriptions (Sheet 2 of 7)
BGA15 Ball
Designation
Symbol
N3,
M2,
K2,
H3,
F2,
E3,
B4,
C5
RxData0_S
RxData1_S
RxData2_S
RxData3_S
RxData4_S
RxData5_S
RxData6_S
RxData7_S
Type
Signal Description
Receive Data - Ports 0-7.
O, TS
These serial output streams provide data received from the
network. The LXT9785/9785E drives the data out
synchronously to REFCLK.
SS-SMII Specific Signal Descriptions
SS-SMII Transmit Synchronization.
K1
TxSYNC
I, ID
RxSYNC
O, TS,
ID
The MAC must generate a TxSYNC pulse every 10 TxCLK
cycles to mark the start of TxData segments.
SS-SMII Receive Synchronization.
E1
The LXT9785/9785E generates these pulses every 10
RxCLK cycles to mark the start of RxData segments for the
MAC.
SS-SMII Transmit Clock.
J3
TxCLK
I, ID
The MAC sources this 125 MHz clock as the timing
reference for TxData and TxSYNC. See “Clock/SYNC
Requirements” on page 125 for detailed clock requirements.
SS-SMII Receive Clock.
G1
RxCLK
O, TS,
ID
M3,
M1,
J2,
H2,
F3,
C2,
A4,
C6
RxData0_SS
RxData1_SS
RxData2_SS
RxData3_SS
RxData4_SS
RxData5_SS
RxData6_SS
RxData7_SS
O, TS,
ID
The LXT9785/9785E generates these clocks, based on
REFCLK, to provide a timing reference for RxData and
RxSYNC to the MAC. See “Clock/SYNC Requirements” on
page 125 for detailed clock requirements. These outputs are
only enabled when SS-SMII mode is enabled.
Receive Data - Ports 0-7.
These serial output streams provide data received from the
network. The LXT9785/9785E drives the data out
synchronously to REFCLK.
MDIO Control Interface Signal Descriptions
Management Data Input/Output.
N5
P5
MDIO
I/O, TS,
SL, IP
MDINT
OD, TS,
SL,
IP
Bidirectional serial data channel for communication
between the PHY and MAC or switch ASIC. Refer to
Figure 21 on page 140.
Management Data Interrupt.
When Register bit 18.1 = 1, an active Low output on this
Pin indicates status change. Refer to Figure 21 on page 140.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
110
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 39. Intel® LXT9785 BGA15 Signal Descriptions (Sheet 3 of 7)
BGA15 Ball
Designation
Symbol
Type
Signal Description
Management Data Clock.
P4
MDC
I, ST, ID
Clock for the MDIO serial data channel. Maximum
frequency is 20 MHz. Only MDC0 is used when 1x8 port
sectionalization is selected. In 2x4 port sectionalization
mode, MDC0 clocks ports 0-3 register accesses and MDC1
clocks ports 4-7 register accesses. Refer to Figure 21 on
page 140.
Network Interface Signal Description
P13, N13,
N14, P14,
K13, K14,
J14, J13,
F14, F13,
E13, E14,
B14, A14,
A13, B13
TPOP0, TPON0
TPOP1, TPON1
TPOP2, TPON2
TPOP3, TPON3
TPOP4, TPON4
TPOP5, TPON5
TPOP6, TPON6
TPOP7, TPON7
P12, N12,
M14, M13,
L13, L14,
H14, H13,
G14, G13,
D13, D14,
C14, C13,
A12, B12
TPIP0, TPIN0
TPIP1, TPIN1
TPIP2, TPIN2
TPIP3, TPIN3
TPIP4, TPIN4
TPIP5, TPIN5
TPIP6, TPIN6
TPIP7, TPIN7
Twisted-Pair Outputs2, Positive & Negative, Ports 0-7.
AO/AI
During 100BASE-TX or 10BASE-T operation, TPO pins
drive 802.3 compliant pulses onto the line.
Twisted-Pair Inputs3, Positive & Negative, Ports 0-7.
AI/AO
During 100BASE-TX or 10BASE-T operation, TPI pins
receive differential 100BASE-TX or 10BASE-T signals from
the line.
JTAG Test Signal Description
C12
TDI
I, ST, IP
C11
TDO
O, TS
B11
TMS
I, ST, IP
A11
TCK
I, ST, ID
A10
TRST
I, ST, IP
Test Data Input.
Test data sampled with respect to the rising edge of TCK.
Test Data Output.
Test data driven with respect to the falling edge of TCK.
Test Mode Select.
Test Clock.
Clock input for JTAG test.
Test Reset.
Reset input for JTAG test.
Miscellaneous Signal Description
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
111
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 39. Intel® LXT9785 BGA15 Signal Descriptions (Sheet 4 of 7)
BGA15 Ball
Designation
Symbol
Type
Signal Description
Tx Output Slew Controls 0 and 1 Defaults.
These pins are read at startup or reset. Their value at that
time is used to set the default state of Register bits
27.11:10 for all ports. These register bits can be read and
overwritten after startup / reset.
M11,
M12
TxSLEW_0
TxSLEW_1
These pins select the TX output slew rate for all ports (rise
and fall time) as follows:
I, ST, ID
TxSLEW_1
TxSLEW_0
Slew Rate (Rise and Fall
Time)
0
0
3.3 ns
0
1
3.6 ns
1
0
3.9 ns
1
1
4.2 ns
Reset.
C10
RESET
I, ST, IP
This active low input is ORed with the control register Reset
Register bit 0.15. When held Low, all outputs are forced to
inactive state.
Pin is not on JTAG chain.
Address <4:3>.
Sets base address to one of the following four possible
addresses:
• 00000
• 01000
• 10000
• 11000
N10,
P10
ADD_4
ADD_3
I, ST, ID
Each port adds its port number (starting with 0) to this
address to determine its PHY address.
Port 0 Address = Base
Port 1 Address = Base + 1
Port 2 Address = Base + 2
Port 3 Address = Base + 3
Port 4 Address = Base + 4
Port 5 Address = Base + 5
Port 6 Address = Base + 6
Port 7 Address = Base + 7
Mode Select[1:0].
00 = Reserved
E8
C9,
MODESEL_1
MODESEL_0
01 = SMII
I, ST, ID
10 = SS-SMII
11 = Reserved
All ports are configured the same. Interfaces cannot be
mixed and must be all SMII or SS-SMII.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
112
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 39. Intel® LXT9785 BGA15 Signal Descriptions (Sheet 5 of 7)
BGA15 Ball
Designation
Symbol
Type
Signal Description
Auto MDI/MDIX Enable Default.
K8
AMDIX_EN
I, ST, IP
This pin is read at startup or reset. Its value at that time is
used to set the default state of Register bit 27.9 for all ports.
These register bits can be read and overwritten after
startup / reset. Refer to Table 40 on page 119.
When active (High), automatic MDI crossover (MDIX)
(regardless of segmentation) is selected for all ports. When
inactive (Low) MDIX is selected according to the MDIX pin.
Global Port Configuration Defaults 1-3.
M10,
L9,
M9
CFG_1
CFG_2
CFG_3
I, ST, ID
These pins are read at startup or reset. Their value at that
time is used to set the default state of register bits shown in
Table 42, “Intel® LXT9785/9785E Global Hardware
Configuration Settings” on page 129 for all ports. These
register bits can be read and overwritten after startup /
reset.
When operating in Hardware Control Mode, these pins
provide configuration control options for all the ports (refer
to page 129 for details).
FIFO Select <1:0>.
These pins are read at startup or reset. Their value at that
time is used to set the default state of Register bits
18.15:14 for all ports. These register bits can be read and
overwritten after startup/reset.
C1,
F1
FIFOSEL1
FIFOSEL0
I, ID, ST
These pins are shared with RMII-RxER<5:4>. An external
pull-up resistor (see applications section for value) can be
used to set FIFO Select<1:0> to active while RxER<5:4>
are three-stated during hardware reset. If no pull-up is
used, the default FIFO select state is set via the internal
pull-down resistors.
See Table 36, “Intel® LXT9785/LXT9785E Receive FIFO
Depth Configurations” on page 97.
B3
LINKHOLD
I, ID, ST
LINKHOLD Default. This pin is read at startup or reset. Its
value at that time is used to set the default state of Register
bit 0.11 for all ports. This register bit can be read and
overwritten after startup / reset. When High, the LXT9785/
9785E powers down all ports.
This pin is shared with RMII-RxER6. An external pull-up
resistor (see applications section for value) can be used to
set LINKHOLD active while RxER6 is three-stated during
H/W reset. If no pull-up is used, the default LINKHOLD
state is set inactive via the internal pull-down resistor.
LED Signal Descriptions
Port 0 LED Drivers 1-2.
N9,
P9
LED0_1
LED0_2
OD, TS,
SL, IP
These pins drive LED indicators for Port 0. Each LED can
display one of several available status conditions as
selected by the LED Configuration Register (refer to
Table 96, “LED Configuration Register (Address 20, Hex
14)” on page 213 for details).
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
113
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 39. Intel® LXT9785 BGA15 Signal Descriptions (Sheet 6 of 7)
BGA15 Ball
Designation
Symbol
Type
Signal Description
Port 1 LED Drivers 1-2.
N8,
P8
LED1_1
LED1_2
OD, TS,
SL, IP
These pins drive LED indicators for Port 1. Each LED can
display one of several available status conditions as
selected by the LED Configuration Register (refer to
Table 96, “LED Configuration Register (Address 20, Hex
14)” on page 213 for details).
Port 2 LED Drivers 1-2.
P7,
N7,
LED2_1
LED2_2
OD, TS,
SL, IP
These pins drive LED indicators for Port 2. Each LED can
display one of several available status conditions as
selected by the LED Configuration Register (refer to
Table 96, “LED Configuration Register (Address 20, Hex
14)” on page 213 for details).
Port 3 LED Drivers 1-2.
P6,
N6
LED3_1
LED3_2
OD, TS,
SL, IP
These pins drive LED indicators for Port 3. Each LED can
display one of several available status conditions as
selected by the LED Configuration Register (refer to
Table 96, “LED Configuration Register (Address 20, Hex
14)” on page 213 for details).
Port 4 LED Drivers 1-2.
B9,
A9
LED4_1
LED4_2
OD, TS,
SL, IP
These pins drive LED indicators for Port 4. Each LED can
display one of several available status conditions as
selected by the LED Configuration Register (refer to
Table 96, “LED Configuration Register (Address 20, Hex
14)” on page 213 for details).
Port 5 LED Drivers 1-2.
B8,
A8
LED5_1
LED5_2
OD, TS,
SL, IP
These pins drive LED indicators for Port 5. Each LED can
display one of several available status conditions as
selected by the LED Configuration Register (refer to
Table 96, “LED Configuration Register (Address 20, Hex
14)” on page 213 for details).
Port 6 LED Drivers 1-2.
A7,
B7
LED6_1
LED6_2
OD, TS,
SL, IP
These pins drive LED indicators for Port 6. Each LED can
display one of several available status conditions as
selected by the LED Configuration Register (refer to
Table 96, “LED Configuration Register (Address 20, Hex
14)” on page 213 for details).
Port 7 LED Drivers 1-2.
B6,
A6
LED7_1
LED7_2
OD, TS,
SL, IP
These pins drive LED indicators for Port 7. Each LED can
display one of several available status conditions as
selected by the LED Configuration Register (refer to
Table 96, “LED Configuration Register (Address 20, Hex
14)” on page 213 for details).
Power Supply Signal Descriptions
D12, E12,
F12, G12,
H12, J12,
K12, L12,
AVCC
–
Analog Power Supply.
+2.5 V supply for analog circuits.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
114
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 39. Intel® LXT9785 BGA15 Signal Descriptions (Sheet 7 of 7)
BGA15 Ball
Designation
Symbol
Type
E11, F9, F10,
F11, G9, G10,
G11, H9, H10,
H11, J9, J10,
J11, K11, L11
AVSS
–
D7, L7
VCCD
–
Signal Description
Analog Ground.
Ground return for analog supply (AVCC). all grounds can
be tied together using a single ground plane.
Digital Power Supply - Core.
+2.5 V supply for core digital circuits.
Digital Power Supply - I/O Ring.
D4, F4, H4,
L3, L5,
VCCIO
–
A1, A2, A3,
B1, B2, B5,
B10, D9, D11,
E5, E6, E9,
E10, F5, F6,
F7, F8, G4,
G6, G7, G8,
H6, H7, H8,
J5, J6, J7, J8,
K5, K6, K9,
K10, L2, N1,
N11, P1, P11
GNDD
–
C8
SGND
–
+2.5/3.3 V supply for digital I/O circuits. The digital input
circuits running off of this rail, having a TTL-level threshold
and over-voltage protection, may be interfaced with 3.3/5.0
V, when the IO supply is 3.3 V, and 2.5/3.3/5.0 V when 2.5
V.
Digital Ground.
Ground return for core digital supplies (VCCD). All ground
pins can be tied together using a single ground plane.
Substrate Ground.
Ground for chip substrate. All ground pins can be tied
together using a single ground plane.
Unused/Reserved Balls
C4, C7, D1,
D2, D5, D6,
D8, D10, E4,
E7, G2, G5,
H1, H5, J4,
K4, K7, L1,
L6, L8, L10,
M4, M5, M6,
M7, M8, P2,
P3
N/C
–
No Connection.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
115
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.0
Functional Description
4.1
Introduction
The Intel® LXT9785/LXT9785E is an 8-port Fast Ethernet 10/100 PHY transceiver that supports
10 Mbps and 100 Mbps networks, complying with all applicable requirements of IEEE 802.3
standards. The device incorporates a Serial Media Independent Interface (SMII), Source
Synchronous-Serial Media Independent Interface (SS-SMII), and a Reduced Serial Independent
Interface (RMII) to enable each individual network port to interface with multiple 10/100 MACs.
Each port directly drives either a 100BASE-TX line or a 10BASE-T line. The LXT9785/9785E
also supports 100BASE-FX operation via an LVPECL interface. The device has a 241-ball BGA, a
208-pin QFP, or a 196-ball BGA package.
The 196-ball BGA package (BGA15) is a reduced feature-set product. The BGA15 package does
not support the following features:
•
•
•
•
•
RMII
Fiber
Sectionalization
Third LED port (only two LEDs per port)
Hardware control pins:
— PAUSE
— MDIX
— MDDIS
— PWRDWN
— Lower three PHY address (out of five PHY address bits)
• Extended temperature
Note:
4.1.1
Unless otherwise noted, all information in this document applies to the LXT9785 and LXT9785E.
OSP™ Architecture
The Intel LXT9785/LXT9785E incorporates high-efficiency Optimal Signal Processing™ design
techniques, combining the best properties of digital and analog signal processing to produce a truly
optimal device.
The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by
as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques
in the receive equalizer avoids the quantization noise and calculation truncation errors found in
traditional DSP-based receivers (typically complex DSP engines with A/D converters). The result
is improved receiver noise and cross-talk performance.
The OSP architecture also requires substantially less computational logic than traditional DSPbased designs. The result is lower power consumption and reduced logic switching noise generated
by DSP engines clocked at speeds up to 125 MHz. The logic switching noise can be a considerable
source of EMI when generated from the device’s power supplies.
116
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
The OSP-based LXT9785/LXT9785E provides improved data recovery, EMI performance and
power consumption.
4.1.2
Comprehensive Functionality
The LXT9785/LXT9785E performs all functions of the Physical Coding Sublayer (PCS) and
Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X
specification. This device also performs all functions of the Physical Media Dependent (PMD)
sublayer for 100BASE-TX connections.
On power-up, the LXT9785/LXT9785E reads its configuration inputs to check for forced operation
settings. If not configured for forced operation, each port uses auto-negotiation/parallel detection to
automatically determine line operating conditions. If the PHY device on the other side of the link
supports auto-negotiation, the LXT9785/LXT9785E auto-negotiates with it using Fast Link Pulse
(FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT9785/LXT9785E
automatically detects the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps
PHY) and set its operating conditions accordingly.
The LXT9785/LXT9785E provides half-duplex and full-duplex operation at 100 Mbps and 10
Mbps.
4.1.2.1
Sectionalization
The LXT9785/LXT9785E’s sectional design allows flexibility with large multiport MACs and
ASICs. With the use of the Section pin, the LXT9785/LXT9785E can be configured into a single 8port or two separate 4-port sections, each with its own MDIO (with separate MDC clock) and MII
data (with separate REFCLK/TxCLK/RxCLK clocks) interfaces. See Figure 16, “Intel®
LXT9785/LXT9785E Typical SMII Quad Sectionalization Diagram” on page 134, Figure 21,
“Intel® LXT9785/LXT9785E Typical SS-SMII Quad Sectionalization Diagram” on page 140, and
Figure 26, “Intel® LXT9785/LXT9785E Typical RMII Quad Sectionalization Diagram” on
page 144.
Note:
The BGA15 package does not support sectionalization.
4.2
Interface Descriptions
4.2.1
10/100 Network Interface
The LXT9785/LXT9785E supports 10 Mbps and 100 Mbps (10BASE-T and 100BASE-TX)
Ethernet over twisted-pair, or 100 Mbps (100BASE-FX) Ethernet over fiber media. Each network
interface port consists of four external pins (two differential signal pairs). The pins are shared
between twisted-pair (TP) and fiber. The LXT9785/LXT9785E pinout is designed to interface
seamlessly with dual-high stacked RJ-45 connectors. Refer to Table 11, “Intel® LXT9785/
LXT9785E Network Interface Signal Descriptions – PQFP” on page 42 for specific pin
assignments.
The LXT9785/LXT9785E output drivers generate either 100BASE-TX, 10BASE-T, or 100BASEFX output. When not transmitting data, the device generates IEEE 802.3-compliant link pulses or
idle code. Input signals are decoded either as a 100BASE-TX, 100BASE-FX, or 10BASE-T input,
depending on the mode selected. Auto-negotiation/parallel detection or manual control is used to
determine the speed of this interface.
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Revision Number: 007
Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 7. Intel® LXT9785/LXT9785E Interfaces
TXENn
TXDn_0
TXDn_1
Data
Interface
TXCLK
TPFOPn
TPFONn
RXCLK
RXDn_1
TPFIPn
RXDn_0
TPFINn
Network
Interface
RXERn
CRS_DVn
MDIO
Management
Interface
MDIOn
MDCn
MDINTn
MDDIS
Direct Drive
Port LEDs/
Controls
Addr &
MDIX/
Contr
LEDn_2
LEDn_2
LEDn_3
MDIX_Enb
Mode Select
ADD<4:0>
VCCIO
+3.3 V
OR
+2.5 V
VCCD
+2.5 V
GNDD
.01 uF
4.2.1.1
Twisted-Pair Interface
The LXT9785/LXT9785E supports either 100BASE-TX or 10BASE-T connections over 100 Ω,
Category 5, Unshielded Twisted-Pair (UTP). Only a transformer, RJ-45, and bypass capacitors are
required to complete this interface. Using Intel's patented waveshaping technology, the transmitter
shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings
(refer to Table 13, “Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP” on
page 43) allow the designer to match the output waveform to the magnetic characteristics. Both
transmit and receive terminations are built into the LXT9785/LXT9785E so no external
components are required between the LXT9785/LXT9785E and the external transformer. The
transmitter uses a transformer with a center tap to help reduce power consumption.
When operating at 100 Mbps, MLT3 symbols are continuously transmitted and received. When not
transmitting data, the LXT9785/LXT9785E generates “IDLE” symbols.
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During 10 Mbps operation, LXT9785/LXT9785E encoded data is exchanged. When no data are
being exchanged, the line is left in an idle state with NLPs transmitted to maintain link.
4.2.1.2
MDI Crossover (MDIX)
The LXT9785/LXT9785E crossover function, which is compliant to the IEEE 802.3, clause 23
standard, connects the transmit output of the device to the far-end receiver in a link segment. This
function can be disabled via Register bits 27.9:8 or by using the hardware configuration pins.
Table 40. Intel® LXT9785/LXT9785E MDIX Selection
Note:
4.2.1.3
AMDIX_EN
MDIX
MDIX Mode
0
0
MDI forced
0
1
MDIX forced
1
X
Auto MDI/MDIX
The BGA15 package does not support MDIX hardware configuration. Software must be used to
control the function after power-up.
Fiber Interface
The LXT9785/LXT9785E fiber ports are designed to interface with common industry-standard 3.3
V and 5 V fiber-optic transceivers. Each of the 8 ports incorporates a Low-Voltage PECL interface
that complies with the ANSI X3.166 standard for seamless integration.
Note:
The BGA15 package does not support the fiber interface.
Fiber mode is selected through Register bit 16.0 by the following two methods:
1. Configure Register bit 16.0 = 1 on a global basis (all 8 ports) by driving the Hardware Control
pin G_FX/TP to a logic High value on power-up and/or reset.
2. Configure Register bit 16.0 = 1 on a per-port basis through the MDIO interface.
The fiber interface is capable of full-duplex or half-duplex operation. In half duplex, operation
collisions must be managed by external Layer 2 logic (MAC). Auto negotiation is not supported for
fiber mode.
4.3
Media Independent Interface (MII) Interfaces
The LXT9785/LXT9785E supports Reduced MII or Serial MII, but not concurrently. The interface
mode selection pins configures the device for either RMII or SMII/SS-SMII on all eight ports.
Refer to Table 41 for the mode select settings.
Note:
4.3.1
The BGA15 package does not support the RMII interface.
Global MII Mode Select
The mode select pins are used for MII interface configuration settings upon power-up sequencing.
All ports are configured the same and cannot be intermixed.
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Revision Number: 007
Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 41. Intel® LXT9785/LXT9785E MII Mode Select
ModeSel1
ModeSel0
RMII1
0
0
SMII
0
1
SS-SMII
1
0
Reserved
1
1
1. Invalid for the BGA15 package.
4.3.2
Internal Loopback
Register bit 0.14 must be set to enable internal loopback operation. Register bits 16.14 and 0.8
must be set for 10 Mbps operation. Intel recommends that auto-negotiation be disabled while
internal loopback is enabled. The normal auto-negotiation process code word exchange cannot be
completed.The following two-step sequence is recommended for the most efficient mode change
when enabling forced 100 Mbps internal loopback mode directly from auto-negotiation mode:
1. Write Register 0 with 0x2100h (forced 100 Mbps), and
2. Write Register 0 with 0x6100h (enable internal loopback with forced 100 Mbps)
This two-step process ensures the 100 Mbps link comes up quickly. If the one-write process of
writing 0x6100h is followed, it may take up to 1.5 seconds before link is established and data is
received on the port. The 1.5 second delay is due to the IEEE auto-negotiation Break Link Timer
(BLT) requirement. The timer must expire before link is established when changing modes directly
from auto-negotiation to internal loopback forced 100 Mbps mode. Use the above two-step process
to eliminate the auto-negotiation BLT timer requirement.
Figure 8. Intel® LXT9785/LXT9785E Internal Loopback
LXT9785/9785E
RMII/
SMII/
SSSMII
inter
face
4.3.3
Fx
Driver
Digital
Block
Loopback
Analog
Block
Tx
Driver
RMII Data Interface
The LXT9785/LXT9785E provides a separate RMII for each network port, each complying with
the RMII Specification, Revision 1.2. The RMII includes both a data interface and an MDIO
management interface. The RMII Data Interface exchanges data between the LXT9785/LXT9785E
and up to eight Media Access Controllers (MACs).
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4.3.4
Serial Media Independent Interface (SMII) and Source SynchronousSerial Media Independent Interface (SS-SMII)
4.3.4.1
SMII Interface
The LXT9785/LXT9785E provides an independent serial interface for each network port,
complying with the Serial-MII Specification, Revision 1.2. All SMII ports use a common reference
clock and SYNC signal. The SMII Data Interface exchanges data between the LXT9785/
LXT9785E and multiple Media Access Controllers (MACs). All signals are synchronous to the
reference clock. One SYNC control stream is sourced by the MAC to the PHY. Both the transmit
and receive data streams are segmented into boundaries delimited by the SYNC pulses. This
interface is expected to drive up to 6 inches of trace lengths.
4.3.4.2
Source Synchronous-Serial Media Independent Interface
The new revision to the SMII interface, SS-SMII, allows for a longer trace length and helps to
relieve timing constraints, requiring the addition of four new signals, TxCLK, TxSYNC, RxCLK,
and RxSYNC. The transmit TxCLK and TxSYNC are sourced from the MAC to the PHY and
referenced to the REFCLK input. The receive RxCLK and RxSYNC are sourced by the PHY to the
MAC and in reference to the REFCLK.
4.3.5
Configuration Management Interface
The LXT9785/LXT9785E provides an MDIO Management Interface and a Hardware Control
Interface (via the CFG pins) for device configuration and management. Mode control selection is
provided via the MDDIS pin as shown in Table 9, “Intel® LXT9785/LXT9785E MDIO Control
Interface Signals – PQFP” on page 41. When sectionalization (2x4) is selected, separate MDIO
interfaces are enabled (see Figure 13 on page 127).
4.3.6
MII Isolate
In applications where the MII must be isolated from the bus, the RMII and the SMII/SS-SMII
configurations can be three-stated using Register 0.10. On each individual port, Register bit 0.10
controls the isolation of the transmit and receive data signals for that port. Register bit 0.10 on ports
0 and 4 isolate the RxCLKn/TxCLKn and SYNC signals.
When 1x8 sectionalization is selected, TxCLK0, TxSYNC0, RxCLK1, and RxSYNC1 are used for
the clocking and synchronization interface. Port 4 controls the isolation of RxCLK0, RxCLK1,
RxSYNC0, and RxSYNC1, and must be used to isolate the receive clock and synchronization
interface.
When 2x4 sectionalization is selected, TxCLK0, TxSNC0, RxCLK0, and TxCLK0 are used for
Port 0 through Port 3 and TxCLK1, TxSYNC1, RxCLK1, and RxSYNC1 are used for Port 4
through Port 7. Port 0 must be isolated to isolate the receive clock and synchronization interface for
Port 0 through Port 3. Port 4 must be isolated to isolate Port 4 through Port 7.
4.3.7
MDIO Management Interface
The LXT9785/LXT9785E supports the IEEE 802.3 MII Management Interface, also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to
monitor and control the state of the LXT9785/LXT9785E. The MDIO interface consists of a
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
physical connection, a specific protocol that runs across the connection, and an internal set of
addressable registers. Some registers are required and their functions are defined by the IEEE
802.3 specification. Additional registers allow for expanded functionality. Specific bits in the
registers are referenced using an “X.Y” notation, where X is the register number (0-32) and Y is
the bit number (0-15).
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this
interface is controlled by the MDDIS input pin. When MDDIS is High, all the MDIOs are
completely disabled. The Hardware Control Interface provides primary configuration control.
When MDDIS is Low, the MDIO port is enabled for both read and write operations and the
Hardware Control Interface is not used.
Note:
The BGA15 package does not support the MDDIS pin.
The timing for the MDIO Interface is shown in Table 79, “Intel® LXT9785/LXT9785E MDIO
Timing Parameters” on page 197. MDIO read and write cycles are shown in Figure 9, “Intel®
LXT9785/LXT9785E Management Interface Read Frame Structure” on page 122 and Figure 10,
“Intel® LXT9785/LXT9785E Management Interface Write Frame Structure” on page 122.
Figure 9. Intel® LXT9785/LXT9785E Management Interface Read Frame Structure
MDC
MDIO
(Read)
High Z
32 "1"s
0
Preamble
1
ST
1
0
A4
Op Code
A3
A0
R4
R3
R0
Z
D15 D15D14 D14 D1
0
Turn
Around
Register Address
PHY Address
D1 D0
Data
Write
Idle
Read
Figure 10. Intel® LXT9785/LXT9785E Management Interface Write Frame Structure
MDC
MDIO
(Write)
32 "1"s
Idle
Preamble
0
1
ST
0
1
Op Code
A4
A3
A0
R4
R3
Register Address
PHY Address
R0
1
0
Turn
Around
D15
D14
D1
Data
D0
Idle
Write
The protocol allows one controller to communicate with multiple LXT9785/LXT9785E chips. Pins
ADD_<4:0> determine the base address. Each port adds its port number to the base address to
obtain its port address as shown in Figure 11.
The BGA15 package uses a similar scheme where the ADD_[2:0] bits internally set to 0 and the
ADD_[4:3] bits are used to select from four base addresses (0x00000b, 0x01000b, 0x10000b, or
0x11000b.
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Figure 11. Intel® LXT9785/LXT9785E Port Address Scheme
BASE ADD_<4:0>
(example ADD_<4:0> = 4)
LXT9785
LXT9785/9785E
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
4.3.8
PHY ADD_<4:0> (BASE+0)
ex. 4
PHY ADD_<4:0> (BASE+1)
ex. 5
PHY ADD_<4:0> (BASE+2)
ex. 6
PHY ADD_<4:0> (BASE+3)
ex. 7
PHY ADD_<4:0> (BASE+4)
ex. 8
PHY ADD_<4:0> (BASE+5)
ex. 9
PHY ADD_<4:0> (BASE+6)
ex. 10
PHY ADD_<4:0> (BASE+7)
ex. 11
MII Sectionalization
When sectionalized into two quad sections, the MDIO bus splits into two separate PHY access
ports. Ports 0-3 of the MDIO section operate independently of ports 4-7. The MII isolate function
is unaffected and operates normally. Sectionalization is selected by pulling pin 176 (Section) High
on the initial power-up sequence (refer to Figure 13). In applications that need sectionalization,
such as 1x8 and 2x4 and have a single MDIO bus structure, it is necessary that the addressing
scheme be contiguous. For example, the first eight ports are addressed 0-7, so the next four ports
must be addressed 8-11.
Note:
4.3.9
The BGA15 package does not support the MII sectionalization feature.
MII Interrupts
The LXT9785/LXT9785E provides a single per-section interrupt pin that is available to all ports.
Interrupt logic is shown in Figure 12. The LXT9785/LXT9785E also provides two dedicated
interrupt registers for each port. Register 18 provides interrupt enable and mask functions and
Register 19 provides interrupt status. Setting Register bit 18.1 = 1 enables a port to request
interrupt via the MDINT pin. An active Low on this pin indicates a status change on the device.
Because it is a shared interrupt, there is no indication which port is requesting interrupt service (see
Figure 12).
There are five conditions that may cause an interrupt:
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
•
•
•
•
•
Auto-negotiation complete.
Speed status change.
Duplex status change.
Link status change.
Isolate status change.
Figure 12. Intel® LXT9785/LXT9785E Interrupt Logic
Event X Enable Reg
AND
Event X Status Reg
..
.
OR
AND
Per Event
Force Interrupt
Interrupt Enable
...
Port
Combine
Logic
Interrupt Pin
Per port
Interrupt (Event) Status Register is cleared on read.
X = Any Interrupt capabi lity
4.3.10
Global Hardware Control Interface
The LXT9785/LXT9785E provides a Hardware Control Interface for applications where the
MDIO is not desired. Refer to “Initialization” on page 126 for additional details.
4.3.11
FIFO Initial Fill Values
The FIFO initial fill value sets the number of bits required to be written into the FIFO before the
process of reading the packet out of the FIFO is started. The read operation is aligned on nibble
boundaries because the FIFO is one nibble wide. The read clock on the RMII and SMII interfaces
may occur any time within the next available nibble. Therefore, the effective size of the FIFO is
one nibble less than the selected size.
Large initial fill FIFO settings alter both the data-path latency and the InterFrame Gap (IFG) output
on the RMII and SMII interfaces. The latency values are increased or decreased depending on the
number of bits the FIFO size is increased or decreased. The IFG may decrease up to twice the size
of the initial fill FIFO setting. When the following three conditions are met, the IPG on the RMII
and SMII interfaces may become nonexistent between packets, effectively concatenating the
packets into one long corrupted packet:
• The frequency difference between the link partner and the local LXT9895 device exceed
200 ppm (the IEEE standard requirement).
• Jumbo packets (8192 byte packets or longer) are used.
• Packets on the wire occur with minimum Inter-Packet Gap (IPG) of 96 bit times.
The concatenation of the packets is flagged by the MAC as a CRC error and possibly an oversized
packet depending upon the length indication capabilities of the MAC. The possibility of packet
concatenation can be minimized on the RMII interface by setting the initial fill FIFO Register bits
18.15:14 to 01. The FIFO setting bits should be set to 10 for the SMII interfaces.
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4.4
Operating Requirements
4.4.1
Power Requirements
The LXT9785/LXT9785E requires four power supply inputs: VCCD, VCCA, VCCPECL and
VCCIO. The digital and analog circuits require 2.5 V supplies (VCCD, VCCR, and VCCT). These
inputs may be supplied from a single source although decoupling is required to each respective
ground. The fiber VCCPECL supply can be connected to either 2.5 V or 3.3 V.
A separate power supply may be used for the MII, JTAG and MDIO (VCCIO) interfaces. The
power supply may be either +2.5 V or +3.3 V. VCCIO should be supplied from the same power
source used to supply the controller on the other side of the interface. Refer to Table 53, “Intel®
LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 2.5 V +/- 5%)” on
page 174, Table 54, “Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics
(VCCIO = 3.3 V +/- 5%)” on page 175, and Table 55, “Intel® LXT9785/LXT9785E Digital I/O
DC Electrical Characteristics – SD Pins” on page 175 for I/O characteristics.
As a matter of good practice, these supplies should be as clean as possible. Typical filtering and
decoupling are shown in Figure 34 on page 168. The power supplies should be brought up as close
to the same time as possible. However, there are no specific timing requirements.
4.4.2
Clock/SYNC Requirements
4.4.2.1
Reference Clock
The LXT9785/LXT9785E requires a constant enabled reference clock (REFCLK). REFCLK’s
frequency must be 50 MHz for RMII or 125 MHz for SMII/SS-SMII. The reference clock is used
to generate transmit signals and recover receive signals. A crystal-based clock is recommended
over a derived clock (that is, PLL-based) to minimize transmit jitter. Refer to Table 56, “Intel®
LXT9785/LXT9785E Required Clock Characteristics” on page 175 for clock timing requirements.
For applications that use a single 8-port sectionalization, REFCLK0 and REFCLK1 must always
be tied together and to the source. In 2x4 applications, REFCLK0 and REFCLK1 are not tied
together.
4.4.2.2
TxCLK Signal (SS-SMII only)
The LXT9785/LXT9785E requires a 125 MHz input transmit clock synchronous with TxDatan
and frequency locked to REFCLK. See Figure 22 on page 141.
4.4.2.3
TxSYNC Signal (SMII/SS-SMII)
The LXT9785/LXT9785E requires a 12.5 MHz input pulse for SMII synchronization. See
Figure 22 on page 141.
4.4.2.4
RxSYNC Signal (SS-SMII only)
The LXT9785/LXT9785E provides a 12.5 MHz output pulse synchronous with the RxDatan
outputs. See Figure 23 on page 141.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.4.2.5
RxCLK Signal (SS-SMII only)
In SS-SMII mode, the LXT9785/LXT9785E provides a 125 MHz clock output in reference to the
output RxDatan. RxCLK is referenced and synchronized to the REFCLK. See Figure 23 on page
141.
4.5
Initialization
When the LXT9785/LXT9785E is first powered on, reset, or encounters a link failure state, it
checks the MDIO register configuration bits to determine the line speed and operating conditions
to use for the network link. The configuration bits may be set by the Hardware Control or MDIO
interface as shown in Figure 13 on page 127.
4.5.1
MDIO Control Mode
In the MDIO Control mode, the LXT9785/LXT9785E reads the Hardware Control Interface pins to
set the initial (default) values of the MDIO registers. Once the initial values are set, bit control
reverts to the MDIO interface.
4.5.2
Hardware Control Mode
In the Hardware Control Mode, the LXT9785/LXT9785E disables direct write operations to the
MDIO registers via the MDIO Interface. On power-up or hardware reset, the LXT9785/LXT9785E
reads the Hardware Control Interface pins and sets the MDIO registers accordingly.
The following modes are available using either Hardware Control or MDIO Control:
• Force network link to 100BASE-FX (Fiber).
• Force network link operation to:
— 100BASE-TX, Full-Duplex
— 100BASE-TX, Half-Duplex
— 10BASE-T, Full-Duplex
— 10BASE-T, Half-Duplex
•
•
•
•
Allow auto-negotiation/parallel-detection.
Auto/Manual MDIX enable/disable.
Pause for full-duplex links operation.
Global Output Slew Rate Control.
When the network link is forced to a specific configuration, the LXT9785/LXT9785E immediately
begins operating the network interface as commanded. When auto-negotiation is enabled, the
LXT9785/LXT9785E begins the auto-negotiation/ parallel-detection operation.
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Figure 13. Intel® LXT9785/LXT9785E Initialization Sequence
Power-up or Reset
Read H/W Control
Interface
Initialize MDIO Registers
MDIO Control
Mode
Low
MDDIS Voltage
Level?
Hardware Control
Mode
High
Pass Control to MDIO
Interface
Disable MDIO Writes
Software
Reset?
Hardware
Reset?
Yes
Yes
Reset MDIO Registers to
values read at H/W
Control Interface at last
Hardware Reset
4.5.3
Power-Down Mode
The LXT9785/LXT9785E incorporates numerous features to maintain the lowest power possible.
The device can be put into a low-power state via Register 0 as well as a near-zero power state with
the power down pin. When in power-down mode, the device is not capable of receiving or
transmitting packets.
The lowest power operation is achieved using the Global power-down pin, which is active High.
This pin powers down every circuit in the device, including all clocks. All registers are unaltered
and maintained when the Global PWRDWN pin is released.
Note:
The BGA15 package does not support the PWRDWN pin feature.
Individual ports (software power down) can be powered down using Register bit 0.11. This bit
powers down a significant portion of the port, but clocks to the register section remain active. This
allows the management interface to remain active during register power-down. The power-down
bit is active High.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Note:
4.5.3.1
Intel recommends that a minimum recovery time be allowed after bringing up a port from software
or hardware power-down or link hold-off modes. The recovery times are specified in Table 80,
“Intel® LXT9785/LXT9785E Power-Up Timing Parameters” on page 198
Global (Hardware) Power Down
The global power-down mode is controlled by the PWRDWN pin. When PWRDWN is High, the
following conditions are true:
•
•
•
•
•
4.5.3.2
All LXT9785/LXT9785E ports and the clock are shut down.
All outputs are three-stated.
All weak pad pull-up and pull-down resistors are disabled.
The MDIO registers are not accessible.
Configuration pins are read upon release of the PWRDWN pin, and registers are loaded with
the current values of the hardware configuration pins.
Port (Software) Power Down
Individual port power-down control is provided by Register bit 0.11 in the respective port Control
Registers (refer to Table 83, “Control Register (Address 0)” on page 200). During individual port
power-down, the following conditions are true:
•
•
•
•
4.5.4
The individual port is shut down.
The MDIO registers remain accessible.
Pull-up and pull-down resisters are not affected and the outputs are not three-stated.
The register remains unchanged.
Reset
The LXT9785/LXT9785E provides both hardware and software resets. Configuration control of
Auto-Negotiation, speed, and duplex mode selection is handled differently for each. During a
hardware reset, settings for bits 0.13, 0.12, 0.8, and 4.8:5 are read in from the pins (refer to
Table 42, “Intel® LXT9785/9785E Global Hardware Configuration Settings” on page 129 for pin
settings, and Table 83, “Control Register (Address 0)” on page 200 and Table 87, “AutoNegotiation Advertisement Register (Address 4)” on page 204 for register bit definitions).
During a software reset (Register bit 0.15 = 1), the bit settings are not re-read from the pins and
revert back to the values that were read in during the last hardware reset. Any changes to pin values
from the last hardware reset are not detected during a software reset.
During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset.
All MII interface pins are disabled during a hardware reset and released to the bus on de-assertion
of reset.
During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be
polled to see when the part has completed reset (0.15 = 0). Pull up and pull down resisters are not
affected.
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Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Intel recommends that a minimum recovery time be allowed after bringing up a port from software
or hardware reset. The recovery times are specified in Table 80, “Intel® LXT9785/LXT9785E
Power-Up Timing Parameters” on page 198
4.5.5
Hardware Configuration Settings
The LXT9785/LXT9785E provides a hardware option to set the initial device configuration. The
hardware option uses three Global CFG pins that provide control for all ports (see Table 42).
Table 42. Intel® LXT9785/9785E Global Hardware Configuration Settings
CFG
Pin Settings1
Desired Mode
AutoNeg
Speed
10
Disabled
100
100
Enabled
10/100
Resulting Register Bit Values
Duplex
1
2
3
Half
Low
Low
Low
Full
Low
Low
High
Half
Low
High
Low
Full
Low
High
High
Half
High
Low
Low
Full/Half
High
Low
High
Half
High
High
Low
Full/Half
High
High
High
0.12
0.13
0
0
1
1
0.8
4.8
4.7
4.6
4.5
0
1
N/A
0
Auto-Negotiation
Advertisement
1
1
0
0
1
1
0
1
1
1
0
0
1
0
1
0
0
1
0
1
1
1
1
1. Refer to Table 5, “Intel® LXT9785/LXT9785E RMII Signal Descriptions – PQFP” on page 36 through
Table 17, “Intel® LXT9785/LXT9785E Receive FIFO Depth Considerations” on page 50 Table 24, “Intel®
LXT9785/LXT9785E RMII Signal Descriptions – BGA23” on page 82 through Table 36, “Intel® LXT9785/
LXT9785E Receive FIFO Depth Configurations” on page 97, and Table 39, “Intel® LXT9785 BGA15 Signal
Descriptions” on page 109 for CFG pin assignments.
4.6
Link Establishment
4.6.1
Auto-Negotiation
The LXT9785/LXT9785E attempts to auto-negotiate with its link partner by sending Fast Link
Pulse (FLP) bursts. Each burst consists of 33 link pulses spaced 62.5 µs apart. Odd link pulses
(clock pulses) are always present. Even link pulses (data pulses) may also be present or absent to
indicate a “1” or a “0”. Each FLP burst exchanges 16 bits of data, referred to as a “page”. All
devices that support auto-negotiation must implement the “Base Page”, defined by IEEE 802.3
(registers 4 and 5). The LXT9785/LXT9785E also supports the optional “Next Page” function
(registers 7 and 8).
4.6.1.1
Base Page Exchange
By exchanging Base Pages, the LXT9785/LXT9785E and its link partner communicate their
capabilities to each other. Both sides must receive at least three identical base pages for negotiation
to proceed. Each side finds their highest common capabilities, exchange more pages, and agree on
the operating state of the line.
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129
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.6.1.2
Manual Next Page Exchange
Additional information, exceeding that required by base page exchange, is also sent via “Next
Pages.” The LXT9785/LXT9785E fully supports the IEEE 802.3 method of negotiation via Next
Page exchange. The Next Page exchange uses Register 7 to send information and Register 8 to
receive it. Next Page exchange occurs only if both ends of the link partners advertise their ability to
exchange Next Pages. A special mode has been added to make manual next page exchange easier
for software. When Register 6 “page” is received, it stays set until read. This bit is cleared when a
new negotiation occurs, preventing the user from reading an old value in Register 6 and assuming
there is valid information in Registers 5 and 8. The page received bit is cleared upon reading the
“Auto-Negotiation Expansion Register (Address 6)” on page 206.
4.6.1.3
Controlling Auto-Negotiation
The following steps are recommended when auto-negotiation is controlled by software:
• After power-up, power-down, or reset, the power-down recovery time, as specified in
Table 80, “Intel® LXT9785/LXT9785E Power-Up Timing Parameters” on page 198, must be
exhausted before proceeding.
• Set the auto-negotiation advertisement register bits in Register 4 as desired.
• Enable auto-negotiation (set MDIO Register bit 0.12 = 1).
• Enable or restart auto-negotiation as soon as possible after writing to Register 4 to ensure
proper operation.
4.6.1.4
Link Criteria
In 100 Mbps mode, link is established when the descrambler becomes locked and remains locked
for approximately 50 ms. Link remains up unless the descrambler receives less than 12 consecutive
idle symbols in any 2 ms period. This provides a robust operation, filtering out any small noise hits
that may disrupt the link.
MLT-3 idle waveforms, for short periods, meet all the criteria for 10BASE-T start delimiters. A
working 10BASE-T receive may temporarily indicate link to 100BASE-TX waveforms. However,
the PHY will not bring up a permanent 10 Mbps link.
According to the IEEE standard 10 Mbps link state machine, the last condition that must be met
before 10 Mbps link can come up is a period of transmit and receive idle time. TXEN and RXDV
are inactive at the same time. This ensures that link is not brought up in the middle of transmitting
or receiving a packet. To ensure link establishment, Intel recommends no packet transmission into
the MII interface until link is established.
The IEEE Standard references this requirement in Section 14.2.3 State Diagrams, Figure 14-6-Link
Integrity Test Function State Diagram and in Section 28.3.4 State Diagrams, Figure 28-17-NLP
Receive Link Integrity Test State Diagram. These diagrams illustrate that while the PHY is in the
Link Test Fail Extend state, the last state before Link Pass state) Packet receive activity (RD) and
Transmit Activity (DO) must be idle (RD = idle * D0 = idle) for link to establish.
130
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.6.1.5
Parallel Detection
In parallel with auto-negotiation, the LXT9785/LXT9785E also monitors for 10 Mbps Normal
Link Pulses (NLP) or 100 Mbps Idle symbols. If either symbol is detected, the device
automatically reverts to the corresponding operating speed in half-duplex mode. Parallel detection
allows the LXT9785/LXT9785E to communicate with devices that do not support autonegotiation.
When parallel detection resolves a link, the link must be established in half-duplex mode.
According to IEEE standards, the forced link partner cannot be configured to full-duplex. If the
auto-negotiation link partner does not advertise half-duplex capability at the speed of the forced
link partner, link is not established. The IEEE Standard prevents forced full-duplex-to-half-duplex
link connections.
Figure 14. Intel® LXT9785/LXT9785E Auto-Negotiation Operation
Power-Up, Reset,
Link Failure
Start
Disable
Auto-Negotiation
Go To Forced
Settings
Done
4.6.1.6
0.12 = 0
0.12 = 1
Check Value
0.12
Attempt AutoNegotiation
YES
Enable
Auto-Neg/Parallel Detection
Listen for 100TX
Idle Symbols
Link Set?
Listen for 10T
Link Pulses
NO
Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced
Speed Mode
With auto MDI/MDIX hardware enabled, end users experience reliable link establishment under all
settings of auto MDI/MDIX and speed between the LXT9785/LXT9785E and its link partners. As
stated in the IEEE clauses 40.4.5.1 (Auto MDI/MDIX) and 28.3.2 (Parallel Detect), when ports are
forced to 10 Mbps or 100 Mbps and auto MDI/MDIX is enabled, and the port is connected to a
partner with auto-negotiation enabled, an undefined condition exists between the IEEE auto MDIX
and Parallel Detect specifications. Link may not occur according to the IEEE specification.
During this undefined condition, when the LXT9785/LXT9785E is set to 10 Mbps or 100 Mbps
and auto MDI/MDIX is enabled, the LXT9785/LXT9785E and the link partner auto-negotiation
processes are expected to be skewed enough to establish link in all but the rarest cases. Auto MDI/
MDIX is configured through hardware and software. If auto MDI/MDIX operation is desired in
forced modes, disabling auto MDI/MDIX using the software programming can aid link
establishment.
Datasheet
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Revision Number: 007
Revision Date: August 28, 2003
131
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.7
Serial MII Operation
The LXT9785/LXT9785E exchanges transmit and receive data with the controller via the Serial
MII (SMII). The SMII performs the following functions:
•
•
•
•
Conveys complete MII information between a 10/100 PHY and MAC with two pins per port.
Allows a multi-port MAC/PHY communication with one system clock.
Operates in both half and full-duplex.
Supports per-packet switching between 10 Mbps and 100 Mbps data rates.
The Serial MII operates at 125 MHz using a global reference clock and frame synchronization
signal (REFCLK and SYNC). Each port has an individual two-line data interface (TxDatan and
RxDatan). All signals are synchronous to REFCLK. Table 43 summarizes the SMII signals.
Data is exchanged in 10-bit serial words. Each word contains one data byte (two nibbles of 4B
coded data) and two status bits. When the port is operating at 100 Mbps, each word contains a new
data byte. When the port is operating at 10 Mbps, each data byte is repeated 10 times.
Table 43. Intel® LXT9785/LXT9785E SMII Signal Summary
Signal
To
From
MAC
Purpose
TxData
PHY
Transmit data & control
SYNC
PHY
MAC
Synchronization
RxData
MAC
PHY
Receive data & control
REFCLK
MAC &
PHY
System
Synchronization
1. Refer to Table 7, “Intel® LXT9785/LXT9785E SMII Specific
Signal Descriptions – PQFP” on page 39 for detailed signal
descriptions.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 15. Intel® LXT9785/LXT9785E Typical SMII Interface Diagram
Typical SMII Interface
in a 16-Port System
SECTION
TxDatan
RxDatan
MDIO0
MDC0
MDINT0
RefCLK0
125 MHz Sourced
Externally or from
Switch ASIC
Magnetics/Fiber Transceiver
SYNC0
8
LXT9785/9785E 8-Port Phy
8-Port Media
Access Controller
( MAC)
8
RefCLK1
SYSTEM CLK
8
RxDatan
MDIO0
MDC0
MDINT0
Magnetics/Fiber Transceiver
TxDatan
SYNC0
LXT9785/9785E 8-Port Phy
8-Port Media
Access Controller
(MAC)
RefCLK0 RefCLK1
8
SECTION
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133
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 16. Intel® LXT9785/LXT9785E Typical SMII Quad Sectionalization Diagram
Typical SMII Interface in a
24-Port System
RefClk1
RefClk0
8
SYNC0
8
12-Port Media
Access Controller
( MAC)
RxDatan
MDIO0
MDC0
MDINT0
4
SECTION
TxDatan
SYNC0
RxDatan
MDIO0
MDC0
MDINT0
RefClk0
125 MHz Sourced
Externally or from
Switch ASIC
RefClk1
TxDatan
4
SYNC1
4
RxDatan
VCC
SECTION
8
TxData n
SYNC0
8
RxData n
Magnetics/Fiber Transceiver
MDINT0
MDIO0
MDC0
LXT9785/9785E 8-Port Phy
12-Port Media
Access Controller
( MAC)
MDINT1
MDIO1
MDC1
Magnetics/Fiber Transceiver
LXT9785/9785E
4-Port (sec)
4-Port (sec)
4
Magnetics/Fiber Transceiver
LXT9785/9785E 8-Port Phy
TxDatan
SECTION
RefClk0 RefClk1
134
Datasheet
Document Number: 249241
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 17. Intel® LXT9785/LXT9785E 100 Mbps Serial MII Data Flow
Serial Data Stream
To/From
S0 S1 D0 D1 D2
MAC
Strip
TX_EN &
TX_ER
Status
Bits
2 Nibbles Tx/Rx Data
2 Symbols Tx/Rx Data
D0 D1 D2 D3
S0
S1
S2
S3
S4
S0
S1
S2
S3
S4
4B/5B
D3 D4 D5 D6 D7
4.7.1
Insert
CRS &
RX_DV
Status
Bits
D0 D1 D2 D3
To/From
PMD
Sublayer
SMII Reference Clock
The REFCLK operates at 125 MHz. The transmit and receive data and control streams must always
be synchronized to the REFCLK by the MAC and PHY. The LXT9785/LXT9785E samples these
signals on the rising edge of the REFCLK.
4.7.2
TxSYNC Pulse (SMII/SS-SMII)
The TxSYNC pulse delimits segment boundaries and synchronizes with REFCLK. The MAC must
continuously generate a TxSYNC pulse once every 10 REFCLK cycles. The TxSYNC pulse
signals the start of each new segment (see Figure 21 on page 140).
4.7.3
Transmit Data Stream
Transmit data and control information are signaled in ten- bit segments. In 100 Mbps mode, each
segment contains a new byte of data. In 10 Mbps mode, the MAC must repeat a 10M serial word
ten times on TxData. The LXT9785/LXT9785E may sample that serial word at any point.
The TxSYNC pulse signals the start of a new segment as shown in Figure 18.
4.7.3.1
Transmit Enable
The MAC must assert the TxEN bit in each segment of TxData, and de-assert TxENn after the last
segment of the packet.
4.7.3.2
Transmit Error
When the MAC asserts the TxER bit in 100BASE-X mode, the LXT9785/LXT9785E drives “H”
symbols onto the network interface. TxER does not have any function in 10M operation.
Datasheet
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Revision Date: August 28, 2003
135
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 18. Intel® LXT9785/LXT9785E Serial MII Transmit Synchronization
CLOCK
TxSYNC
TX
4.7.4
TxER
TxEN
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7 TxER
Receive Data Stream
Receive data and control information are signalled in ten-bit segments. In 100 Mbps mode, each
segment contains a new byte of data. In 10 Mbps mode, each segment is repeated ten times (except
for the CRS bit), and the MAC can sample any of the ten segments.
4.7.4.1
Carrier Sense
The CRS bit (slot 0) is generated when a packet is received from the network interface. The CRS
bit is set in real time, even in 10 Mbps mode (all other bits are repeated in 10 sequential segments).
4.7.4.2
Receive Data Valid
The LXT9785/LXT9785E asserts the RX_DV bit (slot 1) when it receives a valid packet. The
assertion timing changes depending on line operating speed:
• For 100BASE-TX and 100BASE-FX links, the RX_DV bit is asserted from the first nibble of
preamble to the last nibble of the data packet.
• For 10BASE-T links, the entire preamble is truncated. The RX_DV bit is asserted with the
first nibble of the Start-of-Frame Delimiter (SFD) “5D” and remains asserted until the end of
the packet.
4.7.4.3
Receive Error
When the LXT9785/LXT9785E receives an invalid symbol from the network in 100BASE-TX
mode, it drives “0101” on the associated RxData signals.
4.7.4.4
Receive Status Encoding
The LXT9785/LXT9785E encodes status information onto the RxData line during IPG as seen in
Table 44 on page 137. Status bit RxData<5> indicates the validity of the upper nibble
(RxData<7:4> of the last byte of the previous frame). RxData and RX_DV are passed through the
internal elasticity FIFO to smooth any clock rate differences between the recovered clock and the
125 MHz reference clock.
4.7.5
Collision
The SMII interface does not provide a collision output and relies on the MAC to interpret COL
conditions using CRS and TxEN. CRS is unaffected by the transmit path.
136
Datasheet
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 19. Intel® LXT9785/LXT9785E Serial MII Receive Synchronization
CLOCK
RxSYNC
RX
CRS
RXD0
RX_DV RXER
RXD1
Speed
RXD2
Duplex
RXD3
Link
RXD4
J abber
RXD5
Valid
RXD6
FCE
RXD7
RXD7
CRS
Table 44. Intel® LXT9785/LXT9785E RX Status Encoding Bit Definitions
Signal
Definition
CRS
Carrier Sense - identical to MII, except that it is not an asynchronous signal.
RxDV
Receive Data Valid - identical to MII. When RX_DV = 0, status
information is transmitted to the MAC. When RX_DV = 1,
received data is transmitted to the MAC.
0 = Status Byte
1 = Valid Data Byte
RxER
(RxData0)
Inter-frame status bit RxData0 indicates whether or not the
PHY detected an error somewhere in the previous frame.
0 = No Error
1 = Error
SPEED
(RxData1)
Inter-frame status bit RxData1 indicates port operating speed.
0 = 10 Mbps
1 = 100 Mbps
DUPLEX
(RxData2)
Inter-frame status bit RxData2 indicates port duplex condition.
0 = Half-duplex
1 = Full-duplex
LINK
(RxData3)
Inter-frame status bit RxData3 indicates port link status.
0 = Down
1 = Up
JABBER
(RxData4)
Inter-frame status bit RxData4 indicates port jabber status.
0 = OK
1 = Error
VALID
(RxData5)
Inter-frame status bit RxData5 conveys the validity of the upper
nibble of the last byte of the previous frame
0 = Invalid
1 = Valid
False Carrier
(RxData6)
Inter-frame status bit RxData6 indicates whether or not the
PHY has detected a false carrier event.
0 = No FC detected
1 = FC detected
RxData7
This bit is set to 1.
1 = Always
1. Both RxData0 and RxData5 bits are valid in the segment immediately following a frame, and remain valid
until the first data segment of the next frame begins.
4.7.6
Source Synchronous-Serial Media Independent Interface
Some system designs require the PHY to be placed between 3 to 12 inches away from the MAC. A
new Source Synchronous-Serial Media Independent Interface (SS-SMII) definition has been added
because of this requirement. To provide a source synchronous interface between the PHY and
MAC, the PHY must drive the RxCLK and the RxSYNC signals to the MAC. Also, the MAC must
drive the TxCLK and the TxSYNC signal to the PHY. The REFCLK is also needed to synchronize
the data to the PHY’s core clock domain. TxData is clocked in using TxCLK and then
synchronized to REFCLK and transmitted to the twisted-pair. The RxData is synchronized to the
RxCLK. See Figure 23 on page 141.
Datasheet
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137
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 45. Intel® LXT9785/LXT9785E SS-SMII
Signal
138
To
From
Purpose
TxData
PHY
MAC
Transmit data & control
TxCLK
PHY
MAC
Transmit clock
TxSYNC
PHY
MAC
Synchronization pulses
RxData
MAC
PHY
Receive data & control
RxCLK
MAC
PHY
Receive clock
RxSYNC
MAC
PHY
Receive Synchronization
REFCLK
MAC
System
Synchronization
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 20. Intel® LXT9785/LXT9785E Typical SS-SMII Interface Diagram
Typical SS-SMII Interface in
a 16-Port System
SECTION
TxDatan
8
RxDatan
RxSYNC1
RxCLK1
MDIO0
MDC0
MDINT0
Magnetics/Fiber Transceiver
TxSYNC0
TxCLK0
LXT9785/9785E 8-Port Phy
8-Port Media
Access Controller
( MAC)
8
RefCLK0,1
125 MHz Sourced
Externally or from
Switch ASIC
SYS_CLK
RxDatan
RxSYNC1
RxCLK1
MDIO0
MDC0
MDINT0
Magnetics/Fiber Transceiver
8
RefCLK0,1
TxDatan
TxSYNC0
TxCLK0
LXT9785/9785E 8-Port Phy
8-Port Media
Access Controller
(MAC)
8
SECTION
Datasheet
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139
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 21. Intel® LXT9785/LXT9785E Typical SS-SMII Quad Sectionalization Diagram
Typical SS-SMII Interface
in a 24-Port System
RefClk1
RefClk0
8
RxSYNC1
12-Port Media
Access Controller
( MAC)
RxCLK1
MDIO0
MDC0
Magnetics/Fiber Transceiver
TxCLK0
RxData n
8
LXT9785/9785E 8-Port Phy
TxData n
TxSYNC0
MDINT0
SECTION
4
MDINT0
RefClk0
125 MHz Sourced
Externally or from
Switch ASIC
RefClk1
TxData n
TxSYNC1
TxCLK1
4
4
RxData n
RxSYNC1
RxCLK1
Magnetics/Fiber Transceiver
MDC0
LXT9785/9785E
4-port (sec)
MDIO0
4-port (sec)
4
TxData n
TxSYNC0
TxCLK0
RxData n
RxSYNC0
RxCLK0
VCC
MDIO1
SECTION
MDC1
MDINT0
MDIO0
MDC0
TxData n
TxSYNC0
TxCLK0
8
RxData n
RxSYNC1
RxCLK1
Magnetics/Fiber Transceiver
8
LXT9785/9785E 8-Port Phy
12-Port Media
Access Controller
( MAC)
MDINT1
SECTION
RefClk0 RefClk1
140
Datasheet
Document Number: 249241
Revision Number: 007
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 22. Intel® LXT9785/LXT9785E SS-SMII Transmit Timing
TxCLK
TxSYNC
TxData
TXER TXEN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXER
TxCLK
TxSYNC
TxData
TXER TXEN Frcerr Speed Dplx LINK Jabr
TXER
All signals are synchronous to the clock
Figure 23. Intel® LXT9785/LXT9785E SS-SMII Receive Timing
RxCLK
RxSYNC
RxData
CRS RXDV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 CRS
RxCLK
RxSYNC
RxData
CRS RXDV RXER Speed Dplx LINK Jabr UPnib FlsCar
CRS
All signals are synchronous to the clock
4.8
RMII Operation
The LXT9785/LXT9785E provides an independent Reduced MII port for each network port. Each
RMII uses four signals to pass received data to the MAC: RxDatan<1:0>, RxERn, and CRS_DVn
(where n reflects the port number). Three signals are used to transmit data from the MAC:
TxDatan_<1:0> and TxENn. Both receive and transmit signals are clocked by REFCLK. Data
transmission across the RMII is implemented in di-bit pairs which equal a 4-bit wide nibble.
Note:
4.8.1
The BGA15 package does not support the RMII interface.
RMII Reference Clock
The LXT9785/LXT9785E requires a 50 MHz reference clock (REFCLK). The device samples the
RMII input signals on the rising edge of REFCLK and drives RMII output signals on the falling
edge.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.8.2
Transmit Enable
TxENn must be asserted and de-asserted synchronously with REFCLK. The MAC must assert
TxENn at the same time as the first nibble of preamble. TxENn must be de-asserted after the last
bit of the packet.
4.8.3
Carrier Sense & Data Valid
The LXT9785/LXT9785E asserts CRS_DVn when it detects activity on the line. However,
RxDatan outputs zeros until the received data is decoded and available for transfer to the controller.
4.8.4
Receive Error
Whenever the LXT9785/LXT9785E receives an error symbol from the network, it asserts RxERn.
When it detects a bad Start-of-Stream Delimiter (SSD) it drives a “10” jam pattern on the RxData
pins to indicate a false carrier event.
4.8.5
Out-of-Band Signaling
The LXT9785/LXT9785E has the capability of encoding status information in the RxData stream
during IPG. See “Monitoring Operations” on page 157 for details.
4.8.6
4B/5B Coding Operations
The 100BASE-X protocol specifies the use of a 5-bit symbol code on the network media. However,
data is normally transmitted across the RMII interface in 2-bit nibblets or “di-bits”. The LXT9785/
LXT9785E incorporates a parallel/serial converter that translates between di-bit pairs and 4-bit
nibbles, and a 4B/5B encoder/decoder circuit that translates between 4-bit nibbles and 5-bit
symbols for the 100BASE-X connection. Figure 24 shows the data conversion flow from nibbles to
symbols. Table 46 on page 147 shows 4B/5B symbol coding (not all symbols are valid).
Figure 24. Intel® LXT9785/LXT9785E RMII Data Flow
Reduced MII Mode Data Flow
D0
D2
+1
Parallel
to
Serial
Scramble
D0 D1 D2 D3
D1
D3
di-bit
pairs
142
Serial
to
Parallel
0
4-bit
nibbles
4B/5B
S0
S1
S2
5-bit
symbols
S3
S4
DeScramble
MLT3
0
0
-1
Transition = 1.
No Transition = 0.
All transitions must follow
pattern: 0, +1, 0, -1, 0, +1...
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 25. Intel® LXT9785/LXT9785E Typical RMII Interface Diagram
Typical RMII Interface
in a 16-Port System
8
8
8-Port Media
Access Controller
( MAC)
8
8
8
TxENn
RxD0n
RxD1n
CRS_DVn
RxERn
MDIO0
MDC0
Magnetics/Fiber Transceiver
8
TxD1n
LXT9785/9785E 8-Port Phy
8
SECTION
TxD0n
MDINT0
RefClk0 RefClk1
50 Mhz Sourced
Externally or from
Switch ASIC
RefClk0
RefClk1
MDINT0
MDIO0
8-Port Media
Access Controller
( MAC)
TxD0 n
8
TxD1 n
8
8
8
TxEN n
RxD0 n
RxD1n
8
CRS_DV n
8
RxER n
Magnetics/Fiber Transceiver
8
LXT9785/9785E 8-Port Phy
MDC0
SECTION
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
143
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 26. Intel® LXT9785/LXT9785E Typical RMII Quad Sectionalization Diagram
Typical RMII Interface
in a 24-Port System
RefClk0 RefClk1
TxD0n
TxD1n
8
TxENn
8
RxD0n
8
RxD1n
12-Port Media
Access Controller
( MAC)
8
CRS_DVn
8
RxERn
MDIO0
MDC0
MDINT0
4
4
4
4
4
TxD0n
TxD1n
TxENn
RxD0n
RxD1n
CRS_DV n
RxERn
MDIO0
MDC0
MDINT0
RefClk0
50 MHz Sourced
Externally or from
Switch ASIC
RefClk1
4
TxD0 n
TxD1 n
TxEN n
RxD0 n
RxD1n
CRS_DVn
RxER n
4
4
4
4
4
MDINT1
MDIO1
MDC1
MDINT0
MDIO0
8
TxD0 n
TxD1 n
8
TxEN n
8
RxD0 n
8
8
8
RxD1n
CRS_DV n
RxER n
Magnetics/Fiber Transceiver
MDC0
8
VCC
SECTION
LXT9785/9785E 8-Port Phy
12-Port Media
Access Controller
( MAC)
4
Magnetics/Fiber Transceiver
4
SECTION
LXT9785/9785E
4-Port (sec)
4-Port (sec)
4
Magnetics/Fiber Transceiver
8
LXT9785/9785E 8-Port Phy
8
SECTION
RefClk0 RefClk1
144
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.9
100 Mbps Operation
4.9.1
100BASE-X Network Operations
During 100BASE-X operation, the LXT9785/LXT9785E transmits and receives 5-bit symbols
across the network link. Figure 27 shows the structure of a standard frame packet. When the MAC
is not actively transmitting data, the LXT9785/LXT9785E sends out Idle symbols on the line.
In 100BASE-TX mode, the device scrambles the data and transmits it to the network using MLT-3
line code. The MLT-3 signals received from the network are de-scrambled and decoded, and sent
across the RMII to the MAC.
In 100BASE-FX mode, the LXT9785/LXT9785E transmits and receives NRZI signals across the
LVPECL interface. An external 100BASE-FX transceiver module is required to complete the fiber
connection.
As shown in Figure 27, the MAC starts each transmission with a preamble pattern. As soon as the
LXT9785/LXT9785E detects the start of preamble, it transmits a J/K Start-of-Stream Delimiter
(SSD) symbol to the network. It then encodes and transmits the rest of the packet, including the
balance of the preamble, the Start-of-Frame Delimiter (SFD), packet data, and CRC. Once the
packet ends, the LXT9785/LXT9785E transmits the T/R End-of-Stream Delimiter (ESD) symbol
and then returns to transmitting Idle symbols.
Figure 27. Intel® LXT9785/LXT9785E 100BASE-X Frame Format
64-Bit Preamble
(8 Octets)
P0
P1
Replaced by
/J/K/ code-groups
Start-of-Stream
Delimiter (SSD)
4.9.2
P6
Destination and Source
Address (6 Octets each)
SFD
DA
DA
SA
Packet Length
(2 Octets)
SA
L1
L2
Data Field
Frame Check Field InterFrame Gap / Idle Code
(Pad to minimum packet size)
(4 Octets)
(> 12 Octets)
D0
Start-of-Frame
Delimiter (SFD)
D1
Dn
CRC
I0
IFG
Replaced by
/T/R/ code-groups
End-of-Stream Delimiter (ESD)
100BASE-X Protocol Sublayer Operations
In a 7-layer communications model, the LXT9785/LXT9785E is a Physical Layer 1 (PHY) device.
The LXT9785/LXT9785E implements the Physical Coding Sublayer (PCS), Physical Medium
Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model
defined by the IEEE 802.3u specification. The following paragraphs discuss the LXT9785/
LXT9785E operation from the reference model point of view.
4.9.2.1
PCS Sublayer
The Physical Coding Sublayer (PCS) provides the RMII interface, as well as the 4B/5B encoding/
decoding function. For 100BASE-TX and 100BASE-FX operation, the PCS layer provides IDLE
symbols to the PMD-layer line driver as long as TxEN is de-asserted. For 10T operation, the PCS
layer merely provides a bus interface and serialization/de-serialization function. 10T operation
does not use the 4B/5B encoder.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
145
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.9.2.1.1
Preamble Handling
When the MAC asserts TxEN, the PCS substitutes a /J/K/ symbol pair, also known as the Start-ofStream Delimiter (SSD), for the first two nibbles received across the RMII. The PCS layer
continues to encode the remaining RMII data until TxEN is de-asserted (see Table 46 on page 147).
It then returns to supplying IDLE symbols to the line driver.
The PCS layer performs the opposite function in the receive direction by substituting two preamble
nibbles for the SSD.
Figure 28. Intel® LXT9785/LXT9785E Protocol Sublayers
MII Interface
PCS
Sublayer
PMA
Sublayer
PMD
Sublayer
LXT9785
Encoder/Decoder
Serializer/De-serializer
Link/Carrier Detect
LVPECL Interface
Scrambler/
De-scrambler
100BASE-TX
146
Fiber Transceiver
100BASE-FX
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.9.3
PMA Sublayer
The 100BASE-X PMA protocol uses the 4B/5B data encoding scheme to encode/decode the data
streams. The coding scheme is shown in Table 46.
Table 46. 4B/5B Coding
Code Type
DATA
IDLE
CONTROL
INVALID
1.
2.
3.
4.
4B Code
3210
Name
5B Code
43210
0000
0
11110
Data 0
0001
1
01001
Data 1
0010
2
10100
Data 2
0011
3
10101
Data 3
0100
4
01010
Data 4
0101
5
01011
Data 5
0110
6
01110
Data 6
0111
7
01111
Data 7
1000
8
10010
Data 8
1001
9
10011
Data 9
1010
A
10110
Data A
1011
B
10111
Data B
1100
C
11010
Data C
1101
D
11011
Data D
1110
E
11100
Data E
1111
F
11101
Data F
I
1
1 1 1 11
Idle. Used as inter stream fill code.
0101
J
2
11000
Start-of-Stream Delimiter (SSD),
part 1 of 2.
0101
K2
10001
Start-of-Stream Delimiter (SSD),
part 2 of 2.
undefined
T3
01101
End-of-Stream Delimiter (ESD),
part 1 of 2.
undefined
R3
00111
End-of-Stream Delimiter (ESD),
part 2 of 2.
undefined
H4
00100
Transmit Error. Used to force
signaling errors.
undefined
Invalid
00000
Invalid
undefined
Invalid
00001
Invalid
undefined
Invalid
00010
Invalid
undefined
Invalid
00011
Invalid
undefined
Invalid
00101
Invalid
undefined
Invalid
00110
Invalid
undefined
Invalid
01000
Invalid
undefined
Invalid
01100
Invalid
undefined
Invalid
10000
Invalid
undefined
Invalid
11001
Invalid
undefined
Interpretation
The /I/ (Idle) code group is sent continuously between frames.
The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.
The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.
An /H/ (Error) code group is used to signal an error condition.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
147
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.9.3.1
Link
In 100 Mbps mode, the LXT9785/LXT9785E establishes a link whenever the descrambler
becomes locked and remains locked for approximately 50 ms. Whenever the descrambler loses
lock (<12 consecutive idle symbols during a 2 ms window), the link is taken down. This provides a
robust link, filtering out any small noise hits that may otherwise disrupt the link. Furthermore, 100
Mbps idle patterns will not bring up a 10 Mbps link.
The LXT9785/LXT9785E reports link failure via the Register status bits (1.2, 17.10, and 19.4) and
interrupt functions. If auto-negotiate is enabled, link failure causes the device to re-negotiate.
4.9.3.2
Link Failure Override
The LXT9785/LXT9785E normally transmits 100 Mbps data packets or Idle symbols only if it
detects the link is up, and transmits only FLP bursts if the link is not up. Setting bit 16.14 = 1
overrides this function, allowing the LXT9785/LXT9785E to transmit data packets even when the
link is down. This feature is provided as a diagnostic tool.
Note:
4.9.3.3
Auto-negotiation must be disabled to transmit data packets in the absence of link. If autonegotiation is enabled, the LXT9785/LXT9785E automatically begins transmitting FLP bursts if
the link goes down.
Carrier Sense/Data Valid (RMII)
The LXT9785/LXT9785E asserts CRS_DV whenever the respective port receiver is in a non-idle
state (as defined by the RMII Specification Revision 1.2), including false carrier events. Assertion
of CRS_DV is asynchronous with respect to REFCLK. In the event that signal decoding is not
complete when CRS_DV is asserted, the LXT9785/LXT9785E outputs 00 on the RxData1:0 lines
until the decoded data are available.
When the line returns to an idle state, CRS_DV is de-asserted synchronously with respect to
REFCLK. If the FIFO still contains data to be passed to the MAC via the RMII when CRS is deasserted, CRS_DV toggles on nibble boundaries until the FIFO is empty. For 100BASE-X signals,
CRS_DV toggles at 25 MHz. For 10BASE-T signals, CRS_DV toggles at 2.5 MHz.
4.9.3.4
Carrier Sense (SMII)
For 100BASE-TX and 100BASE-FX links, a Start-of-Stream Delimiter (SSD) or /J/K/ symbol pair
causes assertion of carrier sense (CRS). An End-of-Stream Delimiter (ESD), or /T/R/ symbol pair
causes de-assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received
without /T/R/. In this event, receive error is indicated during the IPG until the next packet is
received.
For 10T links, CRS assertion is based on receipt of valid preamble, and de-assertion on receipt of
an End-of-Frame (EOF) marker.
4.9.3.5
Receive Data Valid (SMII)
The LXT9785/LXT9785E asserts the RX_DV bit when it receives a valid packet. However,
RxData outputs zeros until the received data are decoded and available for transfer to the controller.
148
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.9.3.6
Twisted-Pair PMD Sublayer
The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and
descrambling, line coding and decoding (MLT-3 for 100BASE-TX, Manchester for 10T), as well
as receiving, polarity correction, and baseline wander correction functions.
4.9.3.6.1
Scrambler/Descrambler (100BASE-TX Only)
The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using
an 11-bit, non-data-dependent polynomial. The receiver automatically decodes the polynomial
whenever IDLE symbols are received.
The scrambler/descrambler can be bypassed by setting Register bit 16.12 = 1. The scrambler is
automatically bypassed when the fiber port is enabled. Scrambler bypass is provided for diagnostic
and test support.
4.9.3.6.2
Baseline Wander Correction
The LXT9785/LXT9785E provides a baseline wander correction function which makes the device
robust under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is,
by definition, “unbalanced”. This means that the DC average value of the signal voltage can
“wander” significantly over short time intervals (tenths of seconds). This wander may cause
receiver errors, particularly in less robust designs, at long line lengths (100 meters). The exact
characteristics of the wander are completely data dependent.
The LXT9785/LXT9785E baseline wander correction characteristics allow the device to recover
error-free data while receiving worst-case “killer” packets over all cable lengths.
4.9.3.6.3
Polarity Correction
The LXT9785/LXT9785E automatically detects and corrects for the condition where the receive
signal (TPFIP/N) is inverted. Reversed polarity is detected if eight inverted link pulses or four
inverted End-of-Frame (EOF) markers are received consecutively. If link pulses or data are not
received by the maximum receive time-out period, the polarity state is reset to a non-inverted state.
Before the polarity switch occurs, every frame is inverted and causes RxER to assert. The specific
number of RxER events observed depends on how many link pulses occur between packets.
4.9.3.7
Fiber PMD Sublayer
The LXT9785/LXT9785E provides an LVPECL interface for connection to an external 3.3 V or
5 V fiber-optic transceiver. (The external transceiver provides the PMD function for the optical
medium.) The LXT9785/LXT9785E uses a 125 Mbaud NRZI format for the fiber interface, and
does not support 10BASE-FL applications.
Note:
The BGA15 package does not support fiber interface.
4.9.3.7.1
Far End Fault Indications
The LXT9785/LXT9785E Signal Detect pins independently detect signal faults from the local
fiber transceivers via the SD pins. The device also uses Register bit 1.4 to report Remote Fault
indications received from its link partner. The device “ORs” both fault conditions to set bit 1.4.
Register bit 1.4 is set once and clears when read.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
149
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
The far-end fault detection process in fiber operation requires idles to establish link. Link will not
establish if a far-end fault pattern is the initial signal detected.
Either fault condition causes the LXT9785/LXT9785E to drop the link unless Forced Link Pass is
selected (16.14 = 1). Link down condition is then reported via interrupts and status bits.
In response to locally detected signal faults (SD activated by the local fiber transceiver), the
affected port can transmit the far end fault code if fault code transmission is enabled by Register bit
16.2.
• When Register bit 16.2 = 1, transmission of the far end fault code is enabled. The LXT9785/
LXT9785E transmits far end fault code if fault conditions are detected by the Signal Detect
pins.
• When Register bit 16.2 = 0, the LXT9785/LXT9785E does not transmit far end fault code. It
continues to transmit idle code and may or may not drop link depending on the setting for
Register bit 16.14.
The occurrence of a Far End Fault causes all transmission of data from the Reconciliation Sublayer
to stop and the Far End fault code to begin. The Far End Fault code consists of 84 ones’s followed
by a single “0” and is repeated until the Far End Fault condition is removed.
4.10
10 Mbps Operation
The LXT9785/LXT9785E operates as a standard 10BASE-T transceiver and supports all the
standard 10 Mbps functions. During 10BASE-T (10T) operation, the LXT9785/LXT9785E
transmits and receives Manchester-encoded data across the network link. When the MAC is not
actively transmitting data, the device sends out link pulses on the line.
In 10T mode, the polynomial scrambler/descrambler is inactive. Manchester-encoded signals
received from the network are decoded by the LXT9785/LXT9785E and sent across the MII to the
MAC.
Note:
4.10.1
The LXT9785/LXT9785E does not support fiber connections at 10 Mbps.
Preamble Handling
The LXT9785/9785E offers two options for preamble handling, which are selected by Register bit
16.5. In 10BASE-T mode, when Register bit 16.5 = 0, the device strips the preamble off the
received packets. In RMII and the SMII modes, the CRS signal is asserted based upon receive
activity. In the SMII modes, Out-of-Band (OOB) signaling is present until the SFD is output. The
DV signal is initially asserted in the frame that the SFD is output. In RMII mode, zeros are output
after receive activity is detected until the SFD is output. The packet is output following the SFD.
When Register bit 16.5 = 1 in 10BASE-T mode, the LXT9785/LXT9785E passes the preamble
through the RMII and the SMII interfaces. In RMII and the SMII modes, the CRS signal is asserted
based upon receive activity. In the SMII modes, OOB signaling is continued until preamble is
available from the receive FIFO. After the preamble, the SFD is output with the initial assertion of
the DV signal. The RMII interface outputs zeros after receive activity is detected until preamble is
available from the FIFO. The number of zero nibbles output before preamble is based upon the
FIFO initial fill settings (Register bits 18.15:14). The preamble is followed by the SFD and the
packet body. Register bit 16.5 has no effect in 100 Mbps operation.
150
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.10.2
Dribble Bits
The LXT9785/LXT9785E device handles dribble bits in all modes. If one through four dribble bits
are received, the nibble is passed across the RMII. If five through seven dribble bits are received,
the second nibble is not sent onto the RMII bus.
4.10.3
Link Test
The LXT9785/LXT9785E always transmits link pulses in 10T mode. When enabled, the link test
function monitors the connection for link pulses. Once link pulses are detected, data transmission is
enabled and remains enabled as long as either the link pulses or data transmission continue. If link
pulses stop, the data transmission is disabled.
If the link test function is disabled, the LXT9785/LXT9785E transmits to the connection regardless
of detected link pulses. The link test function is disabled by setting Register bit 16.14 = 1.
4.10.3.1
Link Failure
Link failure occurs if Link Test is enabled and link pulses or packets stop being received. If this
condition occurs, the LXT9785/LXT9785E returns to the auto-negotiation phase if autonegotiation is enabled.
4.10.4
Jabber
If a transmission exceeds the jabber timer, the LXT9785/LXT9785E disables the transmit and
loopback functions and the Collision Status bit (Register bit 17.11) is set regardless of duplex. The
jabber timer, according to the IEEE standard, must be between 20 ms to 150 ms. The RMII does
not include a Jabber pin, but the MAC may read Register 1 to determine jabber status. The
LXT9785/LXT9785E automatically exits jabber mode after the unjab time expires. This function is
disabled by setting Register bit 16.10 = 1.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
151
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.11
DTE Discovery Process
The DTE discovery process is port dependent and must be enabled through software. The process
is implemented as a next page option to the auto-negotiation flow. When the process is enabled,
manual control of auto-negotiation next pages is not allowed. This feature applies to the
LXT9785E transceiver only.
The process depends upon an IP phone, or any other DTE capable of being powered remotely,
having a specific filter that passes NLPs and FLPs. This filter should be non-polarized to insure
that the latest status of Auto-MDIX operation does not effect operation. This filter attenuates
100 Mbps MLT3 signals and 10 Mbps Manchester-encoded signals, and must be bypassed when
power is applied to the IP phone. Figure 29 shows a typical IP telephone system connection.
Figure 29. Typical IP Telephone System Connection
VoIP-Enabled Switch
SD
Pr oCurve Switch 2424M
HP J4122B
10/100Base -T Ports
Module Status
Self Test
1
2
3
6
13 14 1 5 16 17 18
8
9 10 11 12
4
5
19 20 2 1 22 23 24
Link
1X
2X
3X
4X
5X
6X
13X
14X
15X
16X
17X
18X
7X
8X
9X
10X
11X
12X
19X
20X
21X
22X
23X
24X
Mode
7
Console
Link
Mode
Power
Fault
Reset
Clear
Act Fdx 100
Mode Select
Power cable
Power and data over
Category 5 cable
Power
Outlet
UPS/
Generator
Power cable
1 2
3
4 5
6
7 8
9
8
#
*
IP Telephone
4.11.1
Data only over
Category 5 cable
Computer
Power
Outlet
Definitions
The following terms are used throughout the DTE discovery sections:
152
Negotiation Process:
This includes auto-negotiation and parallel detection processes
System:
The switch system using the LXT9785E for DTE Discovery
Link Partner:
A device connected to the LXT9785E through twisted pair cables
DTE:
Data Terminal Equipment; any end-of-link partner
Standard Link Partner:
A link partner that is not requiring power over a Category 5 cable;
typically a PC
Remote-Power DTE:
Data Terminal Equipment requiring power over a Category 5 cable;
typically an IP telephone
Discovery:
The process of identifying the type of link partner present
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.11.2
Interaction between Processor, MAC, and PHY
The state machines that control the mechanics of the Discovery process reside within the
LXT9785E device. However, control of the power supply and overall system control reside in the
system processor. The processor communicates with the power supply unit (PSU) and switches it
on and off dependant on the data that is supplied by the PHY. The PHY register data is read by the
MAC using the MDIO interface. The required control bits are contained in the PHY device register
map and are discussed in detail in the section labeled “Management Interface and Control” on
page 153.
Note:
The details of the processor/MAC interface and the processor/PSU interface are implementation
specific and therefore are out of the scope of this specification.
The following is an overview of the system control for a successful Remote-Power DTE discovery:
1. The discovery process is enabled by the DTE Discovery Process Enable (Dis_EN) Register bit
27.6 and the Auto-Negotiation Enable Register bit 0.12. Writing Register bit 27.6 immediately
affects the Auto-Negotiation Base Page. If already enabled, auto-negotiation should be
restarted after this bit is written to ensure proper operation. Register bit 4.15 is used for manual
control of auto-negotiation next pages and should be left in the default state (cleared).
2. The LXT9785E PHY then tests to see if a Remote-Power DTE is present as the link partner. If
a Remote-Power DTE is found, the Power Enable (Power_EN) Register bit 27.4 is set. The
processor polls this signal via the MAC.
3. Upon detecting a Remote-Power DTE, the processor instructs the power supply to switch on.
Once power has been applied to the DTE, normal negotiation takes place. The processor must
enable the required negotiation process by restarting auto-negotiation, or by setting forced
speed mode after power has been applied. The processor must poll the link-up Register bit 1.2
for the corresponding LXT9785E port, or the link status change interrupt, to ensure that the
link has been established.
4. A time-out must be connected with this feature so that if link is not established within a predetermined time period (system dependant), the processor instructs the power supply to switch
off. If link is not established prior to the expiration of the “link fail inhibit timer”, the
LXT9785E restarts negotiation with DTE detection if auto-negotiation mode was used to
establish link with the phone, and the DTE process is still enabled. The LXT9785E restarts
negotiation without DTE detection if either forced speed mode is used to establish link with
the phone, or the DTE process is disabled.
5. If power is applied and link is established, the system must still poll the Link Status Register
bit 1.2 for the corresponding LXT9785E port or the link status change interrupt. This is
required since link status is the only way to know when the Remote-Power DTE is removed or
unplugged. On seeing the Link_Down condition, the processor instructs the power supply to
switch off, and the DTE Discovery begins again or is disabled.
4.11.3
Management Interface and Control
The management and control of the DTE discovery process is via the MDIO port. Each port on the
LXT9785E is capable of running the discovery process, thus each port is independently controlled.
This is achieved by each port having a dedicated set of control and status bits. These bits are found
in Register 27 as follows:
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
153
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
DTE DISCOVERY PROCESS ENABLE - Register Bit 27.6 (Dis_EN)
R/W Default value = 0: Disabled.
Register bit 27.6 controls the operation of the process. The discovery process is disabled when
Register bit 27.6 = 0, and enabled when Register bit 27.6 = 1. The MAC controller sets Register bit
27.6 to a 1 when a port search for a DTE requiring power is desired. Once set, Register bit 27.6
remains = 1 until the MAC clears it, either by directly clearing it or by resetting the PHY. This
allows the discovery process to continue to function if unsuccessful in detecting a DTE, without
being continually re-enabled by the MAC. If Register bit 27.6 is set after link is established, no
action is taken until after the link goes down.
POWER ENABLE - Register Bit 27.4 (Power_EN)
R Default value = 0: No Remote-Power DTE found.
Register bit 27.4 contains the result of the discovery process. When Register bit 27.4 = 0, the
discovery process has not found Remote-Power DTE, and when Register bit 27.4 = 1, the
discovery process has potentially found a DTE requiring power. This indicates power should be
applied to the Category 5 cable. Register bit 27.4 is polled by the MAC during the discovery
process, and is cleared when the PHY is reset, when auto-negotiation is restarted, or when autonegotiation is disabled. In the event of a discovery process being interrupted due to detection of an
already powered link partner (auto-negotiation completion or Parallel Detection), Register
bit 27.4 = 0.
STANDARD LINK PARTNER DETECTED - Register Bit 27.3 (SLP_Det)
R/W Clear on Read Default value = 0: No link partner found.
When Register bit 27.3 = 1, a standard link partner has been detected by the LXT9785E (NLPs,
MLT3 data, FLPs without next page support, or FLPs with non-matching next pages). This
indicates power should not be applied to the Category 5 cable. When Register bit 27.3 = 0, other
bits are checked to determine overall status of the link partner. Register bit 27.3 is cleared on read,
or DTE discovery is disabled, link is established, or auto-negotiation is either restarted or disabled.
LINK FAIL TIMEOUT - Register Bit 27.2 (LFIT Expired)
R/W Clear on Read Default value = 0 (Link Fail Inhibit timer has expired without establishment of
link with a standard link partner). Valid only when Standard Link Partner Detected Register bit
27.3 = 1.
Register bit 27.2 is set if link is not established prior to the Link Fail Inhibit Timer expiring. This
indicates that the Discovery process has restarted and the Standard Link Partner Detected Register
bit may no longer be valid. Register bit 27.2 is cleared on read, or DTE discovery is disabled, link
is established, or auto-negotiation is either restarted or disabled.
4.11.4
DTE Discovery Process Flow
The following section describes the DTE Discovery process.See Figure 30, “Intel® LXT9785E
Negotiation Flow Chart” on page 156 for a flow chart of the discovery process.When DTE
Discovery (27.6) and auto-negotiation (0.12) are enabled (auto-negotiation mode is required), the
LXT9785E transmits the auto-negotiation base page with the next page ability bit set (“AutoNegotiation Advertisement Register (Address 4)” on page 204).
System software polls Register 27 to determine if or when a Remote-Power DTE is detected. The
receiver monitors the line to determine if NLPs, MLT3 data, or FLP bursts are being received. If
the receive activity is FLP bursts, the status of the next page ability bit is checked. If the detected
“link partner” also supports next page, then the LXT9785E transmits out the next page sequence
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associated with message code #5 (Organizationally Unique Identifier (OUI) Tag Code). The
definition for the next pages to be sent out for this message code include some user-defined code
values. These values are loaded with randomly created data from an internal LSFR that is free
running and seeded with the PHY address of the LXT9785E port. The Next Pages are hard coded
in the logic (the LXT9785E ignores any data written into Register 7) and are outlined in Table 47.
The receiver monitors the next pages to determine that the exact next page data (especially the
random data) transmitted is received. As soon as the first non-matching next page is detected, the
DTE Discovery process is stopped and the base page is used to determine the capability options.
The Power-Enable Register bit 27.4 is set when a Remote-Power DTE is detected as the link
partner, and the last next page is repeatedly transmitted until software restarts the required
negotiation process (auto-negotiation or forced-speed mode).
The software should be written so that the negotiation is not restarted until the DTE has been
powered up over the Category 5 cable. The Power-Enable Register bit 27.4 is cleared upon
restarting or disabling auto-negotiation (selecting forced mode). The system must be able to detect
over-current conditions and be capable of disabling power in case the link partner is not a RemotePower DTE. Some examples of devices that would mistakenly set Power-Enable Register bit 27.4
are a token-ring balun and a loopback cable. Once link partner power has been stabilized and
sufficient time has passed for the link partner to initialize, the auto-negotiation process may be
restarted.
The negotiation process establishes link if a compatible mode exists between the LXT9785E and
the link partner. If a compatible mode does not exist (not compatible or not established within the
Link Fail Inhibit Timer period), the LXT9785E either restarts auto-negotiation/DTE discovery
(discovery is enabled (27.6=1) and auto-negotiation is enabled (0.12 = 1)), or normal negotiation
(discovery is disabled (27.6=0) and auto-negotiation is enabled (0.12 = 1)), or either 10 Mbps or
100 Mbps forced-mode operation (auto-negotiation is disabled (0.12 = 0)). The software must
detect this non-link state and disable power.
Table 47. Next Page Message #5 Code Word Definitions
Next Page
Encoding
D15
OUI
Tagged
Message
1
a
1
0
t
User Page
1
1
a
0
0
t
3.10 3.11 3.12 3.13 3.14 3.15
User Page
2
1
a
0
0
t
2.5
2.6
2.7
2.8
2.9
2.10 2.11 2.12 2.13 2.14 2.15
User Page
3
1
a
0
0
t
0
0
L.8
L.7
L.6
L.5
L.4
L.3
L.2
L.1
L.0
User Page
4
1
a
0
0
t
L.10
L.9
L.8
L.7
L.6
L.5
L.4
L.3
L.2
L.1
L.0
D14 D13 D12 D11 D10
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
0
1
2.0
2.1
2.2
2.3
2.4
1. a is the acknowledge bit; t is the toggle bit; L is the LFSR
4.11.5
DTE Discovery Behavior
The device behavior checks the comparison bit after each next page is successfully autonegotiated. If the first next page or any subsequent next page does not match, the DTE Discovery
process transmits one last null page with the next page bit cleared to stop the DTE Discovery
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
process. If each page is successfully auto-negotiated (it matches the transmitted page), DTE
Discovery completes as previously described. The five Next Pages consist of a message page and
four user pages.
Figure 30. Intel® LXT9785E Negotiation Flow Chart
Start
Power Up
or
Link Down 1.2 = 0 and Dis_EN 27.6 = 0
or
Link Down 1.2 = 0 and Forced Mode
Default Mode
Transmit based upon hardware
configuration
FLP, NLP or IDLE Symbols
LFIT Expired 27.2 = 1
Dis_EN 27.6 = 0
Assumptions:
Auto-Negotiation/Forced Speed Set by Pins
Advertisement Requirements Set by Pins
LFIT Expired 27.2 = 1
Link Fail Timeout = 1
Dis_EN Not Set 27.6 = 0
NLPs or IDLE Symbols
Detected
Software Intervention
Auto-negotiation 0.12 = 1 (if needed)
Power_EN 27.6 = 1
FLP Detected
Link Down 1.2 = 0
and
Dis_EN 27.6 = 1
and
Auto-Neg 0.12 = 1
NLPs or IDLE Symbols
Detected
Discovery Base
Transmit FLPs
Base Page (Register 4)
with Next Page 4.15 = 1
Parallel Detection
Determine Compatibility on
Speed and Duplex
Check Advertisement
LFIT Expired 27.2 = 1
Dis_EN 27.6 = 1
FLP Detected
LFIT Expired 27.2 = 1
Dis_EN 27.6 = 1
Auto Negotiation
Determine Compatibility Options
No
Next Page
Set?
No
Yes
Yes
Nonmatching DTE
Discovery NP
Received
AutoNegotiation?
Next Page Transmission
Use Random Data for User Defined
Bits as Code
Compatibility
Power Applied
No
Compatibility
Next Pages Received
Power On
Wait State for
Proper Power
Assertiion
Pages = Code
Transmitted?
Set Mode
Restart
Auto-Negotiation
Yes
or
DTE Discovered
Transmit Last Page Continuously
Power_EN 27.4 = 1
Software Intervention
Software Polled Power_EN 27.4 = 1
Turn On Power Supply
Force Speed
Link Up
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Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.12
Monitoring Operations
4.12.1
Monitoring Auto-Negotiation
Auto-negotiation may be monitored as follows:
• Bits 1.2 and 17.10 = 1 once the link is established.
• Additional bits in Register 1 (refer to Table 84, “Status Register (Address 1)” on page 201) and
Register 17 (refer to Table 93, “Quick Status Register (Address 17, Hex 11)” on page 209) can
be used to determine the link operating conditions and status.
4.12.2
Per-Port LED Driver Functions
The LXT9785/LXT9785E incorporates three direct drive LEDs per port (LEDn_1, LEDn_2, and
LEDn_3).
Note:
The BGA15 package only supports two LEDs per port (LEDn_1 and LEDn_2).
On power up, all the LEDs lights up for approximately one second after reset de-asserts. Each LED
may be programmed to one of several different display modes using the LED Configuration
Register. Each per-port LED may be programmed (refer to Table 96, “LED Configuration Register
(Address 20, Hex 14)” on page 213) to indicate one of the following conditions:
•
•
•
•
•
•
•
Operating Speed
Transmit Activity
Receive Activity
Collision Condition
Link Status
Duplex Mode
Isolate Condition
The LEDs can also be programmed to display various combined status conditions. For example,
setting bits 20.15:12 = 1101 produces the following combination of Link and Activity indications:
• If Link is down, LED is off.
• If Link is up, LED is on.
• If Link is up AND activity is detected, the LED blinks at the stretch interval selected by bits
20.3:2 and continues to blink as long as activity is present.
The LED driver pins are open drain circuits (10mA max current rating). Refer to “LED Circuit” on
page 167 under the Application Information Section for LED circuit design details. The LED
Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. If during
this pulse stretch period, the event occurs again, the pulse stretch time is further extended (see
Table 96, “LED Configuration Register (Address 20, Hex 14)” on page 213).
When an event such as receiving a packet occurs, it is edge detected and starts the stretch timer.
The LED driver remains asserted until the stretch timer expires. If another event occurs before the
stretch timer expires, the stretch timer is reset and the stretch time extended.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
When a long event (such as duplex status) occurs, it is edge detected and starts the stretch timer.
When the stretch timer expires, the edge detector is reset so that a long event causes another pulse
to be generated from the edge detector. The edge detector resets the stretch timer, causing the LED
driver to remain asserted. Figure 31 on page 158 shows how the stretch operation functions.
Figure 31. Intel® LXT9785/LXT9785E LED Pulse Stretching
Event
LED
stretch
stretch
stretch
Note: The direct drive LED outputs in this diagram are shown as active L ow.
4.12.3
Out-of-Band Signaling
The LXT9785/LXT9785E provides an out-of-band signaling option to transfer status information
across the RMII receive interface. This feature is enabled when Register bit 25.0 = 1 and uses the
RxData(1:0) data bus during the Inter-Packet Gap (IPG) time as shown in Figure 32. Out-of-Band
signaling is disabled when Isolate mode is enabled by setting Register 0.10.
Note:
The BGA15 package does not support Out-of-Band Signaling nor the RMII interface.
The two status bits transferred across the RxData bus are software selectable via Register 25 (see
Table 98, “RMII Out-of-Band Signaling Register (Address 25, Hex 19)” on page 215).
In normal operation, the LXT9785/LXT9785E stuffs the RxData bus with zeros during the IPG. A
software-selectable bit enables the RMII out-of-band signaling feature. Once this bit is set, the
LXT9785/LXT9785E replaces the zeros with selected status bits during the IPG.
Figure 32. Intel® LXT9785/LXT9785E RMII Programmable Out-of-Band Signaling
REFCLK
CRS_DV
RXD(1)
sta tus 1
status 1
0s
data
data
data
data
status 1
status 1
status 1
status 1
status 1
RXD(0)
sta tus 0
status 0
0s
data
data
data
data
status 0
status 0
status 0
status 0
status 0
1. When network activity is detected, the LXT9785/LXT9785E asserts CRS_DV asynchronously with respect
to REFCLK.
2. After CRS_DV is asserted, the LXT9785/LXT9785E zero-stuffs the RxData bits until the received data has
been processed through the FIFO.
3. When network activity ceases, the LXT9785/LXT9785E de-asserts CRS_DV synchronously with respect
to REFCLK. CRS_DV toggles until all data in the FIFO has been processed through the RMII. Once the
FIFO is empty, LXT9785/LXT9785E drives the status bits selected by the Out-of-Band Signaling Register
(refer to Table 98, “RMII Out-of-Band Signaling Register (Address 25, Hex 19)” on page 215) on the
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
The LXT9785/LXT9785E includes an IEEE 1149.1 boundary scan test port for board level testing.
All digital input, output, and input/output pins are accessible.
4.12.4
Boundary Scan Interface
This interface consists of five pins (TMS, TDI, TDO, TCK and TRST). It includes a state machine,
data register array, and instruction register. The TMS and TDI pins are internally pulled up and the
TCK pin is internally pulled down. TDO does not have an internal pull-up or pull-down.
4.12.5
State Machine
The TAP controller is a 16-state machine driven by the TCK and TMS pins. Upon reset, the
TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS and TDI are
High for five TCK periods.
4.12.6
Instruction Register
The IDCODE instruction is always invoked after the state machine resets. The decode logic
ensures the correct data flow to the Data registers according to the current instruction. Valid
instructions are listed in Table 49.
4.12.7
Boundary Scan Register
Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the
serial shift stage and the parallel output stage. There are four modes of operation as listed in
Table 48. Refer to the Identification Information section in the LXT9785/LXT9785E Specification
Update (document number 249357) for the JTAG ID numbers.
Table 48. BSR Mode of Operation
Mode
Description
1
Capture
2
Shift
3
Update
4
System Function
Table 49. Supported JTAG Instructions
Name
Code
Description
Data
Register
EXTEST
0000 Hex
External Test
BSR
IDCODE
FFFE Hex
ID Code Inspection
ID REG
SAMPLE
FFF8 Hex
Sample Boundary
BSR
High Z
FFCF Hex
Force Float
Bypass
Clamp
FFEF Hex
Clamp
BSR
BYPASS
FFFF Hex
Bypass Scan
Bypass
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.13
Cable Diagnostics Overview
Debugging cable problems increases the overall cost of owning and operating a local area network.
Cable Diagnostic tools were incorporated into the LXT9785 device to help customers debug
network cable problems. The Cable Diagnostic tools provide the ability to detect severe cable
problems, such as open and short circuits, and determine the distance to the discontinuity.
4.13.1
Features
The following are three cases to consider for Cable Diagnostics:
• Distance to a short circuit between wires of a single twisted-pair
• An open circuit
• Detection of an improperly terminated cable by the link partner.
An improperly terminated cable will not meet IEEE 802.3 return loss requirements. Register 29 has
been added to control cable testing and report cable testing results.
Cable Diagnostics provides a method to determine the distance to opens and shorts when the link
partner is inactive on the twisted-pair under test. The cable tests produce undefined results if the
link partner is transmitting signals. Implementation methods may vary depending upon the system
use requirements of Cable Diagnostics.
4.13.2
Operation
Cable Diagnostics utilizes the PHY transmit drivers and receivers to test a single twisted-pair. A
transmit pulse is driven down the twisted-pair under test and the reflected signal is analyzed. Link
partners transmitting NLP, FLP, MLT3, or other TDR pulses may interfere with the ability of the
LXT9785 to properly analyze the reflected Cable Diagnostic pulse. Implementation algorithms
must take these potential situations into consideration.
4.13.2.1
Short and Long Cable Testing Requirements
Implementing Cable Diagnostic tests, by enabling short and long cable tests sequentially, allows
more accurate measurements to a detected fault. Both tests are necessary to reach full precision.
The short and long cable tests can be run by writing 0x7400h and 0x6C00h to Register 29,
respectively. See Section 4.13.4, “Basic Implementation” on page 161 for implementation details.
4.13.2.2
Precision
Cable Diagnostics estimates the distance to a fault up to 150 m. Category 5 or better cable produces
the most accurate test results. Less than Category 5 cable may produce less accurate results on long
cable lengths. Cable Diagnostics returns the distance to the closest fault, if a fault is present.
Cable Diagnostic tests report the distance to a cable fault based on the velocity of signal
propagation, which is used to determine the electrical length to the fault. The electrical length may
vary slightly from the physical cable length. The measurement accuracy may vary by +/- 2 m.
The following basic equation is used to calculate the distance to a fault:
Distance_to_Fault = (Reg29[7:0] - 3.5) / 1.16
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4.13.3
Implementation Considerations
Before performing Cable Diagnostics, the twisted-pair to be tested may be verified to be inactive.
All applicable link configurations should be attempted. Cable Diagnostic tests may be started if the
attempts indicate no link partners are active. If link partners are detected, additional tests and
decisions as to next steps may need to be implemented in the cable testing algorithm to ensure the
most accurate results.
Intel recommends that a 100BASE-TX link be attempted with MDI and MDIX enabled
sequentially, prior to performing Cable Diagnostic testing, to determine if a 100BASE-TX-only
link partner is present. If a link partner is in forced 100BASE-TX operation, transmitting MLT3,
the Cable Diagnostic test result will be undefined due to the interference MLT3 causes in
attempting to process the reflected Cable Diagnostic pulse. Auto MDI/MDIX on the link partner
should be accounted for in deriving the cable testing algorithm.
Intel recommends auto MDI/MDIX be disabled when running the cable tests. The transmit and
receive twisted-pairs must be tested one at a time with both short and long cable test suites. The
MDI/MDIX control bits in Table 99, “Trim Enable Register (Address 27, Hex 1B)” on page 216
can be used to select the twisted-pair to be tested. This requirement creates a minimum of four test
permutations that must be completed to determine if the fault exists, the distance to the fault.
If Cable Diagnostics testing is completed using a powered down LXT9785 device as the link
partner, specific results can be expected. The results will indicate an open connection when the
PWRDWN hardware configuration pin is used. These power-down methods disable the internal
termination resistors to create a high impedance connection equivalent to an open circuit.
If Transmit Disable (Register bit 16.13) or software controlled Power-Down (Register bit 0.11) is
used, the powered down device transmit logic will look like an open circuit and the receive circuit
will look like a 100 Ω terminated connection. The Transmit Disable bit and the software PowerDown bit disable the transmit circuit but do not affect the receive circuit.
The result of Cable Diagnostic tests using an IP Phone indicate an open or a short fault at a gross
approximation of the distance to the IP Phone. The termination resistors are not powered and do
not create a proper termination. The filter circuit used by some manufacturers adversely affects the
test results.
Transmission and reception of packets is disabled when Cable Diagnostics is enabled. Internal
loopback must be disabled for Cable Diagnostics to operate properly. Internal loopback disables
the analog interface.
4.13.4
Basic Implementation
Register 29 is used to control and report the Cable Diagnostics test results. The function tests one
pair of the twisted-pair cable at a time. The basic process flow is described as follows (see
Table 100, “Cable Diagnostics Register (Address 29, Hex 1D)” on page 217 for Register 29 bit
definitions):
1. Disable auto-negotiation by clearing Register bit 0.12, set to MDI by clearing Register bits
27.9:8, and ensure internal loopback is disabled, Register bit 0.14 = 0.
2. Write 0x7400h to Register 29. Setting these bits places the device in short cable Cable
Diagnostics mode and forces link to drop. The device waits a specific amount of time (1.2 s to
1.5 s) to ensure link drops on any connected link partner, and initiates the Cable Diagnostics
test on the selected twisted-pair.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3. Poll Register bit 29.9. When this bit is set, the test is complete and Register bits 29.7:0 contain
a value used to determine if a cable fault was found and the distance to that fault. A value of
0xFFh indicates no fault was found. Any other value indicates a fault was found, that value
should be stored for later use.
4. Write 0x6C00h to Register 29. Setting these bits places the device in long cable Cable
Diagnostics mode.
5. Poll Register bit 29.9. When set, record the value of Register bits 29.7:0 if a fault is found.
6. If a fault is present, a calculation is used to determine the distance to the fault. Insert the
smallest value recorded from Register bits 29.7:0 in steps 3 and 5 above into the following
formula:
Distance_to_Fault = (Reg29[7:0] - 3.5) / 1.16
Register bit 29.8 is set if the fault is detected as a short circuit and is cleared if the fault is
detected as an open circuit. Register bits 29.12:11 are cleared when read and are cleared during
the same read cycle when Register bit 29.9 is read, indicating a fault condition exists.
7. Normal PHY operation can be resumed by writing 0x4000h to Register 29 or by software or
hardware reset. The test suite can be run again by resuming at step 2 above.
4.14
Link Hold-Off Overview
The PHY link is established as soon as the system platform powers-up. In many cases, the system
platform is not capable of supporting network operation until configuration firmware is loaded. It is
desirable in such cases to prevent the PHY from establishing a link until the system platform is
fully configured and ready for network operation. Link Hold-Off was incorporated into the
LXT9785 device to satisfy these requirements. Enabling Link Hold-Off disables the PHY Link
capability until the system platform is fully capable of supporting network operation. The feature is
enabled by hardware control at power-up or software control during normal operation.
4.14.1
Features
Link Hold-Off prevents the LXT9785 from establishing a link by disabling the analog transmit and
receive capability. The digital capabilities of the PHY are unaffected including register access and
LED operation. Link Hold-Off can be enabled by an external hardware pin for all ports or by
software register access for individual ports. When Link Hold-Off is enabled, the transmitter and
receiver on the selected ports are forced into software power-down mode (see Section 4.5.3,
“Power-Down Mode” on page 127) to block signal activity from establishing a link and passing
packets through the PHY.
The hardware enabled Link Hold-Off is controlled by the LINKHOLD pin. Internal pull-down
resistors hold the pin in the inactive state. Connecting a 5k pull-up resistor to the pin enables the
feature at power-up reset or external hardware pin Reset. Once a PHY port is programmed as
desired, clearing Register bit 0.11 will re-enable that port. Each port must be individually reenabled.
When a port is software reset, by setting Register 0.15, the state of the hardware configuration pin
captured by the last hardware or power-up reset determines the default register values for the
specific function for that port. Link Hold-Off, once enabled by hardware configuration, is reenabled on a port by issuing a software reset for that port. It is not necessary to reset the entire PHY
or switch system to re-enable Link Hold-Off.
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Link Hold-Off software control is enabled or disabled on individual ports by respectively setting or
clearing Register bit 0.11, the power-down bit, during normal operation. It is not required to have
previously enabled Link Hold-Off by hardware configuration.
Link Hold-Off is disabled if the external pin MDDIS is active. The MDDIS pin disables the MDIO
interface required to re-enable normal transmit and receive link operation. MDDIS is intended to
disable the MDIO management interface for unmanaged applications. Internal loopback circuitry
is unaffected in Link Hold-Off mode.
4.14.2
Operation
Link Hold-Off is implemented in one of the following two ways:
• Using a hardware pin at power-up or hardware reset
• Using software control through the MII Management (MDC/MDIO) interface.
Link Hold-Off use by an external hardware pin is as follows:
1. Pull the LINKHOLD pin High with a pull-up resistor (approximately 5 k Ohms).
2. Power up the system or drive the reset pin active.
3. All ports are link disabled.
4. Program all ports to the desired configuration.
5. Clear Register Bit 0.11, power-down for each individual port.
6. Normal operation resumes on each port after Register bit 0.11 is cleared (see Table 83 for the
recovery time).
Link Hold-Off is enabled on a per port basis by software control using the following two methods:
Method One:
This method requires that Link Hold-Off is enabled by the LINKHOLD pin during the last powerup or hardware reset.
1. Set Register bit 0.15 to reset and re-enable Link Hold-Off for the desired port.
2. Program the PHY to the desired configuration.
3. Clear Register bit 0.11 (power-down) to disable Link Hold-Off.
4. Normal operation resumes.
Method Two:
This method enables Link Hold-Off regardless of the LINKHOLD hardware configuration state.
1. Set Register bit 0.11(power-down) to enable Link Hold-Off for the desired port.
2. Program the PHY to the desired configuration.
3. Clear Register bit 0.11 (power-down) to disable Link Hold-Off.
4. Normal operation resumes.
Note:
High is defined by the IO voltage supply level selected (2.5V or 3.3V).
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
5.0
Application Information
5.1
Design Recommendations
The LXT9785/LXT9785E is designed to comply with IEEE 802.3 requirements to provide
outstanding receive Bit Error Rate (BER), and long-line-length performance. To achieve maximum
performance from the LXT9785/LXT9785E, attention to detail and good design practices are
required. Refer to the LXT9785 Design and Layout Guide application note for detailed design and
layout information.
5.2
General Design Guidelines
Adherence to generally accepted design practices is essential to minimize noise levels on power
and ground planes. Up to 50 mV maximum of noise is considered acceptable. High-frequency
switching noise can be reduced, and its effects eliminated, by following these simple guidelines
throughout the design:
• Fill in unused areas of the signal planes with solid copper and attach them with vias to a VCC
or ground plane that is not located adjacent to the signal layer.
• Use ample bulk and decoupling capacitors throughout the design (a value of 0.01µF is
recommended for decoupling caps).
•
•
•
•
•
•
Provide ample power and ground planes.
Provide termination on all high-speed switching signals and clock lines.
Provide impedance matching on long traces to prevent reflections.
Route high-speed signals next to a continuous, unbroken ground plane.
Filter and shield DC-DC converters, oscillators, etc.
Do not route any digital signals between the LXT9785/LXT9785E and the RJ-45 connectors at
the edge of the board.
• Do not extend any circuit power and ground plane past the center of the magnetics or to the
edge of the board. Use this area for chassis ground, or leave it void.
5.2.1
Power Supply Filtering
Power supply ripple and digital switching noise on the VCC plane may cause EMI problems and
degrade line performance. The best approach to this problem is to minimize ground noise as much
as possible using good general techniques and by filtering the VCC plane. It is generally difficult to
predict in advance the performance of any design, although certain factors greatly increase the risk
of having problems:
• Poorly-regulated or over-burdened power supplies.
• Wide data busses (32-bits+) running at a high clock rate.
• DC-to-DC converters.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Intel recommends filtering the power supply to the analog VCC pins of the LXT9785/LXT9785E.
This has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the
LXT9785/LXT9785E, helping with line performance. Second, if the VCC planes are laid out
correctly, digital switching noise is kept away from external connectors, reducing EMI problems.
The recommended implementation is to break the VCC plane into two sections. The digital section
supplies power to the VCCD and VCCIO pins of the LXT9785/LXT9785E. The analog section
supplies power to the VCCA pins. The break between the two planes should run underneath the
device. In designs with more than one the LXT9785/LXT9785E, a single continuous analog VCC
plane can be used to supply them all.
The digital and analog VCC planes should be joined at one or more points by ferrite beads. The
beads should produce at least a 100 Ω impedance at 100 MHz. Beads should be placed so that
current flow is evenly distributed. The maximum current rating of the beads should be at least
150% of the current that is actually expected to flow through them. A bulk cap (2.2 -10µF) should
be placed on each side of each bead.
In addition, a high-frequency bypass cap (0.01 µF) should be placed near each analog VCC pin.
5.2.2
Power and Ground Plane Layout Considerations
Great care needs to be taken when laying out the power and ground planes.
• Follow the guidelines in the LXT9785 Design and Layout Guide (formerly Application Note
151) for locating the split between the digital and analog VCC planes.
• Keep the digital VCC plane away from the TPFOP/N and TPFIP/N signals, the magnetics, and
the RJ-45 connectors.
• Place the layers so that the TPFOP/N and TFPIP/N signals can be routed near or next to the
ground plane. For EMI reasons, it is more important to shield TPFOP/N than TPFIP/N.
5.2.2.1
Chassis Ground
For ESD reasons, it is a good design practice to create a separate chassis ground that encircles the
board and is isolated via moats and keep-out areas from all circuit-ground planes and active
signals. Chassis ground should extend from the RJ-45 connectors to the magnetics, and can be used
to terminate unused signal pairs (Bob Smith termination). In single-point grounding applications,
provide a single connection between chassis and circuit grounds with a 2 kV isolation capacitor. In
multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide
2 kV isolation to the Bob Smith termination.
5.2.3
MII Terminations
Series termination resistors are required on all the SS-SMII output signals driven by the LXT9785/
LXT9785E. Special trace layout consideration should be used when using the SMII interface. Keep
all traces orthogonal and as short as possible. Whenever possible, route the clock and sync traces
evenly between the longest and shortest data routes. This minimizes round-trip, clock-to-data
delays and allows a larger margin to the setup and hold requirements.
5.2.4
Twisted-Pair Interface
Use the following standard guidelines for a twisted-pair interface:
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Revision Number: 007
Revision Date: August 28, 2003
165
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
•
•
•
•
•
Place the magnetics as close as possible to the LXT9785/LXT9785E.
Keep transmit pair traces as short as possible; both traces should have the same length.
Avoid vias and layer changes as much as possible.
Keep the transmit and receive pairs apart to avoid cross-talk.
Route the transmit pair adjacent to a ground plane. The optimum arrangement is to place the
transmit traces two to three layers from the ground plane, with no intervening signals.
• Improve EMI performance by filtering the TPO center tap. A single ferrite bead rated at 400
mA may be used to supply center tap current to all ports.
5.2.4.1
Magnetic Requirements
The LXT9785/LXT9785E requires a 1:1 ratio for both the receive transformers and the transmit
transformers. The transmit isolation voltage should be rated at 1.5 kV to protect the circuitry from
static voltages across the connectors and cables. The LXT9785/LXT9785E is a current driven
transceiver that requires an external voltage (center tap) to drive the transmit signal. In order to
support the Auto-MDIX functionality of the LXT9785/LXT9785E, the magnetic must provide a
center tap for both the transmit and receive magnetic winding, with both connected to VCCT. See
the LXT9785/LXT9785E Design and Layout Guide (249509-001) for magnetic testing with the
LXT9785/LXT9785E. Before committing to a specific component, designers should contact the
manufacturer for current product specifications, and validate the magnetics for the specific
application. Table 50 provides the magnetics requirements.
Table 50. Intel® LXT9785/LXT9785E Magnetics Requirements
Parameter
Rx turns ratio
Nom
Max
Units
–
1:1
–
–
Test Condition
Tx turns ratio
–
1:1
–
–
Insertion loss
0.0
0.6
1.1
dB
Primary inductance
350
–
–
µH
Transformer isolation
–
2
–
kV
Differential to common mode
rejection
40
–
–
dB
.1 to 60 MHz
Return Loss
5.2.5
Min
35
–
–
dB
60 to 100 MHz
-16
–
–
dB
30 MHz
-10
–
–
dB
80 MHz
The Fiber Interface
The fiber interface consists of an LVPECL transmit and receive pair to an external fiber-optic
transceiver. Both 3.3 V fiber-optic transceivers and 5 V fiber-optic transceivers can be used with
the LXT9785/LXT9785E. See the 100BASE-FX Fiber Optic Transceivers-Connecting a PECL/
LVPECL Interface Application Note (document number 250781) for detailed information on fiber
interface designs and recommendations for Intel PHYs.
The following should occur in 3.3 V fiber transceiver applications as shown in Figure 36:
• The transmit pair should be AC-coupled with 2.5 V supplies and re-biased to 3.3 V LVPECL
levels
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
• The transmit pair should contain a balance offset in the pull-up resistors to prevent PHY-to-
fiber transceiver crosstalk amplification in power-down, loopback, and reset states (see fiber
interface application note)
• The receive pair should be DC-coupled with an emitter current path for the fiber transceiver
• The signal detect pin should be DC-coupled with an emitter current path for the fiber
transceiver
Refer to the fiber transceiver manufacturer’s recommendations for termination circuitry. Figure 36
shows a typical example of an LXT9785/LXT9785E-to-3.3 V fiber transceiver interface.
The following occurs in 5 V fiber transceiver applications as shown in Figure 37:
• The transmit pair should be AC-coupled and re-biased to 5 V PECL input levels
• The transmit pair should contain a balance offset in the pull-up resistors to prevent PHY-to-
fiber transceiver crosstalk amplification in power-down, loopback, and reset states (see fiber
interface application note)
• The receive pair should be AC-coupled with an emitter current path for the fiber transceiver
and re-biased to 1.2 V
• The signal detect pin on a 5 V fiber transceiver interface should use the logic translator
circuitry as shown in Figure 38.
Refer to the fiber transceiver manufacturer’s recommendations for termination circuitry. Figure 37
shows a typical example of an LXT9785/LXT9785E-to-5 V fiber transceiver interface, while
Figure 38 shows the interface circuitry for the logic translator.
5.2.6
LED Circuit
Each Direct Drive LED has a corresponding open-drain pin. The LEDs are connected through a
current-limiting resistor to a positive-voltage rail. The LEDs are turned on when the output pin
drives Low. The open-drain LED pins are 5 V tolerant, allowing use of either a 3.3 V or 5 V rail (a
2.5 V rail is unlikely to work with standard forward voltage LEDs). A 5 V rail eases LED
component selection by allowing more common, high-forward voltage LEDs to be used. Refer to
Figure 33 for a circuit illustration.
Figure 33. LED Circuit
VLED
R
LEDn_m
Inside Outside
IC
IC
VCCIO < VLED < 5 V + 5%
Datasheet
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
5.3
Typical Application Circuits
Figure 34 through Figure 37 on page 171 show typical application circuits for the LXT9785/
LXT9785E. Figure 38 on page 172 shows the interface circuitry for the logic translator.
Figure 34. Intel® LXT9785/LXT9785E Power and Ground Supply Connections
SGND
GNDR/GNDT
0.01µF
VCCR/VCCT
10µF
Analog Supply Plane
LXT9785/9785E
Ferrite
Bead
Digital Supply Plane
VCCD
+
10 µF
+2.5 V
0.01 µF
GNDD
0.01 µF
VCCIO
+ 2.5 V
or +3.3 V
VCCPECL
+2. 5 V
or +3.3 V
0.1 µF
GNDPECL
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Document Number: 249241
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 35. Intel® LXT9785/LXT9785E Typical Twisted-Pair Interface
TPFOP
1:1
1
1
2
3
TPFON
50 Ω
50 Ω
4
TPFIP
50 Ω
1:1
LXT9785/9785E
5
6
50 Ω
2
50 Ω
50 Ω
To Twisted-Pair Network
RJ-45
7
8
TPFIN
.01 µF
* = 0.001 µF /
2.0 kV
* = 0.001 µF /
2.0 kV
VCCT
0.1µF
.01µF
GNDA
1. The 100 Ω transmit load termination resistor typically required is integrated in the LXT9785/
LXT9785E.
2. The 100 Ω receive load termination resistor typically required is integrated in the LXT9785/
Datasheet
Document Number: 249241
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169
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 36. Recommended Intel® LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface
Circuitry
+3.3V
+2.5V
27Ω
0.01µF
− 0.1µF
50Ω
50Ω
0.01µF
− 0.1µF
1.4kΩ
1.3kΩ
0.01 µF
TD -
TPFONn
TPFOPn
TD +
0.01 µF
2kΩ
2kΩ
LXT9785(E)
3.3V
Fiber Txcvr
+3.3V
To Fiber
Network
+2.5V
130Ω
SD
SDn
82Ω
1
TPFINn
RD -
TPFIPn
RD +
130Ω
130Ω
SD_2P5V
GNDPECL
3.3V
VCCPECL
1. Refer to the transceiver manufacturers’ recommendations for termination circuitry.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 37. Recommended Intel® LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface
Circuitry
+2.5V
+5V
+2.5V
27Ω
0.01µF
− 0.1µF
50Ω
50Ω
0.01µF
− 0.1µF
1.15kΩ
1.1kΩ
0.01µF
TD -
TPFONn
0.01µF
TD +
3.1kΩ
LXT9785(E)
2
3.1kΩ
ON Semiconductor*
MC100LVEL92
PECL-to-LVPECL
Logic Translator
SDn
5V
Fiber Txcvr
To Fiber
Network
TPFOPn
SD
+2.5V
0.01µF
− 0.1µF
127Ω
1
127Ω
0.01µF
TPFINn
RD -
0.01µF
RD +
TPFIPn
118Ω
118Ω
270Ω
270Ω
SD_2P5V
GNDPECL
3.3V
VCCPECL
1. Refer to the transceiver manufacturers’ recommendations for termination circuitry.
2. See Figure 38 on page 172 for recommended logic translator interface circuitry.
Datasheet
Document Number: 249241
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 38. ON Semiconductor Triple PECL-to-LVPECL Translator
5V
0.01 µF
0.01 µF
5V
3.3V
ON Semiconductor*
PECL Input
Signal
(5V Fiber
Txcvr)
82Ω
130Ω
1
Vcc
Vcc
20
2
Q0
__
Q0
19
3
D0
__
D0
4
VBB PECL
LVCC
17
5
D1
__
D1
Q1
__
Q1
16
6
7
VBB PECL
LVCC
14
8
Q2
__
Q2
13
9
D2
__
D2
10
GND
Vcc
11
18
130Ω
LVPECL
Output Signal
(LXT9785)
82Ω
3.3V
15
12
0.01 µF
3.3V
130Ω
MC100LVEL92
82Ω
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Document Number: 249241
Revision Number: 007
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
6.0
Test Specifications
Note:
Table 51 through Table 81 and Figure 39 through Figure 62 represent the target specifications of
the LXT9785/LXT9785E. These specifications are not guaranteed and are subject to change
without notice. Minimum and maximum values listed in Table 53 through Table 81 apply over the
recommended operating conditions specified in Table 52.
Table 51. Intel® LXT9785/LXT9785E Absolute Maximum Ratings
Parameter
Supply voltage
Sym
Min
Max
Units
VCCIO, VCCPECL
-0.3
4.0
V
VCCA, VCCD
-0.3
3.0
V
TST
-65
+150
ºC
Storage temperature
Caution:
Exceeding these values may cause permanent damage. Functional operation
under these conditions is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
Table 52. Intel® LXT9785/LXT9785E Operating Conditions (Sheet 1 of 2)
Parameter
Sym
Min
Typ1
(2.5 VCCIO)
Typ1
(3.3 VCCIO)
Max
Units
Commercial
Operating
Temperature
Ambient
TOPA
0
–
–
70
ºC
Case
TOPC
0
–
–
108
ºC
Extended
Operating
Temperature
Ambient
TOPA
-40
85
ºC
Case
TOPC
-40
123
ºC
Vcca, Vccd
2.38
2.5
2.5
2.63
V
Vccio
2.38
2.5
3.3
3.46
V
3.14
N/A
3.3
3.46
V
2.38
2.5
N/A
2.63
V
810
mA
160
mA
410
mA
200
mA
765
mA
90
mA
20
mA
4
mA
540
mA
4
mA
Analog & Digital
Supply voltage2
I/O
I/O (SD_2P5V = 0)
I/O (SD_2P5V = 1)
100BASE-TX
100BASE-FX
Operating
Current - RMII3
10BASE-T
Power-Down
Mode
Hardware
Auto-Negotiation
VCCPECL
ICC
–
ICCIO
–
ICC
–
ICCIO
–
ICC
–
ICCIO
–
ICC
–
ICCIO
–
ICC
–
ICCIO
–
780
60
130
380
90
170
710
30
70
20
2
3
500
2
4
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. Voltages with respect to ground unless otherwise specified.
3. Values are aggregated for all eight ports.
Datasheet
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 52. Intel® LXT9785/LXT9785E Operating Conditions (Sheet 2 of 2)
Parameter
100BASE-TX
100BASE-FX
Operating
Current - SMII3
10BASE-T
Power-Down
Mode
Hardware
Auto-Negotiation
100BASE-TX
100BASE-FX
Operating
Current SS-SMII3
10BASE-T
Power-Down
Mode
Hardware
Auto-Negotiation
Sym
Min
ICC
–
ICCIO
–
ICC
–
ICCIO
–
ICC
–
ICCIO
–
ICC
–
ICCIO
–
ICC
–
ICCIO
–
ICC
–
ICCIO
–
ICC
–
ICCIO
–
ICC
–
ICCIO
–
ICC
–
ICCIO
–
ICC
–
ICCIO
–
Typ1
(2.5 VCCIO)
Typ1
(3.3 VCCIO)
800
70
130
380
90
170
740
60
110
50
3
5
520
20
160
mA
410
mA
200
mA
770
mA
130
mA
50
mA
5
mA
mA
835
mA
170
200
mA
410
mA
170
200
mA
780
mA
180
mA
40
mA
5
mA
570
mA
80
mA
740
150
30
3
5
530
50
mA
mA
380
90
830
30
800
90
Units
570
30
90
Max
70
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. Voltages with respect to ground unless otherwise specified.
3. Values are aggregated for all eight ports.
Table 53. Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 2.5 V +/5%)
Sym
Min
Typ1
Max
Units
Test Conditions
Input Low voltage
VIL
–
–
0.75
V
–
Input High voltage
VIH
1.75
–
–
V
–
II
-100
–
100
µA
0.0 < VI < VCC
Parameter
Input current
Output Low voltage
Output Low voltage (LEDm_n pins)
Output High voltage
VOL
–
–
0.2
V
IOL = 4 mA
VOL-LED
–
–
0.5
V
IOL = 10 mA
VOH
2.07
–
–
V
IOH = -4 mA
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 54. Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/5%)
Sym
Min
Typ1
Max
Units
Test Conditions
Input Low voltage
VIL
–
–
0.8
V
–
Input High voltage
VIH
2.0
–
–
V
–
II
-100
–
100
µA
0.0 < VI < VCC
Parameter
Input current
Output Low voltage
Output Low voltage (LEDm_n pins)
VOL
–
–
0.2
V
IOL = 4 mA
VOL-LED
–
–
0.5
V
IOL = 10 mA
VOH
2.4
–
–
V
IOH = -4 mA
Output High voltage
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
Table 55. Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics – SD Pins
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
2.5 V Operation
Input Low voltage
VIL
0.69
0.8
1.03
V
VCCPECL = 2.5 V
Input High voltage
VIH
1.34
1.6
1.62
V
VCCPECL = 2.5 V
3.3 V Operation
Input Low voltage
VIL
1.49
1.6
1.83
V
VCCPECL = 3.3 V
Input High voltage
VIH
2.14
2.4
2.42
V
VCCPECL = 3.3 V
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. For 2.5 V operation, SD_2P5V = VCCPECL and VCCPECL=2.5 V.
3. For 3.3 V operation, SD_2P5V = GNDPECL or Floating and VCCPECL=3.3 V.
Table 56. Intel® LXT9785/LXT9785E Required Clock Characteristics
Parameter
SMII Input frequency
RMII Input frequency
Sym
Min
Typ2
Max
Units
Test Conditions
f
–
125
–
MHz
–
f
–
50
–
MHz
–
∆f
–
–
± 50
ppm
–
Input clock duty cycle
Tdc
35
50
65
%
RMII selection
Input clock duty cycle - REFCLK,
TxCLK1
Tdc
40
50
60
%
SMII/SS-SMII selection
Output RxCLK duty cycle
Tdc
45
50
55
%
SS-SMII only
Input clock frequency tolerance1
1
1. Parameter is guaranteed by design; not subject to production testing.
2. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 57. Intel® LXT9785/LXT9785E 100BASE-TX Transceiver Characteristics
Sym
Min
Typ1
Max
Units
Test Conditions
Peak differential output
voltage
VP
0.95
–
1.05
V
Note 2
Signal amplitude symmetry
Parameter
Vss
98
–
102
%
Note 2
Signal rise/fall time
trf
3
–
5
ns
Note 2
Rise/fall time symmetry
trfs
–
–
0.5
ns
Note 2
–
–
–
+/- 0.5
ns
Offset from 16 ns pulse
width at 50% of pulse
peak
Overshoot
VO
–
–
5
%
–
Jitter magnitude (measured
differentially)
ttx-jit
–
–
1.4
ns
–
Duty cycle distortion
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. Measured at the line side of the transformer, line replaced by 100Ω (+/-1%) resistor.
Table 58. Intel® LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics
Parameter
Sym
Typ1
Min
Max
Units
Test Conditions
Transmitter
Peak-to-peak differential
output voltage
Signal rise/fall time
Jitter magnitude (measured
differentially)
VDIFFP-P
0.6
1.44
–
V
–
trf
–
–
1.8
ns
Note 2
ttx-jit
–
–
1.4
ns
–
Receiver
Peak differential input
voltage
0.55
–
–
V
–
VCMIR
–
–
VCC - 0.5
V
–
Input Low Voltage (SD pins)
VIL
VCC
-1.84
VCC
-1.63
V
–
Input High Voltage (SD Pins)
VIH
VCC
-1.04
VCC
-0.88
V
–
Common mode input range
VIP
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. 20 - 80 percent into 100 Ω equivalent load of a typical fiber transceiver.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 59. Intel® LXT9785/LXT9785E 10BASE-T Transceiver Characteristics
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
Transmitter
Peak differential output voltage
Link transmit period
Jitter magnitude added by the
MAU and PLS sections 3, 4
VOP
2.2
2.5
2.8
V
Note 2
–
8
–
24
ms
–
ttx-jit
–
–
11
ns
–
–
W
Between TPFIP and
TPFIN
Receiver
Receive input impedance3
ZIN
–
100
Link min receive timer
TLRmin
2
–
7
ms
–
Link max receive timer
TLRmax
50
–
150
ms
–
VDS
–
475
–
mV Peak
5 MHz square wave
input
Differential squelch threshold
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. Parameter is guaranteed by design; not subject to production testing.
3. IEEE 802.3 specifies maximum jitter addition at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5
ns from the MAU.
4. After line model specified by IEEE 802.3 for 10BASE-T MAU.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
177
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 39. Intel® LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing
REFCLK
t5
t6
SYNC
t1
t2
RxData
t3
t4
TPFI
Table 60. Intel® LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Parameters
Sym
Min
Typ1
Max
Units
RxData output delay from REFCLK
rising edge
t1
1.5
–
5
ns
RxData Rise/Fall Time
t2
–
1.0
–
ns
Receive start of /J/ to CRS asserted
t3
–
21
29
BT2
Synchronous sampling of
SMII
Receive start of /T/ to CRS deasserted
t4
–
25
30
BT2
Synchronous sampling of
SMII
SYNC setup to REFCLK rising edge
t5
1.5
–
–
ns
–
SYNC hold from REFCLK rising edge
t6
1.0
–
–
ns
–
Parameter
Test Conditions
Minimum CL = 5 pF
Maximum CL = 20 pF
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
178
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 40. Intel® LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing
REFCLK
t1
t2
SYNC
t1
t2
TxData
t3
TPFO
Table 61. Intel® LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing Parameters
Sym
Min
Typ1
Max
Units
Test
Conditions
SYNC setup to REFCLK rising edge and
TxData setup to REFCLK rising edge
t1
1.5
–
–
ns
–
SYNC hold from REFCLK rising edge and
TxData hold from REFCLK rising edge
t2
1.0
–
–
ns
–
TxEN sampled to start of /J/
t3
–
11
18
BT2
–
Parameter
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
179
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 41. Intel® LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing
REFCLK
t5
t6
SYNC
t1
t2
RxData
t3
t4
TPFI
Table 62. Intel® LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing Parameters
Sym
Min
Typ1
Max
Units
Test Conditions
RxData output delay from REFCLK
rising edge
t1
1.5
–
5
ns
Minimum CL = 5 pF
Maximum CL = 20 pF
RxData Rise/Fall Time
t2
–
1
–
ns
–
Receive start of /J/ to CRS asserted
t3
–
18
26
BT2
Synchronous
sampling of SMII
Receive start of /T/ to CRS deasserted
t4
–
23
27
BT2
Synchronous
sampling of SMII
SYNC setup to REFCLK rising edge
t5
1.5
–
–
ns
–
SYNC hold from REFCLK rising edge
t6
1.0
–
–
ns
–
Parameter
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
180
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 42. Intel® LXT9785/LXT9785E SMII - 100BASE-FX Transmit Timing
REFCLK
t1
t2
SYNC
t1
t2
TxData
t3
TPFO
Table 63. Intel® LXT9785/LXT9785E SMII - 100BASE-FX Transmit Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
SYNC setup to REFCLK rising edge and
TxData setup to REFCLK rising edge
t1
1.5
–
–
ns
–
SYNC hold from REFCLK rising edge
and TxData hold from REFCLK rising
edge
t2
1.0
–
–
ns
–
TxEN sampled to start of /J/
t3
–
10
17
BT2
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
181
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 43. Intel® LXT9785/LXT9785E SMII - 10BASE-T Receive Timing
REFCLK
t5
t6
SYNC
t1
t2
RxData
t3
t4
TPFI
Table 64. Intel® LXT9785/LXT9785E SMII - 10BASE-T Receive Timing Parameters
Sym
Min
Typ1
Max
Units
RxData output delay from
REFCLK rising edge
t1
1.5
–
5
ns
RxData Rise/Fall Time
t2
–
1
–
ns
Receive Start-of-Frame to CRS
asserted
t3
–
17
21
BT3
Synchronous sampling of SMII2
Receive Start-of-Idle to CRS
de-asserted
t4
–
17
18
BT3
Synchronous sampling of SMII2
SYNC setup to REFCLK rising
edge
t5
1.5
–
–
ns
–
SYNC hold from REFCLK rising
edge
t6
1.0
–
–
ns
–
Parameter
Test Conditions
Minimum CL = 5 pF
Maximum CL = 20 pF
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. Assumes each SMII segment is sampled for CRS.
3. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
182
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 44. Intel® LXT9785/LXT9785E SMII - 10BASE-T Transmit Timing
REFCLK
t1
t2
SYNC
t1
t2
TxData
t3
TPFO
Table 65. Intel® LXT9785/LXT9785E SMII-10BASE-T Transmit Timing Parameters
Sym
Min
Typ1
Max
Units
Test
Conditions
SYNC setup to REFCLK rising edge and
TxData setup to REFCLK rising edge
t1
1.5
–
–
ns
–
SYNC hold to REFCLK rising edge and
TxData hold from REFCLK rising edge
t2
1.0
–
–
ns
–
TxEN sampled to start-of-frame
t3
–
10
14
BT2
–
Parameter
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
183
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 45. Intel® LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing
REFCLK
t1
RxCLK
t2
RxSYNC
t3
t3
t3
RxData
t4
t5
TPFI
Table 66. Intel® LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing Parameters
Sym
Min
Typ1
Max
Units
Test Conditions
REFCLK rising edge to RxCLK
rising edge
t1
–
1.5
–
ns
–
RxData/RxSYNC output delay
from RxCLK rising edge
t2
1.5
–
5
ns
Minimum CL = 5pF
Maximum CL = 40pF
RxData/RxSYNC Rise/Fall time
t3
–
1.0
–
ns
–
Receive start of /J/ to CRS
asserted
t4
–
21
27
BT2
–
Receive start of /T/ to CRS
de-asserted
t5
–
25
30
BT2
–
Parameter
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
184
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 46. Intel® LXT9785/LXT9785E SS-SMII - 100BASE-TX Transmit Timing
TxCLK
t1
t2
TxSYNC
t1
t2
TxData
t3
TPFO
Table 67. Intel® LXT9785/LXT9785E SS-SMII - 100BASE-TX Transmit Timing
Sym
Min
Typ1
Max
Units
Test
Conditions
TxSYNC setup to TxCLK rising edge and
TxData setup to TxCLK rising edge
t1
1.5
–
–
ns
–
TxSYNC hold from TxCLK rising edge and
TxData hold to TxCLK rising edge
t2
1.0
–
–
ns
–
TxEN sampled to start of /J/
t3
–
11
18
BT2
–
Parameter
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
185
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 47. Intel® LXT9785/LXT9785E SS-SMII - 100BASE-FX Receive Timing
REFCLK
t1
RxCLK
t2
RxSYNC
t3
t3
t3
RxData
t4
t5
TPFI
Table 68. Intel® LXT9785/LXT9785E SS-SMII - 100BASE-FX Receive Timing Parameters
Parameter
Sym
Min
Typ1
REFCLK rising edge to RxCLK rising edge
t1
–
1.5
RxData/RxSYNC output delay from RxCLK
rising edge
t2
1.5
–
Max
5
Units
Test Conditions
ns
–
ns
Minimum CL = 5pF
Maximum CL = 40pF
RxData/RxSYNC Rise/Fall time
t3
–
1
–
ns
–
Receive start of /J/ to CRS asserted
t4
–
18
23
BT2
–
Receive start of /T/ to CRS de-asserted
t5
–
21
26
BT2
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
186
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 48. Intel® LXT9785/LXT9785E SS-SMII - 100BASE-FX Transmit Timing
TxCLK
t1
t2
TxSYNC
t1
t2
TxData
t3
TPFO
Table 69. Intel® LXT9785/LXT9785E SS-SMII - 100BASE-FX Transmit Timing Parameters
Sym
Min
Typ1
Max
Units
Test Conditions
TxSYNC setup to TxCLK rising edge and
TxData setup to TxCLK rising edge
t1
1.5
–
–
ns
–
TxSYNC hold from TxCLK rising edge and
TxData hold to TxCLK rising edge
t2
1.0
–
–
ns
–
TxData to TPFO Latency
t3
–
11
13
BT2
–
Parameter
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
187
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 49. Intel® LXT9785/LXT9785E SS-SMII - 10BASE-T Receive Timing
REFCLK
t1
RxCLK
t2
RxSYNC
t3
RxData
t4
t5
TPFI
Table 70. Intel® LXT9785/LXT9785E SS-SMII - 10BASE-T Receive Timing Parameters
Sym
Min
Typ1
Max
Units
Test Conditions
REFCLK rising edge to RxCLK rising
edge
t1
–
1.5
–
ns
–
RxData/RxSYNC output delay from
RxCLK rising edge
t2
1.5
–
5
ns
RxData/RxSYNC Rise/Fall time
t3
–
1
–
ns
–
Receive Start-of-Frame to CRS asserted
t4
–
10
11
BT3
Synchronous sampling of
SMII2
Receive Start-of-Idle to CRS de-asserted
t5
–
18
21
BT3
Synchronous sampling of
SMII2
Parameter
Minimum CL = 5pF
Maximum CL = 40pF
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. Assumes each SMII segment is sampled for CRS.
3. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
188
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 50. Intel® LXT9785/LXT9785E SS-SMII - 10BASE-T Transmit Timing
TxCLK
t1
t2
TxSYNC
t1
t2
TxData
t3
TPFO
Table 71. Intel® LXT9785/LXT9785E SS-SMII - 10BASE-T Transmit Timing Parameters
Sym
Min
Typ1
Max
Units
Test
Conditions
TxSYNC setup to TxCLK rising edge and
TxData setup to TxCLK rising edge
t1
1.5
–
–
ns
–
TxSYNC hold to TxCLK rising edge and TxData
hold from TxCLK rising edge
t2
1.0
–
–
ns
–
TxData to TPFO Latency
t3
–
10
14
BT2
–
Parameter
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
189
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 51. Intel® LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing
REFCLK
t1
t2
RxData[1:0]
TPFI
t3
t4
CRS_DV
Table 72. Intel® LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing Parameters
Sym
Min
Typ1
Max
Units
Test
Conditions
RxData<1:0>, CRS_DV, RXER setup to REFCLK
rising edge3
t1
4
–
14
ns
–
RxData<1:0>, CRS_DV, RXER hold from REFCLK
rising edge3
t2
2
–
14
ns
–
Receive start of /J/ to CRS_DV asserted
t3
–
16
21
BT2
–
27
2
–
Parameter
Receive start of /T/ to CRS_DV de-asserted
t4
–
20
BT
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
3. Values and conditions from RMII Specification, Rev. 1.2.
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
190
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 52. Intel® LXT9785/LXT9785E RMII - 100BASE-TX Transmit Timing
REFCLK
t1
t2
TxData(1:0)
TPFO
t1
t3
t2
TxEN
Table 73. Intel® LXT9785/LXT9785E RMII - 100BASE-TX Transmit Timing Parameters
Sym
Min
Typ1
Max
Units
Test
Conditions
TxData<1:0>/TxEN setup to REFCLK rising
edge
t1
4
–
–
ns
–
TxData<1:0>/TxEN hold from REFCLK rising
edge
t2
2
–
–
ns
–
TxEN sampled to TPFO out (Tx latency)
t3
–
12
17
BT2
–
Parameter
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
191
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 53. Intel® LXT9785/LXT9785E RMII - 100BASE-FX Receive Timing
REFCLK
t1
t2
RxData[1:0]
TPFI
t3
t4
CRS_DV
Table 74. Intel® LXT9785/LXT9785E RMII - 100BASE-FX Receive Timing Parameters
Sym
Min
Typ1
Max
Units
Test
Conditions
RxData<1:0>, CRS_DV, RXER setup to
REFCLK rising edge3
t1
4
–
14
ns
–
RxData<1:0>, CRS_DV, RXER hold from
REFCLK rising edge3
t2
2
–
14
ns
–
Receive start of /J/ to CRS_DV asserted
t3
–
14
18
BT2
–
25
2
–
Parameter
Receive start of /T/ to CRS_DV de-asserted
t4
–
18
BT
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
3. Values and conditions from RMII Specification, Rev. 1.2.
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
192
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 54. Intel® LXT9785/LXT9785E RMII - 100BASE-FX Transmit Timing
REFCLK
t1
t2
TxData(1:0)
TPFO
t1
t3
t2
TxEN
Table 75. Intel® LXT9785/LXT9785E RMII - 100BASE-FX Transmit Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test
Conditions
TxData<1:0>/TxEN setup to REFCLK rising edge
t1
4
–
–
ns
–
TxData<1:0>/TX-EN hold from REFCLK rising
edge
t2
2
–
–
ns
–
TxEN sampled to TPFO out (Tx latency)
t3
–
10
12
BT2
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
193
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 55. Intel® LXT9785/LXT9785E RMII - 10BASE-T Receive Timing
REFCLK
t1
t2
RxData[1:0]
TPFI
t3
t4
CRS_DV
Table 76. Intel® LXT9785/LXT9785E RMII - 10BASE-T Receive Timing Parameters
Sym
Min
Typ1
Max
Units
Test
Conditions
RxData<1:0>, CRS_DV setup to REFCLK rising
edge3
t1
4
–
14
ns
–
RxData<1:0>, CRS_DV hold from REFCLK rising
edge3
t2
2
–
14
ns
–
TPFI in to CRS_DV asserted
t3
1.5
3
4
BT2
–
2
–
Parameter
TPFI quiet to CRS_DV de-asserted
t4
12
15
16
BT
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
3. Values and conditions from RMII Specification, Rev. 1.2.
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
194
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 56. Intel® LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing
REFCLK
t1
t2
TxData(1:0)
TPFO
t1
t3
t2
TxEN
Table 77. Intel® LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing Parameters
Sym
Min
Typ1
Max
Units
Test
Conditions
TxData<1:0>/TxEN setup to REFCLK rising
edge
t1
4
–
–
ns
–
TxData<1:0>/TxEN hold from REFCLK rising
edge
t2
2
–
–
ns
–
TxEN sampled to TPFO out (Tx latency)
t3
–
8.5
14
BT2
–
Parameter
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
Datasheet
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Revision Number: 007
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 57. Intel® LXT9785/LXT9785E Auto-Negotiation and Fast Link Pulse Timing
Clock Pulse
Data Pulse
Clock Pulse
TPFOP
t1
t1
t2
t3
Figure 58. Intel® LXT9785/LXT9785E Fast Link Pulse Timing
FLP Burst
FLP Burst
TPFOP
t4
t5
Table 78. Intel® LXT9785/LXT9785E Auto-Negotiation and Fast Link Pulse Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
Clock/Data pulse width
t1
–
100
–
ns
–
Clock pulse to Data pulse
t2
55.5
–
69.5
µs
–
Clock pulse to Clock pulse
t3
111
–
139
µs
–
FLP burst width
t4
–
2
–
ms
–
FLP burst to FLP burst
t5
8
–
24
ms
–
Clock/Data pulses per burst
–
17
–
33
ea
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
196
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 59. Intel® LXT9785/LXT9785E MDIO Write Timing (MDIO Sourced by MAC)
MDC
t2
t1
MDIO
Figure 60. Intel® LXT9785/LXT9785E MDIO Read Timing (MDIO Sourced by PHY)
MDC
t3
MDIO
Table 79. Intel® LXT9785/LXT9785E MDIO Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
MDIO setup before MDC, sourced by
STA
t1
10
–
–
ns
–
MDIO hold after MDC,
sourced by STA
t2
10
–
–
ns
–
MDC to MDIO output delay, sourced
by PHY
t3
0
–
40
ns
–
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
testing.
Datasheet
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197
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 61. Intel® LXT9785/LXT9785E Power-Up Timing
v1
VCC
tPDR
MDIO,etc
Table 80. Intel® LXT9785/LXT9785E Power-Up Timing Parameters
Sym
Min
Typ1
Max
Units
Test Conditions
v1
2.1
–
–
V
–
Power-up recovery time
tPDR
100
–
–
ms
–
Software power-down2
tSPDR
20
–
–
ms
–
Parameter
Voltage Threshold
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
testing.
2. The minimum time required between bringing up consecutive ports powered down by Register bit 0.11, or
a software or hardware reset.
Figure 62. Intel® LXT9785/LXT9785E Reset Recovery Timing
tPW
RESET
tRcdly
MDIO,etc
Table 81. Intel® LXT9785/LXT9785E Reset Recovery Timing Parameters
Parameter
Reset pulse width
Reset recovery delay
Sym
Min
Typ1
Max
Units
Test Conditions
tPW
10
–
–
ns
–
tRcdly
0.4
–
–
ms
–
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
testing.
198
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
7.0
Register Definitions
The LXT9785/LXT9785E register set includes multiple 16-bit registers, 18 registers per port.
Table 82 presents a complete register listing. Table 83, “Control Register (Address 0)” on page 200
through Table 100, “Cable Diagnostics Register (Address 29, Hex 1D)” on page 217 define
individual registers and Table 101, “Intel® LXT9785/LXT9785E Register Bit Map” on page 219
provides a consolidated memory map of all registers.
Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and
Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps AutoNegotiation” sections of the IEEE 802.3 standard.
Additional registers (16 through 21, 25, 27, and 29) are defined in accordance with the IEEE 802.3
standard for adding unique chip functions.
The BGA15 package on some registers has different default values. Some LXT9785 features are
not available on the BGA15 package. These differences are called out in the register description
and in the table notes in individual register tables.
Table 82. Intel® LXT9785/LXT9785E Register Set (Sheet 1 of 2)
Address
Register Name
Bit Assignments
0
“Control Register (Address 0)”
Refer to Table 83 on page 200
1
“Status Register (Address 1)”
Refer to Table 84 on page 201
2
“PHY Identification Register 1 (Address 2)”
Refer to Table 85 on page 203
3
“PHY Identification Register 2 (Address 3)”
Refer to Table 86 on page 203
4
“Auto-Negotiation Advertisement Register (Address 4)”
Refer to Table 87 on page 204
5
“Auto-Negotiation Link Partner Base Page Ability Register
(Address 5)”
Refer to Table 88 on page 205
6
“Auto-Negotiation Expansion Register (Address 6)”
Refer to Table 89 on page 206
7
“Auto-Negotiation Next Page Transmit Register (Address 7)”
Refer to Table 90 on page 206
8
“Auto-Negotiation Link Partner Next Page Receive Register
(Address 8)”
Refer to Table 91 on page 207
9
1000BASE-T/100BASE-T2 Control
Not Implemented
10
1000BASE-T/100BASE-T2 Status
Not Implemented
15
Extended Status
Not Implemented
16
“Port Configuration Register (Address 16, Hex 10)”
Refer to Table 92 on page 207
17
“Quick Status Register (Address 17, Hex 11)”
Refer to Table 93 on page 209
18
“Interrupt Enable Register (Address 18, Hex 12)”
Refer to Table 94 on page 211
19
“Interrupt Status Register (Address 19, Hex 13)”
Refer to Table 95 on page 212
20
“LED Configuration Register (Address 20, Hex 14)”
Refer to Table 96 on page 213
21
“Receive Error Count Register (Address 21, Hex 15)”
Refer to Table 97 on page 214
22-24
Reserved
N/A
25
“RMII Out-of-Band Signaling Register (Address 25, Hex 19)”
Refer to Table 98 on page 215
26
Reserved
N/A
Datasheet
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199
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 82. Intel® LXT9785/LXT9785E Register Set (Sheet 2 of 2)
Address
Register Name
Bit Assignments
27
“Trim Enable Register (Address 27, Hex 1B)”
Refer to Table 99 on page 216
28
Reserved
N/A
29
“Cable Diagnostics Register (Address 29, Hex 1D)”
Refer to Table 100 on page 217
Reserved
N/A
30 - 31
Table 83. Control Register (Address 0) (Sheet 1 of 2)
Bit
Name
Description
15
RESET
0 = Normal operation
1 = PHY reset
Type1
R/W
SC
Default
02
0 = Disable loopback mode
1 = Enable loopback mode
14
Loopback
Not recommended to enable auto-negotiation
while in internal loopback operation.
0.6
1
1
0
0
1 = Reserved
0 = 1000 Mbps (not allowed)
1 = 100 Mbps
0 = 10 Mbps
Speed Selection
12
Auto-Negotiation
Enable
0 = Disable auto-negotiation process
1 = Enable auto-negotiation process
11
Power-Down
0 = Normal operation
1 = Power-down
10
Isolate
8
Restart
Auto-Negotiation
Duplex Mode
0
R/W
LSHR3,4
R/W
LSHR3,4
R/W
LSHR3,5
R/W
0
0.13
13
9
R/W
0 = Normal operation
1 = Electrically isolate PHY from RMII/SMII/SSSMII interfaces
0 = Normal operation
1 = Restart auto-negotiation process
0 = Half-duplex
1 = Full-duplex
R/W
SC
R/W
0
LSHR3,4
1. R/W = Read/Write, SC = Self Clearing when operation complete.
2. During a hardware reset, all LHR information is latched in from the pins. During a software reset (0.15), the
LSHR information is not re-read from the pins. This information reverts back to the information that was
read in during the hardware reset. During a hardware rest, register information is unavailable from 1 ms
after de-assertion of the reset. During a software reset (0.15) the registers are available for reading. The
reset bit should be polled to see when the part has completed reset.
3. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
the pin(s) are latched at startup or hardware reset.
4. Default value of Register bits 0.12, 0.13, and 0.8 are determined by the CFG pins as described in Table 42,
“Intel® LXT9785/9785E Global Hardware Configuration Settings” on page 129.
5. Default value of Register bit 0.11 is determined by the LINKHOLD configuration pin.
200
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 83. Control Register (Address 0) (Sheet 2 of 2)
Bit
Name
Description
Type1
Default
R/W
0
R/W
0
R/W
000000
This bit is ignored by the LXT9785/LXT9785E
7
Collision Test
6
Speed Selection
1000 Mbps
0 = Disable COL signal test
1 = Enable COL signal test
0.6
5:0
Reserved
1
1
0
0
0.13
1 = Reserved
0 = 1000 Mbps (not allowed)
1 = 100 Mbps
0 = 10 Mbps
Write as 0, ignore on Read
1. R/W = Read/Write, SC = Self Clearing when operation complete.
2. During a hardware reset, all LHR information is latched in from the pins. During a software reset (0.15), the
LSHR information is not re-read from the pins. This information reverts back to the information that was
read in during the hardware reset. During a hardware rest, register information is unavailable from 1 ms
after de-assertion of the reset. During a software reset (0.15) the registers are available for reading. The
reset bit should be polled to see when the part has completed reset.
3. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
the pin(s) are latched at startup or hardware reset.
4. Default value of Register bits 0.12, 0.13, and 0.8 are determined by the CFG pins as described in Table 42,
“Intel® LXT9785/9785E Global Hardware Configuration Settings” on page 129.
5. Default value of Register bit 0.11 is determined by the LINKHOLD configuration pin.
Table 84. Status Register (Address 1)
Type1,2
Default
0 = PHY not able to perform 100BASE-T4
1 = PHY able to perform 100BASE-T4
R
0
100BASE-X
Full-Duplex
0 = PHY not able to perform full-duplex 100BASE-X
1 = PHY able to perform full-duplex 100BASE-X
R
1
13
100BASE-X
Half-Duplex
0 = PHY not able to perform half-duplex 100BASE-X
1 = PHY able to perform half-duplex 100BASE-X
R
1
12
10 Mbps Full-Duplex
0 = PHY not able to operate at 10 Mbps in full-duplex
mode
1 = PHY able to operate at 10 Mbps in full-duplex
mode
R
1
11
10 Mbps Half-Duplex
0 = PHY not able to operate at 10 Mbps in half-duplex
1 = PHY able to operate at 10 Mbps in half-duplex
mode
R
1
10
100BASE-T2
Full-Duplex
0 = PHY not able to perform full-duplex 100BASE-T2
1 = PHY able to perform full-duplex 100BASE-T2
R
0
9
100BASE-T2
Half-Duplex
0 = PHY not able to perform half-duplex 100BASE-T2
1 = PHY able to perform half-duplex 100BASE-T2
R
0
8
Extended Status
0 = No extended status information in Register 15
1 = Extended status information in Register 15
R
0
7
Reserved
Write as 0, ignore on Read
R
0
MF Preamble
Suppression
0 = PHY will not accept management frames with
preamble suppressed
1 = PHY accepts management frames with preamble
suppressed
R
0
Bit
Name
Description
15
100BASE-T4
14
6
1. R = Read Only
2. Bits that Latch High (LH) or Latch Low (LL) automatically clear when read.
Datasheet
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201
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 84. Status Register (Address 1)
Bit
Type1,2
Default
R
0
R/LL
0
R
1
0 = Link is down
1 = Link is up
R/LL
0
Jabber Detect
0 = Jabber condition not detected
1 = Jabber condition detected
R/LH
0
Extended Capability
0 = Basic register capabilities
1 = Extended register capabilities
R
1
Name
Description
5
Auto-Negotiation
complete
0 = Auto-negotiation not complete
1 = Auto-negotiation complete
4
Remote Fault
0 = No remote fault condition detected
1 = Remote fault condition detected
3
Auto-Negotiation
Ability
0 = PHY is not able to perform auto-negotiation
1 = PHY is able to perform auto-negotiation
2
Link Status
1
0
1. R = Read Only
2. Bits that Latch High (LH) or Latch Low (LL) automatically clear when read.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 85. PHY Identification Register 1 (Address 2)
Bit
15:0
Name
Description
PHY ID Number
The PHY identifier composed of bits 3 through 18 of the
OUI
Type1
Default
R
0013 hex
1. R = Read Only
Table 86. PHY Identification Register 2 (Address 3)
Type1
Default
The PHY identifier composed of bits 19 through 24 of
the OUI
R
011110
Manufacturer’s
Model Number
6 bits containing manufacturer’s part number
R
001111
3:1
Manufacturer’s
Revision
Number
3 bits containing manufacturer’s revision number
R
XXX2
0
Model Variant
0 = LXT9785
1 = LXT9785/LXT9785E
R
X2
Bit
Name
Description
15:10
PHY ID Number
9:4
1. R = Read Only
2. Refer to the Identification Information section in the Intel® LXT9785/LXT9785E Specification Update.
Figure 63. PHY Identifier Bit Mapping
a
b
r
c
s
x
Organizationally Unique Identifier
1
2
18 19
3
0
I/G
0
1
24
3
15
15
0
10
PHY ID Register #1 (Address 2)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
9
4
0
2
1
0
1
1
1
B
1
1
0
X
X
X
X
X
0
20
The Intel OUI is 00207B hex.
X
X
0
3
X
X
X
1
0
7
5
00
3
PHY ID Register #2 (Address 3)
7B
Manufacturer's
Model Number
Revision
Number
Model
Variant
Datasheet
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 87. Auto-Negotiation Advertisement Register (Address 4)
Bit
Name
Type1
Default
R/W
0
R
0
0 = No remote fault
1 = Remote fault
R/W
0
Write as 0, ignore on Read
R/W
0
R/W
0
R/W
LSHR2,3
R/W
0
Description
0 = Port has no ability to send manual next pages
1 = Port has ability to send manual next pages
15
Next Page
Note: This bit should only be set to manually control the autonegotiation process. It is not needed and should be cleared
for DTE Discovery.
14
Reserved
Write as 0, ignore on Read
136
Remote Fault
12
Reserved
11
Asymmetric
Pause
10
Pause5
Pause operation defined in Clause 40 and 27
0 = Port is not Pause capable
1 = Port can only send Pause
0 = Pause operation disabled
1 = Port can send and receive Pause
NOTE: Default for the BGA15 package is 0.
0 = 100BASE-T4 capability is not available
1 = 100BASE-T4 capability is available
(The LXT9785/LXT9785E does not support 100BASE-T4 but
allows this bit to be set to advertise in the auto-negotiation
sequence for 100BASE-T4 operation. An external
100BASE-T4 transceiver could be switched in if this
capability is desired.)
9
100BASE-T4
8
100BASE-TX
Full-Duplex
0 = Port is not 100BASE-TX full-duplex capable.
1 = Port is 100BASE-TX full-duplex capable
R/W
LSHR2,4
7
100BASE-TX
Half-Duplex
0 = Port is not 100BASE-TX half-duplex capable
1 = Port is 100BASE-TX half-duplex capable
R/W
LSHR2,4
6
10BASE-T
Full-Duplex
0 = Port is not 10BASE-T full-duplex capable
1 = Port is 10BASE-T full-duplex capable
R/W
LSHR2,4
5
10BASE-T
Half-Duplex
0 = Port is not 10BASE-T half-duplex capable
1 = Port is 10BASE-T half-duplex capable
R/W
LSHR2,4
4:0
Selector
Field,
S<4:0>
<00001> = IEEE 802.3
<00010> = IEEE 802.9 ISLAN-16T
<00000> = Reserved for future auto-negotiation development
<11111> = Reserved for future auto-negotiation development
Unspecified or reserved combinations should not be
transmitted
R/W
00001
1. R/W = Read/Write, R = Read Only
2. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
the pin(s) are latched at startup or hardware reset.
3. The default setting of Register bit 4.10 is determined by the PAUSE pin. The BGA15 package does not
have a Pause hardware configuration pin and has a default of 0.
4. Default settings for bits 4.5:8 are determined by CFG pins as described in Table 42, “Intel® LXT9785/
9785E Global Hardware Configuration Settings” on page 129.
5. Pause operation is only valid for full-duplex modes.
6. If Register bit 4.13 is set to advertise a fault, Register bit 1.4 will be set.
NOTE: Restart the auto-negotiation process whenever Register 4 is written/modified.
204
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 88. Auto-Negotiation Link Partner Base Page Ability Register (Address 5)
Type1
Default2
0 = Link partner has no ability to send multiple pages
1 = Link partner has ability to send multiple pages
R
0
Acknowledge
0 = Link partner has not received Link Code Word from the
the LXT9785/LXT9785E
1 = Link partner has received Link Code Word from the
LXT9785/LXT9785E.
R
0
13
Remote Fault
0 = No remote fault
1 = Remote fault
R
0
12
Reserved
Write as 0, ignore on Read
R
0
11
Asymmetric
Pause
R
0
10
Pause
0 = Link partner is not Pause capable
1 = Link partner can send and receive Pause
R
0
9
100BASE-T4
0 = Link partner is not 100BASE-T4 capable
1 = Link partner is 100BASE-T4 capable
R
0
8
100BASE-TX
Full-Duplex
0 = Link partner is not 100BASE-TX full-duplex capable
1 = Link partner is 100BASE-TX full-duplex capable
R
0
7
100BASE-TX
0 = Link partner is not 100BASE-TX capable
1 = Link partner is 100BASE-TX capable
R
0
0 = Link partner is not 10BASE-T full-duplex capable
1 = Link partner is 10BASE-T full-duplex capable
R
0
10BASE-T
0 = Link partner is not 10BASE-T capable
1 = Link partner is 10BASE-T capable
R
0
Selector Field
S<4:0>
<00001> = IEEE 802.3
<00010> = IEEE 802.9 ISLAN-16T
<00000> = Reserved for future auto-negotiation development
<11111> = Reserved for future auto-negotiation development
Unspecified or reserved combinations shall not be transmitted
R
00000
Bit
Name
Description
15
Next Page
14
6
5
4:0
10BASE-T
Full-Duplex
Pause operation defined in Clause 40 and 27
0 = Link partner is not Pause capable
1 = Link partner can only send Pause
1. R = Read Only
2. Default value at the start of auto-negotiation code word transmission.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
205
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 89. Auto-Negotiation Expansion Register (Address 6)
Bit
15:5
Name
Description
Type1
Default
Reserved
Write as 0, ignore on Read
R
0x000
4
Parallel
Detection Fault
0 = Parallel detection fault has not occurred
1 = Parallel detection fault has occurred
R/
LH
0
3
Link Partner
Next Page Able
0 = Link partner is not next page able
1 = Link partner is next page able
R
0
2
Next Page Able
0 = Local device is not next page able
1 = Local device is next page able
R
1
R/
LH
0
R
0
Type1
Default
R/W
0
R
0
Indicates that a new page has been received and the
received code word has been loaded into Register 5 or
Register 8 as specified in clause 28 of 802.3.
1
Page Received
0 = Three identical and consecutive link code words have
not been received from link partner
1 = Three identical and consecutive link code words have
been received from link partner
0
Link Partner
A/N Able
0 = Link partner is not auto-negotiation able
1 = Link partner is auto-negotiation able
1. R = Read Only, LH = Latching High – cleared when read
Table 90. Auto-Negotiation Next Page Transmit Register (Address 7)
Bit
15
14
13
12
11
10:0
Name
Description
Next Page
(NP)
0 = Last page
1 = Additional next pages follow
Reserved
Write as 0, ignore on Read.
Message Page
0 = Unformatted page
1 = Message page
R/W
1
0 = Cannot comply with message
1 = Complies with message
R/W
0
R
0
R/W
0000000
0001
(MP)
Acknowledge 2
(ACK2)
Toggle
(T)
Message/
Unformatted
Code Field
0 = Previous value of the transmitted link code word
equalled logic one
1 = Previous value of the transmitted link code word
equalled logic zero
MP = 0: Code interpreted as “unformatted page”
MP = 1: Code interpreted as “message page”
1. R/W = Read Write, R = Read Only
206
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 91. Auto-Negotiation Link Partner Next Page Receive Register (Address 8)
Bit
15
14
13
12
11
10:0
Type1
Default2
0 = Link partner has no additional next pages to send
1 = Link partner has additional next pages to send
R
0
0 = Link partner has not received Link Code Word from
the LXT9785/LXT9785E
1 = Link partner has received Link Code Word from the
LXT9785/LXT9785E
R
0
0 = Page sent by the link partner is an unformatted page
1 = Page sent by the link partner is a message page
R
0
0 = Link partner cannot comply with the message
1 = Link partner complies with the message
R
0
0 = Previous value of the transmitted Link Code Word
equalled logic one
1 = Previous value of the transmitted Link Code Word
equalled logic zero
R
0
MP = 1: Code interpreted as message page
MP = 0: Code interpreted as unformatted page
R
0x000
Type 1
Default
R/W
0
R/W
0
Name
Description
Next Page
(NP)
Acknowledge
(ACK)
Message Page
(MP)
Acknowledge 2
(ACK2)
Toggle
(T)
Message/
Unformatted
Code Field
1. R = Read Only
2. Default value at the start of auto-negotiation code word transmission.
Table 92. Port Configuration Register (Address 16, Hex 10) (Sheet 1 of 2)
Bit
Name
Description
15
Reserved
Write as 0, ignore on Read
0 = Normal operation
1 = Force link pass (sets appropriate registers and LEDs
to pass)
14
Link Disable
13
Transmit Disable
0 = Normal operation
1 = Disable twisted-pair transmitter
R/W
0
12
Bypass Scramble
(100BASE-TX)
0 = Normal operation
1 = Bypass scrambler and descrambler
R/W
0
11
Reserved
Write as 0, ignore on Read
R/W
0
10
Jabber
(10BASE-T)
0 = Normal operation
1 = Jabber function is enabled; however, jabber status
reporting to Register bit 1.1 is disabled
R/W
0
Note: Setting this bit in 100 Mbps mode by-passes the
descrambler lock requirement to establish link and forces
the link to the link-good state. Setting this bit produces
unreliable results if the descrambler is not locked,
1. R/W = Read/Write
2. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
the pin(s) are latched at startup or hardware reset.
3. The default value of Register bit 16.0 is determined by the G_FX/TP pin.
If G_FX/TP is tied Low, the default value of Register bit 16.0 = 0. If G_FX/TP is not tied Low, the default
value of Register bit 16.0 = 1. The BGA15 package does not have a G_FX/TP hardware configuration pin.
4. The default value of Register bit 16.5 is determined by the PREASEL pin. The BGA15 package does not
have a PREASEL hardware configuration pin and has a default of 0.
5. The BGA15 package does not support fiber. Default for the BGA15 package is 0.
6. NA means the bits do not have a default value and may initially contain any value.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
207
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 92. Port Configuration Register (Address 16, Hex 10) (Sheet 2 of 2)
Bit
9
8
Name
Description
Type 1
Default
Reserved
Write as 0, ignore on Read.
R/W
0
TP Loopback
(10BASE-T)
0 = Normal operation
1 = Disable twisted-pair loopback during half-duplex
operation
R/W
1
Note: Valid function in SMII and S-SMII modes only.
7
Reserved
Write as 1, ignore on Read
R/W
1
6
Reserved
Write as 0, ignore on Read
R/W
0
10 Mbps
5
Preamble Enable
100
Mbps
0 = No preamble (default)
1 = Preamble enabled
NOTE: Default for BGA15 package is 0.
LSHR2,4
R/W
No effect
N/A
4
Reserved
Write as 0, ignore on Read
R/W
0
3
Reserved
Write as 0, ignore on Read
R/W
0
2
Far End Fault
Transmission
Enable
0 = Disable Far End Fault transmission
1 = Enable Far End Fault transmission
R/W
1
Invalid for
BGA15
Write as '0', ignore on Read (BGA15).
Reserved
Write as 0, ignore on Read.
R/W
0
Fiber Select5
0 = Select twisted-pair mode for this port
1 = Select fiber mode for this port
Reserved for
BGA15
Write as '0', ignore on Read (BGA15).
NOTE: Default for BGA15 is 0.
R/W
LSHR2,3
1
0
1. R/W = Read/Write
2. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
the pin(s) are latched at startup or hardware reset.
3. The default value of Register bit 16.0 is determined by the G_FX/TP pin.
If G_FX/TP is tied Low, the default value of Register bit 16.0 = 0. If G_FX/TP is not tied Low, the default
value of Register bit 16.0 = 1. The BGA15 package does not have a G_FX/TP hardware configuration pin.
4. The default value of Register bit 16.5 is determined by the PREASEL pin. The BGA15 package does not
have a PREASEL hardware configuration pin and has a default of 0.
5. The BGA15 package does not support fiber. Default for the BGA15 package is 0.
6. NA means the bits do not have a default value and may initially contain any value.
208
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 93. Quick Status Register (Address 17, Hex 11) (Sheet 1 of 2)
Type 1
Default2
Write as 0, ignore on Read
R
0
0 = The LXT9785/LXT9785E is operating in 10 Mbps
mode
1 = The LXT9785/LXT9785E is operating in 100 Mbps
mode
R
0
Bit
Name
Description
15
Reserved
10/100 Mode
14
NOTE: The status is valid for TX and FX operation.
13
Transmit Status
0 = The LXT9785/LXT9785E is not transmitting a packet
1 = The LXT9785/LXT9785E is transmitting a packet
R
LH
0
12
Receive Status
0 = Packet has not been received since last read
1 = Packet has been received since last read
R
LH
0
R
LH
0
0 = A collision is not occurring
1 = A collision is occurring
11
Collision Status
NOTE: This bit is set when jabber is detected, regardless
of duplex.
10
Link
0 = Link is down
1 = Link is up
R
0
9
Duplex Mode
0 = Half-duplex
1 = Full-duplex
R
0
8
Auto-Negotiation
R
Note 3
0 = The LXT9785/LXT9785E is in manual mode
1 = The LXT9785/LXT9785E is in auto-negotiation mode
This signal is based upon Register bit 0.12.
7
Auto-Negotiation
Complete
0 = Auto-negotiation process is not complete
1 = Auto-negotiation process is complete
R
0
6
FIFO Error
0 = No FIFO error occurred
1 = FIFO error occurred (overflow or underflow)
R
LH
0
R
0
0 = Polarity is not reversed
1 = Polarity is reversed
5
Polarity
NOTE: During 100 Mbps operation, this bit is not valid
and may vary. Auto MDIX activity may increase
the variability.
1. R = Read Only, LH = Latching High – cleared when read.
2. The default values are updated on completion of reset and reflect the status or change in status at that
time. Intel recommends that the register status be read on completion of reset.
3. The default value is determined by the default value of Register bit 0.12.
4. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
the pin(s) are latched at startup or hardware reset.
5. Default values are set by the hardware configuration PAUSE pin. The BGA15 package does not have a
Pause hardware configuration pin. The default for the BGA15 package is 0.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
209
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 93. Quick Status Register (Address 17, Hex 11) (Sheet 2 of 2)
Bit
Name
Description
Type 1
Default2
R
LSHR4,5
R
0
R
0
0 = The LXT9785/LXT9785E is not Pause capable
1 = The LXT9785/LXT9785E is pause capable
4
Pause
NOTE: This bit is not affected by Register bit 4.10.
NOTE: The default for the BGA15 package is 0.
3
Error
0 = No error occurred
1 = Error Occurred (remote fault, RxERCntFUL, FIFO
error, jabber, parallel detect fault)
NOTE: The register is cleared when the registers that
generated the error condition are read.
2:0
Reserved
Write as 0, ignore on Read.
1. R = Read Only, LH = Latching High – cleared when read.
2. The default values are updated on completion of reset and reflect the status or change in status at that
time. Intel recommends that the register status be read on completion of reset.
3. The default value is determined by the default value of Register bit 0.12.
4. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
the pin(s) are latched at startup or hardware reset.
5. Default values are set by the hardware configuration PAUSE pin. The BGA15 package does not have a
Pause hardware configuration pin. The default for the BGA15 package is 0.
210
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 94. Interrupt Enable Register (Address 18, Hex 12)
Bit
Name
Description
Type 1
Default
R/W
LSHR4,5
R/W
0
R/W
0
R/W
0000
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00 = Reserved
2
15:14
RxFIFO Initial
Fill
01 = Low, 16 bits
10 = Normal, 32 bits (default)
11 = Jumbo packets, 128 bits
When Register bit 16.5 = 1, preamble is
not suppressed.
SFD Frame
Alignment3
13
10 Mbps
When Register bit 16.5 = 0, SFD is always
aligned, and preamble is suppressed.
(RxDV asserts
with CRS when
enabled)
100 Mbps
12:9
Reserved
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
When enabled, all but one byte of
preamble is suppressed.
Write as 0, ignore on Read
Mask for Counter Full
8
CNTRMSK
7
ANMSK
6
SPEEDMSK
5
DUPLEXMSK
4
LINKMSK
3
ISOLMSK
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
R/W
0
2
Reserved
Write as 0, ignore on Read
R/W
0
1
INTEN
0 = Disable interrupts on this port
1 = Enable interrupts on this port
R/W
0
0
TINT
0 = Normal operation
1 = Test force interrupt on MDINT
R/W
0
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
Mask for Auto-Negotiate Complete
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
Mask for Speed Interrupt
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
Mask for Duplex Interrupt
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
Mask for Link Status Interrupt
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
Mask for Isolate Interrupt
1. R/W = Read/Write
2. In 10 Mbps operation, Register bit 18.13 = 1 cannot be used when Register bits 18.15:14 = “11” and in
RMII mode, Registers bits 18.15:14 = “11” or “10” cannot be used because the minimum Inter Gap Packet
becomes less than specified in the *IEEE 802.3 specification.
3. SFD Frame Alignment is applicable to SMII and SS-SMII only.
4. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
the pin(s) are latched at startup or hardware reset
5. Default values are set by hardware configuration pins FIFOSEL1 and FIFOSEL0 (see Table 17, “Intel®
LXT9785/LXT9785E Receive FIFO Depth Considerations” on page 50).
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
211
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 95. Interrupt Status Register (Address 19, Hex 13)
Bit
15:9
Name
Reserved
Description
Write as 0, ignore on Read
Type 1
Default2
R
0
R/LH
0
R/LH
N/A
R/LH
0
R/LH
0
R/LH
0
R/LH
0
R/LH
0
R
0
RxER Counter Full Status.
8
RxERCntFUL
7
ANDONE
0 = The internal counters have not reached maximum
values
1 = One of the internal counters has reached its maximum
value
Auto-Negotiation Status.
0 = Auto-negotiation has not completed
1 = Auto-negotiation has completed
Speed Change Status.
6
SPEEDCHG
0 = A speed change has not occurred since last reading
this register
1 = A speed change has occurred since last reading this
register
Duplex Change Status.
5
DUPLEXCHG
0 = A duplex change has not occurred since last reading this
register
1 = A duplex change has occurred since last reading this
register
Link Status Change Status.
4
LINKCHG
0 = A link change has not occurred since last reading this
register
1 = A link change has occurred since last reading this
register
MII Isolate Change Status.
0 = An Isolate change has not occurred since last reading
this register
1 = An Isolate change has occurred since last reading this
register
3
Isolate
2
MDINT
0 = Interrupt not pending
1 = Interrupt pending
Reserved
Reserved
1:0
1. R = Read Only, LH = Latching High – cleared when read
2. The default values are updated on completion of reset and reflect the status or change in status at that
time. Intel recommends that the register status be read on completion of reset.
212
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 96. LED Configuration Register (Address 20, Hex 14) (Sheet 1 of 2)
Bit
Name
Description
Type1
Default
R/W
0000
R/W
1101
0000 = Display Speed Status (Continuous, Default)
0001 = Display Transmit Status (Stretched)
0010 = Display Receive Status (Stretched)
0011 = Display Collision Status (Stretched)
0100 = Display Link Status (Continuous)
0101 = Display Duplex Status (Continuous)
0110 = Display Isolate Status (Continuous)
0111= Display Receive or Transmit Activity (Stretched)
15:12
LED1
1000= est mode- turn LED on (Continuous)
Programming
bits
1001= Test mode- turn LED off (Continuous)
1010= Test mode- blink LED fast (Continuous)
1011= Test mode- blink LED slow (Continuous)
1100= Display Link and Receive Status combined2
(Stretched)3
1101= Display Link and Activity Status combined2
(Stretched)3
1110= Display Duplex and Collision Status combined4
(Stretched)3
1111 = Display Link and RxER Status combined2 (Blink)
0000 = Display Speed Status
0001 = Display Transmit Status
0010 = Display Receive Status
0011 = Display Collision Status
0100 = Display Link Status
0101 = Display Duplex Status
0110 = Display Isolate Status
0111= Display Receive or Transmit Activity
11:8
LED2
1000= Test mode- turn LED on
Programming
bits
1001= Test mode- turn LED off
1010= Test mode- blink LED fast
1011= Test mode- blink LED slow
1100= Display Link and Receive Status combined2
(Stretched)3
1101= Display Link and Activity Status combined2 (Default)
(Stretched)3
1110= Display Duplex and Collision Status combined4
(Stretched)3
1111= Display Link and RxER Status combined 2 (Blink)
1. R/W = Read/Write
2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.
The secondary LED driver (Receive, Activity, or Error) causes the LED to change state (blink).
3. Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings
are stretched regardless of the value of 20.1.
4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex.
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
213
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 96. LED Configuration Register (Address 20, Hex 14) (Sheet 2 of 2)
Bit
Name
Description
LED3
0000 = Display Speed Status
Programming
bits
0001 = Display Transmit Status
Type1
Default
R/W
1110
R/W
00
R/W
1
R/W
0
0010 = Display Receive Status
0011 = Display Collision Status
0100 = Display Link Status
0101 = Display Duplex Status
0110 = Display Isolate Status
0111= Display Receive or Transmit Activity
1000= Test mode- turn LED on
1001= Test mode- turn LED off
7:4
1010= Test mode- blink LED fast
1011= Test mode- blink LED slow
1100= Display Link and Receive Status combined2
(Stretched)3
1101= Display Link and Activity Status combined2
(Stretched)3
1110= Display Duplex and Collision Status combined4
(Default) (Blink)3
1111 = Display Link and RxER Status combined 2 (Blink)
Reserved for
BGA15
Write as '1001', ignore on Read (BGA15)
00 = Stretch LED events to 30 ms
3:2
LEDFREQ
01 = Stretch LED events to 60 ms
10 = Stretch LED events to 100 ms
11 = Reserved
1
0
PULSESTRETCH
Reserved
0 = Disable pulse stretching of all LEDs3
1 = Enable pulse stretching of all LEDs
NOTE: Receive activity LEDs are initially active based upon
carrier sense.
Write as 0, ignore on Read
1. R/W = Read/Write
2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.
The secondary LED driver (Receive, Activity, or Error) causes the LED to change state (blink).
3. Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings
are stretched regardless of the value of 20.1.
4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex.
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
Table 97. Receive Error Count Register (Address 21, Hex 15)
Bit
15:0
Type1
Name
Description
Receive Error
Count
A 16-bit counter value indicating the number of times a
receive packet with errors occurred. Only one event gets
counted per packet. When maximum count is reached, the
16-bit counter remains full until cleared.
R/
LH
Default
0x0000
1. R = Read Only, LH = Latching High – cleared when read
NOTE: Intel recommends reading this register once every time link is established to clear the register.
214
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 98. RMII Out-of-Band Signaling Register (Address 25, Hex 19)
Bit
Name
Description
Type1
Default
R/W
0x0000
R/W
0x000
R/W
000
R/W
000
R/W
0
BGA15
15:0
Reserved for
BGA15
Write as 0, ignore on Read.
PQFP and BGA23
15:7
Reserved
Write as 0, ignore on Read
These three bits select which status information is
available on the RxData(1) bit of the RMII bus.
000 = Link
001 = Speed
6:4
BIT1
010 = Duplex
011 = Auto-negotiation complete
100 = Polarity reversed
101 = Jabber detected
110 = Interrupt pending
111 = Reserved
These three bits select which status information is
available on the RxData(0) bit of the RMII bus.
000 = Link
001 = Speed
3:1
BIT0
010 = Duplex
011 = Auto-negotiation complete
100 = Polarity reversed
101 = Jabber detected
110 = Interrupt pending
111 = Reserved
0
PROGRMII
0 = Disable Out-of-Band signaling.
1 = Enable programmable RMII Out-of-Band
signaling. When enabled, Register bits 6:1 specify
which status bits are available on the RMII
RxData data bus.
Note: Out-of-Band signaling is disabled when the
Isolate mode is enabled by setting Register bit 0.10.
1. R/W = Read/Write
NOTE: The BGA15 package does not support RMII operation.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
215
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 99. Trim Enable Register (Address 27, Hex 1B) (Sheet 1 of 2)
Bit
Type5
Default
Write as 0, ignore on Read
R
N/A
Write as 0, ignore on Read.
R/W
0
R/W
LSHR1,2
R/W
LSHR1,3
R/W
LSHR1,4
R/W
0
R/W
0
R/W
0
R
0
Name
Description
15:13
Reserved
12
Reserved
00 = 3.3 ns
11:10
Per-Port
Rise Time
Control
01 = 3.6 ns
10 = 3.9 ns
11 = 4.2 ns
NOTE: Values represent nominal load conditions.
9
AMDIX_EN
0 = Disable auto MDI/MDIX
1 = Enable auto MDI/MDIX
0 = MDI, transmit on pair A (TPFINn/TPFIPn) and receive on
pair B (TPFONn/TPFOPn)
1 = MDIX transmit on pair B (TPFONn/TPFOPn) and receive
on pair A (TPFINn/TPFIPn)
8
MDIX
NOTE: Manual MDI/MDIX selection (This bit is ignored when
Register bit 27.9 = 1).
NOTE: BGA15 does not support the MDIX hardware
configuration.
7
Analog
Loopback
0 = Disable analog loopback
1 = Enable analog loopback (twisted-pair transmit outputs are
active)
NOTE: In fiber mode, SD for the port must be asserted.
DTE Discovery Process Enable.
6
Dis_EN
0 = Disable DTE discovery process
1 = Enable DTE discovery process
Restart auto-negotiation after writing to this bit to ensure
proper operation.
5
Reserved
Write as 0, ignore on Read.
Power Enable (Requires Auto-Negotiation Enable
Register bit 0.12 = 1).
4
Power_EN
0 = Remote-Power DTE not discovered; process may not be
complete.
1 = Potential Remote-Power DTE discovered; indication to
turn on power over the cable.
1. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
the pin(s) are latched at startup or hardware reset.
2. Default values for Register bits 27.11:10 are determined by the TxSLEW pins.
3. Default value for Register bit 27.9 is determined by the AMDIX_EN pin.
4. Default value for Register bit 27.8 is determined by the MDIX pin. BGA15 does not support the MDIX
hardware configuration. The BGA15 default = 0.
5. R/W = Read/Write, R = Read Only, LH = Latching High – cleared when read.
6.
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Datasheet
Document Number: 249241
Revision Number: 007
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 99. Trim Enable Register (Address 27, Hex 1B) (Sheet 2 of 2)
Bit
Name
Description
Type5
Default
R, LH
0
R, LH
0
R
00
Standard Link Partner Detected.
3
SLP_Det
0 = Standard link partner not discovered; process may not be
complete.
1 = Standard link partner discovered; indication not to turn on
power over the cable.
Note: This bit is only valid while link is down.
Link Fail Inhibit Timer expiration indicator. Valid only
when SLP_Det = 1.
2
1:0
LFIT
Expired
0 = Link Fail Inhibit Timer has not expired or standard link
partner not discovered
1 = Link Fail Inhibit Timer expired with a standard link partner
detected since last register read or link establishment
Reserved
Write as 0, ignore on Read.
1. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
the pin(s) are latched at startup or hardware reset.
2. Default values for Register bits 27.11:10 are determined by the TxSLEW pins.
3. Default value for Register bit 27.9 is determined by the AMDIX_EN pin.
4. Default value for Register bit 27.8 is determined by the MDIX pin. BGA15 does not support the MDIX
hardware configuration. The BGA15 default = 0.
5. R/W = Read/Write, R = Read Only, LH = Latching High – cleared when read.
6.
Table 100. Cable Diagnostics Register (Address 29, Hex 1D) (Sheet 1 of 2)
Bit
15:14
Name
Reserved
Description
Write as 01, ignore on read
Type1
Default2
R/W
01
R/W
LH
000
R/W
0
000 = Do not perform cable fault test (Default)
101 = Perform long cable fault test only
110 = Perform short cable fault test only
13:11
Start-Test
Once Register bit 29.9 is set, the Start-Test
bits will clear when read.
Any other combination of the Register bit
settings are reserved and should not be used.
10
CD_EN
0 = Normal operation
1 = Enable cable diagnostic tests. Forces
link to drop.
1. R/W = Read/Write, R = Read only, LH = Latching High, cleared when read
2. Recommended default value.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
217
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 100. Cable Diagnostics Register (Address 29, Hex 1D) (Sheet 2 of 2)
Bit
Name
9
Test_Done
8
Fault_Type
Description
0 = Testing is still in progress
1 = Testing is complete
The Line Fault Counter and Fault_Type bits
are valid.
0 = Open condition has been detected
1 = Short Condition has been detected
Type1
Default2
R
LH
0
R
LH
0
R
LH
0x00
“FF” if no line fault is found, or
7:0
Line Fault Counter
Distance to fault, approximately 1 m * counter
value (refer to Section 4.13, “Cable
Diagnostics Overview” on page 160 for
details).
(Valid only when Test_Done bit is set.)
1. R/W = Read/Write, R = Read only, LH = Latching High, cleared when read
2. Recommended default value.
218
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Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Next Page
A/N Link
Ability
Next Page
Next Page
A/N Next
Page Txmit
A/N Link
Next Page
A/N
Expansion
Next Page
A/N
Advertise
PHY ID2
15
100Base-T4
Status
PHY ID 1
Reset
B15
Control
Reg Title
Ack
Reserved
Ack
Reserved
Message Page
Message Page
Remote Fault
Remote Fault
12
10
B8
B7
Duplex
Mode
COL Test
100Base-T2
Half-Duplex
Extended
Status
Reserved
Speed
Select
B6
MF
Preamble
Suppress
Status Register (Address 1)
Re-start
A/N
Control Register (Address 0)
B9
9
8
7
MFR Model No
6
PHY ID Registers (Address 2 and 3)
100BaseT2 FullDuplex
Isolate
B10
5
A/N
Complete
B5
Asymm
Pause
Pause
100Base-T4
100BaseTX FullDuplex
100BaseTX
10Base-T
Full-Duplex
10Base-T
Auto-Negotiation Advertisement Register (Address 4)
11
10 Mbps
HalfDuplex
Power
Down
B11
4
Remote
Fault
B4
Pause
100Base-T4
100BaseTX FullDuplex
100BaseTX
10Base-T
Full-Duplex
10Base-T
Toggle
Parallel
Detect Fault
Message / Unformatted Code Field
Auto-Negotiation Next Page Transmit Register (Address 7)
Base Page
Auto-Negotiation Expansion Register (Address 6)
Reserved
Asymm
Pause
Ack 2
Toggle
Port Configuration Register (Address 16)
Message / Unformatted Code Field
Auto-Negotiation Link Partner Next Page Ability Register (Address 8)
Ack 2
Reserved
Auto-Negotiation Link Partner Base Page Ability Register (Address 5)
Reserved
PHY ID No
13
100Base-X
Half-Duplex
100BaseX FullDuplex
14
A/N
Enable
Speed
Select
Loopback
10 Mbps
FullDuplex
B12
B13
B14
Bit Fields
Table 101. Intel® LXT9785/LXT9785E Register Bit Map (Sheet 1 of 2)
Link Partner
Next Page
Able
3
B2
Next Page
Able
IEEE Selector Field
IEEE Selector Field
MFR Rev No
2
Link Status
Reserved
A/N Ability
B3
Page
Received
1
Jabber
Detect
B1
Link
Partner
A/N Able
3
Model
Variant
8
7
6
5
4
2
1
0
Addr
0
Extended
Capability
B0
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
219
220
LED1
Cable
Diagnostics
Trim Enable
RMII OOB
Signaling
Rcv Error
Count
LED Config
Reserved
Receiver
Status
Reserved
Collision
Status
SQE
(10T)
B9
TP
Loopback
(10T)
B8
Reserved
B7
Reserved
B6
Duplex Mode
Auto-Neg
Auto-Neg
Complete
FIFO Error
Auto-Neg
Mask
Speed Mask
Auto-Neg
Done
Speed
Change
Receive Error Count
B5
Duplex
Change
Duplex
Mask
Polarity
PRE_EN
LED3
Receive Error Count Register (Address 21)
LED2
LED Configuration Register (Address 20)
RxER
Counter
Full
Interrupt Status Register (Address 19)
Counter
Mask
Interrupt Enable Register (Address 18)
Link
Quick Status Register (Address 17)
Jabber
(10T)
B10
Bit Fields
MDIX
Analog
Loopback
Dis_EN
CD_EN
Test-Done
Fault_
Type
Cable Diagnostics Register (Address 29)
AMDIX_EN
Trim Enable Register (Address 27)
Per Port Rise Time Control
Reserved
Loop Back
Speed Up
Enable
Bit 1
B4
Link Change
Link Mask
Pause
Reserved
SLP_Det
B2
LFIT Expired
Bit 0
MD Interrupt
Reserved
Reserved
Far End Fault
Enable
LED Freq
Isolate
Change
Isolate Mask
Error
Reserved
B3
Line Fault Counter
Power_EN
Programmable RMII Out-of-Band Signaling Register (Register 25)
Start-Test
Reserved
Transmit
Status
Bypass
4B/5B
(100BASE
-TX)
Bypass
Scrambler
(100BASETX)
Interrupt
Status
10/100
Mode
Txmit
Disable
Link
Disable
B11
B12
Reserved
Reserved
Quick
Status
B13
B14
Interrupt
Enable
Reserved
B15
Port Config
Reg Title
Table 101. Intel® LXT9785/LXT9785E Register Bit Map (Sheet 2 of 2)
Fiber
Select
B0
Program
RMII
Reserved
Reserved
Test
Interrupt
Reserved
Reserved
Pulse
Stretch
Reserved
Interrupt
Enable
Reserved
Reserved
B1
29
27
25
21
20
19
18
17
16
Addr
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Datasheet
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
8.0
Package Specifications
Figure 64. Intel® LXT9785/LXT9785E 208-Pin PQFP Plastic Package Specification
208-Pin Plastic Quad Flat Package
• Part Number LXT9785HC, LXT9785EHC,
LXT9785HE
• Commercial Temperature Range (0°C to 70°C)
• Extended Temperature Range (-40°C to +85°C)
D
D1
Millimeters
Dim
A
e
E1
E
e
/2
θ2
Max
-
4.10
A1
0.25
-
A2
3.20
3.60
b
0.17
0.27
D
30.30
30.90
D1
27.70
28.30
E
30.30
30.90
E1
27.70
28.30
e
L1
L
A2
A
θ
A1
L
Min
b
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
θ3
.50 BASIC
0.50
L1
0.75
1.30 REF
q
0°
7°
θ2
5°
16°
θ3
5°
16°
221
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 65. Intel® LXT9785/LXT9785E 241-Ball BGA23 Package Specs - Top/Side View
(LXT9785BC)
D
D1
Pin A1 corner
Pin A1 I.D.
14.70 REF
E1 E
14.70 REF
45° Chamfer
(4 places)
Top View
A2
A
c
30°
A1
Side View
Seating Plane
241_pkg1.vsd
222
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 66. Intel® LXT9785/LXT9785E 241-Ball BGA23 Package Specs - Bottom View
(LXT9785BC)
Pin A1 corner
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B
b
C
D
E
F
G
e
H
J
K
L
M
N
P
R
T
U
J
l
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
241 BGA
Bottom View
e
223
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Intel® LXT9785/LXT9785E 241-Ball BGA23 Package Dimensions
Symbol
Min
Nominal
Max
Units
A
2.19
2.38
2.57
mm
A1
0.50
0.60
0.70
mm
A2
1.12
1.17
1.22
mm
D
22.90
23.00
23.10
mm
D1
19.30
19.50
19.70
mm
E
22.90
23.00
23.10
mm
E1
19.30
19.50
19.70
mm
e
1.27 (solder ball pitch)
mm
I
1.34 REF.
mm
J
1.34 REF.
mm
M
17 x 17 Matrix
mm
b
0.60
0.75
0.90
mm
c
0.52
0.56
0.60
mm
e
1.27
Note
mm
All dimensions and tolerances conform to ANSI Y14.5-1982. Dimension is measured at maximum solder ball
diameter parallel to primary datum (-C-). Primary datum (-C-) and seating plane are defined by the spherical
crowns of the solder balls.
224
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 67. Intel® LXT9785MBC 196-Ball BGA15 Package Specs - Top/Side View (LXT9785MBC)
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
225
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 102. Intel® LXT9785MBC 196-Ball BGA15 Package Dimensions
Symbol
Min
Nominal
Max
Units
A
1.62
1.81
2.00
mm
A1
0.30
0.40
0.50
mm
A2
0.80
0.85
0.90
mm
D
14.90
15.00
15.10
mm
D1
12.80
13.00
13.20
mm
E
14.90
15.00
15.10
mm
E1
12.80
13.00
13.20
mm
e
1.00 (solder ball pitch)
mm
I
1.00 REF.
mm
J
1.00 REF.
mm
M
14 x 14 Matrix
mm
b
0.40
0.50
0.60
mm
c
0.52
0.56
0.60
mm
e
Note
1.00
mm
NOTE: All dimensions and tolerances conform to ANSI Y14.5-1982.Dimension is measured at maximum
solder ball diameter parallel to primary datum (-C-). Primary datum (-C-) and seating plane are
defined by the spherical crowns of the solder balls.
226
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
9.0
Ordering Information
Table 103. Product Information
Number
Revision
Qualification
Tray MM
Tape & Reel MM
HBLXT9785HC.D0 853353
D0
S
853353
Tray
HBLXT9785HC.D0 853355
D0
S
853355
Tape & reel
FWLXT9785BC.D0 853308
D0
S
853308
Tray
FWLXT9785BC.D0 853312
D0
S
853312
Tape & reel
HBLXT9785EHC.D0 853334
D0
S
853334
Tray
HBLXT9785EHC.D0 853335
D0
S
853335
Tape & reel
FWLXT9785EBC.D0 853300
D0
S
853300
Tray
FWLXT9785EBC.D0 853304
D0
S
853304
Tape & reel
HBLXT9785HE.D0 853357
D0
S
853357
Tray
HBLXT9785HE.D0 853363
D0
S
853363
Tape & reel
GDLXT9785MBC.D0
D0
Q
TBD
TBD
GDLXT9785MBC.D0
D0
Q
TBD
TBD
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
227
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 68. Ordering Information - Sample
FW
LXT
9785
B
C
D0
S
E001
Build Format
E000 = Tray
E001 = Tape and reel
Qualification
= Pre-production material
Q
= Production material
S
Product Revision
= 2 Alphanumeric characters
xn
Temperature Range
= Ambient (0 - 55° C)
A
= Commercial (0 - 70° C)
C
= Extended (-40 - +85° C)
E
Internal Package Designator
= LQFP
L
= PLCC
P
= DIP
N
= PQFP
Q
= QFP with heat spreader
H
= TQFP
T
= BGA
B
= CBGA
C
= TBGA
E
= HSBGA (BGA with heat slug)
K
xxxx
= 3-5 Digit Alphanumeric Product Code
IXA Product Prefix
= PHY layer device
LXT
= Switching engine
IXE
= Formatting device (MAC)
IXF
= Network processor
IXP
Intel Package Designator
DJ
= LQFP
FA
= TQFP
FL
= PBGA (<1.0 mm pitch)
FW
= PBGA (1.27 mm pitch)
HB
= QFP with heat spreader
HD
= QFP with heat slug
HF
= CBGA
HG
= SOIC
S
= QFP
GC
= TBGA
N
= PLCC
228
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003

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