DM74LS293 4-Bit Binary Counter General Description The ’LS293 counter is electrically and functionally identical to the ’LS93. Only the arrangement of the terminals has been changed for the ’LS293. Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the count cycle length is divide-by-eight. All of these counters have a gated zero reset. To use the maximum count length (four-bit binary) of these counters, the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are as described in the appropriate function table. Features Y Y Y GND and VCC on Corner Pins (Pins 7 and 14 respectively) Typical power dissipation 45 mW Count frequency 42 MHz Connection Diagram Dual-In-Line Package TL/F/6423 – 1 Order Number DM74LS293M or DM74LS293N See NS Package Number M14A or N14A C1995 National Semiconductor Corporation TL/F/6423 RRD-B30M105/Printed in U. S. A. DM74LS293 4-Bit Binary Counter June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Input Voltage Operating Free Air Temperature Range DM74LS 7V 7V 0§ C to a 70§ C b 65§ C to a 150§ C Storage Temperature Range Recommended Operating Conditions Symbol VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current fCLK Clock Frequency (Note 1) fCLK tW DM74LS293 Parameter Clock Frequency (Note 2) Pulse Width (Note 6) Units Min Nom Max 4.75 5 5.25 V 2 V 0.8 V b 0.4 mA 8 mA A to QA 0 32 B to QB 0 16 A to QA 0 20 B to QB 0 10 A 15 B 30 Reset 15 tREL Reset Release Time (Note 6) 25 TA Free Air Operating Temperature 0 MHz MHz ns ns 70 §C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VOH High Level Output Voltage VCC e Min, II e b18 mA VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIL e Max, VIH e Min II Input Current @ Max Input Voltage VCC e Max VI e 7V Min 2.7 IOL e 4 mA, VCC e Min IIH IIL High Level Input Current Low Level Input Current VCC e Max VI e 2.7V VCC e Max VI e 0.4V IOS Short Circuit Output Current VCC e Max (Note 4) ICC Supply Current VCC e Max (Note 5) Typ (Note 3) Units b 1.5 V 3.4 V 0.35 0.5 0.25 0.4 Reset 0.1 A 0.2 B 0.2 Reset 20 A 40 B 40 Reset b 0.4 A b 2.4 B b 1.6 b 20 9 2 Max V mA mA mA b 100 mA 15 mA Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) RL e 2 kX From (Input) Symbol Parameter CL e 15 pF To (Output) Min tMAX Maximum Clock Frequency Max CL e 50 pF Min A to QA 32 20 B to QB 16 10 Units Max MHz tPLH Propagation Delay Time Low to High Level Output A to QA 16 23 ns tPHL Propagation Delay Time High to Low Level Output A to QA 18 30 ns tPLH Propagation Delay Time Low to High Level Output A to QD 70 87 ns tPHL Propagation Delay Time High to Low Level Output A to QD 70 93 ns tPLH Propagation Delay Time Low to High Level Output B to QB 16 23 ns tPHL Propagation Delay Time High to Low Level Output B to QB 21 35 ns tPLH Propagation Delay Time Low to High Level Output B to QC 32 48 ns tPHL Propagation Delay Time High to Low Level Output B to QC 35 53 ns tPLH Propagation Delay Time Low to High Level Output B to QD 51 71 ns tPHL Propagation Delay Time High to Low Level Output B to QD 51 71 ns tPHL Propagation Delay Time High to Low Level Output SET-0 to Any Q 40 53 ns Note 1: CL e 15 pF, RL e 2 kX, TA e 25§ C and VCC e 5V. Note 2: CL e 50 pF, RL e 2 kX, TA e 25§ C and VCC e 5V. Note 3: All typicals are at VCC e 5V, TA e 25§ C. Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 5: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded. Note 6: TA e 25§ C and VCC e 5V. 3 Function Tables Count Sequence (See Note C) Reset/Count Truth Table Outputs Count QD 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 L L L L L L L L H H H H H H H H QC L L L L H H H H L L L L H H H H QB L L H H L L H H L L H H L L H H Reset Inputs QA L H L H L H L H L H L H L H L H Outputs R0(1) R0(2) QD QC QB QA H L X H X L L L L L COUNT COUNT H e High Level, L e Low Level, X e Don’t Care. Note C: Output QA is connected to input B. Logic Diagram LS293 TL/F/6423 – 2 Note: The J and K inputs shown without connection are for reference only and are functionally at a high level. 4 Physical Dimensions inches (millimeters) 14-Lead Small Outline Molded Package (M) Order Number DM74LS293M NS Package Number M14A 5 DM74LS293 4-Bit Binary Counter Physical Dimensions inches (millimeters) (Continued) 14-Lead Molded Dual-In-Line Package (N) Order Number DM74LS293N NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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