Revised May 2000 DM74S299 3-STATE 8-Bit Universal Shift/Storage Register General Description Features This Schottky TTL eight-bit universal register features multiplexed inputs/outputs to achieve full eight bit data handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose the modes of operation listed in the function table. ■ Multiplexed inputs/outputs provide improved bit density Synchronous parallel loading is accomplished by taking both function-select lines, S0 and S1, HIGH. This places the 3-STATE outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. A direct overriding input is provided to clear the register whether the outputs are ENABLED or OFF. ■ 3-STATE outputs drive bus lines directly ■ Four modes of operation: Hold (Store) Shift Left Shift Right Load Data ■ Can be cascaded for N-bit word lengths ■ Operates with outputs enabled or at high Z ■ Guaranteed shift (clock) frequency 50 MHz ■ Typical power dissipation 700 mW Ordering Code: Order Number DM74S299N Package Number N20A Package Description 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram © 2000 Fairchild Semiconductor Corporation DS006485 www.fairchildsemi.com DM74S299 3-STATE 8-Bit Universal Shift/Storage Register August 1986 DM74S299 Function Table Inputs Mode Function Clear Select S1 Clear Hold Inputs/Outputs Outputs Output Control Clock G2 G1 S0 (Note 1) (Note 1) Serial A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH QA′ QH′ SL SR L X L L L X X X L L L L L L L L L L L L X L L X X X L L L L L L L L L L H L L L L X X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 H X X L L L X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0 Shift Right H L H L L ↑ X H H QAn QBn QCn QDn QEn QFn QGn H L H L L ↑ X L L QAn QBn QCn QDn QEn QFn QGn Shift Left H H L L L ↑ H X QBn QCn QDn QEn QFn QGn QHn H QBn H H H L L L ↑ L X QBn QCn QDn QEn QFn QGn QHn L QBn L H H H X X ↑ X X a g h a h Load b c d e f QH0 QA0 QH0 H QGn L QGn a...h = The level of the steady-state input at inputs A through H, respectively. These data are loaded into the flip-flops while the flip-flop outputs are isolated from the input/output terminals. H = HIGH Level L = LOW Logic Level X = Either LOW or HIGH Logic Level QA0...QH0 = The output logic level of QX before the indicated input conditions were established. QAn...QHn = The output logic level before the active transition (↑) of the clock input. Note 1: When one or both output controls are HIGH the eight input/output terminals are disabled to the high-impedance state; however, sequential operation or clearing of the register is not affected Logic Diagram www.fairchildsemi.com 2 Supply Voltage Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 5.5V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 IOH HIGH Level Output Current (QA thru QH) −6.5 HIGH Level Output Current (QA′, QH′) −0.5 IOL 2 Units V V LOW Level Output Current (QA thru QH) 20 HIGH Level Output Current (QA′, QH′) 6 V mA mA fCLK Clock Frequency (Note 3) 0 70 50 MHz fCLK Clock Frequency (Note 4) 0 60 40 MHz tW Pulse Width (Note 5) tSU Setup Time (Note 6)(Note 5)(Note 7) tH Hold Time (Note 5)(Note 7) tREL Clear Release Time (Note 5) TA Free Air Operating Temperature Clock HIGH 10 Clock LOW 10 Clear LOW 10 Select 15↑ Data HIGH 7↑ Data LOW 5↑ ns ns 5↑ ns 10↑ 0 ns 70 °C Note 3: CL = 15 pF, RL = 280Ω, TA = 25°C and VCC = 5V. Note 4: CL = 50 pF, RL = 280Ω, TA = 25°C and VCC = 5V. Note 5: TA = 25°C and VCC = 5V. Note 6: The symbol (↑) indicates the rising edge of the clock pulse is used for reference. Note 7: Data includes the two serial inputs and the eight input/output data lines. 3 www.fairchildsemi.com DM74S299 Absolute Maximum Ratings(Note 2) DM74S299 Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter Conditions Typ Min (Note 8) VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max QA thru QH 2.4 3.2 Output Voltage VIL = Max, VIH = Min QA′, QH′ 2.7 3.4 LOW Level VCC = Min, IOL = Max Output Voltage VIH = Min, VIL = Max II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V IIH HIGH Level VCC = Max A thru H, Input Current VI = 2.7V S0, S1 VOL IOZH Units −1.2 V V 0.5 1 mA µA 50 LOW Level VCC = Max Clock, Clear Input Current VI = 0.5V S0, S1 −0.5 Other −0.25 Off-State Output Current with VCC = Max, VO = 2.4V HIGH Level Output Voltage VIH = Min, VIL = Max V 100 Any Other IIL Max −2 mA 100 µA −250 µA Applied (QA thru QH) IOZL Off-State Output Current with VCC = Max, VO = 0.5V LOW Level Output Voltage VIH = Min, VIL = Max Applied (QA thru QH) IOS VCC = Max Short Circuit Output Current (QA thru QH) (Note 10) Current (QA′, QH′) ICC −100 −20 −100 mA VCC = Max Short Circuit Output −40 (Note 10) VCC = Max Supply Current 140 225 mA Note 8: TA = 25°C and VCC = 5V. Note 9: All typicals are at VCC = 5V, TA = 25°C. Note 10: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics at VCC = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load) RL = 280Ω (Note 12) Symbol Parameter fMAX Maximum Clock Frequency tPLH Propagation Delay Time From (Input) To (Output) Min (Note 13) 50 Clock to QA′ or QH′ LOW-to-HIGH Level Output (Note 12) tPHL Propagation Delay Time Clock to QA′ or QH′ HIGH-to-LOW Level Output (Note 12) tPLH Propagation Delay Time CL = 15 pF Max Propagation Delay Time 40 ns 20 23 ns 21 ns 21 ns 24 ns 24 ns Clock to QA thru QH Clock to QA thru QH Propagation Delay Time Clear to QA′ or QH′ HIGH-to-LOW Level Output (Note 12) tPHL Propagation Delay Time MHz 22 HIGH-to-LOW Level Output tPHL Units Max 20 LOW-to-HIGH Level Output tPHL CL = 50 pF Min 21 Clear to QA thru QH HIGH-to-LOW Level Output tPZH Output Enable Time to HIGH Level Output G1, G2 to QA thru QH 18 ns tPZL Output Enable Time to LOW Level Output G1, G2 to QA thru QH 18 ns tPHZ Output Disable Time to HIGH Level Output (Note 11) G1, G2 to QA thru QH 12 ns tPLZ Output Disable Time to LOW Level Output (Note 11) 12 ns G1, G2 to QA thru QH Note 11: CL = 5 pF. Note 12: RL = 1KΩ for delays measured to QA′ and QH′. Note 13: For testing fMAX all outputs are loaded simultaneously. www.fairchildsemi.com 4 DM74S299 3-STATE 8-Bit Universal Shift/Storage Register Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 5 www.fairchildsemi.com