NSC DP8405 Dp8402a/dp8403/dp8404/dp8405 32-bit parallel error detection and correction circuits (edacs) Datasheet

August 1989
DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel
Error Detection and Correction Circuits (EDAC’s)
General Description
The DP8402A, DP8403, DP8404 and DP8405 devices are
32-bit parallel error detection and correction circuits
(EDACs) in 52-pin DP8402A and DP8403 or 48-pin DP8404
and DP8405 600-mil packages. The EDACs use a modified
Hamming code to generate a 7-bit check word from a 32-bit
data word. This check word is stored along with the data
word during the memory write cycle. During the memory
read cycle, the 39-bit words from memory are processed by
the EDACs to determine if errors have occurred in memory.
Single-bit errors in the 32-bit data word are flagged and corrected.
Single-bit errors in the 7-bit check word are flagged, and the
CPU sends the EDAC through the correction cycle even
though the 32-bit data word is not in error. The correction
cycle will simply pass along the original 32-bit data word in
this case and produce error syndrome bits to pinpoint the
error-generating location.
Double bit errors are flagged but not corrected. These errors may occur in any two bits of the 39-bit word from memory (two errors in the 32-bit data word, two errors in the 7-bit
check word, or one error in each word). The gross-error
condition of all lows or all highs from memory will be detected. Otherwise, errors in three or more bits of the 39-bit word
are beyond the capabilities of these devices to detect.
Read-modify-write (byte-control) operations can be performed with the DP8402A and DP8403 EDACs by using output latch enable, LEDBO, and the individual OEB0 thru
OEB3 byte control pins.
Diagnostics are performed on the EDACs by controls and
internal paths that allow the user to read the contents of the
DB and CB input latches. These will determine if the failure
occurred in memory or in the EDAC.
Features
Y
Y
Y
Y
Y
Y
Detects and corrects single-bit errors
Detects and flags double-bit errors
Built-in diagnostic capability
Fast write and read cycle processing times
Byte-write capability . . . DP8402A and DP8403
Fully pin and function compatible with TI’s
SN74ALS632A thru SN74ALS635 series
System Environment
TL/F/8535 – 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
C1995 National Semiconductor Corporation
TL/F/8535
RRD-B30M105/Printed in U. S. A.
DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel
Error Detection and Correction Circuits (EDAC’s)
PRELIMINARY
Simplified Functional Block and Connection Diagrams
TL/F/8535 – 2
Device
Package
Byte-Write
Output
DP8402A
DP8403
DP8404
DP8405
52-pin
52-pin
48-pin
48-pin
yes
yes
no
no
TRI-STATEÉ
Open-Collector
TRI-STATE
Open-Collector
Plastic Chip Carrier
Dual-In-Line Packages
TL/F/8535 – 11
Top View
Order Number DP8402AV
See NS Package Number V68A
TL/F/8535–10
Top View
TL/F/8535– 3
Top View
Order Number DP8402AD,
DP8403D, DP8404D or DP8405D
See NS Package Number D48A or D52A
2
Mode Definitions
PCC Pin Definitions DP8402A
MODE PIN NAME DESCRIPTION
S1 S0
MODE
OPERATION
0
L
L WRITE
Input dataword and output
checkword
1
L
H DIAGNOSTICS Input various data words
against latched
checkword/output valid
error flags.
2
H
L READ & FLAG Input dataword and output
error flags
3
H
H CORRECT
Latched input data and
checkword/output
corrected data and
syndrome code
Pin Definitions
S0, S1
Control of EDAC mode, see preceding
Mode Definitions
DB0 thru DB31 I/O port for 32 bit dataword.
CB0 thru CB6 I/O port for 7 bit checkword. Also output
port for the syndrome error code during
error correction mode.
OEB0 thru
Dataword output buffer enable. When high,
OEB3
output buffers are at TRI-STATE. Each pin
(DP8402A,
controls 8 I/O ports. OEB0 controls DB0
DP8403)
thru DB7, OEB1 controls DB8 thru DB15,
OEB2 controls DB16 thru DB23 and OEB3
controls DB24 thru DB31.
LEDBO
Data word output Latch enable. When high
(DP8402A,
it inhibits input to the Latch. Operates on all
DP8403)
32 bits of the dataword.
OEDB
TRI-STATE control for the data I/O port.
(DP8404,
When high output buffers are at
DP8405)
TRI-STATE.
OECB
Checkword output buffer enable. When
high the output buffers are in TRI-STATE
mode.
ERR
Single error output flag, a low indicates at
least a single bit error.
MERR
Multiple error output flag, a low indicates
two or more errors present.
pin 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
VCC
LEDBO
MERR
ERR
DB0
DB1
DB2
NC
NC
NC
DB3
DB4
DB5
OEBO
DB6
DB7
GND
GND
DB8
DB9
OEB1
DB10
DB11
DB12
DB13
DB14
NC
NC
NC
DB15
NC
CB6
CB5
CB4
pin 35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
OECB
CB3
CB2
CB1
CB0
DB16
DB17
NC
NC
DB18
DB19
DB20
DB21
OEB2
DB22
DB23
GND
GND
DB24
DB25
OEB3
DB26
DB27
DB28
NC
NC
NC
NC
DB29
DB30
DB31
S0
S1
VCC
TABLE I. Write Control Function
Memory
Cycle
EDAC
Function
Write
Generate
check word
Control
S1
S0
L
Data I/O
DB Control
OEBn or
OEDB
DB Output Latch
DP8402A, DP8403
LEDBO
Check I/O
CB
Control
OECB
Input
H
X
Output
check bits ²
L
L
Error Flags
ERR MERR
H
H
² See Table II for details on check bit generation.
Memory Write Cycle Details
2. These seven check bits are stored in memory along with
the original 32-bit data word. This 32-bit word will later be
used in the memory read cycle for error detection and correction.
During a memory write cycle, the check bits (CB0 thru CB6)
are generated internally in the EDAC by seven 16-input parity generators using the 32-bit data word as defined in Table
3
TABLE II. Parity Algorithm
Check Word
32-Bit Data Word
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CB0
CB1
CB2
CB3
CB4
CB5
CB6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X X X
X
X
X X
X
X
X
X X X
X
X
X
X
X
X
X X
X X X
X
X X
X X
X X X X X
X X X X X X X
The seven check bits are parity bits derived from the matrix of data bits as indicated by ‘‘X’’ for each bit.
Check bits 0, 1, 2 are odd parity or the exclusive NORing of the ‘‘X’’ed bits for the particular check bit. Check bits 3, 4, 5, 6 are even parity or the exclusive ORing of
the ‘‘X’’ed bits for the particular check bit.
Memory Read Cycle (Error
Detection & Correction Details)
next two cases of single-bit errors give a high on MERR and
a low on ERR, which is the signal for a correctable error,
and the EDAC should be sent through the correction cycle.
The last three cases of double-bit errors will cause the
EDAC to signal lows on both ERR and MERR, which is the
interrupt indication for the CPU.
During a memory read cycle, the 7-bit check word is retrieved along with the actual data. In order to be able to
determine whether the data from the memory is acceptable
to use as presented on the bus, the error flags must be
tested to determine if they are at the high level.
The first case in Table III represents the normal, no-error
conditions. The EDAC presents highs on both flags. The
TABLE III. Error Function
Total Number of Errors
32-Bit Data Word
7-Bit Check Word
0
1
0
1
2
0
0
0
1
1
0
2
Error Flags
ERR MERR
H
L
L
L
L
L
H
H
H
L
L
L
Data Correction
Not applicable
Correction
Correction
Interrupt
Interrupt
Interrupt
During a READ operation (mode 2, error detection) the data
and check bits that were stored in memory, now possibly in
error, are input through the data and check bit I/O ports.
New check bits are internally generated from the data word.
These new check bits are then compared, by an EXCLUSIVE NOR operation, with the original check bits that were
stored in memory. The EXCLUSIVE NOR of the original
check bits, that were stored in memory, with the new check
bits is called the syndrome word. If the original check bits
are the same as the new check bits, a no error condition,
then a syndrome word of all ones is produced and both
error flags (ERR and MERR) will be high. The DP8402 matrix encodes errors as follows:
The DP8402 check bit syndrome matrix can be seen in TABLE II. The horizontal rows of this matrix generate the
check bits by selecting different combinations of data bits,
indicated by ‘‘X’’s in the matrix, and generating parity from
them. For instance, parity check bit ‘‘0’’ is generated by
EXCLUSIVE NORing the following data bits together; 31,
29, 28, 26, 21, 19, 18, 17, 14, 11, 9, 8, 7, 6, 4, and 0. For
example, the data word ‘‘00000001H’’ would generate the
check bits CB6 – 0 e 48H (Check bits 0, 1, 2 are odd parity
and check bits 3, 4, 5, 6 are even parity).
During a WRITE operation (mode 0) the data enters the
DP8402 and check bits are generated at the check bit input/output port. Both the data word and the check bits are
then written to memory.
TABLE IV. Read, Flag, and Correct Function
Memory
Cycle
EDAC
Function
Read
Read & flag
Read
Latch input
data and check
bits
Read
Output
corrected data
& syndrome bits
Data I/O
DB Control
OEBn or
OEDB
DB Output Latch
DP8402A, DP8403
LEDBO
L
Input
H
H
H
Input
data
latched
H
H
Output
corrected
data word
Control
S1 S0
H
Check I/O
CB
Control
OECB
Error Flags
ERR MERR
X
Input
H
Enabled ²
H
L
Input
check word
latched
H
Enabled ²
L
X
Output
syndrome
bits ³
L
Enabled ²
² See Table III for error description.
³ See Table V for error location.
4
Memory Read Cycle (Error Detection & Correction Details) (Continued)
2) A single check bit error will cause that particular check bit
to go low in the syndrome word.
3) A double bit error will cause an even number of bits in the
syndrome word to go low. The syndrome word will then
be the EXCLUSIVE NOR of the two individual syndrome
words corresponding to the 2 bits in error. The two-bit
error is not correctable since the parity tree can only
identify single bit errors.
If any of the bits in the syndrome word are low the ‘‘ERR’’
flag goes low. The ‘‘MERR’’ (dual error) flag goes low during
any double bit error conditions. (See Table III).
Three or more simultaneous bit errors can cause the EDAC
to believe that no error, a correctable error, or an uncorrectable error has occurred and will produce erroneous results
in all three cases. It should be noted that the gross-error
conditions of all lows and all highs will be detected.
1) Single data bit errors cause 3 or 5 bits in the syndrome
word to go low. The columns of the check bit syndrome
matrix (TABLE II) are the syndrome words for all single bit
data errors in the 32 bit word (also see TABLE V). The
data bit in error corresponds to the column in the check
bit syndrome matrix that matches the syndrome word.
For instance, the syndrome word indicating that data bit
31 is in error would be (CB6-CB0) e ‘‘0001010’’, see the
column for data bit 31 in TABLE II, or see TABLE V.
During mode 3 (S0 e S1 e 1) the syndrome word is
decoded, during single data bit errors, and used to invert
the bit in error thus correcting the data word. The corrected word is made available on the data I/O port (DB0 thru
DB31), the check word I/O port (CB0 thru CB6) presents
the 7-bit syndrome error code. This syndrome error code
can be used to locate the bad memory chip.
TABLE V. Syndrome Decoding
Syndrome Bits
Syndrome Bits
Error
Syndrome Bits
Error
Syndrome Bits
Error
Error
6 5 4 3 2 1 0
6 5 4 3 2 1 0
6 5 4 3 2 1 0
6 5 4 3 2 1 0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L unc
H 2-bit
L 2-bit
H unc
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L 2-bit
H unc
L DB7
H 2-bit
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L 2-bit
H unc
L unc
H 2-bit
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L unc
H 2-bit
L 2-bit
H DB23
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L 2-bit
H unc
L unc
H 2-bit
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
DB6
2-bit
2-bit
DB5
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L unc
H 2-bit
L 2-bit
H unc
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
2-bit
DB22
DB21
2-bit
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L 2-bit
H unc
L DB31
H 2-bit
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
DB4
2-bit
2-bit
DB3
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L unc
H 2-bit
L 2-bit
H DB15
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
2-bit
DB20
DB19
2-bit
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L unc
H 2-bit
L 2-bit
H DB30
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L 2-bit
H DB2
L unc
H 2-bit
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L 2-bit
H unc
L DB14
H 2-bit
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
DB18
2-bit
2-bit
CB4
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L 2-bit
H unc
L DB29
H 2-bit
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L DB0
H 2-bit
L 2-bit
H unc
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L unc
H 2-bit
L 2-bit
H DB13
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L 2-bit
H DB16
L unc
H 2-bit
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
DB28
2-bit
2-bit
DB27
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L 2-bit
H DB1
L unc
H 2-bit
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
2-bit
DB12
DB11
2-bit
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
DB26
2-bit
2-bit
DB25
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L 2-bit
H unc
L unc
H 2-bit
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
2-bit
DB10
DB9
2-bit
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L unc
H 2-bit
L 2-bit
H CB2
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L 2-bit
H DB24
L unc
H 2-bit
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L unc
H 2-bit
L 2-bit
H CB6
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
DB8
2-bit
2-bit
CB5
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
CB X e error in check bit X
DB Y e error in data bit Y
2-bit e double-bit error
unc e uncorrectable multibit error
5
DB17
2-bit
2-bit
CB3
2-bit
CB1
CB0
none
TABLE VI. Read-Modify-Write Function
MEMORY
EDAC FUNCTION
CYCLE
CONTROL
S1
S0
Read
Read & Flag
H
Read
Latch input data
& check bits
Read
Latch corrected
data word into
output latch
Modify
/write
Modify appropriate
byte or bytes &
generate new
check word
DB OUTPUT
LATCH
CB
CHECK I/O
LEDBO
CONTROL
ERROR FLAG
ERR MERR
BYTEn ²
OEBn ²
L
Input
H
X
Input
H
Enabled
H
H
Input
data
latched
H
L
Input
check word
latched
H
Enabled
H
H
Output
data
word
latched
H
H
Input
modified
BYTE0
H
Ouput
unchanged
BYTE0
L
L
L
H
Hi-Z
H
Output
Syndrome
bits
L
Output
check word
L
Enabled
H
H
² OEB0 controls DB0 –DB7 (BYTE0), OEB1 controls DB8 –DB15 (BYTE1), OEB2 controls DB16–DB23 (BYTE2), OEB3 controls DB24–DB31 (BYTE3).
Read-Modify-Write (Byte Control)
Operations
Diagnostic Operations
The DP8402A thru DP8405 are capable of diagnostics that
allow the user to determine whether the EDAC or the memory is failing. The diagnostic function tables will help the
user to see the possibilities for diagnostic control.
In the diagnostic mode (S1 e L, S0 e H), the checkword is
latched into the input latch while the data input remains
transparent. This lets the user apply various data words
against a fixed known checkword. If the user applies a diagnostic data word with an error in any bit location, the ERR
flag should be low. If a diagnostic data word with two errors
in any bit location is applied, the MERR flag should be low.
After the checkword is latched into the input latch, it can be
verified by taking OECB low. This outputs the latched
checkword. With the DP8402A and DP8403, the diagnostic
data word can be latched into the output data latch and
verified. It should be noted that the DP8404 and DP8405 do
not have this pass-through capability because they do not
contain an output data latch. By changing from the diagnostic mode (S1 e L, S0 e H) to the correction mode (S1 e H,
S0 e H), the user can verify that the EDAC will correct the
diagnostic data word. Also, the syndrome bits can be produced to verify that the EDAC pinpoints the error location.
Table VII DP8402A and DP8403 and Table VIII DP8404 and
DP8405 list the diagnostic functions.
The DP8402A and DP8403 devices are capable of bytewrite operations. The 39-bit word from memory must first be
latched into the DB and CB input latches. This is easily accomplished by switching from the read and flag mode (S1 e
H, SO e L) to the latch input mode (S1 e H, S0 e H). The
EDAC will then make any corrections, if necessary, to the
data word and place it at the input of the output data latch.
This data word must then be latched into the output data
latch by taking LEDBO from a low to a high.
Byte control can now be employed on the data word
through the OEB0 through OEB3 controls. OEB0 controls
DB0 – DB7 (byte 0), OEB1 controls DB8–DB15 (byte 1),
OEB2 controls DB16–DB23 (byte 2), and OEB3 controls
DB24 – DB31 (byte 3). Placing a high on the byte control will
disable the output and the user can modify the byte. If a low
is placed on the byte control, then the original byte is allowed to pass onto the data bus unchanged. If the original
data word is altered through byte control, a new check word
must be generated before it is written back into memory.
This is easily accomplished by taking control S1 and S0 low.
Table VI lists the read-modify-write functions.
6
TABLE VII. DP8402A, DP8403 Diagnostic Function
CONTROL
EDAC FUNCTION
Read & flag
DATA I/O
S1
S0
H
L
Input correct
data word
H
L
H
H
Latch input check
word while data
input latch remains
transparent
L
H
Input
diagnostic
data word ²
Latch diagnostic
data word into
output latch
L
H
Input
diagnostic
data word ²
Latch diagnostic
data word into
input latch
DB BYTE DB OUTPUT
CONTROL
LATCH
OEBn
LEDBO
H
Output diagnostic
data word &
syndrome bits
H
Output corrected
diagnostic data
word & output
syndrome bits
H
H
H
H
Input
diagnostic
data word
latched
H
Output
diagnostic
data word
L
Output
corrected
diagnostic
data word
L
CB
CONTROL
OECB
Input correct
check bits
X
H
CHECK I/O
H
Input
check bits
latched
H
H
L
ERROR FLAGS
ERR
MERR
H
H
Output latched
check bits
L
Hi-Z
H
Output
syndrome
bits
L
Hi-Z
H
Output
syndrome
bits
L
Hi-Z
H
Output
syndrome
bits
L
Hi-Z
H
H
Enabled
Enabled
Enabled
Enabled
Enabled
² Diagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case, the diagnostic data word will contain errors in
two bit locations.
TABLE VIII. DP8404, DP8405 Diagnostic Function
EDAC FUNCTION
CONTROL
S1
S0
Read & flag
H
L
Input correct
data word
H
Input correct
check bits
H
Latch input check
bits while data
input latch remains
transparent
L
H
Input
diagnostic
data word ²
H
Input
check bits
latched
H
Enabled
Output input
check bits
L
H
Input
diagnostic
data word ²
H
Output input
check bits
L
Enabled
H
Output
syndrome bits
L
H
Input
diagnostic
data word
latched
Hi-Z
H
Output corrected
diagnostic
data word
L
Output
syndrome bits
L
Hi-Z
H
Latch diagnostic
data into
input latch
H
Output corrected
diagnostic
data word
H
H
DATA I/O
DB CONTROL
OEDB
CHECK I/O
DB CONTROL
OECB
ERROR FLAGS
ERR
MERR
H
H
Enabled
Enabled
² Diagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case, the diagnostic data word will contain errors in
two bit locations.
7
DP8402A, DP8403 Logic Diagram (Positive Logic)
TL/F/8535 – 4
8
DP8404, DP8405 Logic Diagram (Positive Logic)
TL/F/8535 – 5
9
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Over Operating Free-Air Temperature Range (unless otherwise noted)
Supply Voltage, VCC (See Note 1)
Input Voltage: CB and DB
All Others
7V
5.5V
7V
Operating Free-Air Temperature: Military b55§ C to a 125§ C
Commercial 0§ to a 70§ C
b 65§ C to a 150§ C
Storage Temperature Range
Recommended Operating Conditions
Symbol
Parameter
VCC
Supply Voltage
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
IOH
High-Level Output Current
tw
Low-Level Output Current
Pulse Duration
tsu
th
Setup Time
Hold Time
Commercial
Typ
Max
Min Typ
Max
4.5
5
5.5
4.5
5.5
V
0.8
0.8
V
b 0.4
b 0.4
b1
b 2.6
ERR Or MERR
DP8402A, DP8404
5
2
V
ERR Or MERR
4
8
DB or CB
12
24
LEDBO Low
25
25
(1) Data And Check Word Before S0u
(S1 e H)
15
10
(2) SO High Before LEDBOu (S1 e H) ²
45
45
(3) LEDBO High Before The Earlier
of S0v or S1v ²
0
0
(4) LEDBO High Before S1u (S0 e H)
0
0
(5) Diagnostic Data Word Before S1u
(S0 e H)
15
10
(6) Diagnostic Check Word Before
The Later Of S1v or S0u
15
10
(7) Diagnostic Data Word Before
LEDBOu (S1 e L and S0 e H) ³
25
20
(8) Read-Mode, S0 Low And S1 High
35
30
(9) Data And Check Word After
S0u (S1 e H)
20
15
(10) Data Word After S1u (S0 e H)
20
15
(11) Check Word After The Later
of S1v or S0u
20
15
(12) Diagnostic Data Word After
LEDBOu (S1 e L And S0 e H) ³
0
0
tcorr
Correction Time (see Figure 1 )*
65
TA
Operating Free-Air Temperature
b 55
0
10
mA
mA
ns
ns
ns
58
125
*This specification may be interpreted as the maximum delay to guarantee valid corrected data at the output and includes the tsu setup delay.
² These times ensure that corrected data is saved in the output data latch.
³ These times ensure that the diagnostic data word is saved in the output data latch.
Units
Min
2
DB Or CB
IOL
Military
Conditions
ns
70
§C
DP8402A, DP8404 Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range (unless otherwise noted)
Military
Symbol
Parameter
Test Conditions
Min
VIK
VCC e 4.5V, II e b18 mA
All outputs
VOH
DB or CB
ERR or MERR
VOL
DB or CB
II
Typ ²
Min
b 1.5
VCC e 4.5V to 5.5V, IOH e b 0.4 mA
VCC e 4.5V, IOH e b1 mA
VCCb2
2.4
b 1.5
3.3
V
2.4
0.25
3.2
0.4
VCC e 4.5V, IOL e 8 mA
VCC e 4.5V, IOL e 12 mA
0.25
0.4
VCC e 4.5V, IOL e 24 mA
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.1
All others
VCC e 5.5V, VI e 5.5V
0.1
0.1
All others ³
20
20
20
20
b 0.4
b 0.4
b0.1
b 0.1
VCC e 5.5V, VI e 2.7V
VCC e 5.5V, VI e 0.4V
IO õ
VCC e 5.5V, VO e 2.25V
ICC
VCC e 5.5V, (See Note 1)
b 30
b 112
150
b 30
250
150
V
0.5
0.1
S0 or S1
V
VCCb2
VCC e 4.5V, IOH e b2.6 mA
VCC e 4.5V, IOL e 4 mA
Units
Max
VCC e 5.5V, VI e 7V
All others ³
IIL
Max
S0 or S1
S0 or S1
IIH
Commercial
Typ ²
mA
mA
mA
b 112
mA
250
mA
DP8403, DP8405 Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range (unless otherwise noted)
Military
Symbol
Parameter
Test Conditions
Min
VIK
VOH
IOH
VCC e 4.5V, II e b18 mA
VCC e 4.5V to 5.5V, IOH e b0.4 mA
DB or CB
VCC e 4.5V, VOH e 5.5V
ERR or MERR
DB or CB
IIH
IIL
IO õ
All others ³
ERR or MERR
ICC
² All typical values are at VCC e
b 1.5
0.25
0.4
0.25
0.4
V
V
0.1
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
mA
V
mA
VCC e 5.5V, VI e 2.7V
mA
VCC e 5.5V, VI e 0.4V
mA
VCC e 5.5V, VO e 2.25V
b 30
VCC e 5.5V, (See Note 1)
5V, TA e a 25§ C.
b 112
150
b 30
b 112
150
³ For I/O ports (QA through QH), the parameters IIH and IIL include the off-state output current.
õ The
Units
Max
VCCb2
VCC e 4.5V, IOL e 24 mA
VCC e 5.5V, VI e 5.5V
Typ ²
0.1
VCC e 4.5V, IOL e 12 mA
All others
S0 or S1
Min
VCC e 4.5V, IOL e 8 mA
VCC e 5.5V, VI e 7V
All others ³
VCCb2
VCC e 4.5V, IOL e 4 mA
S0 or S1
S0 or S1
Commercial
Max
b 1.5
ERR or MERR
VOL
II
Typ ²
output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
Note 1: ICC is measured with S0 and S1 at 4.5V and all CB and DB pins grounded.
11
mA
mA
DP8402A Switching Characteristics
VCC e 4.5V to 5.5V, CL e 50 pF, TA e Min to Max (unless otherwise noted)
Symbol
From
(Input)
To
(Output)
Military
Test Conditions
Commercial
Min
Max
Min
Max
Units
DB and CB
ERR
S1 e H, S0 e L, RL e 500X
10
43
10
40
DB
ERR
S1 e L, S0 e H, RL e 500X
10
43
10
40
DB and CB
MERR
S1 e H, S0 e L, RL e 500X
15
67
15
55
DB
MERR
S1 e L, S0 e H, RL e 500X
15
67
15
55
tpd
S0v and S1v
CB
R1 e R2 e 500X
10
60
10
48
ns
tpd
DB
CB
S1 e L, S0 e L, R1 e R2 e 500X
10
60
10
48
ns
tpd
LEDB0v
DB
S1 e X, S0 e H, R1 e R2 e 500X
7
35
7
30
ns
tpd
S1u
CB
S0 e H, R1 e R2 e 500X
10
60
10
50
ns
ten
OECBv
CB
S0 e H, S1 e X, R1 e R2 e 500X
2
30
2
25
ns
tdis
OECBu
CB
S0 e H, S1 e X, R1 e R2 e 500X
2
30
2
25
ns
ten
OEB0 thru OEB3v
DB
S0 e H, S1 e X, R1 e R2 e 500X
2
30
2
25
ns
tdis
OEB0 thru OEB3u
DB
S0 e H, S1 e X, R1 e R2 e 500X
2
30
2
25
ns
tpd
tpd
ns
ns
DP8403 Switching Characteristics
VCC e 4.5V to 5.5V, CL e 50 pF, TA e Min to Max (unless otherwise noted)
Commercial
Test Conditions
DB and CB
ERR
S1 e H, S0 e L, RL e 500X
26
26
DB
ERR
S1 e L, S0 e H, RL e 500X
26
26
tpd
DB and CB
MERR
S1 e H, S0 e L, RL e 500X
40
40
S1 e L, S0 e H, RL e 500X
40
40
tpd
S0v and S1v
CB
RL e 680X
40
40
ns
tpd
DB
CB
S1 e L, S0 e L, RL e 680X
40
40
ns
tpd
LEDB0v
DB
S1 e X, S0 e H, RL e 680X
26
26
ns
tpd
S1u
CB
S0 e H, RL e 680X
40
40
ns
tPLH
OECBu
CB
S1 e X, S0 e H, RL e 680X
24
24
ns
tPHL
OECBv
CB
S1 e X, S0 e H, RL e 680X
24
24
ns
tPLH
OEB0 thru OEB3u
DB
S1 e X, S0 e H, RL e 680X
24
24
ns
tPHL
OEB0 thru OEB3v
DB
S1 e X, S0 e H, RL e 680X
24
24
ns
tpd
From
(Input)
Military
To
(Output)
Symbol
Min
² All typical values are at VCC e 5V, TA e a 25§ C.
12
Typ ²
Max
Min
Typ ²
Units
Max
ns
ns
DP8404 Switching Characteristics, VCC e 4.5V to 5.5V, CL e 50 pF, TA e Min to Max
Symbol
tpd
tpd
From
(Input)
To
(Output)
DB and CB
ERR
DB and CB
MERR
Military
Test Conditions
Min
Typ ²
Commercial
Max
Min
Typ ²
S1 e H, S0 e L, RL e 500X
26
26
S1 e L, S0 e H, RL e 500X
26
26
S1 e H, S0 e L, RL e 500X
40
40
S1 e L, S0 e H, RL e 500X
40
40
Units
Max
ns
ns
tpd
S0v and S1v
CB
R1 e R2 e 500X
35
35
ns
tpd
DB
CB
S1 e L, S0 e L, R1 e R2 e 500X
35
35
ns
tpd
S1u
CB
S0 e H, R1 e R2 e 500X
35
35
ns
ten
OECBv
CB
S1 e X, S0 e H, R1 e R2 e 500X
18
18
ns
tdis
OECBu
CB
S1 e X, S0 e H, R1 e R2 e 500X
18
18
ns
ten
OECBv
DB
S1 e X, S0 e H, R1 e R2 e 500X
18
18
ns
tdis
OECBu
DB
S1 e X, S0 e H, R1 e R2 e 500X
18
18
ns
DP8405 Switching Characteristics, VCC e 4.5V to 5.5V, CL e 50 pF, TA e Min to Max
Symbol
tpd
tpd
tpd
Military
Commercial
From
(Input)
To
(Output)
Test Conditions
DB and CB
ERR
S1 e H, S0 e L, RL e 500X
26
26
DB
ERR
S1 e L, S0 e H, RL e 500X
26
26
DB and CB
MERR
S1 e H, S0 e L, RL e 500X
40
40
S1 e L, S0 e H, RL e 500X
40
40
CB
RL e 680X
40
40
ns
ns
S0v and S1v
Min
Typ ²
Max
Min
Typ ²
Units
Max
ns
ns
tpd
DB
CB
S1 e L, S0 e L, RL e 680X
40
40
tpd
S1u
DB
S0 e H, RL e 680X
40
40
ns
tPLH
OECBu
CB
S1 e X, S0 e H, RL e 500X
24
24
ns
tPHL
OECBv
CB
S1 e X, S0 e H, RL e 680X
24
24
ns
tPLH
OEDBu
DB
S1 e X, S0 e H, RL e 680X
24
24
ns
tPHL
OEDBv
DB
S1 e X, S0 e H, RL e 680X
24
24
ns
² All typical values are at VCC e 5V, TA e a 25§ C.
13
Switching Waveforms
TL/F/8535 – 6
FIGURE 1. Read, Flag, and Correct Mode
TL/F/8535 – 7
FIGURE 2. Read, Correct Modify Mode
14
Switching Waveforms (Continued)
TL/F/8535 – 8
FIGURE 3. Diagnostic Mode
15
DP8402A Interfaced to the DP8418/19/28/29 System Diagram
TL/F/8535 – 9
16
DP8402A Interfaced to the DP8420A/21A/22A System Diagram
Tl/F/8535 – 12
Physical Dimensions inches (millimeters)
Hermetic Dual-In-Line (D)
Order Number DP8402AD or DP8403D
NS Package Number D52A
17
DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel
Error Detection and Correction Circuits (EDAC’s)
Physical Dimensions inches (millimeters) (Continued)
Lit. Ý103062
Plastic Chip Carrier (V)
Order Number DP8402AV
NS Package Number V68A
48 Lead Hermetic DIP (D)
Order Number DP8404D or DP8405D
NS Package Number D48A
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