NSC DP8440V-40 Microcmos programmable 16/64 mbit dynamic ram controller/driver Datasheet

DP8440-40/DP8440-25/DP8441-40/DP8441-25
microCMOS Programmable 16/64 Mbit
Dynamic RAM Controller/Driver
General Description
Features
The DP8440/41 Dynamic RAM Controllers provide an easy
interface between dynamic RAM arrays and 8-, 16-, 32- and
64-bit microprocessors. The DP8440/41 DRAM Controllers
generate all necessary control and timing signals to successfully interface and design dynamic memory systems.
With significant enhancements over the DP8420/21/22
predecessors, the DP8440/41 are suitable for high performance memory systems. These controllers support page and
burst accesses for fast page, static column and nibble
DRAMs. Refreshes and accesses are arbitrated on chip.
RAS low time during refresh and RAS precharge time are
guaranteed by these controllers. Separate precharge counters for each RAS output avoid delayed back to back accesses due to precharge when using memory interleaving.
Programmable features make the DP8440/41 DRAM Controllers flexible enough to fit many memory systems.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
40 MHz and 25 MHz operation
Page detection
Automatic CPU burst accesses
Support 1/4/16/64 Mbits DRAMs
High capacitance drivers for RAS, CAS, WE and Q outputs
Support for fast page, static column and nibble mode
DRAMs
High precision PLL based delay line
Byte enable for word size up to 32 bits on the DP8440
or 64 bits on the DP8441
Automatic Internal Refresh
Staggered RAS-Only refresh
Burst and CAS-before-RAS refresh
Error scrubbing during refresh
TRI-STATEÉ outputs
Easy interface to all major microprocessors
Block Diagram
TL/F/11718 – 1
FIGURE 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/11718
RRD-B30M75/Printed in U. S. A.
DP8440-40/DP8440-25/DP8441-40/DP8441-25 microCMOS Programmable 16/64 Mbit
Dynamic RAM Controller/Driver
February 1995
DRAM
Controller
Maximum Clock
Frequency
Package
Type
Bus Width
Supporting
Largest DRAM
Possible
DP8440V-40
40 MHz
84-Pin PLCC
8, 16, 32
16 Mbits
DP8440VLJ-40
40 MHz
100-Pin PQFP
8, 16, 32
16 Mbits
DP8440VLJ-25
25 MHz
100-Pin PQFP
8, 16, 32
16 Mbits
DP8441VLJ-40
40 MHz
100-Pin PQFP
8, 16, 32, 64
64 Mbits
DP8441VLJ-25
25 MHz
100-Pin PQFP
8, 16, 32, 64
64 Mbits
Table of Contents
7.0 WAIT SUPPORT
1.0 CONNECTION DIAGRAMS
7.1 DTACK During Opening Access
2.0 FUNCTIONAL INTRODUCTION
7.2 DTACK During Page Access
3.0 SIGNAL DESCRIPTION
7.3 DTACK During Burst Access
3.1 Address and Control Signals
7.4 Next Address or Early DTACK Support
3.2 DRAM Control Signals
3.3 Refresh Signals
8.0 ABSOLUTE MAXIMUM RATINGS
3.4 Reset and Programming Signals
9.0 DC ELECTRICAL CHARACTERISTICS
3.5 Clock Inputs
10.0 LOAD CAPACITANCE
3.6 Power Signals and Capacitor Input
11.0 AC TIMING PARAMETERS
4.0 PROGRAMMING AND RESETTING
12.0 AC TIMING WAVEFORMS
4.1 Reset
CLK and DECLK Timing
4.2 Programming Sequence
Refresh Timing
4.3 Programming Selection Bits
Refresh and Access Timing
5.0 ACCESS MODES
Programming and Initialization Period Timing
5.1 Opening Access
Normal Mode Access Timing
5.2 Normal Mode
Page Mode Access Timing
5.3 Page Mode
Burst Mode Access Timing
5.4 Burst Access
13.0 ERRATA
5.5 Inner Page Burst Access
14.0 PHYSICAL DIMENSIONS
6.0 REFRESH MODES
6.1 Auto-Internal Refresh
6.2 Externally Controlled Refresh
6.3 Error Scrubbing during Refresh
6.4 Extending Refresh
6.5 Refresh Types
2
1.0 Connection Diagrams
TL/F/11718 – 2
Top View
FIGURE 2
Order Number DP8441VLJ-40 (40 MHz Operation), DP8441VLJ-25 (25 MHz Operation)
See NS Package Number VLJ100A
3
1.0 Connection Diagrams (Continued)
TL/F/11718 – 38
Top View
FIGURE 3
Order Number DP8440VLJ-40 (40 MHz Operation), DP8440VLJ-25 (25 MHz Operation)
See NS Package Number VLJ100A
4
1.0 Connection Diagrams (Continued)
TL/F/11718 – 3
Top View
FIGURE 4
Order Number DP8440V-40 (40 MHz Operation)
See NS Package Number V84A
5
2.0 Functional Introduction
Burst Access: These controllers can also generate new
addresses to burst a specific number of locations. The user
can choose to burst in a wrap around fashion for 2, 4, 8, 16
locations. Or, if the input NoWRAP is asserted, the controller will burst consecutive locations and the column address
will not wrap around. The controller must be programmed in
Latch Mode to generate the burst addresses.
Refresh Modes: The DP8440/41 can perform Automatic
Internal Refreshes, or Externally Controlled Refreshes. During a long page access the controller can queue up to six
refresh requests and burst refresh the addresses missed
when the access finishes.
Refresh Types: The DP8440/41 can be programmed to do
all RAS Refresh, Staggered Refresh, Error Scrubbing during
Refresh or CAS-before-RAS refresh.
Wait Support: These controllers provide wait logic for all
three types of accesses. The user needs to program the
desired number of wait states for opening, page and burst
accesses.
RAS and CAS Configurations: The RAS outputs can be
programmed to drive one, two or four banks of memory and
the CAS drivers can be programmed for byte writing in buses up to 64 bits wide.
TRI-STATE Outputs and Multiporting: The GRANT input
can be used for multi-porting. When high this input will
TRI-STATE the outputs, allowing another controller to drive
the DRAM.
Other Features: Independent RAS precharge counters allow memory interleaving, thus back to back access to different memory banks is not delayed due to precharge.
The output NADTACK can be used to pipeline one address,
getting the next access to start one clock early.
The input NoWRAP will increment the address during a
burst access in a linear fashion. This is convenient for
graphics or long page access.
Terminology: This paragraph explains the terminology
used in this data sheet. The terms negated and asserted are
used. For example, ECAS0 asserted means the ECAS0 input is at logic 0. The term NoWRAP asserted means that
NoWRAP is at logic 1.
Reset and Programming: After the power up, the
DP8440/41 must be reset and programmed before it can be
used to access the DRAM. The chip is programmed through
the address bus.
Initialization Period: After programming, the DP8440/41
enter a 60 ms initialization period. During this time the
DP8440/41 perform refreshes to the DRAM. Further warm
up cycles are unnecessary. The user must wait until the
initialization is over to access the memory.
Modes of Operation: The DP8440/41 are synchronous
DRAM controllers. Every access is synchronized to the system clock. The controllers can be programmed in Page
Mode or Normal Mode. Burst accesses are dynamically requested through the input BSTARQ.
Opening Access: They involve a new row address. Regardless of the access mode programmed, opening accesses
behave in the same way. ADS and CS initiate and qualify
every access. After asserting the ADS, the DP8440/41 will
assert RAS from the next rising edge of the CLK. The
DP8440/41 will hold the row address on the DRAM address
bus and guarantee that the row address is held for the Row
Address Hold Time (tRAH) programmed. The DRAM controller will then switch the internal multiplexor to place the column address on the DRAM address bus and assert CAS.
DTACK will wait the programmed number of wait states before asserting to indicate the end of the access.
Normal Access: If the controller is programmed in Normal
Mode (B1 e 1), RAS will assert and negate after the programmed RAS low time. The user can perform burst access
if desired.
Page Access: The DP8440/41 have an internal page comparator. This feature enables the user to do a series of accesses without negating RAS for as long as the row address
remains unchanged. The user needs to provide a new address for every access. The page comparator can also be
programmed as an input. This is beneficial for CPUs that
have an internal page comparator. The user can do burst
accesses while in page if desired.
6
3.0 Signal Descriptions
3.1 ADDRESS AND CONTROL SIGNALS
Pin
Name
Device (if not
Input/
Applicable to All) Output
Description
R0 – 11
R0 – 12
DP8440
DP8441
I
ROW ADDRESS: These inputs are used to specify the row address during an access to
the DRAM. They are also used to program the chip when ML is asserted.
C0 – 11
C0 – 12
DP8440
DP8441
I
COLUMN ADDRESS: These inputs are used to specify the column address during an
access to the DRAM. They are also used to program the chip when ML is asserted.
I
BANK SELECT: Depending on programming, these inputs are used to select group RAS
and CAS outputs to assert during an access. They are also used to program the chip when
the ML is asserted.
I
ENABLE CAS: These inputs asserted enable a single or group of CAS outputs. In
combination with the B0, B1 and the programming selection, these inputs select which
CAS outputs will assert during an access. The ECAS signals can also be used to toggle a
group of CAS outputs during page or burst mode accesses. They are also used to program
the chip when ML is asserted.
I
NO WRAP: Asserting this signal causes the column address to be incremented
sequentially by one. The column address will not wrap around if NoWRAP is asserted.
When RFIP is asserted, this signal is an EXTNDRF, used to extend refresh by any number
of CLK periods until EXTNDRF is negated.
I
COLUMN ADDRESS LATCH DISABLE: This input will disable ADS from latching the
column address when Latch Mode is selected.
I
ADDRESS STROBE: This input starts every access. Depending on programming this input
could latch the column address from the rising edge.
CS
I
CHIP SELECT: This input signal must be asserted to enable ADS to start an access.
DTACK
O
DATA TRANSFER ACKNOWLEDGE: This output can be programmed to insert wait
states into a CPU access cycle. DTACK negated signifies a wait condition, when asserted
signifies that the access has taken place. This signal can be delayed a number of positive
or negative edges of clock. During burst accesses, DTACK transitions increment the
column address.
NADTACK
O
NEXT ADDRESS or EARLY DTACK: This output asserts one clock cycle before DTACK.
This output can be used to request the next address in a sort of pipelining fashion or it
provides more time when DTACK needs to be generated externally.
B0 – B1
ECAS0 – 3
ECAS0 – 7
DP8440
DP8441
NoWRAP
(EXTNDRF)
NoLATCH
DP8441
ADS
WAITIN
I
WAIT INPUT: This input asserted delays DTACK for one extra clock period.
I
MEMORY ACCESS GRANT: The GRANT input functions as an output enable. If negated,
it forces the outputs to a TRI-STATE condition.
PAGMISS
I/O
PAGE MISS: When programmed as an output, this signal asserts when either the row or
the bank address changes from the previous access cycle or the column address has
been incremented beyond the page boundary. If this pin is programmed as an input, it is
the responsibility of the system to tell the controller if the next access is within the page.
Useful for CPUs with internal page comparators, PAGMISS is valid only if ADS and CS are
asserted.
BSTARQ/
BSTARQ
I
BURST ACCESS REQUEST: This input enables the Burst Access Mode. This input can be
programmed to be active high or active low.
GRANT
DP8441
7
3.0 Signal Descriptions (Continued)
3.2 DRAM CONTROL SIGNALS
Pin
Name
Q0 – 11
Q0 – 12
Device (if not
Applicable to All)
DP8440
DP8441
Input/
Output
Description
O
DRAM ADDRESS: These output signals are the multiplexed outputs of the R0 – 11/12 and
C0–11/12 and form the DRAM address bus. These outputs contain the refresh address
whenever RFIP is asserted. They have high capacitive drivers with 20Xs series damping
resistors.
O
ROW ADDRESS STROBES: These outputs are asserted to latch the row address
contained on the outputs Q0 – 11/12 into the DRAM. When RFIP is asserted, the RAS
outputs are used to latch the refresh row address contained on the Q0 – 11/12 outputs into
the DRAM. These outputs have high capacitive drivers with 20X series damping resistors.
O
COLUMN ADDRESS STROBES: These outputs are asserted to latch the column address
contained on the outputs Q0 – 11/12 into the DRAM. When RFIP is asserted and CASbefore-RAS refresh is selected, the CAS outputs will assert 1T (one clock period) before
the RAS outputs are asserted. These outputs have high capacitive drivers with 20X series
damping resistors.
WE
O
WRITE ENABLE: This output asserted specifies a write operation to the DRAM. When
negated, this output specifies a read operation to the DRAM. This output has a high
capacitive driver and a 20X series damping resistor.
WIN
I
WRITE ENABLE IN: This input is used to signify a write operation to the DRAM. The WE
output will follow this input. Also, this input controls the precharge time for Read and Write
during Burst Mode Access.
RAS0 – 3
CAS0 – 3
CAS0 – 7
DP8440
DP8441
3.3 REFRESH SIGNALS
Pin
Name
Device (if not
Input/
Applicable to All) Output
Description
RFRQ
O
REFRESH REQUEST: When RFRQ is asserted, it specifies that 15 ms or 120 ms have
passed. If DISRFSH is negated and the controller is not into an access cycle, the
DP8440/41 will perform an internal refresh. If DISRFSH is asserted, RFRQ can be used to
externally request a refresh by asserting the input RFSH.
RFIP
O
REFRESH IN PROGRESS: This output is asserted prior to a refresh cycle and is negated
when all the RAS outputs are negated for that refresh.
RFSH
I
REFRESH: This input asserted with DISRFSH already asserted will request a refresh. If
this input is continually asserted, the DP8440/41 will perform refresh cycles in a burst
refresh fashion until the input is negated. If RFSH is asserted with DISRFSH negated, the
internal refresh address counter is cleared. This technique is useful for burst refreshes.
DISRFSH
I
DISABLE REFRESH: This input is used to disable internal refreshes and must be asserted
when using RFSH for externally requested refreshes.
3.4 RESET AND PROGRAMMING SIGNALS
Pin
Name
Device (if not
Applicable to All)
Input/
Output
Description
ML
I
MODE LOAD: This input signal, when low, enables the internal programming register that
stores the programming information.
RESET
I
SYSTEM RESET: Reset forces the DP8440/41 to be set at a known state. VCC, CLK and
DELCLK have to reach their proper DC and AC specifications for at least 1 ms before
negating the RESET signal. All outputs are negated when RESET is asserted.
8
3.0 Signal Descriptions (Continued)
3.5 CLOCK INPUTS
Pin
Name
Device (if not
Applicable to All)
Input/
Output
Description
CLK
I
SYSTEM CLOCK: This input may be in the range of 500 kHz to 40 MHz. This input is
generally a constant frequency but it may be controlled externally to change frequencies
for some arbitrary reason. This input provides the clock to the internal state machine that
arbitrates between accesses and refreshes. This clock’s positive edges and negative
edges are used to extend the DTACK signal. This clock is also used as a reference for the
RAS precharge time, the RAS low during refresh time and CAS precharge time.
DELCLK
I
DELAY LINE CLOCK: The clock input DELCLK, may be in the range of 10 MHz to 40 MHz
and should be a multiple of 2 to have the DP8440/41 switching characteristics hold. If
DELCLK is not one of the above frequencies, the accuracy of the internal delay line will
suffer. This happens because the phase lock loop that generates the delay line assumes
an input clock frequency multiple of 2 MHz.
For example, if DELCLK input is 17 MHz and we choose to divide by 8 (program bits
C0–3), this will produce 2.125 MHz which is 6.25% off of 2 MHz. Therefore, the
DP8440/41 delay line will produce delays that are shorter (faster delays) than intended. If
divide by 9 was chosen, the delay line would produce longer delays (slower delays) than
intended (1.89 MHz instead of 2 MHz). This clock is also divided to create the internal
refresh clock.
3.6 POWER SIGNALS AND CAPACITOR INPUT
Pin
Name
Device (if not
Applicable to All)
Input/
Output
Description
VCC
I
POWER: Supply Voltage.
GND
I
GROUND: Supply Voltage Reference.
CAP
I
CAPACITOR: This input is used by the internal PLL for stabilization. The value of the
ceramic capacitor should be 0.1 mF and it should be connected between this input and
ground.
9
4.0 Programming and Resetting
4.1 RESET
When ML goes high the part is programmed. After the first
programming after a reset the part will enter a 60 ms initialization period. During this period the controller will refresh
the memory, so further DRAM warm up cycles are not necessary. The user can program the part on the fly by pulsing
ML low and high (provided that no refresh is in progress)
while a valid programming selection is on the address bus.
The part will not enter the initialization period when it is only
re-programmed.
After power up, the DP8440/41 must be reset and programmed before it can be used to access the DRAM. Reset
is accomplished by asserting the input RESET for at least
16 positive edges of CLK after VCC stabilizes. After reset,
the part can be programmed.
4.2 PROGRAMMING
Programming is accomplished by presenting a valid programming selection on the row, column, bank selects and
ECAS inputs and toggling the ML input from low to high.
TL/F/11718 – 4
FIGURE 5. Reset
TL/F/11718 – 5
FIGURE 6. Programming
10
Programming the DP8440/41
4.3 PROGRAMMING SELECTION
RAS LOW AND PRECHARGE TIME
R1
0
0
1
1
R0
0
1
0
1
2T
3T
4T
5T
DTACK DURING OPENING ACCESS WILL ASSERT AFTER RAS
R3
0
0
1
1
R2
0
1
0
1
1T
2T
3T
4T
DTACK DURING BURST ACCESS WILL ASSERT AFTER CAS
R5
0
0
1
1
R4
0
1
0
1
0T
1T
2T
3T
DTACK DURING PAGE ACCESS WILL ASSERT AFTER CAS
R7
0
0
1
1
R6
0
1
0
1
0T
1T
2T
3T
PAGE SIZE SELECT
R9
0
0
1
1
R8
0
1
0
1
512
1024
2048
4096
WRAP AROUND SIZE
R11
0
0
1
1
R10
0
1
0
1
2
4
8
16
11
Programming the DP8440/41 (Continued)
4.3 PROGRAMMING SELECTION (Continued)
DIVISOR SELECT
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
RAS AND CAS CONFIGURATIONS AND REFRESH BEHAVIOR
C5 C4
0 0 All RAS and all CAS are selected. B0 and B1 are not used. All RAS refresh.
0
1
If C6 e 0 Non Error
B1
B0 is not Used
Scrubbing Selected. All 0 RAS0–1
CAS Selected. 2-Step
1 RAS2–3
Staggered Refresh.
If C6 e 1 Error
B1
B0 is Not Used
Scrubbing Selected. 0 RAS0 – 1 and CAS0 – 1, CAS4 – 5
All RAS Refresh.
1 RAS2 – 3 and CAS2 – 3, CAS6 – 7
CAS Pairs Selected.
1
0
If C6 e 0 Non Error
Scrubbing Selected.
All CASs Selected.
4-Step Staggered
Refresh.
B1
B0
0
0
1
1
0
1
0
1
If C6 e 1 Error
Scrubbing Selected.
All RAS Refresh.
CAS Pairs
Selected.
If C6 e 0 Non Error
Scrubbing. 2-Step
Staggered Refresh.
CAS Pairs Selected.
B1
1
1
RAS0
RAS1
RAS2
RAS3
B0 is not used.
B0
0
0
1
1
0
1
0
1
RAS0, CAS0 – 4
RAS1, CAS1 – 5
RAS2, CAS2 – 6
RAS3, CAS3 – 7
If C6 e 1 Error
B1
B0 is not used.
Scrubbing Selected. 0 RAS0 – 1 and CAS0,1,4,5
All RAS Refresh.
1 RAS2 – 3 and CAS2,3,6,7
CAS Pairs Selected.
0 RAS0–1 and CAS0,1,4,5
1 RAS2–3 and CAS2,3,6,7
ERROR SCRUBBING MODE SELECT
C6
0
1
B1
Staggered Refresh (Non Error Scrubbing)
Error Scrubbing (No CAS-before-RAS and No Staggered Refresh)
12
Programming the DP8440/41 (Continued)
4.3 PROGRAMMING SELECTION (Continued)
ROW ADDRESS HOLD TIME SELECT tRAH
C7
0
1
10 ns
15 ns
PAGMISS INPUT OR OUTPUT SELECT
C8
0
1
Input
Output
CAS PRECHARGE DURING BURST
C9
0
1
Read Cycle
(/2T
1T
Write Cycle
1T
2T
REFRESH MODE SELECT
C10
0
1
RAS Only Refresh
CAS-before-RAS Refresh
FINE TUNE REFRESH CYCLE
C11
0
1
15 ms
120 ms
COLUMN ADDRESS COUNTER CONTROL SELECT
B0
0
1
DTACK Falling Edge
DTACK Rising Edge
PAGE OR NORMAL MODE SELECT
B1
0
1
Page Mode
Normal Mode
ADDRESS LATCH MODE
ECAS 0
0
1
Latch Mode
Fall Through Mode
BURST REQUEST SELECT (BSTARQ INPUT)
ECAS1
0
1
Active Low
Active High
CAS AND DTACK CLOCK EDGE SELECT
ECAS2
0
1
Rising Edge
Falling Edge
RESERVED
ECAS3
0
1
13
5.0 Accessing Modes
The DP8440/41 are synchronous machines. They allow the
user to access the DRAM in three different ways, Page,
Burst and Normal mode. Every one of these accesses starts
in the same way, this datasheet calls it an Opening Access.
5.2 NORMAL MODE
When the controller is programmed in Normal Mode
(B1 e 1), RAS asserts only for the programmed number of
clocks selected by R0 – 1, RAS Low Time, and automatically
negates from a rising clock edge. To finish the access, CAS
negates from the same clock edge at which DTACK negates. After RAS negates, the DP8440/41 will guarantee
the programmed number of positive edges of clock for RAS
precharge. RAS will not assert for another access until precharge is met. Figure 7 shows an opening access (Normal
Mode) followed by a delayed access due to precharge (accessing the same bank). The second access is delayed by
one clock period to meet precharge time requirements.
5.1 OPENING ACCESS
Every access starts with ADS and CS asserting. ADS, CS
and the address inputs must meet setup timings with respect to the next rising edge of CLK. The DP8440/41
places the row address on the Q outputs and RAS asserts
from the rising edge of CLK that ADS is set up to. The
DP8440/41 guarantees the programmed Row Address Hold
Time, tRAH, before switching the internal multiplexer to
place the column address on the Q outputs. After the column address is valid on the Q outputs, the controller asserts
CAS. The DRAM controller always guarantees tASC of 0 ns.
DTACK asserts after RAS according to the programming
selection (R2 – 3). If the user programs Latch Mode, through
programming bit ECAS0, the DRAM controller latches the
column address on the rising edge of ADS (Normal or Page
Mode). If not, the controller keeps the latches in a fall
through mode.
TL/F/11718 – 6
FIGURE 7. A Normal Opening Access and Delayed Access
(RAS Low Time is Programmed for 2 Clocks)
14
5.0 Accessing Modes (Continued)
During page accesses only CAS and DTACK toggle until
there is a page miss. When a page miss is detected, the
DP8440/41 will negate RAS and meet the programmed precharge time. CPUs with page comparators can program the
DRAM controller’s page comparator as an input. When this
input asserts, it indicates that a page change has occurred,
RAS will negate and the controller will meet the precharge
time. Figure 8 shows an opening access followed by two
page accesses. The first page access is a ‘‘page hit,’’ the
second access is out of page.
5.3 PAGE MODE ACCESS
When the DP8440/41 is programmed for Page Accesses,
every access after the opening access needs a new address and a new ADS. During Page Mode the DRAM controller keeps RAS asserted until there is a page miss detected. When a new access is requested, CAS asserts from
the rising CLK edge that ADS is set up to for reads, and
is delayed 1 clock for writes. DTACK asserts according to
the programming selection in bits R6–7. At the end of a
page access only CAS and DTACK negate and they negate
on the same clock edge.
TL/F/11718 – 7
FIGURE 8. Opening Access Followed by Page Accesses
15
5.0 Accessing Modes (Continued)
TL/F/11718 – 39
FIGURE 9. Page ‘‘Hit’’ Write and Read Followed by Page Miss
(CAS Assertion for Write is Delayed One Clock)
16
5.0 Accessing Modes (Continued)
in which case a Page Miss occurs and the burst access
terminates. Burst accesses can be requested at any time.
The user can do burst accesses while in Page Mode (see
Inner Page Burst), or in Normal Mode. The column address
is incremented by DTACK transitions as programmed by B0.
Thus, if DTACK is programmed as 0 T, the column address
will not be incremented and the CPU must provide the addresses to burst. CAS and DTACK can be programmed to
toggle from either clock edge. The CAS precharge time is
programmable to 1 or (/2 clocks during read accesses and 1
or 2 clocks during write accesses ((/2T e 10 ns minimum of
CAS precharge).
5.4 BURST ACCESS
The DP8440/41 can also perform burst accesses to several
locations in different wrap around sizes. The user requests
burst accesses by asserting the input BSTARQ. BSTARQ
must be negated before the last DTACK. This input can be
programmed to be active high or active low. The number of
burst locations can be programmable to be modulo 2, 4, 8,
or 16. If the beginning of the sequence does not start with 0,
00, 000 or 0000, the controller will wrap around. The user
may choose not to wrap by asserting the input NoWRAP, in
this case the controller will increment the column address
linearly. A NoWRAP burst access cannot cross a page
boundary unless the port is programmed in Page Mode,
TL/F/11718 – 40
FIGURE 10. Burst Write Access
Programming Selection
Bits
Mode
DTACK during Opening
R3 e 1, R2 e 0
3T
DTACK during Burst
R5 e 1, R4 e 0
2T
CAS Precharge during Burst
C9 e 0
Read: (/2T, Write: 1T
Column Address Counter Control
BO e 1
DTACK Rising Edge
CAS and DTACK Edge Select
ECAS2 e 0
Rising Edge
FIGURE 11. Burst Write Access
17
5.0 Accessing Modes (Continued)
TL/F/11718 – 41
FIGURE 12. Burst Read Access
Programming Selection
Bits
Mode
DTACK during Opening
R3 e 1, R2 e 0
3T
DTACK during Burst
R5 e 1, R4 e 0
2T
CAS Precharge during Burst
C9 e 0
Read: (/2T, Write: 1T
Column Address Counter Control
BO e 0
DTACK Falling Edge
CAS and DTACK Edge Select
ECAS2 e 0
Falling Edge
18
5.0 Accessing Modes (Continued)
as long as BSTARQ is asserted. If the user asserts the input
NoWRAP, the controller increments the address sequentially. After an InnerPage Burst, RAS will stay asserted until
there is a page miss detected. Figure 13 shows an opening
access followed by a page access, two burst accesses and
a new access in a different page (page miss).
5.5 INNER PAGE BURST ACCESS
If the user plans to burst within page access, the
DP8440/41 must be programmed in Latch Mode. In this
case, the DRAM latches the column address on the rising
edge of ADS. When the controller detects BSTARQ asserted, DTACK transitions will increment the column address in
modulo 2, 4, 8, or 16 with wrap around at the boundaries for
TL/F/11718 – 9
FIGURE 13. Opening Access followed by a Page ‘‘HIT’’ Access with 2 Bursts
19
6.0 Refresh Modes
The DP8440/41 support auto-internal refresh, and externally control refresh. The DP8440/41 arbitrates between refreshes and accesses and guarantees precharge timings after every access and refresh. The DRAM controller will never interrupt an access in progress to do a refresh, nor will it
interrupt a refresh in progress when an access is requested.
After every refresh the DRAM controller will guarantee the
programmed precharge time before RAS can assert for a
new access or for a second refresh. The refresh period can
be programmed for 15 ms or for 120 ms.
6.1 AUTO-INTERNAL REFRESH
This refresh scheme is completely transparent to the CPU.
The DP8440/41 will refresh the DRAM every 15 ms or
120 ms, depending on the programming selection. When the
refresh counter expires (every 15 ms or 120 ms) the RFRQ
output asserts. On the next rising edge of clock RFIP asserts and, one clock period later, RASs assert. RFIP negates on the same clock edge that RASs negate. If the user
is doing long page or burst accesses, the DP8440/41 will
keep track of up to 6 missed refreshes. At the end of the
access the DRAM controller will burst refresh the locations
missed during the access.
TL/F/11718 – 10
FIGURE 14. Autointernal Refresh (2T of RAS Low and Precharge)
20
6.0 Refresh Modes (Continued)
memory for as long as the inputs are valid. The controller
will guarantee the RAS low and RAS precharge times for
every refresh. The user can choose to monitor the output
RFRQ to externally request a refresh. When RFRQ asserts,
it indicates that the refresh counter has expired.
6.2 EXTERNALLY CONTROLLED REFRESH
The user can perform externally controlled refreshes by asserting the DISRFSH and RFSH input signals. When these
inputs assert, the DP8440/41 will perform a refresh as soon
as possible. If the user keeps RFSH asserted with DISRFSH
already asserted, the DRAM controller will burst refresh the
TL/F/11718 – 11
FIGURE 15. Externally Controlled Refresh (2T of RAS Low and Precharge)
21
6.0 Refresh Modes (Continued)
read-modify-write operation can be performed by asserting
WE. It is the responsibility of the designer to ensure that WE
is negated. The DP8440 has a 26-bit internal refresh address counter that contains the 12 row, 12 column and 2
bank addresses. The DP8441 has a 28-bit internal refresh
address counter that contains the 13 row, 13 column and 2
bank addresses. These counters are configured as bank,
column, row with the row address as the least significant
bits. The bank counter bits are then used with the programming selection to determine which CAS or group of CASs
will assert during a refresh.
6.3 ERROR SCRUBBING DURING REFRESH
The DP8440/41 supports error scrubbing during all RAS
DRAM refreshes. Error scrubbing during refresh is selected
through bits C4 – C6 with bit C6 set during programming. Error scrubbing can not be used with staggered refresh. Error
scrubbing during refresh allows a CAS or group of CASs to
assert during the all RAS refresh as shown in Figure 16 .
This allows data to be read from the DRAM array and
passed through an Error Detection And Correction Chip,
EDAC. If the EDAC determines that the data contains a single bit error and corrects that error, the refresh cycle can be
extended with the input extend refresh, EXTNDRF, and a
TL/F/11718 – 42
FIGURE 16. Error Scrubbing during Refresh (Two Refresh Cycles Shown)
22
6.0 Refresh Modes (Continued)
all the RAS outputs during the re fresh cycle and after the
positive edge of CLK which starts all RAS outputs during the
refresh as shown in Figure 17 . This will extend the refresh to
the next positive edge of CLK and EXTNDRF will be sampled again. The refresh cycle will continue until EXTNDRF is
sampled low on a positive edge of CLK.
6.4 EXTENDING REFRESH
The programmed number of periods of CLK that refresh
RASs are asserted can be extended by one or multiple periods of CLK. Only the all RAS (with or without error scrubbing) type of refresh can be extended. To extend a refresh
cycle, the input extend refresh, EXTNDRF, must be asserted before the positive edge of CLK that would have negated
TL/F/11718 – 43
FIGURE 17. Extending Refresh with the Extend Refresh (EXTNDRF) Input
23
6.0 Refresh Modes (Continued)
The DP8440/41 have a large enough refresh address counter for error scrubbing during refresh. If error scrubbing is
desired, the user must select the All RAS refresh option.
6.5 REFRESH TYPES
The DP8440/41 support RAS Only refresh and CAS-beforeRAS refresh. RAS only refresh can be programmed to be
staggered or non-staggered. Staggered refresh reduces
peak current requirements and system noise.
TL/F/11718 – 12
FIGURE 18. All RAS Refresh with 2Ts of RAS Low and Precharge.
All RAS refresh must be programmed when doing Error Scrubbing.
TL/F/11718 – 13
FIGURE 19. Staggered Refresh with 2Ts RAS low and Precharge.
Staggered refresh is good for noise sensitive systems.
Clearing the Refresh Counter and Refresh Clock: The
user can clear the refresh counter by pulsing RFSH low for
two clocks while DISRFSH is negated. If RFSH is kept asserted for 500 ns, the refresh clock will also be cleared.
TL/F/11718 – 34
24
7.0 Wait Support
The DP8440/41 provide full wait support for all types of
accesses. Through the DTACK output, the user can insert
wait states to provide the necessary time for completing a
memory access. The user needs to program how DTACK
will assert during Opening, Page or Burst accesses. The
user can program DTACK to assert from the rising edge of
clock or from the falling edge of clock.
7.1 OPENING ACCESS
Figures 20 and 21 show DTACK during opening accesses.
DTACK asserts for only one clock cycle. CAS negates from
the same clock edge DTACK negates. When programmed
in Normal Mode, RAS will negate after the programmed
RAS low time. When programmed in Page Mode, RAS will
stay asserted until there is a page miss.
TL/F/11718 – 14
FIGURE 20. DTACK Programmed to Assert from a Positive Edge of Clock
TL/F/11718 – 15
FIGURE 21. DTACK Programmed to Assert from a Negative Edge of Clock
25
7.0 Wait Support (Continued)
Figure 22 shows different DTACK assertions during page
accesses, they follow an opening access with 1 wait state.
DTACK and CAS assert on the rising edge of clock.
7.2 PAGE ACCESSES
During page accesses, DTACK (and CAS) will assert from
either clock edge according to programming bit ECAS2.
TL/F/11718 – 16
FIGURE 22a. DTACK is Programmed 1T for Openings and 0T during Page
TL/F/11718 – 17
FIGURE 22b. DTACK is Programmed 1T for Openings and 1T during Page
TL/F/11718 – 18
FIGURE 22c. DTACK is Programmed 1T for Openings and 2T during Page
TL/F/11718 – 19
FIGURE 22d. DTACK is Programmed 1T for Openings and 3T during Page
Note: DTACK is programmed to assert from a positive clock edge.
26
7.0 Wait Support (Continued)
during burst accesses, following an opening access with
one wait state. In Figure 23a , when the number of wait
states in a burst is programmed to zero, DTACK remains
asserted throughout the burst. The address is not incremented by the DRAM controller. It is the responsibility of the
user to provide incrementing addresses.
For the controller to increment the column address DTACK
must toggle.
7.3 BURST ACCESSES
During burst accesses, DTACK will assert from the clock
edge chosen through programming bit ECAS2. CAS automatically negates and the controller guarantees the minimum CAS precharge time according to programming bit C9.
CAS and DTACK can be programmed to assert from either
clock edge.
During burst accesses, the input BSTARQ must be asserted
for CAS to toggle. Figure 23 shows how DTACK asserts
TL/F/11718 – 20
FIGURE 23a. 1T during Opening and 0T during Burst. DTACK stays asserted during the burst.
TL/F/11718 – 21
FIGURE 23b. 1T during Opening, 1T during Burst
TL/F/11718 – 22
FIGURE 23c. 1T during Opening, 2T during Burst
TL/F/11718 – 23
FIGURE 23d. 1T during Opening, 3T during Burst
27
7.0 Wait Support (Continued)
The user can use this output to request the next address in
a sort of pipelining fashion. This output can also be used to
generate a more accurate DTACK for special applications.
The next figures show how NADTACK asserts in different
cases.
7.4 NADTACK
During any accesses, this output asserts one clock period
before DTACK asserts, except when DTACK is programmed for 1T in normal accesses or 0T during page or
burst accesses.
TL/F/11718 – 24
FIGURE 24a. DTACK is Programmed for 4Ts and to Assert from the Rising CLK Edge
TL/F/11718 – 25
FIGURE 24b. DTACK is Programmed for 2Ts and to Assert from the Falling CLK Edge
TL/F/11718 – 26
FIGURE 24c. DTACK and CAS assert from the rising edge of CLK. DTACK is programmed for 1T. NADTACK asserts
with DTACK during the opening access. During Page Accesses, NADTACK asserts one clock before DTACK.
28
8.0 Absolute Maximum Ratings
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Under Bias
Supply Voltage, VCC
Storage Temperature
All Input and Output Voltage
with Respect to GND
4.75V to 5.25V
0§ C to a 70§ C
Operating Free Air Temperature
0§ C to a 70§ C
b 65§ C to a 150§ C
b 0.5V to a 7V
ESD Rating
2000V
9.0 DC Electrical Characteristics TA e 0§ C to a 70§ C, VCC e 5V g 5%, GND e 0V
Symbol
Parameter
Conditions
Min
VIH
Logical 1 Input Voltage
Tested with a Limited
Functional Pattern
VIL
Logical 0 Input Voltage
Tested with a Limited
Functional Pattern
VOH1
Q and WE Outputs
IOH e b10 mA
VOL1
Q and WE Outputs
IOL e 10 mA
VOH2
All Outputs Except Qs, WE
IOH e b5 mA
VOL2
All Outputs Except Qs, WE
IOL e 5 mA
IIN
Input Leakage Current
VIN e VCC or GND
ICC2
Supply Current
CLK at 40 MHz (I/Os Active)
CIN
Input Capacitance
fIN at 1 MHz
Typ
Max
Units
2.00
VCC a 0.5
V
b 0.5
0.8
V
VCC b 1.0
V
0.5
VCC b1.0
V
V
b 10
5
0.5
V
10
mA
260
mA
10
pF
10.0 Load Capacitance
11.0 AC Timing Parameters
Q0 – 11
WE
RAS0 – 3
CAS0 – 3
CAS0 – 7
Other outputs
Two speed selections are given, the DP8440/41-40 and the
DP8440/41-25. The differences between the two parts are
the maximum operating frequencies of the input CLKs and
the maximum delay specifications. Low frequency applications may use the ‘‘-40’’ part to gain improved timing.
The AC timing parameters are grouped into sectional numbers as shown below. These numbers also refer to the timing diagrams.
1–6
Clock Parameters
50 – 53
TRI-STATE Parameters
100 – 109 Refresh Parameters
200 – 203 Programming Parameters
300 – 325 Common Parameters
400 – 423 Fast access parameters used in burst and Page
Mode accesses
CL
CL
CL
CL
CL
CL
e 50 pF
e 50 pF
e 50 pF
e 50 pF (DP8440)
e 50 pF (DP8441)
e 50 pF
Adder Table for Higher Capacitive Loads
Output
ns/10 pF
Linear up to
Maximum Load
Q0 – 11
0.350
360 pF max
WE
0.548
500 pF max
RAS0 –3
0.282
125 pF max
CAS0 –3
0.282
125 pF max (DP8440)
CAS0 –7
0.334
67 pF max (DP8441)
29
11.0 AC Timing Parameters (Continued)
Ý
Symbol
Description
DP8440/41-40
40 MHz Devices
DP8440/41-25
25 MHz Devices
Min
Min
Max
Max
CLOCK PARAMETER
1
tCLKP
Clock Period
25
40
2, 3
tWCLK
Clock Pulse Width
10
15
4
tDCLKP
DELCLK Period
25
25
5, 6
tWDCLK
DELCLK Pulse Width
10
10
TRI-STATE PARAMETER
50
tPZL
TRI-STATE to Low Voltage Level
20
25
51
tPZH
TRI-STATE to High Voltage Level
20
25
52
tPLZ
Low Voltage Level to TRI-STATE
25
30
53
tPHZ
High Voltage Level to TRI-STATE
25
30
REFRESH PARAMETER
100
tSRFCK
RFSH Asserted Set up to CLK High
6
8
101
tHRFCK
RFSH Asserted Hold Time
3
4
102
tSDRFCK
DISRFSH Asserted Setup to CLK High
6
8
103
tHDRFCK
DISRFSH Asserted Hold Time
3
4
104
tPCKRFL
CLK High to RFIP Asserted
17
20
105
tPCKRFH
CLK High to RFIP Negated
34
36
106
tPCKRQL
CLK High to RFRQ Asserted
13
15
107
tPCKRQH
CLK High to RFRQ Negated
12
14
108
tPCKRFRASL
CLK High to RAS Asserted During Refresh
23
25
109
tPCKRFRASH
CLK High to RAS Negated During Refresh
19
21
PROGRAMMING PARAMETER
200
tWML
ML Pulse Width
15
15
201
tSPBML
Programming Bits Setup to ML High
18
18
202
tHPBML
Programming Bits Hold Time
6
203
tPMLRFL
ML High to RFIP Asserted
6
18
30
18
11.0 AC Timing Parameters (Continued)
Ý
Symbol
DP8440/41-40
40 MHz Devices
Description
Min
Max
DP8440/41-25
25 MHz Devices
Min
Max
COMMON PARAMETER
300
tSADSCK
ADS Asserted Setup to CLK High
10
12
301
tSCSCK
CS Asserted Setup to CLK High
10
12
302a
tSADDCK
Row, Column and Bank Address Valid Setup to CLK High
0
0
302b
tSADDCKP
Row and Bank Address Setup to CLK High in Page Mode Access
18
18
303
tSCSADS
CS Asserted Setup to ADS Negated
6
7
304
tWADS
ADS Pulse Width (Asserted)
6
6
305
tPCKRASL
CLK High to RAS Asserted
17
306
tPCKRASH
CLK High to RAS Negated
18
307a
tPRASCAS0
RAS Asserted to CAS Asserted (tRAH e 10 ns)
20
307b
tPRASCAS1
RAS Asserted to CAS Asserted (tRAH e 15 ns)
25
308a
tPCKCAS0
CLK High to Delay CAS Asserted (tRAH e 10 ns)
308b
tPCKCAS1
CLK High to Delay CAS Asserted (tRAH e 15 ns)
309a
tRAH0
Row Address Hold Time (tRAH e 10 ns)
10
309b
tRAH1
Row Address Hold Time (tRAH e 15 ns)
15
310a
tPCKCV0
CLK High to Column Address Valid (tRAH e 10 ns)
310b
tPCKCV1
CLK High to Column Address Valid (tRAH e 15 ns)
311
tASC
Column Address Setup Time (tASC e 0 ns)
312
tPECSCASL
ECAS Asserted to CAS Asserted
14
16
313
tPECSCASH
ECAS Negated to CAS Negated
14
16
314
tPAQ
Row, Column and Bank Address to Q Valid
17
18
315
tPWINWE
WIN to WE Out
14
16
316
tPCKDTL
CLK High to DATCK Asserted
15
17
317
tPCKDTH
CLK High to DTACK Negated
15
17
318
tPCKLDTL
CLK Low to DATCK Asserted
16
18
319
tPCKLDTH
CLK Low to DTACK Negated
16
18
320
tPCKNADL
CLK High to NADTACK Asserted
15
17
321
tPCKNADH
CLK High to NADTACK Negated
15
17
322
tPCKLNADL
CLK Low to NADTACK Asserted
15
17
323
tPCKLNADH
CLK Low to NADTACK Negated
15
17
324a
tPRASCV0
RAS Asserted to Column Address Valid (tRAH e 10 ns)
38
38
324b
tPRASCV1
RAS Asserted to Column Address Valid (tRAH e 15 ns)
43
325
tHCSCK
CS Asserted Hold from CLK High
20
20
25
60
60
65
65
10
15
52
52
57
0
3
31
19
57
0
43
4
11.0 AC Timing Parameters (Continued)
Ý
Symbol
DP8440/41-40
40 MHz Devices
Description
Min
DP8440/41-25
25 MHz Devices
Max
Min
Max
FAST ACCESS PARAMETER
400
tPCKCASL
CLK High to CAS Asserted
15.5
16
401
tPCKCASH
CLK High to CAS Negated
17.5
18
402
tPCKLCASL
CLK Low to CAS Asserted
18.5
19
403
tPCKLCASH
CLK Low to CAS Negated
18.5
19
404
tWCASPC
CAS Precharge when Programmed as (/2T during Burst
10
405
tPCKCASB
CLK to CAS Asserted when Programmed as (/2T during Burst
17
406
tPCKCVB
CLK to Column Address Valid when B0 e 1 during Programming
27
27
407
tPCKCVLB
CLK to Column Address Valid when B0 e 0 during Programming
32
32
408
tPCKPMH
CLK to PAGMISS Asserted During Burst and NoWRAP
14
409
tSBARCK
BSTARQ Asserted Setup to CLK
10
10
410
tHBARNCK
BSTARQ Asserted Hold from CLK (CLK following DTACK Negation)
16
17
411
tSNWCK
NoWRAP Asserted Setup to CLK (NADTACK)
5
6
412
tHNWCK
NoWRAP Asserted Hold from CLK (DTACK)
5
6
413
tSNLADS
NoLATCH Asserted Setup to ADS
5
6
414
tHNLCK
NoLATCH Asserted Hold from CLK
5
6
415
tSPMCK
PAGMISS Input Asserted Setup to CLK
16
16
416
tHPMCK
PAGMISS Input Asserted Hold from CLK
5
417
tPADDPMH
Row and Bank Address Valid to PAGMISS Asserted
13
13
418
tPCKPML
CLK High to PAGMISS Negated
17
17
419
tSWICLK
WAITIN Asserted Setup to CLK (NADTACK)
5
6
420
tHWICLK
WAITIN Asserted Hold from CLK (NADTACK)
5
6
421
tSADSCKP
ADS Setup to CLK in Page Mode
22
422
tPADSPMH
ADS to PAGMISS High in Page Mode
423
tHADSCKP
ADS Hold from CLK before Assertion in Page Mode
4
4
424
tSCSKP
CS Setup to CLK in Page Mode
22
22
10
35
17
36
14
6
22
16
16
12.0 AC Timing Waveforms: DP8440/41
Number
TL/F/11718–27
FIGURE 25. CLK and DELCLK Timing
32
DP8440/41-40
DP8440/41-25
Min
Min
Max
1
25
40
2
10
15
3
10
15
4
25
25
5
10
10
6
10
10
Max
12.0 AC Timing Waveforms: DP8440/41 (Continued)
TL/F/11718 – 28
FIGURE 26. Refresh Timing
DP8440/41-25
DP8440/41-40
Number
Min
Number
Min
100
6
Max
100
8
101
3
101
4
102
6
102
8
103
3
103
4
Max
104
17
104
20
105
34
105
36
106
13
106
15
107
12
107
14
305
17
305
19
306
18
306
19
400
15.5
400
16
401
17.5
401
18
33
12.0 AC Timing Waveforms: DP8440/41 (Continued)
TL/F/11718 – 29
FIGURE 27. Refresh and Access Timing
Number
DP8440/41-40
Min
Max
DP8440/41-25
Min
Max
104
17
20
105
34
36
106
13
15
107
12
14
300
10
12
301
10
12
302a
0
0
302b
18
18
305
17
19
306
18
19
308a
60
60
308b
65
65
315
14
16
316
15
17
401
17.5
18
34
12.0 AC Timing Waveforms: DP8440/41 (Continued)
TL/F/11718 – 30
FIGURE 28. Programming and Initialization Period Timing
Number
Min
200
15
201
18
202
6
203
Max
18
35
12.0 AC Timing Waveforms: DP8440/41 (Continued)
TL/F/11718 – 31
FIGURE 29a. Normal Mode Access TimingÐDP8440/41-40
Number
DP8440/41-40
Min
Number
Max
DP8440/41-40
Min
300
10
308b
301
10
309a
302a
0
309b
303
6
310a
304
6
310b
Number
Max
65
DP8440/41-40
Min
Max
316
15
10
317
15
15
318
16
52
319
16
57
320
0
325
15
305
17
311
3
306
18
312
14
400
15.5
307a
20
313
14
401
17.5
307b
25
314
17
402
18.5
315
14
403
18.5
308a
60
36
12.0 AC Timing Waveforms: DP8440/41 (Continued)
TL/F/11718 – 31
FIGURE 29b. Normal Mode Access TimingÐDP8440/41-25
Number
DP8440/41-25
Min
Number
Max
DP8440/41-25
Min
300
12
308b
301
12
309a
302a
0
309b
303
7
310a
304
6
310b
Number
Max
65
DP8440/41-25
Min
Max
316
17
10
317
17
15
318
18
52
319
18
57
320
0
325
17
305
19
311
4
306
19
312
16
400
16
307a
20
313
16
401
18
307b
25
314
18
402
19
315
16
403
19
308a
60
37
12.0 AC Timing Waveforms: DP8440/41 (Continued)
TL/F/11718 – 32
FIGURE 30. Burst Mode Access Timing When Using Rising CLK Edge
Number
DP8440/41-40
DP8440/41-25
Min
Min
Max
Number
Max
DP8440/41-40
DP8440/41-25
Min
Min
Max
Max
300
10
12
318
16
18
301
10
12
400
15.5
16
302a
0
0
401
17.5
18
304
6
6
402
18.5
19
18.5
305
17
19
403
306
18
19
404
10
405
17
307a
20
307b
25
20
25
406
19
10
35
17
27
36
27
308a
60
60
409
10
10
308b
65
65
410
16
17
310a
52
52
411
5
6
310b
57
57
412
5
314
17
18
417
13
13
316
15
17
418
17
17
317
15
17
38
6
12.0 AC Timing Waveforms: DP8440/41 (Continued)
TL/F/11718 – 33
FIGURE 31a. Page Mode Access TimingÐDP8440/41-40
Number
DP8440/41-40
Min
Number
Max
DP8440/41-40
Min
Number
Max
DP8440/41-40
Min
302b
21
310a
52
414
5
303
6
310b
57
415
16
304
6
5
Max
314
17
416
305
17
316
15
417
13
306
18
317
15
418
17
307a
20
400
15.5
419
307b
25
401
17.5
420
5
5
308a
60
407
32
421
22
308b
65
408
14
423
4
424
22
413
5
39
12.0 AC Timing Waveforms: DP8440/41 (Continued)
TL/F/11718 – 33
FIGURE 31b. Page Mode Access TimingÐDP8440/41-25
Number
DP8440/41-25
Min
Number
Max
DP8440/41-25
Min
Number
Max
DP8440/41-25
Min
302b
18
310a
52
414
6
303
7
310b
57
415
16
304
6
5
Max
314
18
416
305
19
316
17
417
13
306
19
317
17
418
17
307a
20
400
16
419
307b
25
401
18
420
5
5
308a
60
407
32
421
22
308b
65
408
14
423
4
424
22
413
6
40
12.0 AC Timing Waveforms: DP8440/41 (Continued)
TL/F/11718 – 35
FIGURE 32. Burst Mode Access Timing When Using Falling CLK Edge (ECAS2 e 1)
Number
DP8440/41-40
DP8440/41-25
Min
Min
Max
Number
Max
DP8440/41-40
DP8440/41-25
Min
Min
Max
Max
300
10
12
318
16
18
301
10
12
400
15.5
16
302b
21
18
401
17.5
18
304
6
6
402
18.5
19
305
17
19
403
306
18
19
404
10
17
307a
20
20
405
307b
25
25
407
18.5
19
10
35
17
32
308a
60
60
409
10
10
308b
65
65
410
16
17
310a
52
52
411
5
6
310b
57
57
412
5
314
17
18
417
316
15
17
418
317
15
17
419
41
6
13
13
17
5
36
32
17
6
13.0 Errata for DP8440/41
ERRATUM Ý1
Recommended Fix
While programmed in Normal Mode, the RAS signals may
negate (/2 clock before the CAS signals for the last burst
access. This can be a problem for write accesses, in which
the RAS hold time may not be met for some DRAM arrays.
The RAS assertion time can be extended (/2 clock by holding off the negation of the BSTARQ signal (Burst Access
Request) until after the falling edge of the last DTACK. If
this approach is taken, then BSTARQ must then be negated
before the clock edge which negates the last DTACK to
guarantee no other accesses take place.
TL/F/11718 – 36
ERRATUM Ý2
The NoWrap signal and EXTNDRF signal are multiplexed
on the same pin. NoWrap is asserted when doing sequential
burst acceses that don’t wrap around. EXTNDRF (Extend
Refresh) is used to extend a refresh while it is occurring.
A problem arises when a NoWrap burst access occurs
slightly before or during a refresh cycle. The DP8440/41
goes into a refresh cycle, however, because the NoWrap/
EXTNDRF signal is asserted, the refresh cycle may last indefinitely and the access will never complete.
ERRATUM Ý3
The NoWrap signal and BSTARQ (Burst Request) signal
should not be asserted on the same clock edge. This is only
a problem when doing NoWrap burst accesses.
Recommended Fix
The NoWrap signal should be asserted from ONE clock after the BSTARQ signal is asserted. This will have no effect
on the operation of the burst access and will prevent any
problems from occurring.
ERRATUM Ý4
Recommended Fix
The designer must be reminded that NoWrap/EXTNDRF
are multiplexed and if NoWrap acceses are used in the design, it is recommended that the NoWrap be gated with the
RFIP signal as outlined below.
When using external refreshes, the start of an access may
be delayed slightly if the access occurs near the assertion
of the RFRQ (Refresh Request) signal.
Recommended Fix
There is no guarantee the access will begin immediately
after the assertion of ADS, therefore, the internal timing signals, DTACK or NADTACK, should always be used as a
reference to generate the acknowledge signal to the CPU.
TL/F/11718–37
Delayed Access due to RFRQ
TL/F/11718 – 44
42
13.0 Errata for DP8440/41 (Continued)
Recommended Fix
ERRATUM Ý5
When operating in Page Mode, an access cannot start on
the clock edge immediately following the negation of
DTACK. If back-to-back accesses are done in this way, the
CAS signals will remain low during a refresh as shown in the
timing diagram.
There should be at least one idle clock between the negation of DTACK and the start of a new access.
Illegal Back-to-Back Accesses in Page Mode
TL/F/11718 – 45
Recommended Fix
ADS assertion should be delayed at least 4 ns from the
rising edge of the clock when in Page Mode operation.
ERRATUM Ý6
When starting a page access, there is a hold time from the
rising edge of the clock when ADS cannot assert. This hold
time (parameter 423 in the datasheet) is 4 ns and only applies when operating in Page Mode.
Parameter 423: ADS Hold Time before Assertion
TL/F/11718 – 46
43
13.0 Errata for DP8440/41 (Continued)
Recommended Fix
ERRATUM Ý7
Both CS and ADS are sampled asynchronously to the clock,
consequently there should be no overlap in their assertion
unless an access is being attempted.
Avoid asserting CS and ADS simultaneously unless attempting a DRAM access.
Illegal Overlap of CS and ADS
TL/F/11718 – 47
44
14.0 Physical Dimensions inches (millimeters)
Plastic Chip Carrier (PLCC)
Order Number DP8440V-40
NS Package Number V84A
45
DP8440-40/DP8440-25/DP8441-40/DP8441-25 microCMOS Programmable 16/64 Mbit
Dynamic RAM Controller/Driver
14.0 Physical Dimensions inches (millimeters) (Continued)
100-Lead Plastic Quad Flatpak (PQFP)
Order Number DP8440VLJ-40, DP8440VLJ-25, DP8441VLJ-40 or DP8441VLJ-25
NS Package Number VLJ100A
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