Maxim DS3232M V1 ±5ppm, i2c real-time clock with sram Datasheet

19-6247; Rev 1; 8/12
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
General Description
The DS3232M is a low-cost, extremely accurate, I2C
real-time clock (RTC) with 236 bytes of battery-backed
SRAM. The device incorporates a battery input and
maintains accurate timekeeping when main power to the
device is interrupted. The integration of the microelectromechanical systems (MEMS) resonator enhances the
long-term accuracy of the device and reduces the piecepart count in a manufacturing line.
The RTC maintains seconds, minutes, hours, day, date,
month, and year information. The date at the end of the
month is automatically adjusted for months with fewer
than 31 days, including corrections for leap year. The
clock operates in either the 24-hour or 12-hour format
with an AM/PM indicator. Two programmable time-of-day
alarms and a 1Hz output are provided. Address and data
are transferred serially through an I2C bidirectional bus.
A precision temperature-compensated voltage reference
and comparator circuit monitors the status of VCC to
detect power failures, to provide a reset output, and to
automatically switch to the backup supply when necessary. Additionally, the RST pin is monitored as a pushbutton input for generating a microprocessor reset. See the
Block Diagram for more details.
Applications
Features
S Timekeeping Accuracy ±5ppm (±0.432 Second/
Day) from -40NC to +85NC
S 236 Bytes of Battery-Backed User SRAM
S Battery Backup for Continuous Timekeeping
S Low Power Consumption
S Functionally Compatible to DS3232
S Complete Clock Calendar Functionality Including
Seconds, Minutes, Hours, Day, Date, Month, and
Year with Leap Year Compensation Up to Year
2100
S Two Time-of-Day Alarms
S 1Hz and 32.768kHz Outputs
S Reset Output and Pushbutton Input with
Debounce
S Fast (400kHz) I2C-Compatible Serial Bus
S +2.3V to +4.5V Supply Voltage
S Digital Temp Sensor with ±3NC Accuracy
S -40NC to +85NC Temperature Range
S 8-Pin SO (150 mils) Package
S Underwriters Laboratories (UL) Recognized
Typical Operating Circuit
Power Meters
Industrial Applications
VCC
VCC
Ordering Information appears at end of data sheet.
SCL
I/O PORT
SDA
DS3232M
INT/SQW
32KHZ
INTERRUPTS
CPU
PUSHBUTTON
RESET
RST
VBAT
For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/DS3232M.related
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may
be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to GND.........-0.3V to +6.0V
Operating Temperature Range........................... -40NC to +85NC
Storage Temperature Range............................. -55NC to +125NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER
MIN
TYP
MAX
VCC
2.3
3.3
4.5
VBAT
2.3
3.0
4.5
Logic 1
VIH
0.7 x
VCC
VCC +
0.3
V
Logic 0
VIL
-0.3
0.3 x
VCC
V
Supply Voltage
SYMBOL
CONDITIONS
UNITS
V
ELECTRICAL CHARACTERISTICS—FREQUENCY AND TIMEKEEPING
(VCC or VBAT = +3.3V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, and
TA = +25NC, unless otherwise noted.) (Note 1)
PARAMETER
1Hz Frequency Tolerance
SYMBOL
Df/fOUT
CONDITIONS
MIN
TYP
Measured over R 10s interval
MAX
UNITS
Q5
ppm
1Hz Frequency Stability vs. VCC
Voltage
Df/V
Timekeeping Accuracy
tKA
Q0.432
Seconds/
Day
Df/fOUT
Q2.5
%
32kHz Frequency Tolerance
ppm/V
Q1
DC ELECTRICAL CHARACTERISTICS—GENERAL
(VCC = +2.3V to +4.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, and
TA = +25NC, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Active Supply Current
(I2C Active)
ICCA
(Note 2)
125
250
µA
Standby Supply Current
(I2C Inactive)
ICCS
(Notes 2, 3)
100
175
µA
2
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
DC ELECTRICAL CHARACTERISTICS—GENERAL (continued)
(VCC = +2.3V to +4.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, and
TA = +25NC, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Temperature Conversion Current
(I2C Inactive)
ICCSCONV
CONDITIONS
MIN
2.45
TYP
MAX
UNITS
200
350
µA
2.575
2.70
V
Power-Fail Voltage
VPF
Logic 0 Output
(32KHZ, INT/SQW, SDA)
VOL
IOL = 3mA
0.4
V
Logic 0 Output (RST)
VOL
IOL = 1mA
0.4
V
Logic 1 Output (32KHZ)
VOH
Active supply > 3.3V, IOH = -1mA
2.0
Active supply > 2.7V, IOH = -0.75mA
Active supply > 2.3V, IOH = -0.14mA
2.0
V
2.0
Output Leakage
(32KHZ, INT/SQW, SDA)
ILO
-0.1
+0.1
µA
Input Leakage (SCL)
ILI
-0.1
+0.1
µA
+10
µA
+100
nA
RST I/O Leakage
VBAT Leakage
Temperature Accuracy
IOL
IBATLKG
TEMPACC
-200
-100
TA = +25NC
VCC or VBAT = +3.3V
25
Q3
NC
Temperature Conversion Time
tCONV
10
ms
Pushbutton Debounce
PBDB
250
ms
Reset Active Time
tRST
Oscillator Stop Flag (OSF) Delay
tOSF
250
(Note 4)
25
ms
100
ms
DC ELECTRICAL CHARACTERISTICS—VBAT CURRENT CONSUMPTION
(VCC = 0V, VBAT = +2.3V to +4.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 0V, VBAT = +3.0V, and
TA = +25NC, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Active Battery Current
(I2C Active)
IBATA
(Note 2)
25
75
µA
Timekeeping Battery Current
(I2C Inactive)
IBATT
EN32KHZ = 0, INTCN = 1 (Note 2)
1.8
3.0
µA
200
350
µA
100
nA
Temperature Conversion Current
(I2C Inactive)
IBATTC
Data Retention Current
(Oscillator Stopped and I2C
Inactive)
IBATDR
TA = +25NC
3
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
AC ELECTRICAL CHARACTERISTICS—POWER SWITCH
(TA = -40NC to +85NC, unless otherwise noted.) (Note 1, Figure 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VCC Fall Time, VPFMAX to
VPFMIN
tVCCF
300
Fs
VCC Rise Time, VPFMIN to
VPFMAX
tVCCR
0
Fs
Recovery at Power-Up
tREC
(Note 5)
250
300
ms
AC ELECTRICAL CHARACTERISTICS—I2C INTERFACE
(VCC or VBAT = +2.3V to +4.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, and
TA = +25NC, unless otherwise noted.) (Notes 1, 6, Figure 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
SCL Clock Frequency
fSCL
0
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
Fs
Hold Time (Repeated) START
Condition
tHD:STA
0.6
Fs
Low Period of SCL
tLOW
1.3
Fs
High Period of SCL
tHIGH
0.6
Fs
Data Hold Time
tHD:DAT
0
Data Set-Up Time
tSU:DAT
100
ns
START Set-Up Time
tSU:STA
0.6
Fs
SDA and SCL Rise Time
tR
(Note 7)
20 +
0.1CB
300
ns
SDA and SCL Fall Time
tF
(Note 7)
20 +
0.1CB
300
ns
STOP Set-Up Time
SDA, SCL Input Capacitance
tSU:STO
CBIN
0.9
0.6
(Note 8)
Fs
Fs
10
pF
Note 1: Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply
voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: Includes the temperature conversion current (averaged).
Note 3: Does not include RST leakage if VCC < VPF.
Note 4: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set.
Note 5: The state of RST does not affect the I2C interface or RTC functions.
Note 6: Interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with standard mode
I2C timing.
Note 7: CB = total capacitance of one bus line in picofarads.
Note 8: Guaranteed by design and not 100% production tested.
4
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Timing Diagrams
SDA
tBUF
tF
tLOW
tHD:STA
tSP
SCL
tHD:STA
tHIGH
tR
tHD:DAT
STOP
START
tSU:STA
tSU:STO
tSU:DAT
REPEATED
START
NOTE: TIMING IS REFERENCED TO VILMAX AND VIHMIN.
Figure 1. I2C Timing
tVCCF
tVCCR
VPFMAX
VPFMIN
VCC
tREC
RST
Figure 2. Power Switch Timing
RST
PBDB
tRST
Figure 3. Pushbutton Reset Timing
5
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
TA = +85°C
120
100
80
TA = +25°C
2.8
DS3232M toc02
1.5
TA = +25°C
0.5
3.8
2.8
3.3
3.8
4.3
0
1
2
3
4
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
OUTPUT CURRENT (mA)
INT/SQW OUTPUT VOLTAGE
vs. OUTPUT CURRENT
POWER-SUPPLY CURRENT
vs. SCL FREQUENCY
THERMOMETER ERROR
vs. TEMPERATURE
170
DS3232M toc04
0.5
VCC = 2.7V
0.3
0.2
0.1
EN32KHZ = 0,
SDA = INACTIVE
160
150
SUPPLY CURRENT (µA)
0.4
4.0V
140
130
3.0V
120
110
100
90
2.6V
80
2
4
6
OUTPUT CURRENT (mA)
8
10
5
5
VCC = 3.3V
4
3
2
1
0
-1
-2
-3
-4
70
0
0
0.2
0
2.3
4.3
0.3
0.1
TA = -40°C
3.3
0.4
DS3232M toc06
2.3
2.0
1.0
VPF TA = -40°C
40
TA = +85°C
VCC = 2.45V
0.5
THERMOMETER ERROR (°C)
60
OUTPUT VOLTAGE (V)
2.5
0.6
OUTPUT VOLTAGE (V)
140
VCC = 0V,
EN32KHZ = 0,
INTCN = 1
DS3232M toc05
SUPPLY CURRENT (µA)
160
BATTERY CURRENT (µA)
VBAT = 2.3V,
EN32KHZ = 0,
INTCN = 1
180
3.0
DS3232M toc01
200
RST OUTPUT VOLTAGE
vs. OUTPUT CURRENT
BATTERY CURRENT
vs. BATTERY VOLTAGE
DS3232M toc03
POWER-SUPPLY CURRENT
vs. POWER-SUPPLY VOLTAGE
-5
0
100
200
300
SCL FREQUENCY (kHz)
400
-40
-10
20
50
80
TEMPERATURE (°C)
6
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
4
2
0
-2
-4
4
2
0
-2
-4
3
2
1
0
-1
-2
-6
-6
-3
-8
-8
-4
-10
-5
-10
5
10
15
20
25
5
10
15
20
25
5
10
15
20
25
TIME (MINUTES)
1Hz FREQUENCY ERROR
(10s THERMAL UPDATES
MEASURED EVERY SECOND)
1Hz FREQUENCY ERROR
(1s THERMAL UPDATES
MEASURED EVERY SECOND)
TIMEKEEPING ACCURACY
vs. TEMPERATURE
0
-2
-4
6
4
2
0
-2
-4
-6
-6
-8
-8
-10
10
15
20
TIME (SECONDS)
25
30
DS3232M ACCURACY
0
-50
TYPICAL 20ppm
CRYSTAL,
UNCOMPENSATED
-100
-150
-200
-10
5
50
FREQUENCY EROR (ppm)
FREQUENCY ERROR (ppm)
2
VBAT = 3.3V,
VCC = 0V,
TA = +25°C
8
30
DS3232M toc12
10
DS3232M toc10
4
0
0
30
TIME (MINUTES)
VBAT = 3.3V,
VCC = 0V,
TA = +25°C
6
0
TIME (SECONDS)
10
8
30
DS3232M toc11
0
FREQUENCY ERROR (ppm)
6
VCC = 3.3V,
TA = +25°C
4
FREQUENCY ERROR (ppm)
FREQUENCY ERROR (ppm)
FREQUENCY ERROR (ppm)
6
VCC = 3.3V,
TA = +25°C
8
5
DS3232M toc08
VCC = 3.3V,
TA = +25°C
8
10
DS3232M toc07
10
1Hz FREQUENCY ERROR
(DELTA FROM T0)
1Hz FREQUENCY ERROR
(MEASURED EVERY SECOND)
DS3232M toc09
1Hz FREQUENCY ERROR
(MEASURED EVERY SECOND)
0
5
10
15
20
TIME (SECONDS)
25
30
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
7
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Pin Configuration
TOP VIEW
32KHZ
1
VCC
2
INT/SQW
RST
+
8 SCL
7
SDA
3
6
VBAT
4
5
GND
DS3232M
SO
Pin Description
PIN
NAME
FUNCTION
32.768KHZ Output (Push-Pull Output, 50% Duty Cycle). If enabled (EN32KHZ = 1), the 32kHz output is
active on VCC. If enabled for battery operation (BB32KHZ = 1), the output is also active on VBAT. When
disabled, the output is forced low. This pin can be left unconnected if not used.
1
32KHZ
2
VCC
DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1FF to 1.0FF capacitor.
Connect to ground if not used.
INT/
SQW
Active-Low Interrupt or 1Hz Square-Wave Output. This open-drain pin requires an external pullup resistor
connected to a supply at 4.5V or less. It can be left open if not used. This multifunction pin is determined
by the state of the INTCN bit in the Control register (0Eh). When INTCN is set to logic 0, this pin outputs
a 1Hz square wave. When INTCN is set to logic 1, a match between the timekeeping registers and either
of the alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the INTCN bit is set to
logic 1 when power is first applied, the pin defaults to an interrupt output with alarms disabled.
4
RST
Active-Low Reset. This pin is an open-drain input/output. It indicates the status of VCC relative to the VPF
specification. As VCC falls below VPF, the RST pin is driven low. When VCC exceeds VPF, for tRST, the
RST pin is pulled high by the internal pullup resistor. The active-low, open-drain output is combined with
a debounced pushbutton input function. This pin can be activated by a pushbutton reset request. It has
an internal 50kI (RPU) nominal value pullup resistor to VCC. No external pullup resistors should be connected. If the oscillator is disabled, tREC is bypassed and RST immediately goes high.
5
GND
Ground
6
VBAT
Backup Power-Supply Input. When using the device with the VBAT input as the primary power source, this
pin should be decoupled using a 0.1FF to 1.0FF low-leakage capacitor. When using the device with the VBAT
input as the backup power source, the capacitor is not required. If VBAT is not used, connect to ground. The
device is UL recognized to ensure against reverse charging when used with a primary lithium battery. Go to
www.maxim-ic.com/qa/info/ul for more information.
7
SDA
Serial-Data Input/Output. This pin is the data input/output for the I2C serial interface. This open-drain pin
requires an external pullup resistor. The pullup voltage can be up to 4.5V, regardless of the voltage on VCC.
8
SCL
Serial-Clock Input. This pin is the clock input for the I2C serial interface and is used to synchronize data
movement on the serial interface. The pullup voltage can be up to 4.5V, regardless of the voltage on VCC.
3
8
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Block Diagram
*SELECTED
POWER
P
DS3232M
DIVIDER
32KHZ
N
INT/SQW
1Hz
TIME-BASE
RESONATOR
VBAT
VCC
POWER
CONTROL*
INTERRUPT
OR 1Hz
SELECT
N
DIGITAL
ADJUSTMENT
RST
TEMP
SENSOR
N
FACTORY TRIM
GND
SDA
SCL
I2C
INTERFACE
CONTROL AND STATUS
REGISTERS
SRAM
Detailed Description
The DS3232M is a serial real-time clock (RTC) driven by
an internal, temperature-compensated, microelectromechanical systems (MEMS) resonator. The oscillator provides a stable and accurate reference clock and maintains the RTC to within Q0.432 seconds-per-day accuracy from -40NC to +85NC. The RTC is a low-power clock/
calendar with two programmable time-of-day alarms. INT/
SQW provides either an interrupt signal due to alarm
conditions or a 1Hz square wave. The clock/calendar
provides seconds, minutes, hours, day, date, month, and
year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days,
including corrections for leap year. The clock operates in
CLOCK/CALENDAR
WITH ALARM
either the 24-hour or 12-hour format with an AM/PM indicator. The internal registers are accessible though an I2C
bus interface. A temperature-compensated voltage reference and comparator circuit monitors the level of VCC to
detect power failures and to automatically switch to the
backup supply when necessary. The RST pin provides
an external pushbutton function and acts as an indicator of a power-fail event. Also available are 236 bytes of
general-purpose battery-backed SRAM.
Operation
The Block Diagram shows the device’s main elements.
Each of the major blocks is described separately in the
following sections.
9
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
High-Accuracy Time Base
+3.3V
VCC
VBAT
Figure 4. Single Supply (VCC Only)
VCC
Power-Supply Configurations
VBAT
Figure 5. Single Supply (VBAT Only)
+3.3V
VCC
VBAT
Figure 6. Dual Power Supply
The temperature sensor, oscillator, and digital adjustment controller logic form the highly accurate time base.
The controller reads the output of the on-board temperature sensor and adjusts the final 1Hz output to maintain
the required accuracy. The device is trimmed at the
factory to maintain a tight accuracy over the operating
temperature range. When the device is powered by VCC,
the adjustment occurs once a second. When the device
is powered by VBAT, the adjustment occurs once every
10s to conserve power. Adjusting the 1Hz time base less
often does not affect the device’s long-term timekeeping
accuracy. The device also contains an Aging Offset register that allows a constant offset (positive or negative) to
be added to the factory-trimmed adjustment value.
The DS3232M can be configured to operate on a single
power supply (using either VCC or VBAT) or in a dualsupply configuration, which provides a backup supply
source to keep the timekeeping circuits alive during
absence of primary system power.
Figure 4 illustrates a single-supply configuration using
VCC only, with the VBAT input grounded. When VCC < VPF,
the RST output is asserted (active low). Temperature conversions are executed once per second.
Figure 5 illustrates a single-supply configuration using
VBAT only, with the VCC input grounded. The RST output
is disabled and is held at ground through the connection
of the internal pullup resistor. Temperature conversions
are executed once every 10s.
Figure 6 illustrates a dual-supply configuration, using
the VCC supply for normal system operation and the
VBAT supply for backup power. In this configuration, the
power-selection function is provided by a temperaturecompensated voltage reference and a comparator circuit
that monitors the VCC level. When VCC is greater than
VPF, the device is powered by VCC. When VCC is less
than VPF but greater than VBAT, the device is powered
by VCC. If VCC is less than VPF and is less than VBAT, the
device is powered by VBAT (see Table 1).
When VCC < VPF, the RST output is asserted (active
low). When VCC is the presently selected power source,
temperature conversions are executed once per second.
When VBAT is the presently selected power source, temperature conversions are executed once every 10s.
10
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Table 1. Power Control
CONFIGURATION
CONDITION
VCC Only
(Figure 4)
VCC > VPF
VCC < VPF
VBAT Only
(Figure 5)
Dual Supply
(Figure 6)
EOSC = 0
EOSC = 1
VCC > VPF
VCC < VPF
I/O ACTIVE
I/O INACTIVE
ICCA
ICCS
Disabled (Low)
IBATDR
ICCA
VCC > VBAT
VCC < VBAT
Active (Low)
IBATT
IBATA
ICCS
ICCA
IBATA
To preserve the battery, the first time VBAT is applied
to the device the oscillator does not start up until VCC
exceeds VPF or until a valid I2C address is written to
the device. Typical oscillator startup time is less than
1s. Approximately 2s after VCC is applied, or a valid
I2C address is written, the device makes a temperature
measurement and applies the calculated correction to
the oscillator. Once the oscillator is running, it continues
to run as long as a valid power source is available (VCC
or VBAT), and the device continues to measure the temperature and correct the oscillator frequency. On the first
application of VCC power, or (if VBAT powered) when a
valid I2C address is written to the device, the time and
date registers are reset to 01/01/00 01 00:00:00 (DD/MM/
YY DOW HH:MM:SS).
VBAT Operation
There are several modes of operation that affect the
amount of VBAT current that is drawn. While the device
is powered by VBAT and the serial interface is active,
the active battery current IBATA is drawn. When the
serial interface is inactive, the timekeeping current IBATT
(which includes the averaged temperature-conversion
current IBATTC) is used. The temperature-conversion
current IBATTC is specified since the system must be
able to support the periodic higher current pulse and
still maintain a valid voltage level. The data-retention
current IBATDR is the current drawn by the device when
VCC > VBAT
VCC < VBAT
RST
Inactive (High)
Inactive (High)
ICCS
IBATT
Active (Low)
the oscillator is stopped (EOSC = 1). This mode can be
used to minimize battery requirements for periods when
maintaining time and date information is not necessary,
e.g., while the end system is waiting to be shipped to a
customer.
Pushbutton Reset Function
The device provides for a pushbutton switch to be connected to the RST input/output pin. When the device is
not in a reset cycle, it continuously monitors RST for a
low-going edge. If an edge transition is detected, the
device debounces the switch by pulling RST low. After
the internal timer has expired (PBDB), the device continues to monitor the RST line. If the line is still low, the
device continuously monitors the line looking for a rising
edge. Upon detecting release, the device forces RST
low and holds it low for tRST. RST is also used to indicate a power-fail condition. When VCC is lower than VPF,
an internal power-fail signal is generated, which forces
RST low. When VCC returns to a level above VPF, RST
is held low for approximately 250ms (tREC) to allow the
power supply to stabilize. If the oscillator is not running
when VCC is applied, tREC is bypassed and RST immediately goes high. Assertion of the RST output, whether
by pushbutton or power-fail detection, does not affect
the device’s internal operation. RST output operation and
pushbutton monitoring are only available if VCC power is
available.
11
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Real-Time Clock (RTC)
With the 1Hz source from the temperature-compensated
oscillator, the RTC provides seconds, minutes, hours,
day, date, month, and year information. The date at the
end of the month is automatically adjusted for months
with fewer than 31 days, including corrections for leap
year. The clock operates in either the 24-hour or the
12-hour format with an AM/PM indicator. The clock provides two programmable time-of-day alarms. INT/SQW
can be enabled to generate either an interrupt due to an
alarm condition or a 1Hz square wave. This selection is
controlled by the INTCN bit in the Control register.
I2C Interface
2
The I C interface is accessible whenever either VCC or
VBAT is at a valid level. If a microcontroller connected
to the device resets because of a loss of VCC or other
event, it is possible that the microcontroller and device’s
I2C communications could become unsynchronized,
e.g., the microcontroller resets while reading data from
the device. When the microcontroller resets, the device’s
I2C interface can be placed into a known state by toggling SCL until SDA is observed to be at a high level. At
that point the microcontroller should pull SDA low while
SCL is high, generating a START condition.
SRAM
The DS3232M provides 236 bytes of general-purpose
battery-backed read/write memory. The I2C address
ranges from 14h–FFh. The SRAM can be written or read
whenever VCC or VBAT is greater than the minimum operating voltage.
Address Map
Table 2 shows the address map for the device’s timekeeping registers. During a multibyte access, when
the address pointer reaches the end of the register
space (12h), it wraps around to location 00h. On an
I2C START or address pointer incrementing to location
00h, the current time is transferred to a second set of
registers. The time information is read from these secondary registers, while the clock can continue to run.
This eliminates the need to reread the registers in case
the main registers update during a read.
Clock and Calendar
The time and calendar information is obtained by reading
the appropriate register bytes. Table 2 shows the RTC
registers. The time and calendar data are set or initialized
by writing the appropriate register bytes. The contents of
the time and calendar registers are in the binary-coded
decimal (BCD) format. The device can be run in either
12-hour or 24-hour mode. Bit 6 of the Hours register is
defined as the 12-hour or 24-hour mode select bit. When
high, the 12-hour mode is selected. In the 12-hour mode,
bit 5 is the AM/PM bit with logic-high being PM. In the
24-hour mode, bit 5 is the 20-hour bit (20–23 hours).
The century bit (bit 7 of the Month register) is toggled
when the Years register overflows from 99 to 00. The
day-of-week register increments at midnight. Values that
correspond to the day of week are user-defined but must
be sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on). Illogical time and date entries result
in undefined operation. When reading or writing the time
and date registers, secondary buffers are used to prevent
errors when the internal registers update. When reading
the time and date registers, the secondary buffers are
synchronized to the internal registers on any I2C START
and when the register pointer rolls over to zero. The time
information is read from these secondary registers, while
the clock continues to run. This eliminates the need to
reread the registers in case the main registers update
during a read. The countdown chain is reset whenever
the seconds register is written. Write transfers occur on
the acknowledge from the device. Once the countdown
chain is reset, to avoid rollover issues the remaining time
and date registers must be written within 1s.
12
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Table 2. Timekeeping Registers
ADDRESS
BIT 7
MSB
00h
0
10 Seconds
01h
0
10 Minutes
02h
0
12/24
20
Hours
03h
0
0
0
04h
0
0
05h
Century
0
BIT 6
BIT 5
AM/PM
06h
BIT 4
BIT 3
BIT 2
0
RANGE
Seconds
Seconds
00–59
Minutes
Minutes
00–59
Hour
Hours
1–12 +
AM/PM
00–23
0
Day
1–7
Date
Day
Date
01–31
Month
Month/Century
01–12 +
Century
Year
Year
00–99
10 Date
10
Month
0
BIT 0
LSB
FUNCTION
10
Hours
BIT 1
10 Year
07h
A1M1
10 Seconds
Seconds
Alarm 1
Seconds
00–59
08h
A1M2
10 Minutes
Minutes
Alarm 1
Minutes
00–59
Hour
Alarm 1 Hours
1–12 +
AM/PM
00–23
AM/PM
10
Hours
09h
A1M3
12/24
0Ah
A1M4
DY/DT
0Bh
A2M2
0Ch
A2M3
12/24
0Dh
A2M4
DY/DT
0Eh
EOSC
OSF
BBSQW
CONV
NA
NA
INTCN
A2IE
0Fh
BB32KHZ
0
0
EN32KHZ
BSY
A2F
10h
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
20
Hours
Day
Alarm 1 Day
1–7
Date
Alarm 1 Date
1–31
Minutes
Alarm 2
Minutes
00–59
Hour
Alarm 2 Hours
1–12 +
AM/PM
00–23
10 Date
10 Minutes
AM/PM
20
Hours
10
Hours
10 Date
Day
Alarm 2 Day
1–7
Date
Alarm 2 Date
1–31
A1IE
Control
—
A1F
Status
—
DATA
Aging Offset
—
—
—
11h
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Temperature
MSB
12h
DATA
DATA
0
0
0
0
0
0
Temperature
LSB
13h
SWRST
0
0
0
0
0
0
0
Test
—
14h–FFh
X
X
X
X
X
X
X
X
SRAM
00h–FFh
Note: Unless otherwise specified, the registers’ state is not defined when power is first applied.
13
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Alarms
The device contains two time-of-day/date alarms.
Alarm 1 can be set by writing to registers 07h–0Ah.
Alarm 2 can be set by writing to registers 0Bh–0Dh.
See Table 2. The alarms can be programmed (by the
alarm enable and INTCN bits in the Control register)
to activate the INT/SQW output on an alarm match
condition. Bit 7 of each of the time-of-day/date alarm
registers are mask bits (Table 2). When all the mask
bits for each alarm are logic 0, an alarm only occurs
when the values in the timekeeping registers match the
corresponding values stored in the time-of-day/date
alarm registers. The alarms can also be programmed
to repeat every second, minute, hour, day, or date.
Table 3 shows the possible settings. Configurations
not listed in the table result in illogical operation. The
DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0–5 of that
register reflects the day of the week or the date of the
month. If DY/DT is written to logic 0, the alarm is the
result of a match with date of the month. If DY/DT is
written to logic 1, the alarm is the result of a match
with day of the week. When the RTC register values
match alarm register settings, the corresponding alarm
flag A1F or A2F bit is set to logic 1. If the corresponding alarm interrupt enable A1IE or A2IE bit is also set
to logic 1, the alarm condition activates the INT/SQW
signal if the INTCN bit is set to logic 1. The match is
tested on the once-per-second update of the time and
date registers.
Table 3. Alarm Mask Bits
DY/DT
ALARM 1 REGISTER MASK BITS (BIT 7)
ALARM RATE
A1M4
A1M3
A1M2
A1M1
X
1
1
1
1
Alarm once a second
X
1
1
1
0
Alarm when seconds match
X
1
1
0
0
Alarm when minutes and seconds match
X
1
0
0
0
Alarm when hours, minutes, and seconds match
0
0
0
0
0
Alarm when date, hours, minutes, and seconds match
1
0
0
0
0
Alarm when day, hours, minutes, and seconds match
DY/DT
ALARM 2 REGISTER MASK BITS (BIT 7)
ALARM RATE
A2M4
A2M3
A2M2
X
1
1
1
Alarm once per minute (00 seconds of every minute)
X
1
1
0
Alarm when minutes match
X
1
0
0
Alarm when hours and minutes match
0
0
0
0
Alarm when date, hours, and minutes match
1
0
0
0
Alarm when day, hours, and minutes match
14
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Control Register (0Eh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
EOSC
0
BBSQW
CONV
NA
NA
INTCN
A2IE
A1IE
0
0
1
1
1
0
0
BIT 7
EOSC: Enable oscillator. When set to logic 0, the oscillator is started. When set to logic 1, the oscillator is
stopped when the device switches to VBAT. This bit is clear (logic 0) when power is first applied. When the
device is powered by VCC, the oscillator is always on regardless of the status of the EOSC bit. When the oscillator is disabled, all register data is static.
BIT 6
BBSQW: Battery-backed square-wave enable. When set to logic 1 with INTCN = 0 and VCC < VPF, this bit
enables the 1Hz square wave. When BBSQW is logic 0, INT/SQW goes high impedance when VCC falls below
VPF. This bit is disabled (logic 0) when power is first applied.
BIT 5
CONV: Convert temperature. Setting this bit to 1 forces the temperature sensor to convert the temperature
into digital code and execute the temperature compensate algorithm to update the oscillator’s accuracy. The
device cannot be forced to execute the temperature-compensate algorithm faster than once per second. A
user-initiated temperature conversion does not affect the internal update cycle. The CONV bit remains at a 1
from the time it is written until the temperature conversion is completed, at which time both CONV and BSY go
to 0. The CONV bit should be used when monitoring the status of a user-initiated conversion. See Figure 7 for
more details.
BITS 4:3
NA: Not applicable. These bits have no affect on the device and can be set to either 0 or 1.
BIT 2
INTCN: Interrupt control. This bit controls the INT/SQW output signal. When the INTCN bit is set to logic 0, a
1Hz square wave is output on INT/SQW. When the INTCN bit is set to logic 1, a match between the timekeeping registers and either of the alarm registers activates the INT/SQW output (if the alarm is also enabled). The
corresponding alarm flag is always set regardless of the state of the INTCN bit. The INTCN bit is set to a logic
1 when power is first applied.
BIT 1
A2IE: Alarm 2 interrupt enable. When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status register to assert INT/SQW (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the
A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied.
BIT 0
A1IE: Alarm 1 interrupt enable. When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status register to assert INT/SQW (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the
A1F bit does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied.
15
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
VCC POWERED
INTERNAL 1Hz
CLOCK
BSY
CONV
THE USER SETS THE CONV BIT
THE DEVICE CLEARS THE CONV BIT
AFTER THE TEMPERATURE CONVERSION
HAS COMPLETED
BSY IS HIGH DURING
THE TEMPERATURE CONVERSION
VBAT POWERED
10 SECONDS
INTERNAL 1Hz
CLOCK
BSY
CONV
THE USER SETS THE CONV BIT
THE DEVICE CLEARS THE CONV BIT
AFTER THE TEMPERATURE CONVERSION
HAS COMPLETED
Figure 7. CONV Control Bit and BSY Status Bit Operation
16
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Status Register (0Fh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OSF
BB32KHZ
0
0
EN32KHZ
BSY
A2F
A1F
1
1
0
0
1
X
X
X
BIT 7
OSF: Oscillator stop flag. A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for
some period and could be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time
that the oscillator stops. This bit remains at logic 1 until written to logic 0. The following are examples of
conditions that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltages present on both VCC and VBAT are insufficient to support the oscillator.
3) The EOSC bit is turned off in battery-backed mode.
4) External influences on the oscillator (i.e., noise, leakage, etc.).
BIT 6
BB32KHZ: Battery-backed 32kHz output (BB32KHZ). This bit enables the 32kHz output when the device is powered from VBAT (provided the 32kHz output is enabled with the EN32KHZ bit). If BB32KHZ = 0, the 32kHz output
is forced low when the device is powered by VBAT.
BITS 5:4
Unused (0). These bits have no meaning and are fixed at 0 when read.
BIT 3
EN32KHZ: Enabled 32.768kHz output. This bit enables and disables the 32KHZ output. When set to a logic 0,
the 32KHZ output is high impedance. On initial power-up, this bit is set to a logic 1 and the 32KHZ output is
enabled and produces a 32.768kHz square wave if the oscillator is enabled.
BIT 2
BSY: Busy. This bit indicates the device is busy executing temperature conversion function. It goes to logic 1
when the conversion signal to the temperature sensor is asserted, and then it is cleared when the device has
completed the temperature conversion. See the Block Diagram for more details.
BIT 1
A2F: Alarm 2 flag. A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. If the
A2IE bit is logic 1 and the INTCN bit is set to logic 1, INT/SQW is also asserted. A2F is cleared when written to
logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
BIT 0
A1F: Alarm 1 flag. A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. If the
A1IE bit is logic 1 and the INTCN bit is set to logic 1, INT/SQW is also asserted. A1F is cleared when written to
logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
17
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Aging Offset Register (10h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
0
0
0
0
0
0
0
0
The Aging Offset register takes a user-provided value to add to or subtract from the factory-trimmed value that adjusts the
accuracy of the time base. Use of the Aging Offset register is not needed to achieve the accuracy as defined in the Electrical
Characteristics tables.
The Aging Offset code is encoded in two’s complement, with bit 7 representing the SIGN bit. One LSB typically represents a
0.12ppm change in frequency. The change in ppm per LSB is the same over the operating temperature range. Positive offsets
slow the time base and negative offsets quicken the time base.
Temperature Registers (11h–12h)
Temperature Register (Upper Byte = 11h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
0
0
0
0
0
0
0
0
Temperature Register (Lower Byte = 12h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DATA
DATA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Temperature is represented as a 10-bit code with a resolution of 0.25°C and is accessible at location 11h and 12h. The temperature is encoded in two’s complement format. The upper 8 bits, the integer portion, are at location 11h and the lower 2 bits,
the fractional portion, are at location 12h. For example, 00011001 01b = +25.25°C. Upon power reset, the registers are set to
a default temperature of 0°C and the controller starts a temperature conversion. The temperature is read upon initial application of VCC or I2C access on VBAT and once every second afterwards with VCC power or once every 10s with VBAT power. The
Temperature registers are also updated after each user-initiated conversion and are read only.
18
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Test Register (13h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
SWRST
0
0
0
0
0
0
0
POR*:
0
0
0
0
0
0
0
0
*POR is defined as the first application of power to the device, either VBAT or VCC.
This register is used for factory test. Bits 6:0 are locked and always read as zeros. Writing to bit locations 6:0 has no affect on the
device. If the SWRST bit is set to Logic 1, the device immediately resets all internal logic and registers (except the SRAM) to their
factory-default POR state.
The device reset occurs during the normal acknowledge time slot following the receipt of the data byte carrying that SWRST
instruction; a NACK occurs due to the resetting action (see Figure 8). The I/O master should terminate the I/O string with a normal STOP instruction (on the 28th SCL clock). The SWRST bit is automatically cleared to logic 0.
SLAVE ACKs
SDA
1
1
0
1
0
0
SLAVE ADDRESS
0
0
0
R/W
0
0
1
0
NACK DURING SWRST
0
1
1
1
REGISTER ADDRESS
0
0
0
0
0
0
0
DATA
SCL
Figure 8. Software Reset I/O Execution
SRAM (14h–FFh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
D7
D6
D5
D4
D3
D2
D1
D0
POR*:
X
X
X
X
X
X
X
X
*POR is defined as the first application of power to the device, either VBAT or VCC.
19
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
I2C Serial Port Operation
I2C Slave Address
The device’s slave address byte is D0h. The first byte
sent to the device includes the device identifier, device
address, and the R/W bit (Figure 9). The device address
sent by the I2C master must match the address assigned
to the device.
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle,
it often initiates a low-power mode for slave devices.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 1 for applicable timing.
STOP Condition: A STOP condition is generated
by the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See Figure 1 for
applicable timing.
Repeated START Condition: The master can use
a repeated START condition at the end of one data
transfer to indicate that it immediately initiates a new
data transfer following the current one. Repeated
STARTs are commonly used during read operations
to identify a specific memory address to begin a data
LSB
MSB
1
1
0
1
DEVICE
IDENTIFIER
Figure 9. I2C Slave Address Byte
0
0
0
R/W
READ/
WRITE BIT
transfer. A repeated START condition is issued identically to a normal START condition. See Figure 1 for
applicable timing.
Bit Write: Transitions of SDA must occur during
the low state of SCL. The data on SDA must remain
valid and unchanged during the entire high pulse of
SCL plus the setup and hold time requirements (see
Figure 1). Data is shifted into the device during the
rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount
of setup time (see Figure 1) before the next rising
edge of SCL during a bit read. The device shifts out
each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising
edge of the current SCL pulse. Remember that the
master generates all SCL clock pulses including when
it is reading bits from the slave.
Acknowledge (ACK and NACK): An acknowledge
(ACK) or not acknowledge (NACK) is always the ninth
bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
during a write operation) performs an ACK by transmitting a 0 during the ninth bit. A device performs
a NACK by transmitting a 1 during the ninth bit.
Timing for the ACK and NACK is identical to all other
bit writes. An ACK is the acknowledgment that the
device is properly receiving data. A NACK is used to
terminate a read sequence or as an indication that the
device is not receiving data.
Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgment from
the slave to the master. The 8 bits transmitted by the
master are done according to the bit write definition
and the acknowledgment is read using the bit read
definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the
bit read definition, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to
terminate communication so the slave returns control
of SDA to the master.
20
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Slave Address Byte: Each slave on the I2C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/W bit in the least significant bit. The
device’s slave address is D0h and cannot be modified by the user. When the R/W bit is 0 (such as in
D0h), the master is indicating it writes data to the
slave. If R/W = 1 (D1h in this case), the master is
indicating it wants to read from the slave. If an incorrect slave address is written, the device assumes the
master is communicating with another I2C device and
ignore the communication until the next START condition is sent.
Memory Address: During an I2C write operation, the
master must transmit a memory address to identify
the memory location where the slave is to store the
data. The memory address is always the second byte
transmitted during a write operation following the
slave address byte.
I2C Communication
See Figure 10 for an I2C communication example.
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write
the byte of data, and generate a STOP condition.
Remember the master must read the slave’s acknowledgment during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a START condition, writes the slave address byte (R/W = 0), writes
the starting memory address, writes multiple data
bytes, and generates a STOP condition.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the specified memory address
byte to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the slave,
the master generates a START condition, writes the
TYPICAL I2C WRITE TRANSACTION
MSB
START
1
LSB
1
0
1
0
0
0
R/W
MSB
SLAVE
ACK
b7
LSB
b6
READ/
WRITE
SLAVE
ADDRESS
b5
b4
b3
b2
b1
b0
MSB
SLAVE
ACK
b7
LSB
b6
b5
b4
REGISTER ADDRESS
b3
b2
b1
b0
SLAVE
ACK
STOP
DATA
EXAMPLE I2C TRANSACTIONS
D0h
A) SINGLE BYTE WRITE
-WRITE CONTROL REGISTER
TO 44h
START
B) SINGLE BYTE READ
-READ CONTROL REGISTER
START 1 1 0 1 0 0 0 0
11010000
D0h
0Eh
SLAVE
00001110
ACK
0Eh
SLAVE
SLAVE
00001110
ACK
ACK
D0h
C) MULTIBYTE WRITE
-WRITE DATE REGISTER
TO "02" AND MONTH
REGISTER TO "11"
D) MULTIBYTE READ
-READ ALARM 2 HOURS
AND DATE VALUES
START 1 1 0 1 0 0 0 0
04h
SLAVE
ACK
00000100
SLAVE
ACK
00001100
D0h
START 1 1 0 1 0 0 0 0
44h
SLAVE
01000100
ACK
SLAVE
ACK
STOP
D1h
REPEATED
START
DATA
11010001
00000010
SLAVE
ACK
REPEATED
START
SLAVE
ACK
00010001
SLAVE
ACK
SLAVE
ACK
VALUE
D1h
0Ch
VALUE
MASTER
NACK
STOP
11h
02h
SLAVE
ACK
SLAVE
ACK
11010001
STOP
DATA
DATA
MASTER
ACK
VALUE
MASTER
NACK
STOP
Figure 10. I2C Transactions
21
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
slave address byte with R/W = 1, reads the data byte
with a NACK to indicate the end of the transfer, and
generates a STOP condition. However, since requiring the master to keep track of the memory address
counter is impractical, use the method for manipulating the address counter for reads.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master generates a START condition, writes the slave
address byte (R/W = 0), writes the memory address
where it desires to read, generates a repeated START
condition, writes the slave address byte (R/W = 1),
reads data with ACK or NACK as applicable, and
generates a STOP condition. See Figure 6 for a read
example using the repeated START condition to
specify the starting memory location.
Reading Multiple Bytes from a Slave: The read
operation can be used to read multiple bytes with a
single transfer. When reading bytes from the slave,
the master simply ACKs the data byte if it desires to
read another byte before terminating the transaction.
After the master reads the last byte it must NACK to
indicate the end of the transfer and then it generates
a STOP condition.
Applications Information
Using Open-Drain Outputs
The INT/SQW output is open drain and requires an external pullup resistor to realize logic-high output level. Pullup
resistor values between 1kI and 10MI are typical.
The RST output is also open drain, but is provided with
an internal 50kI pullup resistor (RPU) to VCC. External
pullup resistors should not be added.
SDA and SCL Pullup Resistors
SDA is an open-drain output and requires an external
pullup resistor to realize a logic-high level.
Because the device does not use clock cycle stretching,
a master using either an open-drain output with a pullup
resistor or CMOS output driver (push-pull) could be used
for SCL.
Battery Charge Protection
The device contains Maxim’s redundant battery-charge
protection circuit to prevent any charging of the external
battery.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DS3232MZ+
-40NC to +85NC
8 SO
DS3232MZ/V+
-40NC to +85NC
8 SO
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Power-Supply Decoupling
To achieve the best results when using the DS3232M,
decouple the VCC and/or VBAT power supplies with
0.1FF and/or 1.0FF capacitors. Use a high-quality,
ceramic, surface-mount capacitor if possible. Surfacemount components minimize lead inductance, which
improves performance, and ceramic capacitors tend to
have adequate high-frequency response for decoupling
applications.
If communications during battery operation are not
required, the VBAT decoupling capacitor can be omitted.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 SO
S8MK+1
21-0041
90-0096
22
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Revision History
REVISION
NUMBER
REVISION
DATE
0
3/12
Initial release
—
1
8/12
Added an automotive qualified part option to the Ordering Information table
22
DESCRIPTION
PAGES
CHANGED
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
©
2012 Maxim Integrated Products
23
Maxim is a registered trademark of Maxim Integrated Products, Inc.