DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz General Description Features The DS90CR287 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR288A receiver converts the four LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec). n n n n n n n n n n n n n This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces. 20 to 85 MHz shift clock support 50% duty cycle on receiver output clock 2.5 / 0 ns Set & Hold Times on TxINPUTs Low power consumption ± 1V common-mode range (around +1.2V) Narrow bus reduces cable size and cost Up to 2.38 Gbps throughput Up to 297.5 Mbytes/sec bandwidth 345 mV (typ) swing LVDS devices for low EMI PLL requires no external components Rising edge data strobe Compatible with TIA/EIA-644 LVDS standard Low profile 56-lead TSSOP package Block Diagrams DS90CR288A DS90CR287 10108727 10108701 Order Number DS90CR287MTD See NS Package Number MTD56 © 2004 National Semiconductor Corporation DS101087 Order Number DS90CR288AMTD See NS Package Number MTD56 www.national.com DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz July 2004 DS90CR287/DS90CR288A Pin Diagram for TSSOP Packages DS90CR287 DS90CR288A 10108721 10108722 Typical Application 10108723 www.national.com 2 Package Derating: If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.5V to (VCC + 0.3V) CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage −0.3V to (VCC + 0.3V) LVDS Driver Output Voltage −0.3V to (VCC + 0.3V) +150˚C Storage Temperature −65˚C to +150˚C > 7kV > 700V (EIAJ, 0Ω, 200pF) Latch Up Tolerance @ +25˚C > ± 300mA Recommended Operating Conditions Continuous Junction Temperature 12.4 mW/˚C above +25˚C (HBM, 1.5kΩ, 100pF) LVDS Output Short Circuit Duration 12.5 mW/˚C above +25˚C DS90CR288AMTD ESD Rating −0.3V to +4V CMOS/TTL Input Voltage DS90CR287MTD Min Nom Max Units Supply Voltage (VCC) Lead Temperature (Soldering, 4 sec.) 3.0 +260˚C Temperature (TA) Solder Reflow Temperature Receiver Input Range Maximum Package Power Dissipation @ +25˚C 1.63 W DS90CR288AMTD 1.61 W 3.6 V −10 +25 +70 ˚C 0 2.4 Supply Noise Voltage (VCC) MTD56 (TSSOP) Package: DS90CR287MTD 3.3 Operating Free Air V 100 mVPP Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ Max Units LVCMOS/LVTTL DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V VOH High Level Output Voltage IOH = −0.4 mA VOL Low Level Output Voltage IOL = 2 mA VCL Input Clamp Voltage ICL = −18 mA IIN Input Current VIN = 0.4V, 2.5V or VCC VIN = GND IOS Output Short Circuit Current 2.7 −10 VOUT = 0V 3.3 V 0.06 0.3 V −0.79 −1.5 V +1.8 +15 µA −60 −120 mA 290 450 mV 35 mV 0 µA LVDS DRIVER DC SPECIFICATIONS VOD Differential Output Voltage ∆VOD Change in VOD between Complimentary Output States VOS Offset Voltage (Note 4) ∆VOS Change in VOS between Complimentary Output States IOS Output Short Circuit Current VOUT = 0V, RL = 100Ω IOZ Output TRI-STATE Current PWR DWN = 0V, VOUT = 0V or VCC RL = 100Ω 250 1.125 1.25 1.375 V 35 mV −3.5 −5 mA ±1 ± 10 µA LVDS RECEIVER DC SPECIFICATIONS VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current VCM = +1.2V +100 −100 VIN = +2.4V, VCC = 3.6V VIN = 0V, VCC = 3.6V 3 mV mV ± 10 ± 10 µA µA www.national.com DS90CR287/DS90CR288A Absolute Maximum Ratings (Note 1) DS90CR287/DS90CR288A Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ Max Units f = 33 MHz 31 45 mA f = 40 MHz 32 50 mA f = 66 MHz 37 55 mA f = 85 MHz 42 60 mA 10 55 µA f = 33 MHz 49 70 mA f = 40 MHz 53 75 mA f = 66 MHz 81 114 mA f = 85 MHz 96 135 mA PWR DWN = Low Receiver Outputs Stay Low during Powerdown Mode 140 400 µA TRANSMITTER SUPPLY CURRENT ICCTW ICCTZ Transmitter Supply Current Worst Case (with Loads) Transmitter Supply Current Power Down RL = 100Ω, CL = 5 pF, Worst Case Pattern (Figures 1, 2) PWR DWN = Low Driver Outputs in TRI-STATE under Powerdown Mode RECEIVER SUPPLY CURRENT ICCRW ICCRZ Receiver Supply Current Worst Case CL = 8 pF, Worst Case Pattern (Figures 1, 3) Receiver Supply Current Power Down Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ∆VOD). Note 4: VOS previously referred as VCM. Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Typ Max LLHT Symbol LVDS Low-to-High Transition Time (Figure 2) 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time (Figure 2) 0.75 1.5 ns TCIT TxCLK IN Transition Time (Figure 4) 6.0 ns TPPos0 Transmitter Output Pulse Position for Bit0 (Figure 14) −0.20 0 0.20 ns TPPos1 Transmitter Output Pulse Position for Bit1 1.48 1.68 1.88 ns TPPos2 Transmitter Output Pulse Position for Bit2 3.16 3.36 3.56 ns TPPos3 Transmitter Output Pulse Position for Bit3 4.84 5.04 5.24 ns TPPos4 Transmitter Output Pulse Position for Bit4 6.52 6.72 6.92 ns TPPos5 Transmitter Output Pulse Position for Bit5 8.20 8.40 8.60 ns TPPos6 Transmitter Output Pulse Position for Bit6 9.88 10.08 10.28 ns TCIP TxCLK IN Period (Figure 5 ) 11.76 T 50 ns TCIH TxCLK IN High Time (Figure 5) 0.35T 0.5T 0.65T ns TCIL TxCLK IN Low Time (Figure 5) 0.35T 0.5T 0.65T ns TSTC TxIN Setup to TxCLK IN (Figure 5) THTC TxIN Hold to TxCLK IN (Figure 5) TCCD TxCLK IN to TxCLK OUT Delay (Figure 7) TPLLS TPDD TJIT TxCLK IN Cycle-to-Cycle Jitter (Input clock requirement) www.national.com Parameter Min 1.0 f = 85 MHz f = 85 MHz TA = 25˚C, VCC = 3.3V Units 2.5 ns 0 ns 6.3 ns Transmitter Phase Lock Loop Set (Figure 9) 10 ms Transmitter Powerdown Delay (Figure 12) 100 ns 2 ns 4 3.8 Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter CLHT CMOS/TTL Low-to-High Transition Time (Figure 3) CHLT CMOS/TTL High-to-Low Transition Time (Figure 3) RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 15) RSPos1 RSPos2 Min Typ Max Units 2 3.5 ns 1.8 3.5 ns 0.49 0.84 1.19 ns Receiver Input Strobe Position for Bit 1 2.17 2.52 2.87 ns Receiver Input Strobe Position for Bit 2 3.85 4.20 4.55 ns RSPos3 Receiver Input Strobe Position for Bit 3 5.53 5.88 6.23 ns RSPos4 Receiver Input Strobe Position for Bit 4 7.21 7.56 7.91 ns RSPos5 Receiver Input Strobe Position for Bit 5 8.89 9.24 9.59 ns RSPos6 Receiver Input Strobe Position for Bit 6 10.57 10.92 11.27 ns RSKM RxIN Skew Margin (Note 5) (Figure 16) RCOP RxCLK OUT Period (Figure 6) 11.76 T 50 ns RCOH RxCLK OUT High Time (Figure 6) 4 5 6.5 ns 5 6 f = 85 MHz f = 85 MHz f = 85 MHz 290 ps RCOL RxCLK OUT Low Time (Figure 6) 3.5 RSRC RxOUT Setup to RxCLK OUT (Figure 6) 3.5 ns ns RHRC RxOUT Hold to RxCLK OUT (Figure 6) 3.5 ns 5.5 RCCD RxCLK IN to RxCLK OUT Delay @ 25˚C, VCC = 3.3V (Note 6)(Figure 8) 9.5 ns RPLLS Receiver Phase Lock Loop Set (Figure 10) 10 ms RPDD Receiver Powerdown Delay (Figure 13) 1 µs 7 Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and source clock (less than 150 ps). Note 6: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency for the 217/287 transmitter and 218/288A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period. AC Timing Diagrams 10108702 FIGURE 1. “Worst Case” Test Pattern 5 www.national.com DS90CR287/DS90CR288A Receiver Switching Characteristics DS90CR287/DS90CR288A AC Timing Diagrams (Continued) 10108703 10108704 FIGURE 2. DS90CR287 (Transmitter) LVDS Output Load and Transition Times 10108705 10108706 FIGURE 3. DS90CR288A (Receiver) CMOS/TTL Output Load and Transition Times 10108707 FIGURE 4. DS90CR287 (Transmitter) Input Clock Transition Time 10108709 FIGURE 5. DS90CR287 (Transmitter) Setup/Hold and High/Low Times www.national.com 6 DS90CR287/DS90CR288A AC Timing Diagrams (Continued) 10108710 FIGURE 6. DS90CR288A (Receiver) Setup/Hold and High/Low Times 10108711 FIGURE 7. DS90CR287 (Transmitter) Clock In to Clock Out Delay 10108712 FIGURE 8. DS90CR288A (Receiver) Clock In to Clock Out Delay 10108713 FIGURE 9. DS90CR287 (Transmitter) Phase Lock Loop Set Time 7 www.national.com DS90CR287/DS90CR288A AC Timing Diagrams (Continued) 10108714 FIGURE 10. DS90CR288A (Receiver) Phase Lock Loop Set Time 10108716 FIGURE 11. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs 10108717 FIGURE 12. Transmitter Powerdown Delay www.national.com 8 DS90CR287/DS90CR288A AC Timing Diagrams (Continued) 10108718 FIGURE 13. Receiver Powerdown Delay 10108719 FIGURE 14. Transmitter LVDS Output Pulse Position Measurement 9 www.national.com DS90CR287/DS90CR288A AC Timing Diagrams (Continued) 10108728 FIGURE 15. Receiver LVDS Input Strobe Position www.national.com 10 DS90CR287/DS90CR288A AC Timing Diagrams (Continued) 10108720 C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos — Transmitter output pulse position (min and max) RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(Note 7) + ISI (Inter-symbol interference)(Note 8) Cable Skew — typically 10 ps–40 ps per foot, media dependent Note 7: Cycle-to-cycle jitter is less than 150ps at 85MHz. Note 8: ISI is dependent on interconnect length; may be zero FIGURE 16. Receiver LVDS Input Skew Margin DS90CR287 MTD56 (TSSOP) Package Pin Description — Channel Link Transmitter Pin Name I/O No. Description TxIN I 28 TTL level input. TxOUT+ O 4 Positive LVDS differential data output. TxOUT− O 4 Negative LVDS differential data output. TxCLK IN I 1 TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN. See Applications Information section. TxCLK OUT+ O 1 Positive LVDS differential clock output. TxCLK OUT− O 1 Negative LVDS differential clock output. PWR DOWN I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down. See Applications Information section. VCC I 4 Power supply pins for TTL inputs. GND I 5 Ground pins for TTL inputs. PLL VCC I 1 Power supply pin for PLL. PLL GND I 2 Ground pins for PLL. LVDS VCC I 1 Power supply pin for LVDS outputs. LVDS GND I 3 Ground pins for LVDS outputs. DS90CR288A MTD56 (TSSOP) Package Pin Description — Channel Link Receiver Pin Name RxIN+ I/O No. I 4 Description Positive LVDS differential data inputs. RxIN− I 4 Negative LVDS differential data inputs. RxOUT O 28 TTL level data outputs. RxCLK IN+ I 1 Positive LVDS differential clock input. RxCLK IN− I 1 Negative LVDS differential clock input. RxCLK OUT O 1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT. PWR DOWN I 1 TTL level input. When asserted (low input) the receiver outputs are low. VCC I 4 Power supply pins for TTL outputs. 11 www.national.com DS90CR287/DS90CR288A DS90CR288A MTD56 (TSSOP) Package Pin Description — Channel Link Receiver (Continued) Pin Name I/O No. GND I 5 PLL VCC I 1 Power supply for PLL. PLL GND I 2 Ground pin for PLL. LVDS VCC I 1 Power supply pin for LVDS inputs. LVDS GND I 3 Ground pins for LVDS inputs. www.national.com Description Ground pins for TTL outputs. 12 The TSSOP version of the DS90CR287 and DS90CR288A are backward compatible with the existing 5V Channel Link transmitter/receiver pair (DS90CR283, DS90CR284). To upgrade from a 5V to a 3.3V system the following must be addressed: 1. Change 5V power supply to 3.3V. Provide this supply to the VCC, LVDS VCC and PLL VCC. 2. Transmitter input and control inputs except 3.3V TTL/ CMOS levels. They are not 5V tolerant. 3. The receiver powerdown feature when enabled will lock receiver output to a logic low. The Channel Link devices are intended to be used in a wide variety of data transmission applications. Depending upon the application the interconnecting media may vary. For example, for lower data rate (clock rate) and shorter cable lengths ( < 2m), the media electrical performance is less critical. For higher speed/long distance applications the media’s performance becomes more critical. Certain cable constructions provide tighter skew (matched electrical length between the conductors and pairs). Additional applications information can be found in the following National Interface Application Notes: AN = #### RECEIVER FAILSAFE FEATURE: These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions receiver inputs will be in a HIGH state. If a clock signal is present, data outputs will all be HIGH; if the clock input is also floating/terminated, data outputs will remain in the last valid state. A floating/terminated clock input will result in a HIGH clock output. BOARD LAYOUT: To obtain the maximum benefit from the noise and EMI reductions of LVDS, attention should be paid to the layout of differential lines. Lines of a differential pair should always be adjacent to eliminate noise interference from other signals and take full advantage of the noise canceling of the differential signals. The board designer should also try to maintain equal length on signal traces for a given differential pair. As with any high-speed design, the impedance discontinuities should be limited (reduce the numbers of vias and no 90 degree angles on traces). Any discontinuities which do occur on one signal line should be mirrored in the other line of the differential pair. Care should be taken to ensure that the differential trace impedance match the differential impedance of the selected physical media (this impedance should also match the value of the termination resistor that is connected across the differential pair at the receiver’s input). Finally, the location of the CHANNEL LINK TxOUT/RxIN pins should be as close as possible to the board edge so as to eliminate excessive pcb runs. All of these considerations will limit reflections and crosstalk which adversely effect high frequency performance and EMI. INPUTS: The TxIN and control pin inputs are compatible with LVTTL and LVCMOS levels. This pins are not 5V tolerant. UNUSED INPUTS: All unused inputs at the TxIN inputs of the transmitter may be tied to ground or left no connect. All unused outputs at the RxOUT outputs of the receiver must then be left floating. TERMINATION: Use of current mode drivers requires a terminating resistor across the receiver inputs. The CHANNEL LINK chipset will normally require a single 100Ω resistor between the true and complement lines on each differential pair of the receiver input. The actual value of the termination resistor should be selected to match the differential mode characteristic impedance (90Ω to 120Ω typical) of the cable. Figure 17 shows an example. No additional pull-up or pulldown resistors are necessary as with some other differential technologies such as PECL. Surface mount resistors are recommended to avoid the additional inductance that accompanies leaded resistors. These resistors should be placed as close as possible to the receiver input pins to reduce stubs and effectively terminate the differential lines. DECOUPLING CAPACITORS: Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a conservative approach three parallel-connected decoupling capacitors (Multi-Layered Ce- Topic AN-1041 Introduction to Channel Link AN-1108 Channel Link PCB and Interconnect Design-In Guidelines AN-806 Transmission Line Theory AN-905 Transmission Line Calculations and Differential Impedance AN-916 Cable Information CABLES: A cable interface between the transmitter and receiver needs to support the differential LVDS pairs. The 21-bit CHANNEL LINK chipset (DS90CR217/218A) requires four pairs of signal wires and the 28-bit CHANNEL LINK chipset (DS90CR287/288A) requires five pairs of signal wires. The ideal cable/connector interface would have a constant 100Ω differential impedance throughout the path. It is also recommended that cable skew remain below 140ps (@ 85 MHz clock rate) to maintain a sufficient data sampling window at the receiver. In addition to the four or five cable pairs that carry data and clock, it is recommended to provide at least one additional conductor (or pair) which connects ground between the transmitter and receiver. This low impedance ground provides a common-mode return path for the two devices. Some of the more commonly used cable types for point-topoint applications include flat ribbon, flex, twisted pair and Twin-Coax. All are available in a variety of configurations and options. Flat ribbon cable, flex and twisted pair generally perform well in short point-to-point applications while TwinCoax is good for short and long applications. When using ribbon cable, it is recommended to place a ground line between each differential pair to act as a barrier to noise coupling between adjacent pairs. For Twin-Coax cable applications, it is recommended to utilize a shield on each cable pair. All extended point-to-point applications should also employ an overall shield surrounding all cable pairs regardless of the cable type. This overall shield results in improved transmission parameters such as faster attainable speeds, longer distances between transmitter and receiver and reduced problems associated with EMS or EMI. 13 www.national.com DS90CR287/DS90CR288A The high-speed transport of LVDS signals has been demonstrated on several types of cables with excellent results. However, the best overall performance has been seen when using Twin-Coax cable. Twin-Coax has very low cable skew and EMI due to its construction and double shielding. All of the design considerations discussed here and listed in the supplemental application notes provide the subsystem communications designer with many useful guidelines. It is recommended that the designer assess the tradeoffs of each application thoroughly to arrive at a reliable and economical cable solution. Applications Information DS90CR287/DS90CR288A Applications Information traces for power and ground and ensure each capacitor has its own via to the ground plane. If board space is limiting the number of bypass capacitors, the PLL VCC should receive the most filtering/bypassing. Next would be the LVDS VCC pins and finally the logic VCC pins. (Continued) ramic type in surface mount form factor) between each VCC and the ground plane(s) are recommended. The three capacitor values are 0.1 µF, 0.01 µF and 0.001 µF. An example is shown in Figure 18. The designer should employ wide 10108724 FIGURE 17. LVDS Serialized Link Termination 10108725 FIGURE 18. CHANNEL LINK Decoupling Configuration data transmission. LVDS supports an input voltage range of Ground to +2.4V. This allows for a ± 1.0V shifting of the center point due to ground potential differences and common-mode noise. TRANSMITTER INPUT CLOCK: The transmitter input clock must always be present when the device is enabled (PWR DOWN = HIGH). If the clock is stopped, the PWR DOWN pin must be used to disable the PLL. The PWR DOWN pin must be held low until after the input clock signal has been reapplied. This will ensure a proper device reset and PLL lock to occur. POWER SEQUENCING AND POWERDOWN MODE: Outputs of the CHANNEL LINK transmitter remain in TRI-STATE until the power supply reaches 2V. Clock and data outputs will begin to toggle 10 ms after VCC has reached 3V and the Powerdown pin is above 1.5V. Either device may be placed into a powerdown mode at any time by asserting the Powerdown pin (active low). Total power dissipation for each device will decrease to 5 µW (typical). The transmitter input clock may be applied prior to powering up and enabling the transmitter. The transmitter input clock may also be applied after power up; however, the use of the PWR DOWN pin is required as described in the Transmitter CLOCK JITTER: The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS interface. The width of each bit in the serialized LVDS data stream is one-seventh the clock period. For example, a 85 MHz clock has a period of 11.76 ns which results in a data bit width of 1.68 ns. Differential skew (∆t within one differential pair), interconnect skew (∆t of one differential pair to another) and clock jitter will all reduce the available window for sampling the LVDS serial data streams. Care must be taken to ensure that the clock input to the transmitter be a clean low noise signal. Individual bypassing of each VCC to ground will minimize the noise passed on to the PLL, thus creating a low jitter LVDS clock. These measures provide more margin for channel-to-channel skew and interconnect skew as a part of the overall jitter/skew budget. INPUT CLOCK: The input clock should be present at all times when the part in enabled. If the clock is stopped, the PWR DOWN pin should be asserted to disable the PLL. Once the clock is active again, the part can then be enabled. Do not enable the part without a clock present. COMMON-MODE vs. DIFFERENTIAL MODE NOISE MARGIN: The typical signal swing for LVDS is 300 mV centered at +1.2V. The CHANNEL LINK receiver supports a 100 mV threshold therefore providing approximately 200 mV of differential noise margin. Common-mode protection is of more importance to the system’s operation due to the differential www.national.com 14 receiver. If power to the transmit board is lost, the receiver clocks (input and output) stop. The data outputs (RxOUT) retain the states they were in when the clocks stopped. When the receiver board loses power, the receiver inputs are shorted to VCC through an internal diode. Current is limited (5 mA per input) by the fixed current mode drivers, thus avoiding the potential for latchup when powering the device. (Continued) Input Clock section. Do not power up and enable (PWR DOWN = HIGH) the transmitter without a valid clock signal applied to the TxCLK IN pin. The CHANNEL LINK chipset is designed to protect itself from accidental loss of power to either the transmitter or 10108726 FIGURE 19. Single-Ended and Differential Waveforms 15 www.national.com DS90CR287/DS90CR288A Applications Information DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small outline Package, JEDEC Order Number DS90CR287MTD or DS90CR288AMTD Dimensions shown in millimeters only NS Package Number MTD56 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: [email protected] National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: [email protected] Tel: 81-3-5639-7560 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.