TI DS92LV2421SQX-NOPB

DS92LV2421, DS92LV2422
www.ti.com
SNLS321B – MAY 2010 – REVISED APRIL 2013
DS92LV2421/DS92LV2422 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer
Check for Samples: DS92LV2421, DS92LV2422
FEATURES
DESCRIPTION
•
The DS92LV2421 (Serializer) / DS92LV2422
(Deserializer) chipset translates a parallel 24–bit
LVCMOS data interface into a single high-speed CML
serial interface with embedded clock information. This
single serial stream eliminates skew issues between
clock and data, reduces connector size and
interconnect cost for transferring a 24-bit or less, bus
over FR-4 printed circuit board backplanes, and
balanced cables.
1
2
•
•
General
– 24–Bit Data, 3–Bit Control, 10 – 75 MHz
Clock
– AC Coupled STP Interconnect Cable up to
10 Meters
– Integrated Terminations on Ser and Des
– AT-SPEED Link BIST Mode and Reporting
Pin
– Optional I2C Compatible Serial Control Bus
– Power Down Mode Minimizes Power
Dissipation
– 1.8V or 3.3V Compatible LVCMOS I/O
Interface
– -40° to +85°C Temperature Range
– >8 kV HBM
SERIALIZER — DS92LV2421
– Data Scrambler for Reduced EMI
– DC-Balance Encoder for AC Coupling
– Selectable Output VOD and Adjustable Deemphasis
DESERIALIZER — DS92LV2422
– FAST Random Data Lock; no Reference
Clock Required
– Adjustable Input Receiver Equalization
– LOCK (Real Time Link Status) Reporting
Pin
– EMI Minimization on Output Parallel Bus
(SSCG)
– Output Slew Control (OS)
In addition to the 24-bit data bus interface, the
DS92LV2421 and DS92LV2422 also features a 3-bit
control bus for slow speed signals. This allows
implementing video and display applications with up
to 24–bits per pixel (RGB).
Programmable
transmit
de-emphasis,
receive
equalization, on-chip scrambling and DC balancing
enables longer distance transmission over lossy
cables
and
backplanes.
The
DS92LV2422
automatically locks to incoming data without an
external reference clock or special sync patterns,
providing easy “plug-and-go” operation. EMI is
minimized by the use of low voltage differential
signaling, receiver drive strength control, and spread
spectrum clocking capability.
The
DS92LV2421,
DS92LV2422
chipset
is
programmable though an I2C interface as well as
through pins. A built-in AT-SPEED BIST feature
validates link integrity and may be used for system
diagnostics.
The DS92LV2421 is offered in a 48-pin WQFN and
the DS92LV2422 is offered in a 60-pin WQFN
package. Both devices operate over the full industrial
temperature range of -40°C to +85°C.
APPLICATIONS
•
•
•
•
•
•
Embedded Video and Display
Medical Imaging
Factory Automation
Office Automation — Printer, Scanner
Security and Video Surveillance
General Purpose Data Communication
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
DS92LV2421, DS92LV2422
SNLS321B – MAY 2010 – REVISED APRIL 2013
www.ti.com
Applications Diagram
VDDIO
VDDn
(1.8V or 3.3V) 1.8V
DI[7:0]
DI[15:8]
DI[23:16]
CI1
CI2
CI3
CLKIN
Graphic
Processor
OR
Video
Imager
OR
ASIC/FPGA
PDB
Channel Link II
1 Pair / AC Coupled
100 nF
100 nF
DOUT+
RIN+
DOUT-
RIN100 ohm STP Cable
DS92LV2421
Serializer
BISTEN
Optional
VDDn
VDDIO
1.8V (1.8V or 3.3V)
CMF
PDB
BISTEN
RFB
VODSEL
DeEmph
SCL
SDA
ID[x]
DS92LV2422
Deserializer
Optional
24-bit RGB
Display
OR
ASIC/FPGA
LOCK
PASS
STRAP pins
not shown
SCL
SDA
ID[x]
DAP
DO[7:0]
DO[15:8]
DO[23:16]
CO1
CO2
CO3
CLKOUT
DAP
Block Diagrams
RFB
CLKIN
PLL
Parallel to Serial
Input Latch
DI[23:0]
CI1/DE
CI2/HS
CI3/VS
DC Balance Encoder
VODSEL
De-Emph
DOUT+
DOUT-
Pattern
Generator
PDB
SCL
SCA
ID[x]
Timing and
Control
BISTEN
DS92LV2421 ± SERIALIZER
2
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DS92LV2421, DS92LV2422
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SNLS321B – MAY 2010 – REVISED APRIL 2013
STRAP INPUT
LF_MODE
OS_CLKOUT
OS_DATA
OSS_SEL
RFB
EQ [3:0]
OSC_SEL [2:0]
SSC [3:0]
SSCG
CMF
RIN+
EQ
RIN-
DO[23:0]
Output Latch
Serial to Parallel
ROUT-
DC Balance Decoder
ROUT+
CO1/DE
CO2/HS
CO3/VS
Error
Detector
BISTEN
PDB
SCL
SCA
ID[x]
Clock and
Data
Recovery
Timing and
Control
STRAP INPUT
PASS
OP_LOW
CLKOUT
LOCK
DS92LV2422 ± DESERIALIZER
DI9
DI8
DI7
DI6
DI5
BISTEN
VDDIO
DI4
DI3
DI2
DI1
DI0
36
35
34
33
32
31
30
29
28
27
26
25
DS92LV2421 Pin Diagram
DI10
37
24
VODSEL
DI11
38
23
De-Emph
DI12
39
22
VDDTX
DI13
40
21
PDB
DI14
41
20
DOUT+
19
DOUT-
18
RES2
DI15
42
DI16
43
DS92LV2421
TOP VIEW
DAP = GND
10
11
12
RFB
CONFIG[0]
CONFIG[1]
CLKIN
13
9
48
SDA
DI21
8
VDDP
SCL
14
7
47
VDDL
DI20
6
RES0
ID[x]
15
5
46
CI1
DI19
4
RES1
CI3
16
3
45
CI2
DI18
2
VDDHS
DI23
17
1
44
DI22
DI17
Figure 1. Top View 48-pin WQFN
See Package Number RHS0048A
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV2421 DS92LV2422
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DS92LV2421, DS92LV2422
SNLS321B – MAY 2010 – REVISED APRIL 2013
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DS92LV2421 Serializer Pin Descriptions
Pin Name
Pin #
I/O, Type
Description (1)
LVCMOS Parallel Interface
DI[7:0]
34, 33, 32, 29,
28, 27, 26, 25
I, LVCMOS Parallel Interface Data Input Pins
w/ pullFor 8–bit RED Display: DI7 = R7 – MSB, DI0 = R0 – LSB.
down
DI[15:8]
42, 41, 40, 39,
38, 37, 36, 35
I, LVCMOS Parallel Interface Data Input Pins
w/ pullFor 8–bit GREEN Display: DI15 = G7 – MSB, DI8 = G0 – LSB.
down
DI[23:16]
2, 1, 48, 47,
46, 45, 44, 43
I, LVCMOS Parallel Interface Data Input Pins
w/ pullFor 8–bit BLUE Display: DI23 = B7 – MSB, DI16 = B0 – LSB.
down
CI1
5
I, LVCMOS Control Signal Input
w/ pullFor Display/Video Application: CI1 = Data Enable Input
down
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2
transitions per 130 clocks regardless of the Control Signal Filter setting.
CI2
3
I, LVCMOS Control Signal Input
w/ pullFor Display/Video Application: CI2 = Horizontal Sync Input
down
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2
transitions per 130 clocks regardless of the Control Signal Filter setting.
CI3
4
I, LVCMOS Control Signal Input
w/ pullFor Display/Video Application: CI3 = Vertical Sync Input
down
CI3 is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed is
130 clock cycle wide.
CLKIN
10
I, LVCMOS Clock Input
w/ pullLatch/data strobe edge set by RFB pin.
down
Control and Configuration
PDB
21
I, LVCMOS Power-down Mode Input
w/ pullPDB = 1, Ser is enabled (normal operation).
down
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Ser is powered down. When the Ser is in the power-down state, the driver outputs
(DOUT+/-) are both logic high, the PLL is shutdown, IDD is minimized. Control Registers are
RESET.
VODSEL
24
I, LVCMOS Differential Driver Output Voltage Select (This is can also be control by I2C register.)
w/ pullVODSEL = 1, LVDS VOD is ±420 mV, 840 mVp-p (typ) — long cable / De-Emph apps
down
VODSEL = 0, LVDS VOD is ±280 mV, 560 mVp-p (typ) — short cable (no De-emph), low
power mode.
De-Emph
23
RFB
11
CONFIG
[1:0]
13, 12
I, Analog
w/ pull-up
De-Emphasis Control (This can also be controlled by I2C register access.)
De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control via register.
See Table 4.
I, LVCMOS Clock Input Latch/Data Strobe Edge Select (This can also be controlled by I2C register
w/ pullaccess.)
down
RFB = 1, parallel interface data and control signals are latched on the rising clock edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock edge.
I, LVCMOS 00: Control Signal Filter DISABLED
w/ pull01: Control Signal Filter ENABLED
down
10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q
11: Reverse compatibility mode to interface with the DS90C124
ID[x]
6
SCL
8
I, LVCMOS I2C Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to VDDIO.
SDA
9
I/O,
I2C Serial Control Bus Data Input / Output - Optional
LVCMOS SDA requires an external pull-up resistor VDDIO.
Open Drain
(1)
4
I, Analog
I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 11.
1= HIGH, 0 L= LOW
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DS92LV2421, DS92LV2422
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SNLS321B – MAY 2010 – REVISED APRIL 2013
DS92LV2421 Serializer Pin Descriptions (continued)
Pin Name
Pin #
BISTEN
31
RES[2:0]
18, 16, 15
I/O, Type
Description (1)
I, LVCMOS BIST Mode — Optional
w/ pullBISTEN = 0, BIST is disabled (normal operation)
down
BISTEN = 1, BIST is enabled
I, LVCMOS Reserved - tie LOW
w/ pulldown
Channel-Link II — CML Serial Interface
DOUT+
20
O, CML
Non–Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
DOUT-
19
O, CML
Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
Power and Ground (2)
VDDL
7
Power
Logic Power, 1.8 V ±5%
VDDP
14
Power
PLL Power, 1.8 V ±5%
VDDHS
17
Power
TX High Speed Logic Power, 1.8 V ±5%
VDDTX
22
Power
Output Driver Power, 1.8 V ±5%
VDDIO
30
Power
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
GND
(2)
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
DO6/SSC3
LOCK
NC
32
31
35
DO7
DO5/SSC2
36
33
DO4/SSC1
37
34
VDDIO
DO3/SSC0
38
DO1
DO2
39
DO0
41
40
VDDR
PASS/OP_LOW
42
44
43
NC
BISTEN
45
DS92LV2422 Pin Diagram
NC
46
30
NC
RES
47
29
VDDL
VDDIR
48
28
DO8/OSC_SEL0
RIN+
49
27
DO9/OSC_SEL1
RIN-
50
26
DO10/OSC_SEL2
CMF
51
25
DO11
ROUT+
52
24
VDDIO
ROUT-
53
TOP VIEW
23
DO12/EQ0
VDDCMLO
54
DAP = GND
22
DO13/EQ1
VDDR
55
21
DO14/EQ2
ID[x]
56
20
DO15/EQ3
VDDPR
57
19
DO16
VDDSC
58
18
DO17/RFB
PDB
59
17
DO18/OSS_SEL
NC
60
16
NC
DS92LV2422
12
13
14
15
DO19/OS_DATA
NC
11
DO21/OS_CLKOUT
VDDIO
10
DO22/CONFIG[1]
DO20/LF_MODE
9
7
CO3
8
6
CO1
CO2
5
VDDSC
CLKOUT
DO23/CONFIG[0]
4
3
2
SCL
1
NC
SDA
BOLD PIN NAME ± indicates I/O strap
pin associated with output pin
Figure 2. Top View 60-pin WQFN
See Package Number NKB0060B
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV2421 DS92LV2422
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DS92LV2421, DS92LV2422
SNLS321B – MAY 2010 – REVISED APRIL 2013
www.ti.com
DS92LV2422 Deserializer Pin Descriptions
Pin Name
Pin #
I/O, Type
Description (1)
LVCMOS Parallel Interface
DO[7:0]
33, 34, 35,
36, 37, 39,
40, 41
I, STRAP,
O, LVCMOS
Parallel Interface Data Output Pins
For 8–bit RED Display: DO7 = R7 – MSB, DO0 = R0 – LSB.
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 8). These pins
are inputs during power-up (See STRAP Inputs).
DO[15:8]
20, 21, 22,
23, 25, 26,
27, 28
I, STRAP,
O, LVCMOS
Parallel Interface Data Output Pins
For 8–bit GREEN Display: DO15 = G7 – MSB, DO8 = G0 – LSB.
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 8). These pins
are inputs during power-up (See STRAP Inputs).
DO[23:16]
9, 10, 11,
12, 14, 17,
18, 19
I, STRAP,
O, LVCMOS
Parallel Interface Data Input Pins
For 8–bit BLUE Display: DO23 = B7 – MSB, DO16 = B0 – LSB.
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 8). These pins
are inputs during power-up (See STRAP Inputs).
CO1
6
O, LVCMOS
Control Signal Output
For Display/Video Application:
CO1 = Data Enable Output
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 8).
CO2
8
O, LVCMOS
Control Signal Output
For Display/Video Application:
CO2 = Horizontal Sync Output
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 8).
CO3
7
O, LVCMOS
Control Signal Output
For Display/Video Application:
CO3 = Vertical Sync Output
CO3 is different than CO1 and CO2 because it is limited to 1 transition per 130 clock cycles.
Thus, the minimum pulse width allowed is 130 clock cycle wide.
The CONFIG[1:0] pins have no affect on CO3 signal
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 8).
CLKOUT
5
O, LVCMOS
Pixel Clock Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 8). Data
strobe edge set by RFB.
LOCK
32
O, LVCMOS
LOCK Status Output
LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, DO[23:0], CO1,
CO2, CO3 and CLKOUT output states are controlled by OSS_SEL (See Table 8). May be
used as Link Status or to flag when Video Data is active (ON/OFF).
PASS
42
O, LVCMOS
PASS Output (BIST Mode)
PASS = 1, error free transmission
PASS = 0, one or more errors were detected in the received payload
Route to test point for monitoring, or leave open if unused.
Control and Configuration — STRAP PINS
For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP pins are read upon
power-up and set device configuration. Pin Number listed along with shared data output name in square brackets.
CONFIG
[1:0]
10 [DO22],
9 [DO23]
STRAP
I, LVCMOS
w/ pull-down
00:
01:
10:
11:
LF_MODE
12 [DO20]
STRAP
I, LVCMOS
w/ pull-down
SSCG Low Frequency Mode
Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE (X).
LF_MODE = 1, SSCG in low frequency mode (CLK = 10-20 MHz)
LF_MODE = 0, SSCG in high frequency mode (CLK = 20-65 MHz)
This can also be controlled by I2C register access.
(1)
6
Control Signal Filter DISABLED
Control Signal Filter ENABLED
Reverse compatibility mode to interface with the DS90UR241 or DS99R241
Reverse compatibility mode to interface with the DS90C241
1= HIGH, 0 L= LOW
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DS92LV2421, DS92LV2422
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SNLS321B – MAY 2010 – REVISED APRIL 2013
DS92LV2422 Deserializer Pin Descriptions (continued)
Pin Name
Description (1)
Pin #
I/O, Type
OS_CLKOUT
11 [DO21]
STRAP
I, LVCMOS
w/ pull-down
Output CLKOUT Slew Select
OS_CLKOUT = 1, Increased CLKOUT slew rate
OS_CLKOUT = 0, Normal CLKOUT slew rate (default)
This can also be controlled by I2C register access.
OS_DATA
14 [DO19]
STRAP
I, LVCMOS
w/ pull-down
Output DO[23:0], CO1, CO2, CO3 Slew Select
OS_DATA = 1, Increased DO slew rate
OS_DATA = 0, Normal DO slew rate (default)
This can also be controlled by I2C register access.
OP_LOW
42 [PASS]
STRAP
I, LVCMOS
w/ pull-down
Outputs held LOW when LOCK = 1
NOTE: Do not use any other strap options with this strap function enabled
OP_LOW = 1: all outputs are held LOW during power up until released by programming
OP_LOW release/set register HIGH.
NOTE: Before the device is powered up, the outputs are in TRI-STATE
See Figure 26 and Figure 27
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default)
This can also be controlled by I2C register access.
OSS_SEL
17 [DO18]
STRAP
I, LVCMOS
w/ pull-down
Output Sleep State Select
OSS_SEL is used in conjunction with PDB to determine the state of the outputs in Power
Down (Sleep). (See Table 8).
NOTE: OSS_SEL STRAP CANNOT BE USED IF OP_LOW = 1
This can also be controlled by I2C register access.
RFB
18 [DO17]
STRAP
I, LVCMOS
w/ pull-down
Clock Output Strobe Edge Select
RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
This can also be controlled by I2C register access.
EQ[3:0]
20 [DO15],
21 [DO14],
22 [DO13],
23 [DO12]
STRAP
I, LVCMOS
w/ pull-down
Receiver Input Equalization
(See Table 5).
This can also be controlled by I2C register access.
OSC_SEL[2:0]
26 [DO10],
27 [DO9],
28 [DO8]
STRAP
I, LVCMOS
w/ pull-down
Oscillator Selectl
(See Table 9 and Table 10).
This can also be controlled by I2C register access.
SSC[3:0]
34 [DO6],
35 [DO5],
36 [DO4],
37 [DO3]
STRAP
I, LVCMOS
w/ pull-down
Spread Spectrum Clock Generation (SSCG) Range Select
(See Table 6 and Table 7).
This can also be controlled by I2C register access.
40[D],
41 [D]
STRAP
I, LVCMOS
w/ pull-down
Bit mapping reverse compatibility / DS90UR241 Options
Pin or Register Control
Default setting is b'00.
Power Down Mode Input
PDB = 1, Des is enabled (normal operation).
Refer to “Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Des is in power-down.
When the Des is in the power-down state, the LVCMOS output state is determined by
Table 8. Control Registers are RESET.
MAP_SEL[1:0]
Control and Configuration
PDB
59
I, LVCMOS
w/ pull-down
ID[x]
56
I, Analog
SCL
3
I, LVCMOS
SDA
2
I/O, LVCMOS I2C Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor to VDDIO.
BISTEN
44
I, LVCMOS
w/ pull-down
BIST Enable Input — Optional
BISTEN = 0, BIST is disabled (normal operation)
BISTEN = 1, BIST is enabled
RES
47
I, LVCMOS
w/ pull-down
Reserved - tie LOW
NC
1, 15, 16,
30, 31, 45,
46, 60
I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See Table 11).
I2C Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to VDDIO.
Not Connected
Leave pin open (float)
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Product Folder Links: DS92LV2421 DS92LV2422
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DS92LV2421, DS92LV2422
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DS92LV2422 Deserializer Pin Descriptions (continued)
Pin Name
Pin #
I/O, Type
Description (1)
Channel-Link II — CML Serial Interface
RIN+
49
I, CML
True Input. The input must be AC Coupled with a 0.1 μF capacitor.
RIN-
50
I, CML
Inverting Input. The input must be AC Coupled with a 0.1 μF capacitor.
CMF
51
I, Analog
Common-Mode Filter
VCM center-tap is a virtual ground which may be ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
ROUT+
52
O, CML
True Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
ROUT-
53
O, CML
Inverting Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
Power and Ground (2)
VDDL
29
Power
Logic Power, 1.8 V ±5%
VDDIR
48
Power
Input Power, 1.8 V ±5%
VDDR
43, 55
Power
RX High Speed Logic Power, 1.8 V ±5%
VDDSC
4, 58
Power
SSCG Power, 1.8 V ±5%
VDDPR
57
Power
PLL Power, 1.8 V ±5%
VDDCMLO
54
Power
RX High Speed Logic Power, 1.8 V ±5%
13, 24, 38
Power
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% (VDDIO)
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connected to the ground plane (GND) with at least 9 vias.
VDDIO
GND
(2)
8
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
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Product Folder Links: DS92LV2421 DS92LV2422
DS92LV2421, DS92LV2422
www.ti.com
SNLS321B – MAY 2010 – REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
−0.3V to +2.5V
Supply Voltage – VDDn (1.8V)
−0.3V to +4.0V
Supply Voltage – VDDIO
−0.3V to (VDDIO + 0.3V)
LVCMOS I/O Voltage
Receiver Input Voltage
−0.3V to (VDD + 0.3V)
Driver Output Voltage
−0.3V to (VDD + 0.3V)
Junction Temperature
+150°C
−65°C to +150°C
Storage Temperature
48L WQFN Package
Maximum Power Dissipation Capacity at
25°C
Derate above 25°C
60L WQFN Package
225 mW
1/ θJA mW / °C
θJA (with 9 thermal via)
27.1 °C/W
θJC (with 9 thermal via)
4.5 °C/W
Maximum Power Dissipation Capacity at
25°C
525 mW
Derate above 25°C
1/ θJA mW / °C
θJA (with 9 thermal via)
24.6 °C/W
θJC (with 9 thermal via)
2.8 °C/W
≥±8 kV
ESD Rating (HBM)
≥±1 kV
ESD Rating (CDM)
≥±250 V
ESD Rating (MM)
ESD Rating (IEC 61000–4–2), RD = 330Ω, CS = 150pF
≥±25kV
Air Discharge (DOUT+, DOUT-)
≥±8kV
Contact Discharge (DOUT+, DOUT-)
≥±25kV
Air Discharge (RIN+, RIN-)
≥±8kV
Contact Discharge (RIN+, RIN-)
For soldering specifications:
See product folder SNOA549
(1)
(2)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV2421 DS92LV2422
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DS92LV2421, DS92LV2422
SNLS321B – MAY 2010 – REVISED APRIL 2013
www.ti.com
Recommended Operating Conditions
Min (1)
Nom
Max (1)
Units
Supply Voltage (VDDn)
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO)
1.71
1.8
1.89
V
OR
LVCMOS Supply Voltage (VDDIO)
3.0
3.3
3.6
V
Operating Free Air Temperature (TA)
−40
+25
+85
°C
Clock Frequency
10
75
MHz
50
mVP-P
Supply Noise
(1)
(2)
(2)
Specification is verified by design and is not tested in production.
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with
amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter
cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the
noise frequency is less than 400 kHz.
Serializer DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
Symbol
Parameter
Conditions
Pin/Freq.
Min (4)
Max (4)
Units
2.2
VDDIO
V
0.65*
VDDIO
VDDIO
V
GND
0.8
V
GND
0.35*
VDDIO
V
Typ
LVCMOS INPUT DC SPECIFICATIONS
VIH
VIL
IIN
High Level Input
Voltage
VDDIO = 3.0 to 3.6V
Low Level Input
Voltage
VDDIO = 3.0 to 3.6V
Input Current
VIN = 0V or VDDIO
DI[23:0],
CI1,CI2,CI3,
CLKIN, PDB,
VODSEL,
RFB,
BISTEN,
CONFIG[1:0]
VDDIO = 1.71 to 1.89V
VDDIO = 1.71 to 1.89V
VDDIO = 3.0
to 3.6V
−15
±1
+15
μA
VDDIO = 1.7
to 1.89V
−15
±1
+15
μA
VODSEL = 0
±205
±280
±355
mV
VODSEL = 1
±320
±420
±520
CML DRIVER DC SPECIFICATIONS (5)
VOD
Differential Output
Voltage
VODp-p
Differential Output
Voltage
(DOUT+) –
(DOUT-)
RL = 100Ω,
De-emph = disabled, Figure 4
VODSEL = 0
560
mVp-p
VODSEL = 1
840
mVp-p
ΔVOD
Output Voltage
Unbalance
RL = 100Ω, De-emph = disabled, VODSEL = L
VOS
Offset Voltage –
Single-ended
At TP A & B,
Figure 3
RL = 100Ω,
De-emph = disabled
ΔVOS
Offset Voltage
Unbalance
Single-ended
At TP A & B,
Figure 3
RL = 100Ω, De-emph = disabled
IOS
Output Short
Circuit Current
DOUT+/- = 0V,
De-emph = disabled
(1)
(2)
(3)
(4)
(5)
10
VODSEL = 0
VODSEL = 1
1
DOUT+,
DOUT-
VODSEL = 0
50
mV
1.65
V
1.57
5
V
1
mV
−36
mA
The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not
verified.
Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at
the time of product characterization and are not verified.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Specification is verified by design and is not tested in production.
Specification is verified by characterization and is not tested in production.
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SNLS321B – MAY 2010 – REVISED APRIL 2013
Serializer DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
Symbol
RTO
Parameter
Conditions
Pin/Freq.
Internal Output
Termination
Resistor
DOUT+,
DOUT-
Min (4)
Typ
Max (4)
Units
80
100
120
Ω
SUPPLY CURRENT
IDDT1
IDDIOT1
IDDT2
Serializer
Supply Current
(includes load
current)
RL = 100 Ω, CLKIN
= 75 MHz
IDDIOT2
IDDZ
IDDIOZ
Serializer
Supply Current
Power-down
Checker Board Pattern,
De-emph = 3kΩ,
VODSEL = H, Figure 11
Checker Board Pattern,
De-emph = 6kΩ,
VODSEL = L, Figure 11
PDB = 0V, (All other LVCMOS
Inputs = 0V)
VDD= 1.89V
75
90
mA
VDDIO= 1.89V VDDIO
3
5
mA
VDDIO = 3.6V
11
15
mA
VDD= 1.89V
All VDD pins
65
80
mA
VDDIO= 1.89V VDDIO
3
5
mA
VDDIO = 3.6V
11
15
mA
40
1000
µA
VDDIO= 1.89V VDDIO
5
10
µA
VDDIO = 3.6V
10
20
µA
Typ
Max
Units
2.2
VDDIO
V
GND
0.8
V
+15
μA
VDD= 1.89V
All VDD pins
All VDD pins
Deserializer DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
(1)
(1)
3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6V
VIH
High Level Input
Voltage
VIL
Low Level Input
Voltage
IIN
Input Current
VIN = 0V or VDDIO
VOH
High Level
Output Voltage
IOH = −0.5 mA, RDS = L
VOL
Low Level Output IOL = +0.5 mA, RDS = L
Voltage
IOS
IOZ
(1)
PDB, BISTEN
DO[23:0], CO1, CO2, CO3,
CLKOUT, LOCK, PASS
−15
±1
2.4
VDDIO
GND
V
0.4
V
Output Short
Circuit Current
VDDIO = 3.3V,
VOUT = 0V,
OS_CLKOUT/DATA = L/H
CLKOUT
36
mA
Output Short
Circuit Current
VDDIO = 3.3V,
VOUT = 0V,
OS_CLKOUT/DATA = L/H
Outputs
37
mA
TRI-STATE
Output Current
PDB = 0V, OSS_SEL = 0V,
VOUT = 0V or VDDIO
Outputs
−15
+15
µA
Specification is verified by design and is not tested in production.
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV2421 DS92LV2422
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SNLS321B – MAY 2010 – REVISED APRIL 2013
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Deserializer DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Max
Units
1.23
5
VDDIO
V
PDB, BISTEN
GND
0.595
V
−15
±1
+15
μA
DO[23:0], CO1, CO2, CO3,
CLKOUT, LOCK, PASS
VDDI
VDDIO
(1)
Typ
(1)
1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89V
VIH
High Level Input
Voltage
VIL
Low Level Input
Voltage
IIN
Input Current
VIN = 0V or VDDIO
IOH = −0.5 mA, RDS = L
VOH
High Level
Output Voltage
VOL
0.45
Low Level Output IOL = +0.5 mA, RDS = L
Voltage
IOS
IOZ
V
O
GND
0.2
V
Output Short
Circuit Current
VDDIO = 1.8V,
VOUT = 0V,
OS_CLKOUT/DATA = L/H
CLKOUT
18
mA
Output Short
Circuit Current
VDDIO = 1.8V,
VOUT = 0V,
OS_CLKOUT/DATA = L/H
Outputs
18
mA
TRI-STATE
Output Current
PDB = 0V, OSS_SEL = 0V,
VOUT = 0V or VDDIO
Outputs
-15
+15
µA
CML RECEIVER DC SPECIFICATIONS
VTH
Differential Input
Threshold High
Voltage
VTL
Differential Input
Threshold Low
Voltage
VCM
Common Mode
Voltage, Internal
VBIAS
IIN
Input Current
RTI
Internal Input
Termination
Resistor
VCM = +1.2V (Internal VBIAS)
+50
mV
−50
mV
RIN+, RIN1.2
VIN = 0V or VDDIO
-15
RIN+,
RIN-
80
100
V
+15
µA
120
Ω
LOOP THROUGH CML DRIVER OUTPUT DC SPECIFICATIONS – EQ TEST PORT (2)
VOD
Differential
Output Voltage
RL = 100Ω
VOS
Offset Voltage
Single-ended
RL = 100Ω
RT
542
mV
1.4
V
ROUT+/-
Internal
Termination
Resistor
80
100
120
Ω
97
115
mA
40
50
mA
75
85
mA
SUPPLY CURRENT
IDD1
IDDIO1
Deserializer
Supply Current
(includes load
current) CLKOUT
Checker Board Pattern, RDS =
= 75 MHz
H,
CL = 4pF, Figure 11
VDD=
1.89V
VDDIO
=1.89
V
All VDD pins
VDDIO
VDDIO
= 3.6V
(2)
12
Specification is verified by characterization and is not tested in production.
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SNLS321B – MAY 2010 – REVISED APRIL 2013
Deserializer DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
IDDZ
Conditions
PDB = 0V, All other LVCMOS
Inputs = 0V
Deserializer
Supply Current
Power Down
Pin/Freq.
VDD=
1.89V
VDDIO
=1.89
V
IDDIOZ
Min
(1)
All VDD pins
Typ
Max
Units
100
3000
µA
6
50
µA
12
100
µA
(1)
VDDIO
VDDIO
= 3.6V
Recommended Serializer Timing for CLKIN Requirements
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Typ
Max (1)
Units
13.3
T
100
ns
tTCP
Transmit Input CLKIN Period
tTCIH
Transmit Input CLKIN High
Time
0.4T
0.5T
0.6T
ns
tTCIL
Transmit Input CLKIN Low Time
0.4T
0.5T
0.6T
ns
tCLKT
CLKIN Input Transition Time
2.4
ns
SSCIN
CLKIN Input – Spread Spectrum fmod
at 75 MHz
fdev
35
kHz
±2
%
Max (1)
Units
(1)
10 MHz to 75 MHz, Figure 6
Min (1)
0.5
Specification is verified by design and is not tested in production.
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tLHT
Parameter
Ser Output Low-to-High
Transition Time, Figure 5
tHLT
Ser Output High-to-Low
Transition Time, Figure 5
Conditions
200
ps
RL = 100Ω, De-emphasis = disabled,
VODSEL = 1
200
ps
RL = 100Ω, De-emphasis = disabled,
VODSEL = 0
200
ps
RL = 100Ω, De-emphasis = disabled,
VODSEL = 1
200
ps
Input Data - Setup Time,
Figure 6
DI[23:0], CI1, CI2, CI3 to CLKIN
tDIH
Input Data - Hold Time,
Figure 6
CLKIN to DI[23:0], CI1, CI2, CI3
tXZD
Ser Ouput Active to OFF Delay,
Figure 8
tPLD
Typ
RL = 100Ω, De-emphasis = disabled,
VODSEL = 0
tDIS
(2)
Min (1)
2
ns
2
ns
8
15
ns
Serializer PLL Lock Time,
Figure 7
RL = 100Ω
1.4
10
ms
tSD
Serializer Delay - Latency,
Figure 9
RL = 100Ω
144*T
145*T
ns
tDJIT
Ser Output Total Jitter,
Figure 10
RL = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 75MHz
0.28
UI (3)
RL = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 43MHz
0.27
UI (3)
RL = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 10MHz
0.35
UI (3)
(1)
(2)
(3)
Specification is verified by design and is not tested in production.
When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data
transfer require tPLD
UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*CLK). The UI scales with clock frequency.
Copyright © 2010–2013, Texas Instruments Incorporated
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Serializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
λSTXBW
Parameter
Serializer Jitter Transfer
Function -3 dB Bandwidth
δSTX
Serializer Jitter Transfer
Function Peaking
Min (1)
Conditions
Typ
Max (1)
Units
RL = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 75MHz
3.3
MHz
RL = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 43MHz
2.3
MHz
RL = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 10MHz
0.8
MHz
RL = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 75MHz
0.86
dB
RL = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 43MHz
0.83
dB
RL = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 10MHz
0.28
dB
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Typ
Max (1)
Units
13.3
T
100
ns
tRCP
CLK Output Period
tRCP = tTCP
tRDC
CLK Output Duty Cycle
SSCG = OFF,
10 – 75 MHz
40
50
60
%
SSCG = ON,
10 – 20MHz
35
59
65
%
SSCG = ON,
10 – 65MHz
40
53
60
%
tCLH
LVCMOS
Low-to-High
Transition Time, Figure 12
CLKOUT
Min (1)
VDDIO = 1.8V,
CL = 4pF,
OS_CLKOUT/DATA = L
CLKOUT
VDDIO = 3.3V
CL = 4pF,
OS_CLKOUT/DATA = H
tCHL
LVCMOS
High-to-Low
Transition Time, Figure 12
VDDIO = 1.8V,
CL = 4pF,
OS_CLKOUT/DATA = L
tROH
tDDLT
Data Valid before CLKOUT –
Set Up Time, Figure 16
tDPJ
(1)
(2)
(3)
(4)
14
2.0
ns
1.6
ns
1.5
ns
VDDIO = 1.71 to 1.89V or 3.0 DO[23:0], CO1, CO2,
to 3.6V
CO3
CL = 4pF (lumped load)
0.23
0.5
UI (2)
Data Valid after CLKOUT – Hold VDDIO = 1.71 to 1.89V or 3.0 DO[23:0], CO1, CO2,
Time, Figure 16
to 3.6V
CO3
CL = 4pF (lumped load)
0.33
0.5
UI (2)
Deserializer Lock Time,
Figure 15
SSC[3:0] = OFF (3)
CLKOUT = 10MHz
3
ms
SSC[3:0] = OFF (3)
CLKOUT = 75MHz
4
ms
(3)
CLKOUT = 10MHz
30
ms
SSC[3:0] = ON (3)
CLKOUT = 65MHz
6
SSC[3:0] = ON
tDD
ns
CLKOUT
VDDIO = 3.3V
CL = 4pF,
OS_CLKOUT/DATA = H
tROS
2.1
Des Delay - Latency, Figure 13
Des Period Jitter
CLKOUT = 10 to 75 MHz
SSC[3:0] = OFF
(4)
ms
139*T
140*T
ns
CLKOUT = 10 MHz
500
1000
ps
CLKOUT = 65 MHz
550
1250
ps
CLKOUT = 75 MHz
435
900
ps
Specification is verified by design and is not tested in production.
UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*CLK). The UI scales with clock frequency.
tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active clock.
tDPJ is the maximum amount the period is allowed to deviate over many samples.
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SNLS321B – MAY 2010 – REVISED APRIL 2013
Deserializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tDCCJ
tIJT
Parameter
Des Cycle-to-Cycle Jitter
Des Input Jitter Tolerance,
Figure 18
Conditions
SSC[3:0] = OFF
Min (1)
Pin/Freq.
(5)
EQ = OFF,
SSCG = OFF,
CLKOUT = 75 MHz
Typ
Max (1)
Units
CLKOUT = 10 MHz
375
900
ps
CLKOUT = 65 MHz
500
1150
ps
CLKOUT = 75 MHz
460
1000
jitter freq <2MHz
0.9
UI (2)
jitter freq >6MHz
0.5
UI (2)
ps
BIST Mode
tPASS
BIST PASS Valid Time,
BISTEN = 1, Figure 19
1
10
μs
SSCG Mode
fDEV
fMOD
(5)
Spread Spectrum
Clocking Deviation
Frequency
CLKOUT = 10 to 65
MHz, SSC[3:0] = ON
±0.5
±2
%
Spread Spectrum
Clocking Modulation
Frequency
CLKOUT = 10 to 65
MHz, SSC[3:0] = ON
8
100
kHz
Max (1)
Units
Standard Mode
100
kHz
Fast Mode
400
kHz
tDCCJ is the maximum amount of jitter between adjacent clock cycles.
Recommended Timing for the Serial Control Bus
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
fSCL
Parameter
SCL Clock Frequency
Conditions
Min (1)
Typ
Standard Mode
4.7
μs
Fast Mode
1.3
μs
Standard Mode
4.0
μs
Fast Mode
0.6
μs
Hold time for a start or a
repeated start condition,
Figure 20
Standard Mode
4.0
μs
Fast Mode
0.6
μs
Set Up time for a start or a
repeated start condition,
Figure 20
Standard Mode
4.7
μs
Fast Mode
0.6
μs
tHD;DAT
Data Hold Time,
Figure 20
Standard Mode
tSU;DAT
Data Set Up Time,
Figure 20
Standard Mode
250
Fast Mode
100
ns
tSU;STO
Set Up Time for STOP
Condition, Figure 20
Standard Mode
4.0
μs
Fast Mode
0.6
μs
tBUF
Bus Free Time
Between STOP and START,
Figure 20
Standard Mode
4.7
μs
Fast Mode
1.3
μs
SCL & SDA Rise Time,
Figure 20
Standard Mode
1000
ns
Fast Mode
300
ns
SCL & SDA Fall Time,
Figure 20
Standard Mode
300
ns
Fast mode
300
ns
tLOW
SCL Low Period
tHIGH
SCL High Period
tHD;STA
tSU:STA
tr
tf
(1)
Fast Mode
0
3.45
μs
0
0.9
μs
ns
Specification is verified by design and is not tested in production.
Copyright © 2010–2013, Texas Instruments Incorporated
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DC and AC Serial Control Bus Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min (1)
Conditions
Typ
Max (1)
Units
V
VIH
Input High Level
SDA and SCL
2.2
VDD 3.3V
VIL
Input Low Level Voltage
SDA and SCL
GND
0.8
VHY
Input Hysteresis
VOL
>50
SDA, IOL = 3mA
Iin
0
SDA or SCL, Vin = VDDIO or GND
tR
SDA RiseTime – READ
tF
-15
SDA, RPU = X, Cb ≤ 400pF
V
mV
0.4
V
+15
µA
40
ns
SDA Fall Time – READ
25
ns
tSU;DAT
Set Up Time – READ
520
ns
tHD;DAT
Hold Up Time – READ
55
ns
tSP
Input Filter
50
ns
Cin
Input Capacitance
<5
pF
(1)
SDA or SCL
Specification is verified by design and is not tested in production.
AC Timing Diagrams and Test Circuits
A
A'
CA
Scope
50:
50:
B
CB
B'
50:
50:
Single-Ended
Figure 3. Serializer Test Circuit
DOUT+
VOD-
VOD+
DOUT-
VOS
VOD+
(DOUT+) - (DOUT+)
VODp-p
0V
VOD-
Differential
GND
Figure 4. Serializer Output Waveforms
16
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SNLS321B – MAY 2010 – REVISED APRIL 2013
+VOD
80%
(DOUT+) - (DOUT-)
0V
20%
-VOD
tLLHT
tLHLT
Figure 5. Serializer Output Transition Times
tTCIH
tTCP
CLKIN
w/ RFB = L
tTCIL
80%
20%
1/2 VDDIO
tCLKT
tDIS
GND
tCLKT
VDDIO
VIHmin
VILmax
DI[23:0],
CI1,CI2,CI3
VDDIO
GND
tDIH
Figure 6. Serializer Input CLKIN Waveform and Set and Hold Times
PDB
CLKIN
1/2 VDDIO
"X"
active
tPLD
DOUT
(Diff.)
Driver OFF, VOD = 0V
Driver On
Figure 7. Serializer Lock Time
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1/2 VDDIO
PDB
CLKIN
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active
"X"
tXZD
DOUT
(Diff.)
active
Driver OFF, VOD = 0V
Figure 8. Serializer Disable Time
DIN[23:0],
CI1,CI2,CI3
SYMBOL N
SYMBOL N+1
tSD
CLKIN
(RFB = L)
START
BIT
STOP START
BIT BIT
STOP
BIT
DOUT
(Diff.)
SYMBOL N-1
SYMBOL N
Figure 9. Serializer Latency Delay
tDJIT
tDJIT
VOD (+)
DOUT
(Diff.)
TxOUT_E_O
0V
VOD (-)
tBIT (1 UI)
Figure 10. Serializer Output Jitter
VDDIO
CLKIN/
CLKOUT
w/ RFB = L
GND
VDDIO
DI/DO (odd),
CI2/CO2, CI3/CO3
GND
VDDIO
DI/DO (even),
CI1/CO1
GND
Figure 11. Checkerboard Data Pattern
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VDDIO
80%
20%
GND
tCLH
tCHL
Figure 12. Deserializer LVCMOS Transition Times
START
BIT
STOP START
BIT BIT
STOP
BIT
RIN
(Diff.)
SYMBOL N
SYMBOL N+1
tDD
CLKOUT
(RFB = L)
DO[23:0],
CO1,CO2,CO3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 13. Deserializer Delay – Latency
1/2 VDDIO
PDB
RIN
(Diff.)
active
"X"
tXZR
CLKOUT,
DO[23:0],
CO1,CO2,CO3
PASS, LOCK
active
Z (TRI-STATE)
Figure 14. Deserializer Disable Time (OSS_SEL = 0)
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PDB
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2.0V
0.8V
RIN
(Diff.)
'RQ¶W &DUH
tDDLT
LOCK
TRI-STATE
or LOW
Z or L
tRxZ
DO[23:0],
CO1,CO2,CO3
TRI-STATE or LOW or Pulled Up
CLKOUT
(RFB = L)
Z or L or PU
TRI-STATE or LOW
OFF
IN LOCK TIME
Z or L
ACTIVE
OFF
Figure 15. Deserializer PLL Lock Times and PDB TRI-STATE Delay
VDDIO
CLKOUT
w/ RFB = H
1/2 VDDIO
GND
DO[23:0],
CO1,CO2,CO3
VDDIO
1/2 VDDIO
1/2 VDDIO
GND
tROS
tROH
Figure 16. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = Off
VDDIO
CLKOUT
w/ RFB = H
1/2 VDDIO
GND
DO[23:0],
CO1,CO2,CO3
1/2 VDDIO
1/2 VDDIO
tROS
tROH
VDDIO
GND
Figure 17. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = On
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Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
RxIN_TOL
Left
VTH
0V
VTL
RxIN_TOL
Right
Ideal Center Position (tBIT/2)
tBIT (1 UI)
tRJIT
= RxIN_TOL (Left + Right)
- tRJIT
Sampling Window = 1 UI
Figure 18. Receiver Input Jitter Tolerance
BISTEN
1/2 VDDIO
tPASS
PASS
(w/ errors)
1/2 VDDIO
Current BIST Test - Toggle on Error
Prior BIST Result
Result Held
Figure 19. BIST PASS Waveform
SDA
tLOW
tf
tHD;STA
tr
tf
tr
tBUF
tSP
SCL
tSU;STA
tHD;STA
tHIGH
tHD;DAT
START
tSU;STO
tSU;DAT
STOP
REPEATED
START
START
Figure 20. Serial Control Bus Timing Diagram
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FUNCTIONAL DESCRIPTION
The DS92LV2421 / DS92LV2422 chipset transmits and receives 24-bits of data and 3 control signals over a
single serial CML pair operating at 280 Mbps to 2.1 Gbps. The serial stream also contains an embedded clock,
video control signals and the DC-balance information which enhances signal quality and supports AC coupling.
The Des can attain lock to a data stream without the use of a separate reference clock source, which greatly
simplifies system complexity and overall cost. The Des also synchronizes to the Ser regardless of the data
pattern, delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without
the need of special training patterns or sync characters. The Des recovers the clock and data by extracting the
embedded clock information, validating and then deserializing the incoming data stream providing a parallel
LVCMOS video bus to the display or ASIC/FPGA.
The DS92LV2421 / DS92LV2422 chipset can operate in 24-bit color depth (with DE, HS, VS encoded within the
serial data stream). In 18–bit color applications, the three video control signals maybe sent encoded within the
serial bit stream (restrictions apply) along with six additional general purpose signals.
Block Diagrams for the chipset are shown at the beginning of this datasheet.
Data Transfer
The DS92LV2421 / DS92LV2422 chipset will transmit and receive a pixel of data in the following format: C1 and
C0 represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW. The
remaining 26 bit spaces contain the scrambled, encoded and DC-Balanced serial data.
SER & DES OPERATING MODES AND REVERSE COMPATIBILITY (CONFIG[1:0])
The DS92LV2421 / DS92LV2422 chipset is compatible with other single serial lane Channel Link II or FPD-Link II
devices. Configuration modes are provided for reverse compatibility with the DS90C241 / DS90C124 and also
the DS90UR241 / DS90UR124 by setting the respective mode with the CONFIG[1:0] pins on the Ser or Des as
shown in Table and Table. This selection also determines whether the Control Signal Filter feature is enabled or
disabled in the Normal mode. These configuration modes are selectable the control pins only.
Table 1. DS92LV2421 Ser Modes
CONFIG1 CONFIG0 MODE
DES DEVICE
L
L
Normal Mode, Control Signal Filter disabled
DS92LV2422, DS92LV2412,
DS92LV0422, DS92LV0412
L
H
Normal Mode, Control Signal Filter enabled
DS92LV2422, DS92LV2412,
DS92LV0422, DS92LV0412
H
L
Reverse Compatibility Mode
DS90UR124, DS99R124
H
H
Reverse Compatibility Mode
DS90C124
Table 2. DS92LV2422 Des Modes
CONFIG1 CONFIG0 MODE
SER DEVICE
L
L
Normal Mode, Control Signal Filter disabled
DS92LV2421, DS92LV2411,
DS92LV0421, DS92LV0411
L
H
Normal Mode, Control Signal Filter enabled
DS92LV2421, DS92LV2411,
DS92LV0421, DS92LV0411
H
L
Reverse Compatibility Mode
DS90UR241, DS99R421
H
H
Reverse Compatibility Mode
DS90C241
VIDEO CONTROL SIGNAL FILTER — SER & DES
When operating the devices in Normal Mode, the Control Signals have the following restrictions:
• Normal Mode with Control Signal Filter Enabled: Control Signal 1 and Control Signal 2 — Only 2 transitions
per 130 clock cycles are transmitted, the transition pulse must be 3 parallel clocks or longer.
• Normal Mode with Control Signal Filter Disabled: Control Signal 1 and Control Signal 2 — Only 2 transitions
per 130 clock cycles are transmitted, no restriction on minimum transition pulse.
• Control Signal 3 — Only 1 transition per 130 clock cycles is transmitted , minimum pulse width is 130 clock
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cycles.
Control Signals are defined as low frequency signals with limited transition. Glitches of a control signal can cause
a visual error in display applications. This feature allows for the chipset to validate and filter out any high
frequency noise on the control signals. See Figure.
SERIALIZER Functional Description
The Ser converts a wide parallel input bus to a single serial output data stream, and also acts as a signal
generator for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins or
through the optional serial control bus. The Ser features enhance signal quality on the link by supporting: a
selectable VOD level, a selectable de-emphasis signal conditioning and also the Channel Link II data coding that
provides randomization, scrambling, and DC Balanacing of the data. The Ser includes multiple features to reduce
EMI associated with display data transmission. This includes the randomization and scrambling of the data and
also the system spread spectrum clock support. The Ser features power saving features with a sleep mode, auto
stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility.
See also the Functional Description of the chipset's serial control bus and BIST modes.
EMI Reduction Features
Data Randomization & Scrambling
Channel Link II Ser / Des feature a 3 step encoding process which enables the use of AC coupled interconnects
and also helps to manage EMI. The serializer first passes the parallel data through a scrambler which
randomizes the data. The randomized data is then DC balanced. The DC balanced and randomized data then
goes through a bit shuffling circuit and is transmitted out on the serial line. This encoding process helps to
prevent static data patterns on the serial stream. The resulting frequency content of the serial stream ranges
from the parallel clock frequency to the nyquist rate. For example, if the Ser / Des chip set is operating at a
parallel clock frequency of 75 MHz, the resulting frequency content of serial stream ranges from 75 MHz to 1.05
GHz ( 75 MHz *28 bits = 2.1 Gbps / 2 = 1.05 GHz ).
Ser — Spread Spectrum Compatibility
The Ser CLKIN is capable of tracking spread spectrum clocking (SSC) from a host source. The CLKIN will
accept spread spectrum tracking up to 35 kHz modulation and ±0.5, ±1 or ±2% deviations (center spread). The
maximum conditions for the CLKIN input are: a modulation frequency of 35 kHz and amplitude deviations of ±2%
(4% total).
Integrated Signal Conditioning Features — Ser
Ser — VOD Select (VODSEL)
The Ser differential output voltage may be increased by setting the VODSEL pin High. When VODSEL is Low,
the VOD is at the standard (default) level. When VODSEL is High, the VOD is increased in level. The increased
VOD is useful in extremely high noise environments and also on extra long cable length applications. When
using de-emphasis it is recommended to set VODSEL = H to avoid excessive signal attenuation especially with
the larger de-emphasis settings. This feature may be controlled by the external pin or by register.
Table 3. Differential Output Voltage
Input
Effect
VODSEL
VOD
mV
VOD
mVp-p
H
±420
840
L
±280
560
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Ser — De-Emphasis (De-Emph)
The De-Emph pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the
Ser drives. This is useful to counteract loading effects of long or lossy cables. This pin should be left open for
standard switching currents (no de-emphasis) or if controlled by register. De-emphasis is selected by connecting
a resistor on this pin to ground, with R value between 0.5 kΩ to 1 MΩ, or by register setting. When using DeEmphasis it is recommended to set VODSEL = H.
Table 4. De-Emphasis Resistor Value
Resistor Value (kΩ)
De-Emphasis Setting
Open
Disabled
0.6
- 12 dB
1.0
- 9 dB
2.0
- 6 dB
5.0
- 3 dB
0.00
VDD = 1.8V,
-2.00
TA = 25oC
DE-EMPH (dB)
-4.00
-6.00
-8.00
-10.00
-12.00
-14.00
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
R VALUE - LOG SCALE (:)
Figure 21. De-Emph vs. R value
Power Saving Features
Ser — Power Down Feature (PDB)
The Ser has a PDB input pin to ENABLE or POWER DOWN the device. This pin is controlled by the host and is
used to save power, disabling the link when the it is not needed. In the POWER DOWN mode, the high-speed
driver outputs are both pulled to VDD and present a 0V VOD state. Note – in POWER DOWN, the optional Serial
Bus Control Registers are RESET.
Ser — Stop Clock Feature
The Ser will enter a low power SLEEP state when the CLKIN is stopped. A STOP condition is detected when the
input clock frequency is less than 3 MHz. The clock should be held at a static Low or high state. When the
CLKIN starts again, the Ser will then lock to the valid input clock and then transmits the serial data to the Des.
Note – in STOP CLOCK SLEEP, the optional Serial Bus Control Registers values are RETAINED.
1.8V or 3.3V VDDIO Operation
The Ser parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (VDDIO) for host compatibility.
The 1.8 V levels will offer lower noise (EMI) and also a system power savings.
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Ser — Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is latched on. If RFB is High, input data is latched on the Rising
edge of the CLKIN. If RFB is Low, input data is latched on the Falling edge of the CLKIN. Ser and Des maybe
set differently. This feature may be controlled by the external pin or by register.
Optional Serial Bus Control
Please see the following section on the optional Serial Bus Control Interface.
Optional BIST Mode
Please see the following section on the chipset BIST mode for details.
DESERIALIZER Functional Description
The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal
check for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins and strap
pins or through the optional serial control bus. The Des features enhance signal quality on the link with an
integrated equalizer on the serial input and Channel Link II data encoding which provides randomization,
scrambling, and DC balanacing of the data. The Des includes multiple features to reduce EMI associated with
data transmission. This includes the randomization and scrambling of the data, the output spread spectrum clock
generation (SSCG) support and output clock and data slew rate select. The Des features power saving features
with a power down mode, and optional LVCMOS (1.8 V) interface compatibility.
Integrated Signal Conditioning Features — Des
Des — Input Equalizer Gain (EQ)
The Des can enable receiver input equalization of the serial stream to increase the eye opening to the Des input.
Note this function cannot be seen at the RxIN+/- input but can be observed at the serial test port (ROUT+/-)
enabled via the Serial Bus control registers. The equalization feature may be controlled by the external pin or by
register.
Table 5. Receiver Equalization Configuration Table
INPUTS
(1)
EQ3
EQ2
L
L
L
L
H
Effect
EQ1
EQ0
L
L
H
~1.5 dB
L
H
H
~3 dB
H
L
H
~4.5 dB
H
H
H
~6 dB
L
L
H
~7.5 dB
H
L
H
H
~9 dB
H
H
L
H
~10.5 dB
H
H
H
H
~12 dB
X
X
X
L
OFF (1)
Default Setting is EQ = Off
EMI Reduction Features
Des — Output Slew Rate Select (OS_CLKOUT/OS_DATA)
The parallel data outputs and clock outputs of the deserializer feature selectable output slew rates. The slew rate
of the CLKOUT pin is controlled by the strap pin or register OS_CLKOUT, while the data outputs (DO[23:0] and
CO[3:1]) are controlled by the strap pin or register OS_DATA. When OS_CLKOUT/DATA = HIGH, the maxium
slew rate is selected. When the OS_CLKOUT/DATA = LOW, the minimum slew rate is selected. Use the higher
slew rate when driving longer traces or a heavier capacitive load.
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Des — Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal termination. A capacitor may be placed on this pin for
additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 4.7 µF capacitor may be connected to this pin to Ground.
Des — SSCG Generation — Optional
The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and
data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2% (4% total) at up
to 100 kHz modulations is available. Note: The device supports SSCG function with CLK = 10 MHz to 65 MHz.
When the CLK = 65 MHz to 75 MHz, it is required to disable SSCG function (SSC[3:0] = 0000). See Table 6.
This feature may be controlled by external STRAP pins or by register.
Frequency
fdev(max)
FCLKOUT+
FCLKOUT
FCLKOUT-
fdev(min)
Time
1/fmod
Figure 22. SSCG Waveform
Table 6. SSCG Configuration (LF_MODE = L) — Des Output
SSC[3:0] Inputs
LF_MODE = L (20 - 65 MHz)
26
Result
SSC3
SSC2
SSC1
L
L
L
L
L
L
L
L
H
L
±1.0
L
L
H
H
±1.5
L
H
L
L
±2.0
L
H
L
H
±0.5
L
H
H
L
±1.0
L
H
H
H
±1.5
H
L
L
L
±2.0
H
L
L
H
±0.5
H
L
H
L
±1.0
H
L
H
H
±1.5
H
H
L
L
±2.0
H
H
L
H
±0.5
H
H
H
L
±1.0
H
H
H
H
±1.5
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SSC0
fdev (%)
fmod (kHz)
L
NA
Disable
H
±0.5
CLK/2168
CLK/1300
CLK/868
CLK/650
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Table 7. SSCG Configuration (LF_MODE = H) — Des Output
SSC[3:0] Inputs
LH_MODE = H (10 - 20 MHz)
Result
SSC3
SSC2
SSC1
SSC0
fdev (%)
fmod (kHz)
L
L
L
L
L
L
L
NA
Disable
H
±0.5
L
L
H
L
±1.0
L
L
H
H
±1.5
L
H
L
L
±2.0
L
H
L
H
±0.5
L
H
H
L
±1.0
L
H
H
H
±1.5
H
L
L
L
±2.0
H
L
L
H
±0.5
H
L
H
L
±1.0
H
L
H
H
±1.5
H
H
L
L
±2.0
H
H
L
H
±0.5
H
H
H
L
±1.0
H
H
H
H
±1.5
CLK/620
CLK/370
CLK/258
CLK/192
1.8V or 3.3V VDDIO Operation
The Des parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (VDDIO) for target (Display)
compatibility. The 1.8 V levels will offer a lower noise (EMI) and also a system power savings.
Power Saving Features
Des — PowerDown Feature (PDB)
The Des has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the
system to save power, disabling the Des when the display is not needed. An auto detect mode is also available.
In this mode, the PDB pin is tied High and the Des will enter POWER DOWN when the serial stream stops.
When the serial stream starts up again, the Des will lock to the input stream and assert the LOCK pin and output
valid data. In POWER DOWN mode, the Data and CLKOUT output states are determined by the OSS_SEL
status. Note – in POWER DOWN, the optional Serial Bus Control Registers are RESET.
Des — Stop Stream SLEEP Feature
The Des will enter a low power SLEEP state when the input serial stream is stopped. A STOP condition is
detected when the embedded clock bits are not present. When the serial stream starts again, the Des will then
lock to the incoming signal and recover the data. Note – in STOP STREAM SLEEP, the optional Serial Bus
Control Registers values are RETAINED.
Des — CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK goes from TRI-STATE to
LOW (depending on the value of the OSS_SEL setting). After the DS92LV2422 completes its lock sequence to
the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial
input is available on the parallel bus and clock outputs. The CLKOUT output is held at its current state at the
change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered clock (or vice versa).
If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the outputs are based
on the OSS_SEL setting (STRAP PIN configuration or register).
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Des — Oscillator Output — Optional
The Des provides an optional clock output when the input clock (serial stream) has been lost. This is based on
an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled by the
external pin or by register. See Table 9 and Table 10.
Table 8. OSS_SEL and PDB Configuration — Des Outputs
INPUTS
OUTPUTS
Serial
Input
PDB
OSS_SEL
CLKOUT
DO[23:0],
CO1, CO2,
CO3
LOCK
PASS
X
L
L
Z
Z
Z
Z
X
L
H
L
L
L
H
Static
H
L
Z
Z
L
H
Static
H
H
L
L
L
H
Active
H
X
Active
Active
H
H
Table 9. OSC (Oscillator) Mode — Des Output
INPUTS
OUTPUTS
Embedded CLK
CLKOUT
DO[23:0]/CO1/CO2
/CO3
LOCK
PASS
See (1)
OSC
Output
L
L
H
Present
Toggling
Active
H
H
(1)
Absent and OSC_SEL ≠ 000
PDB
(DES)
RIN
(Diff.)
LOCK
active serial stream
X
H
Z
L
H
L
Z
DO[23:0],
CO1,CO2,CO3
Z
Z
Z
CLKOUT*
(DES)
Z
Z
Z
PASS
H
Z
OFF
Z
Locking
Active
C0 or C1 Error
In Bit Stream
(Loss of LOCK)
Active
OFF
CONDITIONS: * RFB = L, and OSS_SEL = L
Figure 23. Des Outputs with Output State Select Low (OSS_SEL = L)
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PDB
(DES)
RIN
(Diff.)
active serial stream
X
H
LOCK
H
L
L
L
DO[23:0],
CO1,CO2,CO3
L
L
L
CLKOUT*
(DES)
L
L
L
PASS
H
Locking
OFF
C0 or C1 Error
In Bit Stream
(Loss of LOCK)
Active
Active
OFF
CONDITIONS: * RFB = L, and OSS_SEL = H
Figure 24. Des Outputs with Output State Select High (OSS_SEL = H)
Table 10. OSC_SEL (Oscillator) Configuration
OSC_SEL[2:0] INPUTS
CLKOUT Oscillator Frequency
OSC_SEL2
OSC_SEL1
OSC_SEL0
L
L
L
Off – Feature Disabled – Default
L
L
H
50 MHz ±40%
L
H
L
25 MHz ±40%
L
H
H
16.7 MHz ±40%
H
L
L
12.5 MHz ±40%
H
L
H
10 MHz ±40%
H
H
L
8.3 MHz ±40%
H
H
H
6.3 MHz ±40%
PDB
(DES)
RIN
(Diff.)
LOCK
active serial stream
X
H
H
L
L
L
DO[23:0],
CO1,CO2,CO3
L
L
L
CLKOUT*
(DES)
L
PASS
H
OFF
f
f
Locking
Active
C0 or C1 Error
In Bit Stream
(Loss of LOCK)
L
Active
OFF
CONDITIONS: * RFB = L, OSS_SEL = H , and OSC_SEL not equal to 000.
Figure 25. Des Outputs with Output State High and CLK Output Oscillator Option Enabled
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Des — OP_LOW — Optional
The OP_LOW feature is used to hold the LVCMOS outputs, except for the LOCK output, at a LOW state. When
the OP_LOW feature is enabled, the LVCMOS outputs will be held at logic LOW while LOCK = LOW. The user
must toggle the OP_LOW Set/Reset register bit to release the outputs to the normal toggling state. Note that the
release of the outputs can only occur when LOCK is HIGH. The OP_LOW strap option is assigned to the PASS
pin, at pin location 42.
Restrictions on other straps:
1. Other strap options should not be used in order to keep the data and clock outputs at a true logic LOW state.
Other features should be selected through the I2C register interface.
2. The OSS_SEL feature is not available when OP_LOW is enabled.
Outputs DO[23:0], CO[3:1] and CLKOUT are in TRI-STATE before PDB toggles HIGH because the OP-LOW
strap value has not been recognized until the DS92LV2422 powers up. Figure 26 shows the user controlled
release of the OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 27 shows the
user controlled release of OP_LOW and manual reset of OP_LOW set. Note manual reset of OP_LOW can only
occur when LOCK is HIGH.
PDB
2.0V
LOCK
OP_ LOW
SET
(Strap pin)
User
controlled
User
controlled
OP_ LOW
RELEASE/SET
(Register)
DO[23:0],
CO3, CO2, CO1
TRISTATE
ACTIVE
ACTIVE
CLKOUT
TRISTATE
ACTIVE
ACTIVE
Figure 26. OP_LOW Auto Set
30
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2.0V
PDB
LOCK
OP_LOW
SET
(Strap pin)
User
controlled
User
controlled
OP_ LOW
RELEASE/SET
(Register)
DO[23:0],
CO3, CO2, CO1
TRISTATE
ACTIVE
CLKOUT
TRISTATE
ACTIVE
Figure 27. OP_LOW Manual Set/Reset
Des — Clock Edge Select (RFB)
The RFB pin determines the edge that the data is strobed on. If RFB is High, output data is strobed on the Rising
edge of the CLKOUT. If RFB is Low, data is strobed on the Falling edge of the CLKOUT. This allows for interoperability with downstream devices. The Des output does not need to use the same edge as the Ser input. This
feature may be controlled by the external pin or by register.
Des — Control Signal Filter — Optional
The deserializer provides an optional Control Signal (C3, C2, C1) filter that monitors the three control signals and
eliminates any pulses or glitches that are 1 or 2 parallel clock periods wide. Control signals must be 3 parallel
clock periods wide (in its HIGH or LOW state, regardless of which state is active). This is set by the CONFIG[1:0]
strap option or by I2C register control.
Des — SSCG Low Frequency Optimization (LF_Mode)
Text to come. This feature may be controlled by the external pin or by Register.
Des — Strap Input Pins
Configuration of the device maybe done via configuration input pins and the STRAP input pins, or via the Serial
Control Bus. The STRAP input pins share select parallel bus output pins. They are used to load in configuration
values during the initial power up sequence of the device. Only a pull-up on the pin is required when a HIGH is
desired. By default the pad has an internal pull down, and will bias Low by itself. The recommended value of the
pull up is 10 kΩ to VDDIO; open (NC) for Low, no pull-down is required (internal pull-down). If using the Serial
Control Bus, no pull ups are required.
Optional Serial Bus Control
Please see the following section on the optional Serial Bus Control Interface.
Optional BIST Mode
Please see the following section on the chipset BIST mode for details.
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Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST
mode only a input clock is required along with control to the Ser and Des BISTEN input pins. The Ser outputs a
test pattern (PRBS7) and drives the link at speed. The Des detects the PRBS7 pattern and monitors it for errors.
A PASS output pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the
test, the result of the test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS
indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration
of the test is controlled by the pulse width applied to the Des BISTEN pin.
Inter-operability is supported between this Channel Link II device and all Channel Link II generations (Gen
1/2/3) — see respective datasheets for details on entering BIST mode and control.
Sample BIST Sequence
See Figure 28 for the BIST mode flow diagram.
Step 1: Place the DS92LV2421 Ser in BIST Mode by setting Ser BISTEN = H. For the DS92LV2421 Ser or
DS99R421 Channel Link II Ser BIST Mode is enabled via the BISTEN pin. A CLKIN is required for BIST. When
the Des detects the BIST mode pattern and command (DCA and DCB code) the data and control signal outputs
are shut off.
Step 2: Place the DS92LV2422 Des in BIST mode by setting the BISTEN = H. The Des is now in the BIST mode
and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS pin
will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and
counted to determine the payload error rate.
Step 3: To Stop the BIST mode, the Des BISTEN pin is set Low. The Des stops checking the data and the final
test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there was one or
more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the
device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal.
Step 4: To return the link to normal operation, the Ser BISTEN input is set Low. The Link returns to normal
operation. Figure 29 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and
Case 2 shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the
link (differential data transmission etc.), thus they may be introduced by greatly extending the cable length,
faulting the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or Rx Equalization).
Normal
Step 1: SER in BIST
BIST
Wait
Step 2: Wait, DES in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: SER in Normal
Figure 28. BIST Mode Flow Diagram
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BER Calculations
It
•
•
•
is possible to calculate the approximate Bit Error Rate (BER). The following is required:
Clock Frequency (MHz)
BIST Duration (seconds)
BIST test Result (PASS)
The BER is less than or equal to one over the product of 24 times the CLK rate times the test duration. If we
assume a 65 MHz clock, a 10 minute (600 second) test, and a PASS, the BERT is ≤ 1.07 X 10E-12
The BIST mode runs a check on the data payload bits. The LOCK pin also provides a link status. It the recovery
of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK pin will switch Low. The
combination of the LOCK and At-Speed BIST PASS pin provides a powerful tool for system evaluation and
performance monitoring.
SER
BISTEN
(SER)
DES Outputs
BISTEN
(DES)
Case 1 - Pass
CLKOUT
(RFB = L)
DO[23:0]
CO1,CO2,CO3
DATA
(internal)
PASS
Prior Result
PASS
PASS
X
X
X
FAIL
Prior Result
Normal
Case 2 - Fail
X = bit error(s)
DATA
(internal)
PRBS
BIST Test
BIST Duration
BIST
Result
Held
Normal
Figure 29. BIST Waveforms
Optional Serial Bus Control
The Ser and Des may also be configured by the use of a serial control bus that is I2C protocol compatible. By
default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write of 01'h to
reg_0x00'h will enable/allow configuration by registers; this will override the control/strap pins. Multiple devices
may share the serial control bus since multiple addresses are supported. See Figure 30.
The serial bus is comprised of three pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data
Input / Output signal. Both SCL and SDA signals require an external pull up resistor to VDDIO. For most
applications a 4.7 k pull up resistor to VDDIO may be used. The resistor value may be adjusted for capacitive
loading and data rate requirements. The signals are either pulled High, or driven Low.
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1.8V
10 k
VDDIO
ID[X]
4.7k
HOST
4.7k
RID
SCL
SCL
SDA
SDA
SER
or
DES
To other
Devices
Figure 30. Serial Control Bus Connection
The third pin is the ID[X] pin. This pin sets one of five possible device addresses. Three different connections are
possible. The pin may be tied to ground. The pin may be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor.
Or a 10 kΩ pull up resistor (to VDD1.8V, NOT VDDIO)) and a pull down resistor of the recommended value to set
other three possible addresses may be used. See Table 11 for the Ser and Table 12 for the Des.
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See
Figure 31
SDA
SCL
S
P
START condition, or
START repeat condition
STOP condition
Figure 31. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 32 and a WRITE is shown in Figure 33.
If the Serial Bus is not required, the three pins may be left open (NC).
Table 11. ID[x] Resistor Value – DS92LV2421 Ser
34
Resistor
RID kΩ
Address
7'b
Address
8'b
0 appended
(WRITE)
0.47
7b' 110 1001 (h'69)
8b' 1101 0010 (h'D2)
2.7
7b' 110 1010 (h'6A)
8b' 1101 0100 (h'D4)
8.2
7b' 110 1011 (h'6B)
8b' 1101 0110 (h'D6)
Open
7b' 110 1110 (h'6E)
8b' 1101 1100 (h'DC)
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Table 12. ID[x] Resistor Value – DS92LV2422 Des
Resistor
RID kΩ
Address
7'b
Address
8'b
0 appended
(WRITE)
0.47
7b' 111 0001 (h'71)
8b' 1110 0010 (h'E2)
2.7
7b' 111 0010 (h'72)
8b' 1110 0100 (h'E4)
8.2
7b' 111 0011 (h'73)
8b' 1110 0110 (h'E6)
Open
7b' 111 0110 (h'76)
8b' 1110 1100 (h'EC)
Register Address
Slave Address
S
A
2
A
1
A
0
0
Slave Address
a
c
k
a
c
k
A
2
S
A
1
A
0
Data
1
a
c
k
a
c
k
P
Figure 32. Serial Control Bus — READ
Register Address
Slave Address
A
2
S
A
1
A
0
0
Data
a
c
k
a
c
k
a
c
k
P
Figure 33. Serial Control Bus — WRITE
Table 13. SERIALIZER — Serial Bus Control Registers
ADD ADD Register
(dec) (hex) Name
0
1
0
1
Ser Config 1
Device ID
Bit(s)
R/W
Default
(bin)
Function
Description
7
R/W
0
Reserved
Reserved
6
R/W
0
Reserved
Reserved
5
R/W
0
RFB
0: Data latched on Falling edge of CLKIN
1: Data latched on Rising edge of CLKIN
4
R/W
0
VODSEL
0: Low
1: High
3:2
R/W
00
CONFIG
00:
01:
10:
11:
1
R/W
0
SLEEP
Note – not the same function as PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0
R/W
0
REG
0: Configurations set from control pins
1: Configuration set from registers (except I2C_ID)
7
R/W
0
REG ID
0: Address from ID[X] Pin
1: Address from Register
6:0
R/W
1101000 ID[X]
Control Signal Filter Disabled
Control Signal Filter Enabled
Reserved
Reserved
Serial Bus Device ID, Four IDs are:
7b '1101 001 (h'69)
7b '1101 010 (h'6A)
7b '1101 011 (h'6B)
7b '1101 110 (h'6E)
All other addresses are Reserved.
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Table 13. SERIALIZER — Serial Bus Control Registers (continued)
ADD ADD Register
(dec) (hex) Name
2
2
De-Emphasis
Control
Bit(s)
R/W
Default
(bin)
Function
Description
7:5
R/W
000
De-E Setting
000:
001:
010:
011:
100:
101:
110:
111:
4
R/W
0
De-E EN
0: De-Emphasis Enabled
1: De-Emphasis Disabled
3:0
R/W
000
Reserved
Reserved
set by external Resistor
-1 dB
-2 dB
-3.3 dB
-5 dB
-6.7 dB
-9 dB
-12 dB
Table 14. DESERIALIZER — Serial Bus Control Registers
ADD ADD Register Name
(dec) (hex)
0
1
36
0
1
Des Config 1
Slave ID
Bit(s)
R/W
7
R/W
0
LF_MODE
0: 20 to 65 MHz SSCG Operation
1: 10 to 20 MHz SSCG Operation
6
R/W
0
OS_CLKOUT
0: Normal CLKOUT Slew Rate
1: Increased CLKOUT Slew Rate
5
R/W
0
OS_DATA
0: Normal DATA Slew Rate
1: Increased DATA Slew Rate
4
R/W
0
RFB
0: Data strobed on Falling edge of CLKOUT
1: Data strobed on Rising edge of CLKOUT
3:2
R/W
00
CONFIG
00:
01:
10:
11:
1
R/W
0
SLEEP
Note – not the same function as PowerDown (PDB)
0: Normal Mode
1: Sleep Mode – Register settings retained.
0
R/W
0
REG Control
0: Configurations set from control pins / STRAP pins
1: Configurations set from registers (except I2C_ID)
7
R/W
0
6:0
R/W
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Defau Function
lt
(bin)
11100 ID[X]
00
Description
Normal Mode, Control Signal Filter Disabled
Normal Mode, Control Signal Filter Enabled
Reserved
Reserved
0: Address from ID[X] Pin
1: Address from Register
Serial Bus Device ID, Four IDs are:
7b '1110 001 (h'71)
7b '1110 010 (h'72)
7b '1110 011 (h'73)
7b '1110 110 (h'76)
All other addresses are Reserved.
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Table 14. DESERIALIZER — Serial Bus Control Registers (continued)
ADD ADD Register Name
(dec) (hex)
2
3
2
3
Des Features 1
Des Features 2
Bit(s)
R/W
Defau Function
lt
(bin)
Description
7
R/W
0
OP_LOW
0: Set outputs state LOW (except LOCK)
1: Release output LOW state, outputs toggling normally
Note: This register only workds during LOCK = 1
6
R/W
0
OSS_SEL
Output Sleep State Select
0: CLKOUT, DO[23:0], CO1, CO2, CO3 = Tri-State, LOCK
= Normal, PASS = H
1: CLKOUT, DO[23:0], CO1, CO2, CO3 = L, LOCK =
Normal, PASS = H
5:4
R/W
00
Reserved
Reserved
3
R/W
0
OP_LOW Strap
Bypass
0: Strap will determine whether OP_LOW feature is ON or
OFF
1: Turns OFF OP_LOW feature
2:0
R/W
00
OSC_SEL
000:
001:
010:
011:
100:
101:
110:
111:
disable
50 MHz ±40%
25 MHz ±40%
16.7 MHz ±40%
12.5 MHz ±40%
10 MHz ±40%
8.3 MHz ±40%
6.3 MHz ±40%
7:5
R/W
000
EQ Gain
000:
001:
010:
011:
100:
101:
110:
111:
~1.625 dB
~3.25 dB
~4.87 dB
~6.5 dB
~8.125 dB
~9.75 dB
~11.375 dB
~13 dB
4
R/W
0
EQ Enable
0: EQ = disable
1: EQ = enable
3:0
R/W
0000
SSC
IF LF_MODE = 0, then:
000: SSCG disable
0001: fdev = ±0.5%, fmod = CLK/2168
0010: fdev = ±1.0%, fmod = CLK/2168
0011: fdev = ±1.5%, fmod = CLK/2168
0100: fdev = ±2.0%, fmod = CLK/2168
0101: fdev = ±0.5%, fmod = CLK/1300
0110: fdev = ±1.0%, fmod = CLK/1300
0111: fdev = ±1.5%, fmod = CLK/1300
1000: fdev = ±2.0%, fmod = CLK/1300
1001: fdev = ±0.5%, fmod = CLK/868
1010: fdev = ±1.0%, fmod = CLK/868
1011: fdev = ±1.5%, fmod = CLK/868
1100: fdev = ±2.0%, fmod = CLK/868
1101: fdev = ±0.5%, fmod = CLK/650
1110: fdev = ±1.0%, fmod = CLK/650
1111: fdev = ±1.5%, fmod = CLK/650
IF LF_MODE = 1, then:
000: SSCG disable
0001: fdev = ±0.5%, fmod = CLK/620
0010: fdev = ±1.0%, fmod = CLK/620
0011: fdev = ±1.5%, fmod = CLK/620
0100: fdev = ±2.0%, fmod = CLK/620
0101: fdev = ±0.5%, fmod = CLK/370
0110: fdev = ±1.0%, fmod = CLK/370
0111: fdev = ±1.5%, fmod = CLK/370
1000: fdev = ±2.0%, fmod = CLK/370
1001: fdev = ±0.5%, fmod = CLK/258
1010: fdev = ±1.0%, fmod = CLK/258
1011: fdev = ±1.5%, fmod = CLK/258
1100: fdev = ±2.0%, fmod = CLK/258
1101: fdev = ±0.5%, fmod = CLK/192
1110: fdev = ±1.0%, fmod = CLK/192
1111: fdev = ±1.5%, fmod = CLK/192
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Table 14. DESERIALIZER — Serial Bus Control Registers (continued)
ADD ADD Register Name
(dec) (hex)
4
4
Bit(s)
R/W
7
R/W
6:0
R/W
ROUT Config
Defau Function
lt
(bin)
0
Repeater Enable
00000 Reserved
00
Description
0: Output ROUT+/- = disable
1: Output ROUT+/- = enable
Reserved
Applications Information
DISPLAY APPLICATION
The DS92LV2421/DS92LV2422 chipset is intended for interface between a host (graphics processor) and a
Display. It supports an 24-bit color depth (RGB888). In a RGB888 application, 24 color bits (D[23:0), Pixel Clock
(CLKIN) and three control bits (C1, C2, C3) are supported across the serial link with CLK rates from 10 to 75
MHz. The chipset may also be used in 18-bit color applications. In this application three to six general purpose
signals may also be sent from host to display.
The Des is expected to be located close to its target device. The interconnect between the Des and the target
device is typically in the 1 to 3 inch separation range. The input capacitance of the target device is expected to
be in the 5 to 10 pF range. Care should be taken on the CLK output trace as this signal is edge sensitive and
strobes the data. It is also assumed that the fanout of the Des is one. If additional loads need to be driven, a
logic buffer or mux device is recommended.
TYPICAL APPLICATION CONNECTION
Figure 34 shows a typical application of the DS92LV2421 Ser in Pin control mode for 24-bit Application. The
LVDS outputs require 100 nF AC coupling capacitors to the line. The line driver includes internal termination.
Bypass capacitors are placed near the power supply pins. At a minimum, four 0.1 µF capacitors and a 4.7 µF
capacitor should be used for local device bypassing. System GPO (General Purpose Output) signals control the
PDB and BISTEN pins. In this application the RFB pin is tied Low to latch data on the falling edge of the CLKIN.
In this example the cable is long, therefore the VODSEL pin is tied High and a De-Emphasis value is selected by
the resistor R1. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO pin is connected also to
the 1.8V rail. The optional Serial Bus control is not used in this example, thus the SCL, SDA and ID[x] pins are
left open. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
38
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DS92LV2421 (SER)
VDDIO
VDDIO
C9
C7
FB1
C3
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DI9
DI10
DI11
DI12
DI13
DI14
DI15
LVCMOS
Parallel
Video
Interface
VDDTX
VDDHS
CI1
CI2
CI3
LVCMOS
Control
Interface
BISTEN
PDB
C12
CONFIG1
CONFIG0
RFB
C4
FB2
C5
FB3
C6
FB4
C8
C10
VDDP
C11
VDDL
C1
Serial
Channel Link II
Interface
DOUT+
DOUTC2
DI16
DI17
DI18
DI19
DI20
DI21
DI22
DI23
CLKIN
1.8V
VDDIO
VODSEL
De-Emph
1.8V
R1
10k
ID[X]
SCL
SDA
RES2
RES1
RES0
DAP (GND)
RID
NOTE:
C1-C2 = 0.1 PF (50 WV)
C3-C8 = 0.1 PF
C9-11 = 4.7 PF
C12 = >10 PF
R1 (cable specific)
RID (see ID[x] Resistor Value Table 12)
FB1-FB4: Impedance = 1 k:,
low DC resistance (<1:)
Figure 34. DS92LV2421 Typical Connection Diagram — Pin Control
Figure 35 shows a typical application of the DS92LV2422 Des in Pin/STRAP control mode 24-bit Application.
The LVDS inputs utilize 100 nF coupling capacitors to the line and the receiver provides internal termination.
Bypass capacitors are placed near the power supply pins. At a minimum, seven 0.1 µF capacitors and two 4.7
µF capacitors should be used for local device bypassing. System GPO (General Purpose Output) signals control
the PDB and the BISTEN pins. In this application the RFB pin is tied Low to strobe the data on the falling edge of
the CLKOUT.
Since the device in the Pin/STRAP mode, four 10 kΩ pull up resistors are used on the parallel output bus to
select the desired device features. CFEN is set to 1 for Normal Mode with Control Signal Filter enabled, this is
accomplished with the STRAP pull-up on DO23. The receiver input equalizer is also enabled and set to provide
7.5 dB of gain, this is accomplished with EQ[3:0] set to 1001'b with STRAP pull ups on DO12 and DO15. To
reduce parallel bus EMI, the SSCG feature is enabled and set to fmod = CLK/2168 and ±1% with SSC[3:0] set to
0010'b and a STRAP pull-up on DO4. The desired features are set with the use of the four pull up resistors.
The interface to the target display is with 3.3V LVCMOS levels, thus the VDDIO pin is connected to the 3.3 V rail.
The optional Serial Bus Control is not used in this example, thus the SCL, SDA and ID[x] pins are left open. A
delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV2421 DS92LV2422
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39
DS92LV2421, DS92LV2422
SNLS321B – MAY 2010 – REVISED APRIL 2013
www.ti.com
DS92LV2422 (DES)
1.8V
VDDL
C13
C11
VDDIO
VDDIO
C8
C3
VDDSC
C12
C14
VDDIO
C9
C4
VDDPR
VDDIO
C10
C5
VDDR
C15
C6
VDDIR
VDDIO
EXAMPLE:
STRAP
Input
Pull-Ups
(10k)
VDDCMLO
C16
C7
C1
Serial
Channel Link II
Interface
RIN+
RINCMF
C2
C17
TP_A
ROUT+
ROUT-
TP_B
Host
Control
BISTEN
PDB
C18
1.8V
10k
ID[X]
SCL
SDA
RID
C1 - C2 = 0.1 PF (50 WV)
C3 - C12 = 0.1 PF
C13, C16 = 4.7 PF
C17, C18 = >10 PF
RID (see ID[x] Resistor Value Table 13)
FB1-FB4: Impedance = 1 k:,
low DC resistance (<1:)
8
NC
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DO9
DO10
DO11
DO12
DO13
DO14
DO15
LVCMOS
Parallel
Video
Interface
DO16
DO17
DO18
DO19
DO20
DO21
DO22
DO23
CO1
CO2
CO3
CLKOUT
RES
DAP (GND)
LOCK
PASS
Figure 35. DS92LV2422 Typical Connection Diagram — Pin Control
POWER UP REQUIREMENTS AND PDB PIN
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to VDDIO, it is recommended to use a 10 kΩ pull-up and
a 22 uF cap to GND to delay the PDB input signal.
40
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Product Folder Links: DS92LV2421 DS92LV2422
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SNLS321B – MAY 2010 – REVISED APRIL 2013
TRANSMISSION MEDIA
The Ser/Des chipset is intended to be used in a point-to-point configuration, through a PCB trace, or through
twisted pair cable. The Ser and Des provide internal terminations providing a clean signaling environment. The
interconnect for LVDS should present a differential impedance of 100 Ohms. Use cables and connectors that
have matched differential impedance to minimize impedance discontinuities. Shielded or un-shielded cables may
be used depending upon the noise environment and application requirements.
LIVE LINK INSERTION
The Ser and Des devices support live pluggable applications. The automatic receiver lock to random data “plug &
go” hot insertion capability allows the DS92LV2422 to attain lock to the active data stream during a live insertion
event.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS Ser/Des devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
Information on the WQFN style package is provided in Texas Instruments Application Note: AN-1187(SNOA401).
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV2421 DS92LV2422
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41
DS92LV2421, DS92LV2422
SNLS321B – MAY 2010 – REVISED APRIL 2013
www.ti.com
LVDS INTERCONNECT GUIDELINES
See AN-1108(SNLA008) and AN-905(SNLA035) for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas
Instruments web site at: http://www.ti.com/ww/en/analog/interface/lvds.shtml
42
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Product Folder Links: DS92LV2421 DS92LV2422
DS92LV2421, DS92LV2422
www.ti.com
SNLS321B – MAY 2010 – REVISED APRIL 2013
REVISION HISTORY
Changes from Revision A (April 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 42
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV2421 DS92LV2422
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43
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
DS92LV2421SQ/NOPB
ACTIVE
WQFN
RHS
48
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LV2421SQ
DS92LV2421SQE/NOPB
ACTIVE
WQFN
RHS
48
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LV2421SQ
DS92LV2421SQX/NOPB
ACTIVE
WQFN
RHS
48
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LV2421SQ
DS92LV2422SQ/NOPB
ACTIVE
WQFN
NKB
60
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LV2422SQ
DS92LV2422SQE/NOPB
ACTIVE
WQFN
NKB
60
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LV2422SQ
DS92LV2422SQX/NOPB
ACTIVE
WQFN
NKB
60
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LV2422SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
DS92LV2421SQ/NOPB
WQFN
RHS
48
DS92LV2421SQE/NOPB
WQFN
RHS
DS92LV2421SQX/NOPB
WQFN
RHS
DS92LV2422SQ/NOPB
WQFN
DS92LV2422SQE/NOPB
DS92LV2422SQX/NOPB
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
48
250
178.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
48
2500
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
NKB
60
1000
330.0
16.4
9.3
9.3
1.3
12.0
16.0
Q1
WQFN
NKB
60
250
178.0
16.4
9.3
9.3
1.3
12.0
16.0
Q1
WQFN
NKB
60
2000
330.0
16.4
9.3
9.3
1.3
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS92LV2421SQ/NOPB
WQFN
RHS
48
1000
367.0
367.0
38.0
DS92LV2421SQE/NOPB
WQFN
RHS
48
250
213.0
191.0
55.0
DS92LV2421SQX/NOPB
WQFN
RHS
48
2500
367.0
367.0
38.0
DS92LV2422SQ/NOPB
WQFN
NKB
60
1000
367.0
367.0
38.0
DS92LV2422SQE/NOPB
WQFN
NKB
60
250
213.0
191.0
55.0
DS92LV2422SQX/NOPB
WQFN
NKB
60
2000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
RHS0048A
SQA48A (Rev B)
www.ti.com
MECHANICAL DATA
NKB0060B
SQA60B (Rev B)
www.ti.com
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