E PRELIMINARY BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 4, 8, AND 16 MBIT 28F004S3, 28F008S3, 28F016S3 Includes Commercial and Extended Temperature Specifications n n n n n SmartVoltage Technology Smart 3 Flash: 2.7 V or 3.3 V V CC and 2.7 V, 3.3 V or 12 V V PP High-Performance 120 ns Read Access Time Enhanced Data Protection Features Absolute Protection with V PP = GND Flexible Block Locking Block Write Lockout during Power Transitions Enhanced Automated Suspend Options Program Suspend to Read Block Erase Suspend to Program Block Erase Suspend to Read Industry-Standard Packaging 40-Lead TSOP, 44-Lead PSOP and 40 Bump µBGA* CSP n n n n n n High-Density 64-Kbyte Symmetrical Erase Block Architecture 4 Mbit: Eight Blocks 8 Mbit: Sixteen Blocks 16 Mbit: Thirty-Two Blocks Extended Cycling Capability 100,000 Block Erase Cycles Low Power Management Deep Power-Down Mode Automatic Power Savings Mode Decreases ICC in Static Mode Automated Program and Block Erase Command User Interface Status Register SRAM-Compatible Write Interface ETOX™ V Nonvolatile Flash Technology Intel’s byte-wide Smart 3 FlashFile™ memory family renders a variety of density offerings in the same package. The 4-, 8-, and 16-Mbit byte-wide FlashFile memories provide high-density, low-cost, nonvolatile, read/write storage solutions for a wide range of applications. Their symmetrically-blocked architecture, flexible voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs, and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the 4-, 8-, and 16-Mbit FlashFile memories offer three levels of protection: absolute protection with VPP at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They come in industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged 44-lead PSOP. Based on the 28F008SA architecture, the byte-wide Smart 3 FlashFile memory family enables quick and easy upgrades for designs that demand state-of-the-art technology. December 1997 Order Number: 290598-004 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F004S3, 28F008S3, 28F016S3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725 or visit Intel’s Website at http:\\www.intel.com COPYRIGHT © INTEL CORPORATION, 1997 *Third-party brands and names are the property of their respective owners. CG-041493 E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY CONTENTS PAGE 1.0 INTRODUCTION .............................................5 1.1 New Features...............................................5 1.2 Product Overview.........................................5 1.3 Pinout and Pin Description ...........................6 2.0 PRINCIPLES OF OPERATION .....................11 2.1 Data Protection ..........................................12 3.0 BUS OPERATION .........................................12 3.1 Read ..........................................................12 3.2 Output Disable ...........................................12 3.3 Standby......................................................12 3.4 Deep Power-Down .....................................12 3.5 Read Identifier Codes Operation ................13 3.6 Write ..........................................................13 4.0 COMMAND DEFINITIONS ............................13 4.1 Read Array Command................................16 4.2 Read Identifier Codes Command ...............16 4.3 Read Status Register Command................16 4.4 Clear Status Register Command................16 4.5 Block Erase Command ..............................16 4.6 Program Command....................................17 4.7 Block Erase Suspend Command................17 4.8 Program Suspend Command .....................18 4.9 Set Block and Master Lock-Bit Commands 18 4.10 Clear Block Lock-Bits Command..............19 PAGE 6.0 ELECTRICAL SPECIFICATIONS..................29 6.1 Absolute Maximum Ratings ........................29 6.2 Commercial Temperature Operating Conditions .................................................29 6.3 Capacitance ...............................................29 6.4 DC Characteristics— Commercial Temperature..............................................30 6.5 AC Characteristics—Read-Only Operations—Commercial Temperature .....34 6.6 AC Characteristics—Write Operations— Commercial Temperature..........................36 6.7 Block Erase, Program, and Lock-Bit Configuration Performance—Commercial Temperature..............................................38 6.8 Extended Temperature Operating Conditions .................................................39 6.9 DC Characteristics—Extended Temperature..............................................39 6.10 AC Characteristics—Read-Only Operations—Extended Temperature .........39 7.0 ORDERING INFORMATION..........................40 8.0 ADDITIONAL INFORMATION .......................40 5.0 DESIGN CONSIDERATIONS ........................27 5.1 Three-Line Output Control..........................27 5.2 RY/BY# Hardware Detection ......................27 5.3 Power Supply Decoupling ..........................27 5.4 VPP Trace on Printed Circuit Boards...........27 5.5 VCC, VPP, RP# Transitions .........................27 5.6 Power-Up/Down Protection ........................27 5.7 VPP Program and Erase Voltages on Sub0.4µ S3 Memory Family ............................28 PRELIMINARY 3 BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY E REVISION HISTORY Number 4 Description -001 Original version -002 Table 3 revised to reflect change in abbreviations from “W” for write to “P” for program. Ordering information graphic (Appendix A) corrected: from PB = Ext. Temp. 44-Lead PSOP to TB = Ext. Temp. 44-Lead PSOP Updated Ordering Information and table Correction to table, Section 6.2.3. Under ILO Test Conditions, previously read V IN = VCC or GND, corrected to VOUT = VCC or GND Section 6.2.7, modified Program and Block Erase Suspend Latency Times -003 Updated disclaimer -004 Added 2.7 V VPP specifications. Added µBGA* CSP pinouts and corrected error in PSOP pinout Added Design Consideration for VPP Program and Erase Voltages on future sub-0.4µ devices. PRELIMINARY E 1.0 BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY INTRODUCTION This datasheet contains 4-, 8-, and 16-Mbit Smart 3 FlashFile memory specifications. Section 1.0 provides a flash memory overview. Sections 2.0, 3.0, 4.0, and 5.0 describe the memory organization and functionality. Section 6.0 covers electrical specifications for commercial and extended temperature product offerings. Ordering information is provided in Section 7.0. Finally, the byte-wide Smart 3 FlashFile memory family documentation also includes application notes and design tools which are referenced in Section 8.0. 1.1 New Features The byte-wide Smart 3 FlashFile memory family maintains backwards-compatibility with Intel’s 28F008SA-L. Key enhancements include: • SmartVoltage Technology • Enhanced Suspend Capabilities • In-System Block Locking They share a compatible status register, software commands, and pinouts. These similarities enable a clean upgrade from the 28F008SA-L to byte-wide Smart 3 FlashFile products. When upgrading, it is important to note the following differences: • Because of new feature and density options, the devices have different device identifier codes. This allows for software optimization. • VPPLK has been lowered from 6.5 V to 1.5 V to support low VPP voltages during block erase, program, and lock-bit configuration operations. Designs that switch VPP off during read operations should transition VPP to GND. • To take advantage of SmartVoltage technology, allow VPP connection to 3.3 V. For more details see application note AP-625, 28F008SC Compatibility with 28F008SA (order number 292180). 1.2 Product Overview The byte-wide Smart 3 FlashFile memory family provides density upgrades with pinout compatibility for the 4-, 8-, and 16-Mbit densities. The 28F004S3, 28F008S3, and 28F016S3 are high-performance memories arranged as 512 Kbyte, 1 Mbyte, and 2 Mbyte of eight bits. This data is grouped in eight, sixteen, and thirty-two 64-Kbyte blocks which are individually erasable, lockable, and unlockable insystem. Figure 5 illustrates the memory organization. SmartVoltage technology enables fast factory programming and low power designs. Specifically designed for 3 V systems, Smart 3 FlashFile components support read operations at 2.7 V and 3.3 V VCC and block erase and program operations at 2.7 V, 3.3 V and 12 V VPP. The 12 V VPP option renders the fastest program performance which will increase your factory throughput. With the 2.7 V or 3.3 V VPP option, VCC and VPP can be tied together for a simple, low-power 2.7 V or 3 V design. In addition to the voltage flexibility, the dedicated VPP pin gives complete data protection when VPP ≤ VPPLK. Internal VPP detection circuitry automatically configures the device for optimized block erase and program operations. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device’s 64-Kbyte blocks typically within 1.1 second (12 V VPP), independent of other blocks. Each block can be independently erased 100,000 times (1.6 million block erases per device). A block erase suspend operation allows system software to suspend block erase to read data from or program data to any other block. Data is programmed in byte increments typically within 7.6 µs (12 V VPP). A program suspend operation permits system software to read data or execute code from any other flash memory array location. PRELIMINARY 5 E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY To protect programmed data, each block can be locked. This block locking mechanism uses a combination of bits, block lock-bits and a master lock-bit, to lock and unlock individual blocks. The block lock-bits gate block erase and program operations, while the master lock-bit gates block lock-bit configuration operations. Lock-bit configuration operations (Set Block Lock-Bit, Set Master Lock-Bit, and Clear Block Lock-Bits commands) set and clear lock-bits. The status register and RY/BY# output indicate whether or not the device is busy executing or ready for a new command. Polling the status register, system software retrieves WSM feedback. The RY/BY# output gives an additional indicator of WSM activity by providing a hardware status signal. Like the status register, RY/BY#-low indicates that the WSM is performing a block erase, program, or lock-bit configuration operation. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended, program is suspended, or the device is in deep power-down mode. The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical I CCR current is 3 mA. When CE# and RP# pins are at VCC, the component enters a CMOS standby mode. Driving RP# to GND enables a deep power-down mode which significantly reduces power consumption, provides write protection, resets the device, and clears the status register. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are recognized. 1.3 Pinout and Pin Description The family of devices is available in 40-lead TSOP (Thin Small Outline Package, 1.2 mm thick), 44lead PSOP (Plastic Small Outline Package) and 40bump µBGA* CSP (28F008S3 and 28F016S3 only). Pinouts are shown in Figures 2, 3 and 4. DQ 0 - DQ 7 Input Buffer Output Buffer Identifier Register I/O Logic VCC CE# Status Register WE# Command Register OE# RP# Data Comparator 4-Mbit: A0 - A18 , 8-Mbit: A0 - A19 , 16-Mbit: A0 - A 20 Input Buffer Y Decoder Address Latch X Decoder Y Gating 4-Mbit: Eight 8-Mbit: Sixteen 16-Mbit: Thirty-Two 64-Kbyte Blocks Write State Machine RY/BY# Program/Erase Voltage Switch VPP VCC GND Address Counter Figure 1. Block Diagram 6 PRELIMINARY E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY Table 1. Pin Descriptions Sym A0–A20 Type INPUT Name and Function ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. 4 Mbit → A0–A18 8 Mbit → A0–A19 16 Mbit → A0–A20 DQ0–DQ7 INPUT/ DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; OUTPUT outputs data during memory array, status register, and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and sense amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RP# INPUT RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations which provides data protection during power transitions, puts the device in deep power-down mode, and resets internal automation. RP#-high enables normal operation. Exit from deep power-down sets the device to read array mode. RP# at VHH enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. RP# = V HH overrides block lock-bits, thereby enabling block erase and program operations to locked memory blocks. Block erase, program, or lock-bit configuration with V IH < RP# < VHH produce spurious results and should not be attempted. OE# INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle. WE# INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse. RY/BY# OUTPUT READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is performing an internal operation (block erase, program, or lock-bit). RY/BY#-high indicates that the WSM is ready for new commands, block erase or program is suspended, or the device is in deep power-down mode. RY/BY# is always active. VPP SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY: For erasing array blocks, programming data, or configuring lock-bits. Smart 3 Flash → 2.7 V, 3.3 V and 12 V V PP With VPP ≤ VPPLK, memory contents cannot be altered. Block erase, program, and lock-bit configuration with an invalid VPP (see DC Characteristics) produce spurious results and should not be attempted. VCC SUPPLY DEVICE POWER SUPPLY: Internal detection automatically configures the device for optimized read performance. Do not float any power pins. Smart 3 Flash → 2.7 V and 3.3 V V CC With VCC ≤ VLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VCC voltages (see DC Characteristics) produce spurious results and should not be attempted. Block erase, program, and lock-bit configuration operations with VCC < 2.7 V are not supported. GND NC SUPPLY GROUND: Do not float any ground pins. NO CONNECT: Lead is not internally connected; it may be driven or floated. PRELIMINARY 7 E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 28F016S3 28F008S3 28F004S3 A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC VPP RP# A11 A10 A9 A8 A7 A6 A5 A4 A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC VPP RP# A11 A10 A9 A8 A7 A6 A5 A4 NC A18 A17 A16 A15 A14 A13 A12 CE# VCC VPP RP# A11 A10 A9 A8 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40-LEAD TSOP STANDARD PINOUT 10 mm x 20 mm TOP VIEW 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC NC WE# OE# RY/BY# NC NC WE# OE# RY/BY# A 20 NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ7 DQ6 DQ5 DQ7 DQ6 DQ5 DQ 4 VCC GND GND DQ 4 V CC GND GND DQ 4 VCC GND GND DQ3 DQ2 DQ1 DQ0 DQ3 DQ2 DQ1 DQ0 DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 A0 A1 A2 A3 A0 A1 A2 A3 Figure 2. TSOP 40-Lead Pinout 8 PRELIMINARY E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY Figure 3. PSOP 44-Lead Pinout PRELIMINARY 9 E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 8 7 6 5 4 3 2 1 A A7 A9 RP# VPP VCC A12 A15 A17 A6 A10 A11 CE# A13 A14 A16 A18 B C A4 A5 A3 A8 NC A19 RY/BY# A20 D A2 A0 D1 D3 GND D4 D6 WE# E A1 D0 D2 GND VCC D7 D5 OE# Bottom View - Bump Side Up Pin #1 Indicator 1 2 3 4 5 6 7 8 A17 A15 A12 VCC VPP RP# A9 A7 A18 A16 A14 A13 CE# A11 A10 A6 NC RY/BY# A19 NC A8 A3 A5 A4 A B C D WE# D6 D4 GND D3 D1 A0 A2 OE# D7 D5 VCC GND D2 D0 A1 E Top View - Bump Side Down This is the view of the package as surface mounted on the board. Note that the signals are mirror images of bottom view. NOTES: 1. Figures are not drawn to scale. 2. Address A20 is not included in the 28F008S3. 3. More information on µBGA* packages is available by contacting your Intel/Distribution sales office. Figure 4. µBGA* CSP 40-Bump Pinout (28F008S3 and 28F016S3) 10 PRELIMINARY E 2.0 BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY PRINCIPLES OF OPERATION The byte-wide Smart 3 FlashFile memories include an on-chip WSM to manage block erase, program, and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure, program, and lock-bit configuration, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from deep power-down mode (see Bus Operations), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the VPP voltage. High voltage on VPP enables successful block erasure, program, and lock-bit configuration. All functions associated with altering memory contents—block erase, program, lock-bit configuration, status, and identifier codes—are accessed via the CUI and verified through the status register. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM that controls block erase, program, and lock-bit configuration operations. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. Interface software that initiates and polls progress of block erase, program, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read data from or program data to any other block. Program suspend allows system software to suspend a program to read data from any other flash memory array location. 1FFFFF 1F0000 1EFFFF 1E0000 1DFFFF 1D0000 1CFFFF 1C0000 1BFFFF 1B0000 1AFFFF 1A0000 19FFFF 190000 18FFFF 180000 17FFFF 170000 16FFFF 160000 15FFFF 150000 14FFFF 140000 13FFFF 130000 12FFFF 120000 11FFFF 110000 10FFFF 100000 0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A0000 09FFFF 090000 08FFFF 080000 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000 64-Kbyte Block 31 64-Kbyte Block 30 64-Kbyte Block 29 64-Kbyte Block 28 64-Kbyte Block 27 64-Kbyte Block 26 64-Kbyte Block 25 64-Kbyte Block 24 64-Kbyte Block 23 64-Kbyte Block 22 64-Kbyte Block 21 64-Kbyte Block 20 64-Kbyte Block 19 64-Kbyte Block 18 64-Kbyte Block 17 64-Kbyte Block 16 64-Kbyte Block 15 64-Kbyte Block 14 64-Kbyte Block 13 64-Kbyte Block 12 64-Kbyte Block 11 64-Kbyte Block 10 64-Kbyte Block 9 64-Kbyte Block 8 64-Kbyte Block 7 64-Kbyte Block 6 64-Kbyte Block 5 64-Kbyte Block 4 64-Kbyte Block 3 64-Kbyte Block 2 64-Kbyte Block 1 64-Kbyte Block 0 16-Mbit 8-Mbit 4-Mbit Figure 5. Memory Map PRELIMINARY 11 BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 2.1 Data Protection Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when memory block erase, program, or lock-bit configuration operations are required) or hardwired to VPPH1/2. The device accommodates either design practice and encourages optimization of the processor-memory interface. When VPP ≤ VPPLK, memory contents cannot be altered. When high voltage is applied to VPP, the two-step block erase, program, or lock-bit configuration command sequences provides protection from unwanted operations. All write functions are disabled when VCC voltage is below the write lockout voltage VLKO or when RP# is at VIL. The device’s block locking capability provides additional protection from inadvertent code or data alteration by gating erase and program operations. 3.2 Output Disable E With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0–DQ7 are placed in a high-impedance state. 3.3 Standby CE# at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ0–DQ7 outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, program, or lock-bit configuration, the device continues functioning and consuming active power until the operation completes. 3.4 Deep Power-Down RP# at VIL initiates the deep power-down mode. 3.0 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Block information, identifier codes, or status register can be read independent of the VPP voltage. RP# can be at either VIH or VHH. The first task is to write the appropriate read-mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep powerdown mode, the device automatically resets to read array mode. Four control pins dictate the data flow in and out of the component: CE#, OE#, WE#, and RP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQ0–DQ7) control and when active drives the selected memory data onto the I/O bus. WE# must be at VIH and RP# must be at VIH or VHH. Figure 17 illustrates a read cycle. 12 In read mode, RP#-low deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. RP# must be held low for time tPLPH. Time tPHQV is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI resets to read array mode, and the status register is set to 80H. During block erase, program, or lock-bit configuration, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. PRELIMINARY E 1FFFFF BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 3.5 Block 31 The read identifier codes operation outputs the manufacturer code, device code, block lock configuration codes for each block, and master lock configuration code (see Figure 6). Using the manufacturer and device codes, the system software can automatically match the device with its proper algorithms. The block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting. Reserved for Future Implementation 1F0002 Block 31 Lock Configuration 1F0000 Reserved for Future Implementation (Blocks 16 through 30) 0FFFFF Block 15 Reserved for Future Implementation 0F0002 0F0000 3.6 Block 15 Lock Configuration Reserved for Future Implementation (Blocks 8 through 14) 07FFFF 16-Mbit Block 7 Reserved for Future Implementation 070002 Block 7 Lock Configuration 070000 Reserved for Future Implementation 8-Mbit 01FFFF Block 1 Reserved for Future Implementation 010000 00FFFF 000003 000002 000001 000000 Write The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active and OE# = VIH. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Figure 18 illustrates a write operation. 4.0 (Blocks 2 through 14) 010002 Read Identifier Codes Operation COMMAND DEFINITIONS When the VPP voltage ≤ VPPLK, read operations from the status register, identifier codes, or blocks are enabled. Placing VPPH1/2 on VPP enables successful block erase, program, and lock-bit configuration operations. 4-Mbit Block 1 Lock Configuration Reserved for Future Implementation Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands. Block 0 Reserved For Future Implementation Master Lock Configuration Block 0 Lock Configuration Device Code Manufacturer Code Figure 6. Device Identifier Code Memory Map PRELIMINARY 13 E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY Table 2. Bus Operations Mode Notes RP# CE# OE# WE# Address VPP DQ0–7 RY/BY# 1,2,3 VIH or VHH VIL VIL VIH X X DOUT X Output Disable 3 VIH or VHH VIL VIH VIH X X High Z X Standby 3 VIH or VHH VIH X X X X High Z X Deep Power-Down 4 VIL X X X X X High Z VOH VIH or VHH VIL VIL VIH See Figure 5 X Note 5 VOH VIH or VHH VIL VIH VIL X X DIN X Read Read Identifier Codes Write 3,6,7 NOTES: 1. Refer to DC Characteristics. When VPP ≤ VPPLK, memory contents can be read, but not altered. 2. X can be VIL or VIH for control and address input pins and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK and VPPH1/2 voltages. 3. RY/BY# is VOL when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It is VOH when the WSM is not busy, in block erase suspend, program suspend, or deep power-down mode. 4. RP# at GND ± 0.2 V ensures the lowest deep power-down current. 5. See Section 4.2 for read identifier code data. 6. Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPP = VPPH1/2 and VCC = VCC2 (see Section 6.2 for operating conditions). 7. Refer to Table 3 for valid DIN during a write operation. 14 PRELIMINARY E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY Table 3. Command Definitions(9) Bus Cycles Command Read Array/Reset Req’d. First Bus Cycle Notes 1 Second Bus Cycle Oper(1) Addr(2) Data(3) Oper(1) Addr(2) Data(3) Write X FFH Write X 90H Read IA ID 2 Write X 70H Read X SRD 1 Write X 50H 5 Write BA 20H Write BA D0H 5,6 Write PA 40H or 10H Write PA PD 5 Write X B0H 1 5 Write X D0H Set Block Lock-Bit 2 7 Write BA 60H Write BA 01H Set Master Lock-Bit 2 7 Write X 60H Write X F1H Clear Block Lock-Bits 2 8 Write X 60H Write X D0H Read Identifier Codes ≥2 Read Status Register Clear Status Register Block Erase 2 Program 2 Block Erase and Program Suspend 1 Block Erase and Program Resume 4 NOTES: 1. Bus operations are defined in Table 2. 2. X = Any valid address within the device. IA = Identifier Code Address: see Figure 6. BA = Address within the block being erased or locked. PA = Address of memory location to be programmed. 3. SRD = Data read from status register. See Table 6 for a description of the status register bits. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID = Data read from identifier codes. 4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock codes. See Section 4.2 for read identifier code data. 5. If the block is locked, RP# must be at VHH to enable block erase or program operations. Attempts to issue a block erase or program to a locked block while RP# is VIH will fail. 6. Either 40H or 10H are recognized by the WSM as the program setup. 7. If the master lock-bit is set, RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the master lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is VIH. 8. If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is VIH. 9. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. PRELIMINARY 15 BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 4.1 Read Array Command 4.3 Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, program, or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Program Suspend command. The Read Array command functions independently of the VPP voltage and RP# can be VIH or VHH. 4.2 Read Identifier Codes Command Table 4. Identifier Codes Code Manufacturer Code Address 000000 4-Mbit 000001 Device Code 8-Mbit 000001 16-Mbit 000001 Block Lock Configuration XX0002(1) • Block Is Unlocked • Block Is Locked • Reserved for Future Use Master Lock Configuration 000003 • Device Is Unlocked • Device Is Locked • Reserved for Future Use Data 89 A7 A6 AA DQ0 = 0 DQ0 = 1 DQ1–7 DQ0 = 0 DQ0 = 1 DQ1–7 NOTE: 1. X selects the specific block lock configuration code to be read. See Figure 5 for the device identifier code memory map. 16 Read Status Register Command The status register may be read to determine when a block erase, program, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#, whichever occurs first. OE# or CE# must toggle to VIH to update the status register latch. The Read Status Register command functions independently of the VPP voltage. RP# can be VIH or VHH. 4.4 The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 6 retrieve the manufacturer, device, block lock configuration and master lock configuration codes (see Table 4 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPP voltage and RP# can be VIH or VHH. Following the Read Identifier Codes command, the subsequent information can be read. E Clear Status Register Command Status register bits SR.5, SR.4, SR.3, and SR.1 are set to “1”s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 6). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPP voltage. RP# can be VIH or VHH. This command is not functional during block erase or program suspend modes. 4.5 Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is written first, followed by a block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 7). The CPU can detect block erase completion by analyzing the RY/BY# pin or status register bit SR.7. PRELIMINARY E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to “1.” Also, reliable block erasure can only occur when VCC = VCC2 and VPP = VPPH1/2. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VPP ≤ VPPLK, SR.3 and SR.5 will be set to “1.” Successful block erase requires that the corresponding block lock-bit be cleared or, if set, that RP# = VHH. If block erase is attempted when the corresponding block lock-bit is set and RP# = VIH, the block erase will fail, and SR.1 and SR.5 will be set to “1.” Block erase operations with VIH < RP# < VHH produce spurious results and should not be attempted. 4.6 Program Command Program is executed by a two-cycle command sequence. Program setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the program and verify algorithms internally. After the program sequence is written, the device automatically outputs status register data when read (see Figure 8). The CPU can detect the completion of the program event by analyzing the RY/BY# pin or status register bit SR.7. When program is complete, status register bit SR.4 should be checked. If program error is detected, the status register should be cleared. The internal WSM verify only detects errors for “1”s that do not successfully program to “0”s. The CUI remains in read status register mode until it receives another command. Reliable program only occurs when VCC = VCC2 and VPP = VPPH1/2. In the absence of this high voltage, memory contents are protected against program operations. If a program operation is attempted while VPP ≤ VPPLK, the operation will fail, and status register bits SR.3 and SR.5 will be set to “1.” PRELIMINARY A successful program operation also requires that the corresponding block lock-bit be cleared or, if set, that RP# = VHH. If a program operation is attempted when the corresponding block lock-bit is set and RP# = VIH, the operation will fail, and SR.1 and SR.4 will be set to “1.” Program operations with VIH < RP# < VHH produce spurious results and should not be attempted. 4.7 Block Erase Suspend Command The Block Erase Suspend command allows block-erase interruption to read or program data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to “1”). RY/BY# will also transition to VOH. Specification tWHRH2 defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Program command sequence can also be issued during erase suspend to program data in other blocks. Using the Program Suspend command (see Section 4.8), a program operation can also be suspended. During a program operation with block erase suspended, status register bit SR.7 will return to “0” and the RY/BY# output will transition to VOL. However, SR.6 will remain “1” to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to VOL. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 9). VPP must remain at VPPH1/2 (the same VPP level used for block erase) while block erase is suspended. RP# must also remain at VIH or VHH (the same RP# level used for block erase). Block erase cannot resume until program operations initiated during block erase suspend have completed. 17 BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 4.8 Program Suspend Command The Program Suspend command allows program interruption to read data in other flash memory locations. Once the program process starts, writing the Program Suspend command requests that the WSM suspend the program sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Program Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the program operation has been suspended (both will be set to “1”). RY/BY# will also transition to VOH. Specification tWHRH1 defines the program suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while program is suspended are Read Status Register and Program Resume. After Program Resume command is written to the flash memory, the WSM will continue the program process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to VOL. After the Program Resume command is written, the device automatically outputs status register data when read (see Figure 10). VPP must remain at VPPH1/2 (the same VPP level used for program) while in program suspend mode. RP# must also remain at VIH or VHH (the same RP# level used for program). 4.9 Set Block and Master Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a master lock-bit. The block lock-bits gate program and erase operations while the master lock-bit gates block-lock bit modification. With the master lock-bit not set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set Master Lock-Bit command, in conjunction with RP# = VHH, sets the master lock-bit. After the 18 E master lock-bit is set, subsequent setting of block lock-bits requires both the Set Block Lock-Bit command and VHH on the RP# pin. See Table 5 for a summary of hardware and software write protection options. Set block lock-bit and master lock-bit are initiated using two-cycle command sequence. The set block or master lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set master lock-bit confirm (and any device address). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Figure 11). The CPU can detect the completion of the set lock-bit event by analyzing the RY/BY# pin output or status register bit SR.7. When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of setup followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block or Master Lock-Bit command will result in status register bits SR.4 and SR.5 being set to “1.” Also, reliable operations occur only when VCC = VCC2 and VPP = VPPH1/2. In the absence of this high voltage, lock-bit contents are protected against alteration. A successful set block lock-bit operation requires that the master lock-bit be cleared or, if the master lock-bit is set, that RP# = VHH. If it is attempted with the master lock-bit set and RP# = VIH, the operation will fail, and SR.1 and SR.4 will be set to “1.” A successful set master lock-bit operation requires that RP# = VHH. If it is attempted with RP# = VIH, the operation will fail, and SR.1 and SR.4 will be set to “1.” Set block and master lock-bit operations with VIH < RP# < VHH produce spurious results and should not be attempted. PRELIMINARY E 4.10 BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the master lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the master lock-bit is set, clearing block lock-bits requires both the Clear Block Lock-Bits command and VHH on the RP# pin. See Table 5 for a summary of hardware and software write protection options. Clear block lock-bits operation is initiated using a two-cycle command sequence. A clear block lock-bits setup is written first. Then, the device automatically outputs status register data when read (see Figure 12). The CPU can detect completion of the clear block lock-bits event by analyzing the RY/BY# pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register bits SR.4 and SR.5 being set to “1.” Also, a reliable clear block lock-bits operation can only occur when VCC = VCC2 and VPP = VPPH1/2. If a clear block lock-bits operation is attempted while VPP ≤ VPPLK, SR.3 and SR.5 will be set to “1.” In the absence of this high voltage, the block lock-bits content are protected against alteration. A successful clear block lock-bits operation requires that the master lock-bit is not set or, if the master lockbit is set, that RP# = VHH. If it is attempted with the master lock-bit set and RP# = VIH, SR.1 and SR.5 will be set to “1” and the operation will fail. A clear block lock-bits operation with VIH < RP# < VHH produce spurious results and should not be attempted. If a clear block lock-bits operation is aborted due to VPP or VCC transitioning out of valid range or RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lockbits is required to initialize block lock-bit contents to known values. Once the master lock-bit is set, it cannot be cleared. Table 5. Write Protection Alternatives Operation Master Block Lock-Bit Lock-Bit RP# Effect Block Erase and Program Enabled Block is Locked. Block Erase and Program Disabled Block Lock-Bit Override. Block Erase and Program Enabled Set Block Lock-Bit Enabled Master Lock-Bit is Set. Set Block Lock-Bit Disabled Master Lock-Bit Override. Set Block Lock-Bit Enabled Set Master Lock-Bit Disabled Set Master Lock-Bit Enabled Clear Block Lock-Bits Enabled Master Lock-Bit is Set. Clear Block Lock-Bits Disabled Master Lock-Bit Override. Clear Block Lock-Bits Enabled Block Erase or Byte Write X 0 1 VIH or VHH VIH VHH Set Block Lock-Bit 0 1 X X VIH or VHH VIH VHH Set Master Lock-Bit Clear Block Lock-Bits X X 0 1 X X VIH VHH VIH or VHH VIH VHH PRELIMINARY 19 E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY Table 6. Status Register Definition WSMS ESS ECLBS PSLBS VPPS PSS DPS R 7 6 5 4 3 2 1 0 NOTES: SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy Check RY/BY# or SR.7 to determine block erase, program, or lock-bit configuration completion. SR.6–0 are invalid while SR.7 = “0.” SR.6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR LOCK-BITS STATUS 1 = Error in Block Erasure or Clear Lock-Bits 0 = Successful Block Erase or Clear Lock-Bits If both SR.5 and SR.4 are “1”s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. SR.4 = PROGRAM AND SET LOCK-BIT STATUS 1 = Error in Program or Set Master/Block Lock-Bit 0 = Successful Program or Set Master/Block Lock-Bit SR.3 = VPP STATUS 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR.3 does not provide a continuous indication of VPP level. The WSM interrogates and indicates the VPP level only after a block erase, program, or lockbit configuration operation. SR.3 is not guaranteed to reports accurate feedback only when VPP ≠ VPPH1/2. SR.2 = PROGRAM SUSPEND STATUS 1 = Program Suspended 0 = Program in Progress/Completed SR.1 = DEVICE PROTECT STATUS 1 = Master Lock-Bit, Block Lock-Bit and/or RP# Lock Detected, Operation Abort 0 = Unlock SR.1 does not provide a continuous indication of master and block lock-bit values. The WSM interrogates the master lock-bit, block lock-bit, and RP# only after a block erase, program, or lock-bit configuration operation. It informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or RP# ≠ VHH. SR.0 = RESERVED FOR FUTURE ENHANCEMENTS SR.0 is reserved for future use and should be masked out when polling the status register. 20 PRELIMINARY E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY Start Write 20H, Block Address Bus Operation Command Write Erase Setup Data = 20H Addr = Within Block to Be Erased Write Erase Confirm Data = D0H Addr = Within Block to Be Erased Write D0H, Block Address Comments Status Register Data Read Read Status Register Suspend Block Erase Loop No 0 SR.7 = Suspend Block Erase Yes 1 Full Status Check if Desired Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Repeat for subsequent block erasures. Full status check can be done after each block erase, or after a sequence of block erasures. Write FFH after the last operation to place device in read array mode. Block Erase Complete FULL STATUS CHECK PROCEDURE Bus Operation Read Status Register Data (See Above) Standby SR.3 = 1 VPP Range Error Standby 0 SR.1 = 1 1 Command Sequence Error 0 1 SR.5 = Comments Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect RP# = V IH , Block Lock-Bit Is Set Only required for systems implementing lock-bit configuration Device Protect Error Standby Check SR.4,5 Both 1 = Command Sequence Error Standby Check SR.5 1 = Block Erase Error 0 SR.4,5 = Command Block Erase Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. 0 Block Erase Successful Figure 7. Automated Block Erase Flowchart PRELIMINARY 21 E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY Start Bus Operation Write 40H, Address Command Comments Write Setup Program Data = 40H Addr = Location to Be Programmed Write Program Data = Data to Be Programmed Addr = Location to Be Programmed Write Byte Data and Address Read Status Register Data Read Status Register Suspend Program Loop Standby Check SR.7 1 = WSM Ready 0 = WSM Busy No 0 Suspend Program SR.7 = Yes 1 Full Status Check if Desired Repeat for subsequent byte writes. SR full status check can be done after each program, or after a sequence of program operations. Write FFH after the last program operation to reset device to read array mode. Program Complete FULL STATUS CHECK PROCEDURE Bus Operation Read Status Register Data (See Above) Command Standby SR.3 = 1 VPP Range Error 0 SR.1 = Standby 1 Device Protect Error 0 Standby Comments Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect RP# = V IH , Block Lock-Bit Is Set Only required for systems implementing lock-bit configuration Check SR.4 1 = Program Error 1 SR.4 = 0 Program Successful Program Error SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Figure 8. Automated Program Flowchart 22 PRELIMINARY E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY Start Write B0H Bus Operation Command Write Erase Suspend Read Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed 0 1 Write 0 SR.6 = Data = B0H Addr = X Status Register Data Addr = X Read Status Register SR.7 = Comments Erase Resume Data = D0H Addr = X Block Erase Completed 1 Read Read Array Data Read or Program ? Program No Program Loop Done? Yes Write D0H Write FFH Block Erase Resumed Read Array Data Figure 9. Block Erase Suspend/Resume Flowchart PRELIMINARY 23 E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY Start Bus Operation Write Write B0H Command Program Suspend Read Read Status Register 0 SR.7 = Comments Data = B0H Addr = X Status Register Data Addr = X Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Check SR.2 1 =Program Suspended 0 = Program Completed 1 Write 0 Read Array Data = FFH Addr = X Program Completed SR.2 = Read Read array locations other than that being data written. 1 Write Write FFH Program Resume Data = D0H Addr = X Read Array Data Done Reading No Yes Write D0H Write FFH Program Resumed Read Array Data Figure 10. Program Suspend/Resume Flowchart 24 PRELIMINARY E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY Start Bus Operation Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Command Comments Write Set Block/Master Lock-Bit Setup Data = 60H Addr = Block Address (Block), Device Address (Master) Write Set Block or Master Lock-Bit Confirm Data = 01H (Block), F1H (Master) Addr = Block Address (Block), Device Address (Master) Status Register Data Read Read Status Register Check SR.7 1 = WSM Ready 0 = WSM Busy Standby 0 SR.7 = Repeat for subsequent lock-bit set operations. Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. Write FFH after the last lock-bit set operation to place device in read array mode. 1 Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Bus Operation Read Status Register Data (See Above) Standby SR.3 = 1 V PP Range Error Standby 0 SR.1 = 1 Device Protect Error 1 Command Sequence Error 0 1 SR.4 = Set Lock-Bit Error Comments Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect RP# = V IH , (Set Master Lock-Bit Operation) RP# = VHH , Master Lock-Bit Is Set (Set Block Lock-Bit Operation) Standby Check SR.4,5 Both 1 = Command Sequence Error Standby Check SR.4 1 = Set Lock-Bit Reset Error 0 SR.4,5 = Command SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple lock-bits are set before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. 0 Set Lock-Bit Successful Figure 11. Set Block and Master Lock-Bit Flowchart PRELIMINARY 25 E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY Start Bus Operation Write 60H Command Comments Write Clear Block Lock-Bits Setup Data = 60H Addr = X Write Clear Block Lock-Bits Confirm Data = D0H Addr = X Write D0H Status Register Data Read Read Status Register Check SR.7 1 = WSM Ready 0 = WSM Busy Standby 0 SR.7 = Write FFH after the Clear Block Lock-Bits operation to place device to read array mode. 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Bus Operation Read Status Register Data (See Above) SR.3 = 1 1 Comments Standby Check SR.3 1 = VPP Error Detect Standby Check SR.1 1 = Device Protect Detect RP# = VIH, Master Lock-Bit Is Set Standby Check SR.4,5 Both 1 = Command Sequence Error Standby Check SR.5 1 = Clear Block Lock-Bits Error VPP Range Error 0 SR.1= Command Device Protect Error 0 1 SR.4,5 = Command Sequence Error 0 1 SR.5 = Clear Block Lock-Bits Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command. If error is detected, clear the Status Register before attempting retry or other error recovery. 0 Clear Block Lock-Bits Successful Figure 11. Clear Block Lock-Bits Flowchart 26 PRELIMINARY E 5.0 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY Intel provides three control inputs to accommodate multiple memory connections: CE#, OE#, and RP#. Three-line control provides for: a. Lowest possible memory power dissipation. b. Data bus contention avoidance. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system’s READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. 5.2 RY/BY# Hardware Detection RY/BY# is a full CMOS output that provides a hardware method of detecting block erase program and lock-bit configuration completion. This output can be directly connected to an interrupt input of the system CPU. RY/BY# transitions low when the WSM is busy and returns to VOH when it is finished executing the internal algorithm. During suspend and deep power-down modes, RY/BY# remains at VOH. 5.3 Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected between its VCC and GND and between its VPP and GND. These high-frequency, low-inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array’s power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. PRELIMINARY 5.4 VPP Trace on Printed Circuit Boards Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for byte writing and block erasing. Use similar trace widths and layout considerations given to the VCC power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots. 5.5 VCC, VPP, RP# Transitions Block erase, program and lock-bit configuration are not guaranteed if VPP or VCC fall outside of a valid voltage range (VCC2 and VPPH1/2) or RP# ≠ VIH or VHH. If VPP error is detected, status register bit SR.3 is set to “1” along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to VIL during block erase, program, or lock-bit configuration, RY/BY# will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep powerdown. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal operation is restored. 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block erasure, byte writing, or lock-bit configuration during power transitions. Upon powerup, the device is indifferent as to which power supply (VPP or VCC) powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is active. Since both WE# and CE# must be low for a command write, driving either input signal to VIH will inhibit writes. The CUI’s two-step command sequence architecture provides an added level of protection against data alteration. In-system block lock and unlock renders additional protection during power-up by prohibiting block erase and program operations. The device is disabled while RP# = VIL regardless of its control inputs state. 27 BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 5.7 VPP Program and Erase Voltages on Sub-0.4µ S3 Memory Family E Intel's byte-wide Smart 3 FlashFile™ memory family provides in-system program/erase at 2.7 V and 3.3 V VPP as well as faster factory program/erase at 12 V VPP. Future sub-0.4µ lithography Smart 3 FlashFile memory products will also include a backwardcompatible 12 V programming feature. This mode, however, is not intended for extended use. A 12 V program/erase VPP can be applied for 1000 cycles maximum per block or 80 hours maximum per device. To ensure compatibility with future sub-0.4µ Smart 3 FlashFile memory products, present designs should not permanently connect VPP to 12 V. This will avoid device over-stressing that may cause permanent damage. 28 PRELIMINARY E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 6.0 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* NOTICE: This datasheet contains information on new products production. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. Temperature under Bias .............. –10 °C to +80 °C Storage Temperature................. –65 °C to +125 °C *WARNING: Stressing the device beyond the “Absolute Voltage On Any Pin (except VPP, and RP#) ......... –2.0 V to +7.0 V(2) VPP Voltage ........................... –2.0 V to +14.0 Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. V (1,2) RP# Voltage ........................ –2.0 V to +14.0 V(1,2,4) Output Short Circuit Current.....................100 mA(3) NOTES: 1. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and –0.2 V on VCC, RP#, and VPP pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns. Maximum DC voltage on input/output pins and VCC is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. 2. Maximum DC voltage on VPP and RP# may overshoot to +14.0 V for periods <20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. 4. RP# voltage is normally at VIL or VIH. Connection to supply of VHH is allowed for a maximum cumulative period of 80 hours. 6.2 Commercial Temperature Operating Conditions Commercial Temperature and VCC Operating Conditions Symbol Parameter TA Operating Temperature VCC1 VCC Supply Voltage (2.7 V–3.6 V) VCC2 VCC Supply Voltage (3.3 V ± 0.3 V) Notes 1 Min Max Unit 0 +70 °C 2.7 3.6 V 3.0 3.6 V Test Condition Ambient Temperature NOTE: 1. Block erase, program, and lock-bit configuration with VCC < 2.7 V should not be attempted. Capacitance(1) 6.3 TA = +25 °C, f = 1 MHz Symbol Parameter Typ Max Unit Condition CIN Input Capacitance 6 8 pF VIN = 0.0 V COUT Output Capacitance 8 12 pF VOUT = 0.0 V NOTE: 1. Sampled, not 100% tested. PRELIMINARY 29 E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 6.4 DC Characteristics—Commercial Temperature 2.7 V VCC Sym Parameter Notes Typ Max 3.3 V VCC Typ Test Max Unit Conditions ILI Input Load Current 1 ± 0.5 ± 0.5 µA VCC = VCC Max VIN = VCC or GND ILO Output Leakage Current 1 ± 0.5 ± 0.5 µA VCC = VCC Max VOUT = VCC or GND ICCS VCC Standby Current µA CMOS Inputs VCC = VCC Max CE# = RP# = VCC ± 0.2 V ICCD VCC Deep Power-Down Current ICCR VCC Read Current ICCW VCC Program/ Set 1,3,6 VCC Block Erase/Clear 1,5,6 1,7 20 100 0.1 2 0.2 2 mA TTL Inputs VCC = VCC Max CE# = RP# = VIH 10 µA 10 6 12 7 12 mA CMOS Inputs VCC = VCC Max, CE# = GND f = 5 MHz, I OUT = 0 mA 7 18 8 18 mA TTL Inputs VCC = VCC Max, CE# = GND f = 5 MHz, I OUT = 0 mA 17 mA VPP = 3.3 V ± 0.3 V 12 mA VPP = 12.0 V ± 5% 17 mA VPP = 3.3 V ± 0.3 V 12 mA VPP = 12.0 V ± 5% 1,2 6 mA CE# = VIH ±2 ± 15 ±2 ± 15 µA VPP ≤ VCC 200 10 200 µA VPP > VCC 5 0.1 5 µA RP# = GND ± 0.2 V 40 mA VPP = 3.3 V ± 0.3 V 15 mA VPP = 12.0 V ± 5% 20 mA VPP = 3.3 V ± 0.3 V 15 mA VPP = 12.0 V ± 5% 200 µA IPPS VPP Standby Current 1 IPPR VPP Read Current 1 10 IPPD VPP Deep Power-Down Current 1 0.1 IPPW VPP Program/Set 1,7 Lock-Bit Current IPPE VPP Block Erase/Clear 1,7 Block Lock-Bits Current IPPWS IPPES 30 VPP Block Erase/Program Suspend Current RP# = GND ± 0.2 V IOUT (RY/BY#) = 0 mA 1,7 Block Lock-Bits Current ICCWS VCC Program/Block ICCES Erase Suspend Current 100 1 Lock-Bit Current ICCE 20 1 10 VPP = VPPH1/2 PRELIMINARY E 6.4 BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY DC Characteristics— Commercial Temperature (Continued) 2.7 V VCC Sym Parameter Notes Min 3.3 V VCC Max Min Test Max Unit Conditions VIL Input Low Voltage 7 –0.5 0.8 –0.5 0.8 V VIH Input High Voltage 7 2.0 VCC + 0.5 2.0 VCC + 0.5 V VOL Output Low Voltage 3,7 0.4 V VCC = VCC Min IOL = 2 mA VOH1 Output High Voltage (TTL) 3,7 2.4 2.4 V VCC = VCC Min IOH = –2.5 mA VOH2 Output High Voltage (CMOS) 3,7 0.85 VCC 0.85 VCC V VCC = VCC Min IOH = –2.5 mA VCC –0.4 VCC –0.4 V VCC = VCC Min IOH = –100 µA VPPLK VPP Lockout Voltage 0.4 4,7 1.5 1.5 V VPPH1 VPP Voltage 2.7 3.6 2.7 3.6 V VPPH2 VPP Voltage 11.4 12.6 V 11.4 12.6 V VLKO VCC Lockout Voltage VHH RP# Unlock Voltage 2.0 8,9 2.0 V Set Master Lock-Bit Override Lock-Bit NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA = +25 °C. These currents are valid for all product versions (packages and speeds). 2. ICCWS and ICCES are specified with the device de-selected. If read or written while in erase suspend mode, the device’s current is the sum of ICCWS or ICCES and ICCR or ICCW. 3. Includes RY/BY#. 4. Block erases, program, and lock-bit configurations are inhibited when VPP ≤ VPPLK, and not guaranteed in the range between VPPLK (max) and VPPH1 (min), between VPPH1 (max) and VPPH2 (min), and above VPPH2 (max). 5. Automatic Power Savings (APS) reduces typical ICCR to 3 mA at 3.3 V VCC in static operation. 6. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH. 7. Sampled, not 100% tested. 8. Master lock-bit set operations are inhibited when RP# = VIH. Block lock-bit configuration operations are inhibited when the master lock-bit is set and RP# = VIH. Block erases and program are inhibited when the corresponding block-lock bit is set and RP# = VIH. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be attempted with VIH < RP# < VHH. 9. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours. PRELIMINARY 31 E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 2.7 INPUT 1.35 TEST POINTS 1.35 OUTPUT 0.0 AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.35 V. Input rise and fall times (10% to 90%) <10 ns. Figure 12. Transient Input/Output Reference Waveform for VCC = 2.7 V−3.6 V 3.0 INPUT 1.5 TEST POINTS 1.5 OUTPUT 0.0 AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to 90%) <10 ns. Figure 13. Transient Input/Output Reference Waveform for VCC = 3.3 V ± 0.3 V Test Configuration Capacitance Loading Value 1.3V Test Configuration VCC = 3.3 V ± 0.3 V, 2.7 V−3.6 V 1N914 CL (pF) 50 R L = 3.3 K DEVICE UNDER TEST OUT CL NOTE: CL includes Jig Capacitance Figure 14. Transient Equivalent Testing Load Circuit 32 PRELIMINARY E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY RY/BY# (R) VIH VIL P2 RP# (P) VIH VIL P1 Figure 16. AC Waveform for Reset Operation Table 7. Reset Specifications(1)—Commercial Temperature 2.7 V VCC # Sym Parameter P1 tPLPH RP# Pulse Low Time (If RP# is tied to V CC, this specification is not applicable) P2 tPLRH RP# Low to Reset during Block Erase, Program, or Lock-Bit Configuration Notes Min Max 100 2,3 3.3 V VCC Min Max 100 Unit ns 20 µs NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If RP# is asserted when the WSM is not busy (RY/BY# = “1”), the reset will complete within 100 ns. 3. A reset time, tPHQV, is required from the latter of RY/BY# or RP# going high until outputs are valid. PRELIMINARY 33 E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 6.5 AC Characteristics—Read-Only Operations(1, 4)—Commercial Temperature TA = 0 °C to +70 °C Versions(4) # Sym 3.3V ± 0.3V VCC –120 –150 2.7V−3.6V VCC –150 –170 Parameter Notes Min Max Max 150 Min Max R1 tAVAV Read Cycle Time R2 tAVQV Address to Output Delay R3 tELQV CE# to Output Delay R4 tGLQV OE# to Output Delay R5 tPHQV RP# High to Output Delay R6 tELQX CE# to Output in Low Z 3 0 0 0 ns R7 tGLQX OE# to Output in Low Z 3 0 0 0 ns R8 tEHQZ CE# High to Output in High Z 3 55 55 55 ns R9 tGHQZ OE# High to Output in High Z 3 20 20 25 ns Output Hold from Address, CE# or OE# Change, Whichever Occurs First 3 R10 tOH 120 Min Unit 170 ns 120 150 170 ns 2 120 150 170 ns 2 50 55 55 ns 600 600 600 ns 0 0 0 ns NOTES: 1. See AC Input/Output Reference Waveform for maximum allowable input slew rate. 2. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV. 3. Sampled, not 100% tested. 4. See Ordering Information for device speeds (valid operational combinations). 34 PRELIMINARY E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY VIH Standby ADDRESSES (A) CE# (E) Data Valid Device Address Selection Address Stable VIL VIH R1 VIL OE# (G) WE# (W) R2 R8 VIL VIH R3 R9 VIL VOH R5 VIH R4 R10 R6 DATA (D/Q) High Z Valid Output (DQ0-DQ7) VOL High Z R7 V CC RP# (P) VIH VIL Figure 15. AC Waveform for Read Operations PRELIMINARY 35 E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 6.6 AC Characteristics—Write Operations(1, 2)—Commercial Temperature TA = 0 °C to +70 °C 3.3V ± 0.3V, Valid for All 2.7V−3.6V VCC Speeds Versions(4) # Sym Parameter Notes Min Unit Max W1 tPHWL (tPHEL) RP# High Recovery to WE# (CE#) Going Low 3 1 µs W2 tELWL (tWLEL) CE# (WE#) Setup to WE# (CE#) Going Low 7 0 ns W3 tWP Write Pulse Width 7 70 ns W4 tDVWH (tDVEH) Data Setup to WE# (CE#) Going High 4 50 ns W5 tAVWH (tAVEH) Address Setup to WE# (CE#) Going High 4 50 ns W6 tWHEH (tEHWH) CE# (WE#) Hold from WE# (CE#) High 0 ns W7 tWHDX (tEHDX) Data Hold from WE# (CE#) High 5 ns W8 tWHAX (tEHAX) Address Hold from WE# (CE#) High 5 ns W9 tWPH Write Pulse Width High 9 25 ns W10 tPHHWH (tPHHEH) RP# VHH Setup to WE# (CE#) Going High 3,8 100 ns W11 tVPWH (tVPEH) VPP Setup to WE# (CE#) Going High 3,8 100 ns W12 tWHRL (tEHRL) WE# (CE#) High to RY/BY# Going Low W13 tWHGL (tEHGL) Write Recovery before Read W14 tQVPH RP# VHH Hold from Valid SRD, RY/BY# High W15 tQVVL VPP Hold from Valid SRD, RY/BY# High 8 90 ns 0 ns 3,5,8 0 ns 3,5,8 0 ns NOTES: 1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics—Read-Only Operations. 2. A write operation can be initiated and terminated with either CE# or WE#. 3. Sampled, not 100% tested. 4. Refer to Table 3 for valid AIN and DIN for block erase, program, or lock-bit configuration. 5. VPP should be held at VPPH1/2 (and if necessary RP# should be held at VHH) until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0). 6. See Ordering Information for device speeds (valid operational combinations). 7. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. If CE# is driven low 10 ns before WE# going low, WE# pulse width requirement decreases to tWP - 20 ns. 8. Block erase, program, and lock-bit configuration with VCC < 2.7 V should not be attempted. 9. Write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 36 PRELIMINARY E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY ADDRESSES [A] VIH A VIL C AIN D E F W8 W5 VIH CE# (WE#) [E(W)] B AIN VIL W6 W1 VIH OE# [G] W12 VIL W9 W2 VIH W16 WE# (CE#) [W(E)] VIL W3 W4 VIH DATA [D/Q] W7 High Z VIL DIN W13 VIH RY/BY# [R] Valid SRD DIN DIN VIL W10 W14 VHH VIH RP# [P] VIL V VPP [V] W11 W15 PPH2,1 VPPLK VIL NOTES: A. VCC power-up and standby. B. Write block erase or program setup. C. Write block erase confirm or valid address and data.. D. Automated erase or program delay. E. Read status register data. F. Write Read Array command. Figure 17. AC Waveform for Write Operations PRELIMINARY 37 E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 6.7 Block Erase, Program, and Lock-Bit Configuration Performance(3, 4, 5)— Commercial Temperature VCC = 3.3V ± 0.3V, T A = 0 °C to +70 °C 2.7 V VPP # Sym W16 tWHRH1 tEHRH1 W16 tWHRH2 tEHRH2 W16 Parameter Notes Typ(1) 3.3 V VPP 12 V VPP Max Typ(1) Max Typ(1) Max Unit Byte Program Time 2 TBD TBD 17 300 7.0 125 µs Block Program Time 2 TBD TBD 1.1 4.0 0.5 1.5 sec Block Erase Time 2 TBD TBD 0.8 6.0 0.3 4.0 sec tWHRH3 tEHRH3 Set Lock-Bit Time 2 TBD TBD 21 TBD 11.6 TBD µs W16 tWHRH4 tEHRH4 Clear Block Lock-Bits Time 2 TBD TBD 1.8 TBD 1.1 TBD sec W16 tWHRH5 tEHRH5 Program Suspend Latency Time TBD TBD 7.1 10 7.4 10.4 µs W16 tWHRH6 tEHRH6 Block Erase Suspend Latency Time TBD TBD 15.2 21.1 12.3 17.2 µs NOTES: 1. Typical values measured at TA = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled, but not 100% tested. 5. Reference the AC Waveform for Write Operations, Figure 18. 38 PRELIMINARY E 6.8 BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY Extended Temperature Operating Conditions Except for the specifications given in this section, all DC and AC characteristics are identical to those give in commercial temperature specifications. See the Section 6.2 for commercial temperature specifications. Extended Temperature and VCC Operating Conditions Symbol TA Parameter Notes Operating Temperature 6.9 Min Max Unit –40 +85 °C Test Condition Ambient Temperature DC Characteristics—Extended Temperature TA = –40 °C to +85 °C 2.7 V VCC Sym ICCD Parameter Notes Typ VCC Deep Power-Down Current 1 3.3 V VCC Max Typ 20 Test Max Unit 20 µA Conditions RP# = GND ± 0.2 V IOUT (RY/BY#) = 0 mA NOTE: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact Intel’s Application Support Hotline or your local sales office for information about typical specifications. 6.10 AC Characteristics—Read-Only Operations(1, 3)—Extended Temperature TA = –40 °C to +85 °C Versions(3) # Sym Parameter R1 tAVAV Read Cycle Time R2 tAVQV Address to Output Delay R3 tELQV CE# to Output Delay 3.3 V ± 0.3 V VCC –150 2.7 V−3.6 V VCC –170 Notes Min Max 150 2 Min Unit Max 170 ns 150 170 ns 150 170 ns NOTES: 1. See AC Input/Output Reference Waveform for maximum allowable input slew rate. 2. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV. 3. See Ordering Information for device speeds (valid operational combinations). PRELIMINARY 39 E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 7.0 ORDERING INFORMATION Product line designator for all Intel Flash products E2 8 F0 0 4 S3 - 1 2 0 Operating Temperature/Package E = Comm. Temp. 40-Lead TSOP TE = Extended Temp. 40-Lead TSOP PA = Comm. Temp 44-Lead PSOP TB = Ext. Temp 44-Lead PSOP G = Comm. Temp. 40-Ball µBGA* CSP Access Speed (ns) 120 ns (3.3 V), 150 ns (2.7 V) Voltage Options (VCC/VPP) 3 = Smart 3 Flash (2.7 V/ 2.7 V and 3.3 V/3.3 V and 12 V) Device Density 004 = 4 Mbit 008 = 8 Mbit 016 = 16 Mbit Product Family S = FlashFile™ Memory Order Code by Density(1) 4 Mbit 8 Mbit Valid Operational Combinations 16 Mbit 2.7V–3.6V VCC 50 pF load 3.3V ± 0.3V VCC 50 pF load Commercial Temperature E28F004S3-120 E28F008S3-120 E28F016S3-120 –150 –120 E28F004S3-150 E28F008S3-150 E28F016S3-150 –170 –150 PA28F004S3-120 PA28F008S3-120 PA28F016S3-120 –150 –120 PA28F004S3-150 PA28F008S3-150 PA28F016S3-150 –170 –150 G28F008S3-120 G28F016S3-120 –150 –120 G28F008S3-150 G28F016S3-150 –170 –150 Extended Temperature TE28F004S3-150 TE28F008S3-150 TE28F016S3-150 –170 –150 TB28F004S3-150 TB28F008S3-150 TB28F016S3-150 –170 –150 NOTE: 1. Contact your local Intel or distribution sales office to order components with 2.7 V VPP capability. 40 PRELIMINARY E 8.0 BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY ADDITIONAL INFORMATION Order Number Document/Tool 290597 Byte-Wide Smart 5 FlashFile™ Memory Family Datasheet 290600 Byte-Wide SmartVoltage FlashFile™ Memory Family Datasheet 292183 AB-64 4-, 8-, 16-Mbit Byte-Wide FlashFile™ Memory Family Overview 292094 AP-359 28F008SA Hardware Interfacing 292099 AP-364 28F008SA Automation and Algorithms 292123 AP-374 Flash Memory Write Protection Techniques 292180 AP-625 28F008SC Compatibility with 28F008SA 292182 AP-627 Byte-Wide FlashFile™ Memory Family Software Drivers 297799 Byte-Wide Smart 3 FlashFile™ Memory Family 4, 8, and 16 Mbit Specification Update Contact Intel/Distribution 4-, 8-, and 16-Mbit Schematic Symbols Sales Office Contact Intel/Distribution 4-, 8-, and 16-Mbit TimingDesigner* Files Sales Office Contact Intel/Distribution 4-, 8-, and 16-Mbit VHDL and Verilog Models Sales Office Contact Intel/Distribution 4-, 8-, and 16-Mbit iBIS Models Sales Office NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools. PRELIMINARY 41