PCMCIA Flash Memory Card FLF Series High Density FLASH Memory Card 16, 32, 48, 64, 80 MEGABYTE General Description Features WEDC’s Flash memory cards - FLF Series - offer • Low cost, high density Linear Flash Card high density linear Flash memory for code and data • Single 5V Supply - (3V/5V operation is available as option) storage, high performance disk emulation, mobile PC and embedded applications. • Based on Intel 28F640J5 (MLC) Components The WEDC FLF series is based on Intel’s Multi Level Cell (MLC) Flash memory technology, providing • Fast Read Performance - 250ns Maximum Access Time - (200ns optional) high density Flash components at significantly lower cost per megabyte. MLC technology allows for two bits of information to be stored in a single cell. This •PCMCIA compatible - x8/ x16 Data Interface leads to reduced die size and reduced cost per megabyte. • 32-Byte Write Buffer - 6µs per Byte Effective Write Time WEDC’s FLF series cards are built with Intel’s 64Mb components, 28F640J5, with manufacturer/device ID • Cross-Compatible Command Support - Intel Basic Command Set - Common Flash Interface (CFI) - Scaleable Command Set of 89/15H. The FLF series is available in standard densities of 16, 32, 48 and 64MB. Additionally, WEDC’s FLF series provides densities beyond the 64MB density, supported by PCMCIA • Power-Down Mode - Reset, Power Down Registers standard. These higher densities are based on a “paging scheme”. By writing a page address to the • 10,000 Erase Cycles per Block Configuration Option Register (address 4000H), an additional page of memory could be access. The • 128K word symmetrical Block Architecture current FLF series supports densities to 80MB: total of 2 pages: page 0 := 64MB, page 1 := 16MB. • PC Card Standard Type II Form Factor To provide a 16 bit word wide access and to support PCMCIA standard, devices are paired on the card. Ordering Information Therefore, the Flash array is structured in 128K word (256kB) blocks. Write, read and block erase EDI 7P XXX FLF YY SS T ZZ operations can be performed as either a word or byte where XXX: wide operation. 016 032 048 064 080 16MB 32MB 48MB 64MB 80MB YY: 02 based on 28F640J5 With Attribute Memory SS: 03 04 05 WEDC Logo Blank Housing Type 2 Blank Housing T 2 (Recessed) T: C Commercial ZZ: 20 25 200ns 250ns The FLF series cards conform with the PC Card 95 Standard supported by PCMCIA and JEIDA, providing electrical and physical compatibility. The PC Card form factor offers an industry standard pinout and mechanical outline, allowing density upgrades without system design changes. WEDC’s standard cards are shipped with WEDC’s Flash Logo. Cards are also available with blank housings (no Logo). The blank housings are available in both, a recessed (for label) or flat housing. Please contact WEDC sales representative for further information on Custom artwork. August 2000 Rev. 4 - ECO #13130 1 PC Card Products PCMCIA Flash Memory Card FLF Series Block Diagram N x 28F640J5 Device Pair (N/2 - 1) CLn Device (N-1) CH0 Device (N-2) (B26) + ADDRESS BUS (A1-A25) (A1-A25) A1-A23 A1-A25 ADDRESS BUFFER A24, A25, B26 B26, (B27..) D5-D0=Page Number (PN) SRes LvReq D7 /WRi /RDi M Res Ai CH0 CLn Device 3 Device 2 CL1 CL0 D4 Q2 Q0 Ctrl control logic CL0 Device 1 SR Clr Reg Clr /REG At/Reg enable Registers D1 D0 Register NAME Config. and Status Reg. Configuration Option Register attrib. mem CIS E²PROM 2kB 0000h DATA BUS Q0-Q7 ADDRESS 4008h 4006h 4004h 4002h 4000h Management 4000h Device 0 DATA BUS Q8-Q15 D2 /CE2 /CE1 Device Pair 0 CH0 D3 /WE /OE Qn CH0 - Page Number (PN) D5 Configuration Option Register: A=4000h (Read/Write) CHn Device Pair 1 D6 control Q0-Q7 A0 I/O buffer DATA BUS D8-D15 DATA BUS D0-D7 Reset 220k M Res SR Clr Reg Clr reset circuit C 10k Vcc D0 - D15 Configuration Option Register: ADRS=4000h Read/Write CD1 CD2 Vcc SRes D7 Vcc LvReq D6 D7 OPEN R/B(N-1) D6 VS1 VS2 R/B1 R/B0 OPEN OPEN Vpp2 Vpp1 Configuration index D5-D1 reserved D0 Page Number Config. (PN) Vcc D7 N.C. N.C. /CE1, /CE2,/OE, /WE, /Reg: Power On default =0 Configuration Status Register: ADRS=4002h Read/Write 10k BVD1 BVD2 D0 LevelReq (not supported) D5-D0 R/BUSY - Page Number (PN) D4 D3 D2 D1 Soft Reset, active High 1=Reset State 0=End Reset State GND WAIT D5 D2 pull up reserved PwrDwn reserved D6 D5 D4 D3 D2 D1 D0 Power Down; active High 1 = Place all memory devices in power down mode 0 = normal operation Power On default=0 typ 100k A0, A25, Reset: pull down typ 100k R/Busy - Open Drain output (require pull up on host) Manufacturer ID Device ID Intel 89H 28F640J5 15H FLF Flash Card based on Strata Flash 28F640J5 August 2000 Rev. 4 - ECO #13130 2 PC Card Products PCMCIA Flash Memory Card FLF Series Pinout Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal name GND DQ3 DQ4 DQ5 DQ6 DQ7 CE1# A10 OE# A11 A9 A8 A13 A14 WE# RDY/BSY# Vcc Vpp1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 WP GND I/O I/O I/O I/O I/O I/O I I I I I I I I I O I I I I I I I I I I I I/O I/O I/O O Function Ground Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 Card enable 1 Address bit 10 Output enable Address bit 11 Address bit 9 Address bit 8 Address bit 13 Address bit 14 Write Enable Ready/Busy Supply Voltage Prog. Voltage Address bit 16 Address bit 15 Address bit 12 Address bit 7 Address bit 6 Address bit 5 Address bit 4 Address bit 3 Address bit 2 Address bit 1 Address bit 0 Data bit 0 Data bit 1 Data bit 2 Write Potect Ground Active Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 LOW LOW LOW LOW(1) N.C. HIGH Signal name I/O GND CD1# O DQ11 I/O DQ12 I/O DQ13 I/O DQ14 I/O DQ15 I CE2# I VS1 O RFU RFU A17 I A18 I A19 I A20 I A21 I Vcc Vpp2 A22 I A23 I A24 I A25 I VS2 O RST I Wait# O RFU REG# I BVD2 O BVD1 O DQ8 I/O DQ9 I/O DQ10 O CD2# O GND Function Ground Card Detect 1 Data bit 11 Data bit 12 Data bit 13 Data bit 14 Data bit 15 Card Enable 2 Voltage Sense 1 Reserved Reserved Address bit 17 Address bit 18 Address bit 19 Address bit 20 Address bit 21 Supply Voltage Prog. Voltage Address bit 22 Address bit 23 Address bit 24 Address bit 25 Voltage Sense 2 Card Reset Extended Bus cycle Reserved Attrib Mem Select Bat. Volt. Detect 2 Bat. Volt. Detect 1 Data bit 8 Data bit 9 Data bit 10 Card Detect 2 Ground Active LOW LOW NC (2) N.C. N.C. HIGH LOW(3) (3) (3) LOW Notes: 1. RDY/BSY signal is an open drain type output, pull-up resistors are required on the host side. 2. VS1 is connected to GND for 3.3V/5V cards and N.C. for 5V only cards. 3. Wait#, BVD1 and BVD2 are internally connected to Vcc by resistors for compatibility. Mechanical 1.6mm ± 0.05 0.063” 85.6mm ± 0.20 3.370” 1.0mm ±0.05 0.039’ 3.0mm MIN. Substrate area 1.0mm ±0.05 0.039’ 54.0mm ± 0.10 2.126” 10.0mm MIN 0.400” Interconnect area 5.0mm ± T1 0.197” August 2000 Rev. 4 - ECO #13130 3 PC Card Products PCMCIA Flash Memory Card FLF Series Card Signal Description Symbol A0 - A25 Type INPUT DQ0 - DQ15 INPUT/OUTPUT CE1#, CE2# INPUT OE# INPUT WE# INPUT RDY/BSY# OUTPUT CD1#, CD2# OUTPUT WP OUTPUT VPP1, VPP2 VCC GND REG# N.C. INPUT RST INPUT WAIT# OUTPUT BVD1, BVD2 OUTPUT VS1, VS2 OUTPUT Name and Function ADDRESS INPUTS: A0 through A25 enable direct addressing of up to 64MB of memory on the card. Signal A0 is not used in word access mode. A25 is the most significant bit DATA INPUT/OUTPUT: DQ0 THROUGH DQ15 constitute the bi-directional databus. DQ15 is the MSB. CARD ENABLE 1 AND 2: CE1# enables even byte accesses, CE2# enables odd byte accesses. Multiplexing A0, CE1# and CE2# allows 8bit hosts to access all data on DQ0 - DQ7 (see truth table). OUTPUT ENABLE: Active low signal gating read data from the memory card. WRITE ENABLE: Active low signal gating write data to the memory card. READY/BUSY OUTPUT: Indicates status of internally timed erase or program algorithms. A high output indicates that the card is ready to accept accesses. A low output indicates that one or more devices in the memory card are busy with internally timed erase or write activities. CARD DETECT 1 and 2: Provide card insertion detection. These signals are internally connected to ground on the card. The host shall monitor these signals to detect card insertion. Pulled up on host side. WRITE PROTECT: Write protect reflects the status of the Write Protect switch on the memory card. WP set to high = write protected, providing internal hardware write lockout to the Flash array. If card does not include optional write protect switch, this signal will be pulled low internally indicating write protect = "off". PROGRAMMING VOLTAGES: Not connected for 5V only card. CARD POWER SUPPLY: 5.0V for all internal circuitry. CARD GROUND ATTRIBUTE MEMORY SELECT: Active low signal, enables access to attribute memory space, occupied by the Card Information Structure (CIS) and Card Registers. RESET: Active high signal for placing card in Power-on default state. Reset can be used as a Power-Down control for the memory array. WAIT: This signal is pulled high internally for compatibility. No wait states are generated. BATTERY VOLTAGE DETECT: These signals are pulled high to maintain SRAM card compatibility. VOLTAGE SENSE: Notifies the host socket of the card's VCC requirements. VS1 and VS2 are open to indicate a 5V card. RESERVED FOR FUTURE USE NO INTERNAL CONNECTION TO CARD: pin may be driven or left floating. RFU N.C. Functional Truth Table READ function Function Mode Standby Mode Byte Access (8 bits) Word Access (16 bits) Odd-Byte Only Access /CE2 /CE1 H H H L H L L L L H A0 X L H X X /OE X L L L L /WE X H H H H X L H X X X H H H H X L L L L Common Memory Attribute Memory /REG D15-D8 D7-D0 X High-Z High-Z H High-Z Even-Byte H High-Z Odd-Byte H Odd-Byte Even-Byte H Odd-Byte High-Z /REG D15-D8 D7-D0 X High-Z High-Z L High-Z Even-Byte L High-Z Not Valid L Not Valid Even-Byte L Not Valid High-Z WRITE function Standby Mode Byte Access (8 bits) Word Access (16 bits) Odd-Byte Only Access H H H L L August 2000 Rev. 4 - ECO #13130 H L L L H X H H H H 4 X X X Even-Byte X Odd-Byte Odd-Byte Even-Byte Odd-Byte X X L L L L X X X X X X Even-Byte X Even-Byte X PC Card Products PCMCIA Flash Memory Card FLF Series Card Interface The FLF series flash card complies with PC Card standard (PCMCIA, March 1997). While maintaining PCMCIA compatibility, the FLF series card has integrated special features to extend functionality. Card has built in 2 control registers: - Configuration Option Register (COR) - Configuration and Status Register (CSR) Address = 4000h Address = 4002h COR register: provide a soft reset function (bit D7) and additional page register (bit D0) to extend card capacity beyond 64MB. SReset As defined by PCMCIA, setting the SReset bit to 1, places the card in the reset state. During this state all memory devices are place in power down mode, minimizing power consumption. Returning this bit to 0 leaves the reset cycle and place the card in the same condition as following a power up or hardware reset. This bit must be cleared to 0, to access any device on the card. Complete soft reset cycle must consist of a 2 step write sequence to the SReset bit: 1. Initialization: write 1 to SReset - reset cycle begin - memory devices enters Power-Down mode aborting all operations and clearing all registers. 2. Write 0 to SReset - Reset cycle ends - memory devices and registers enters power on default state Card can be place in Power Down mode by activating Reset signal (pin58) or by controlling the bit D2 in CSR register. LevlRequest Not supported Configuration Index Configuration Index bits (D0 - D5) are defined to provide address extension bits -page address, to extend card capacity beyond 64MB. Only bit D0 is supported: - D0 set to 0 selects page 0 - D0 set to 1 selects: page 1 D0 is set to the value of 0, during power on or any reset. CSR register: provide a power control of memory array. Only bit D2 is supported; all other bits are “don’t care” PwrDwn Writing 1 to PwrDwn bit (D2) forces each memory device on the card into a reset/power down mode by asserting all the devices RP# pins. Writing 0 to the bit returns the array to stand by mode. Card Information Structure (CIS) contains information about Registers addressing and Memory structure. Cards with memory capacity < 64MB do not support Configuration Index bits. Notes: 1. Reading from undefined address location or unsupported bits will return random data. 2. Writing to undefined address location may result in card malfunctioning due to limited address decoding. 3. See block diagram for more details about control registers. August 2000 Rev. 4 - ECO #13130 5 PC Card Products PCMCIA Flash Memory Card FLF Series Absolute Maximum Ratings (2) Operating Temperature TA (ambient) Commercial Storage Temperature Voltage on any pin relative to VSS VCC supply Voltage relative to VSS Note: Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 0°C to +60 °C -10°C to +70 °C -0.5V to VCC+0.5V -0.5V to +7.0V DC Characteristics (1) Symbol Parameter ICCR VCC Read Current ICCW ICCE ICCD (3) Density Notes Typ (Mbytes) 16,32,48,64,80 70 Max Units Test Conditions 110 mA VCC Program Current VCC Erase Current 16,32,48,64,80 70 120 mA VCC = VCCmax tcycle = 200ns 2 memory devices 16,32,48,64,80 70 140 mA 2 memory devices VCC Power-down Current 16 32 48 64 80 16 32 48 64 80 160 320 480 650 800 0.2 0.4 0.6 0.8 1.0 250 µA 500 750 1000 1250 0.4 mA 0.7 1.0 1.3 1.6 ICCS VCC Standby (CMOS) Current 2 2 VCC = VCCmax Control Signals = VCC Reset = VCC (active) VCC = VCCmax Control Signals = VCC Reset = 0V (not active) CMOS Test Conditions: VCC = 5V ± 5%, VIL = VSS ± 0.2V, VIH = VCC ± 0.2V Notes: 1. All currents are RMS values unless otherwise specified. ICCR, ICCW and ICCE are based on Word wide operations (2 memory devices activated). 2. Control Signals: CE1#, CE2#, OE#, WE#. 3. Typical: VCC = 5V, T = +25°C. Symbol Parameter Notes Min Max Units Test Conditions ILI Input Leakage Current 1, 2 ±20 µA 1 ±20 µA VCC = VCCMAX Vin =VCC or GND VCC = VCCMAX Vin =VCC or GND ILO VIL Output Leakage Current Input Low Voltage 1 0.8 V VIH Input High Voltage 1 VOL Output Low Voltage 1 VOH Output High Voltage 1 VCC-0.4 VLKO VCC Erase/Program Lock Voltage 1 3.25 0 0.7xVCC VCC+0.5 V 0.4 V IOL = 3.2mA VCC V IOH = -2.0mA V Notes: 1. Values are the same for byte and word wide modes for all card densities. 2. Exception: Leakage current on control signals with internal pull up resistors (see block diag) will be < 500µA when VIN=GND. August 2000 Rev. 4 - ECO #13130 6 PC Card Products PCMCIA Flash Memory Card FLF Series AC Characteristics Read Timing Parameters 200ns Parameter Min 250ns SYMBOL (PCMCIA) tC(R) Max Read Cycle Time ta(A) Address Access Time 200 250 ns ta(CE) Card Enable Access Time 200 250 ns ta(OE) Output Enable Access Time 90 100 ns tsu(A) Address Setup Time 20 30 ns tsu(CE) Card Enable Setup Time 0 0 ns th(A) Address Hold Time 20 20 ns th(CE) Card Enable Hold Time 20 20 ns tv(A) 0 0 ns tdis(CE) Output Hold from Address Change Output Disable Time from CE# 90 100 ns tdis(OE) Output Disable Time from OE# 90 100 ns ten(CE) Output Enable Time from CE# 5 5 ns ten(OE) Output Enable Time from OE# 5 5 ns trec(RST) Power Down recovery to Output Delay. VCC = 5V 200 Min Max Unit 250 500 ns 500 ns Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications. Read Timing Diagram tc(R ) th(A ) ta(A ) A [2 5::0], /R E G tv(A ) ta(C E ) /C E 1, /C E 2 tsu(C E ) NOTE 1 NOTE 1 tsu(A ) ta (O E ) th(C E ) td is(C E ) /O E td is(O E ) ten(O E ) D [15 ::0] August 2000 Rev. 4 - ECO #13130 D A TA V A LID 7 PC Card Products PCMCIA Flash Memory Card FLF Series Write Timing Parameters 200ns Parameter Min 250ns SYMBOL (PCMCIA) tCW Max Min Max Unit Write Cycle Time 200 250 ns tw(WE) Write Pulse Width 120 150 ns tsu(A) Address Setup Time 20 30 ns tsu(A-WEH) Address Setup Time for WE# 140 180 ns tsu(CE-WEH) Card Enable Setup Time for WE# 140 180 ns tsu(D-WEH) Data Setup Time for WE# 60 80 ns th(D) Data Hold Time 30 30 ns trec(WE) Write Recover Time/Address hold 30 30 ns tdis(WE) Output Disable Time from WE# 90 100 ns tdis(OE) Output Disable Time from OE# 90 100 ns ten(WE) Output Enable Time from WE# 5 5 ns ten(OE) Output Enable Time from OE# 5 5 ns tsu(OE-WE) Output Enable Setup from WE# 10 10 ns th(OE-WE) Output Enable Hold from WE# 50 50 ns tsu(CE) Card Enable Setup Time from OE# 0 0 ns th(CE) Card Enable Hold Time 20 20 ns trec(WEL) Reset recovery to WE going low 1 1 µs Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications. Write Timing Diagram tc(W) A[25::0], /REG tsu(A-WEH) trec(WE) tsu(CE-WEH) th(CE) tsu(CE) /CE1, /CE2 NOTE 1 NOTE 1 /OE th(OE-WE) tw(WE) tsu(A) /WE th(D) tsu(OE-WE) D[15::0](Din) tsu(D-WEH) NOTE 2 DATA INPUT tdis(WE) tdis(OE) ten(OE) ten(WE) D[15::0]( Dout) August 2000 Rev. 4 - ECO #13130 NOTE 2 8 PC Card Products PCMCIA Flash Memory Card FLF Series Data Write and Erase Performance (1,3) VCC = 5V ± 5%, TA = 0C to + 70C SYM Parameter tWHQV1 Word/Byte Program time tWHQV3 Byte Program Time (using Byte program command) Block Program Time (using write to buffer command) Block Erase Time tWHQV4 tWHRH Notes Min 2,4 (1) Typ Max Units Test Conditions 6 µs 120 µs 2 0.8 sec 2 1.0 sec Erase Suspend Latency Time to Read 25 35 Effective time per Byte (using Write Buffer) Word Program Mode µs Notes: 1. Typical: Nominal voltages and TA = 25C. 2. Excludes system overhead. 3. Valid for all speed options. 4. To maximize system performance RDY/BSY# signal should be polled. Waveforms for Reset Operation Write Operation WE# Read Operation Valid Output trec(RST) tWHQV tWHRH trec(WEL) RST tWHRL tw(RST) P2 RDY/BSY SYMBOL tw(RST) P2 trec(RST) Parameter Min Reset pulse High time RST Low to reset during Erase/Program/Lock-bit Reset Low to output delay Reset Recovery to WE going Low tWHRL WE High to Rdy/Bsy going low 9 Unit µs 35 trec(WEL) August 2000 Rev. 4 - ECO #13130 Max 100 ns 500 ns µs 1 100 ns PC Card Products PCMCIA Flash Memory Card FLF Series PRODUCT MARKING WED 7P016FLF0200C15 C995 9915 EDI Date code Lot code / trace number Part number Company Name Note: Some products are currently marked with our pre-merger company name/acronym (EDI). During our transition period, some products will also be marked with our new company name/acronym (WED). Starting October 2000 all PCMCIA products will be marked only with the WED prefix. PART NUMBERING 7 P 016 FLF02 00 C 15 Card access time 15 25 150ns 250ns Temperature range C Commercial 0°C to +70°C I Industrial -40°C to +85°C Packaging option 00 Standard, type 1 Card family and version - See Card Family and Version Info. for details (next page) Card capacity 016 16MB PC card P R Standard PCMCIA Ruggedized PCMCIA Card technology 7 8 August 2000 Rev. 4 - ECO #13130 FLASH SRAM 10 PC Card Products PCMCIA Flash Memory Card FLF Series CIS data for 16-64MB cards based on Intel 28F640J5 Address Value 00H 01H 02H 03H 04H 51H 06H Description Address Value Description CISTPL_DEVICE TPL_LINK 4EH 50H 03H CISTPL_CFTABLE_ENTRY TPL_LINK 52H 00H TPCE_INDEX 3EH FLASH = 250ns (device writable) CARD SIZE: 16MB 54H 00H 7EH 32MB 56H FFH BEH 48MB 58H 15H FEH 64MB 5AH 08H FFH END OF TUPLE 0AH 18H 0CH 03H 0EH 12H INTEL - ID 89H 28F640J5 15H INTEL ID END OF TUPLE FFH 66H 37H 7 14H 17H 68H 50H 16H 18H 1AH 10H 1BH Address Value Description TPCE_FS (no selection) A4H A6H A8H AAH ACH 54H 52H 4FH 4EH 49H T R O N I END OF TUPLE AEH 43H C CISTPL_VERS1 TPL_LINK B0H 20H SPACE 47H B2H 44H D 5CH 05H TPLLV1_MAJOR B4H 45H E CISTPL_JEDEC_C 5EH 00H TPLLV1_MINOR B6H 53H S TPL_LINK 60H 45H E B8H 49H I 62H 44H D BAH 47H G 64H 49H I BCH 4EH N BEH 53H S P C0H C2H 20H 49H SPACE I 4EH N 03H CISTPL_DEVICE_A TPL_LINK 6AH 30H 0 C4H 42H EEPROM - 200ns 6CH 34H 4 C6H 43H C 01H Device Size = 2KBytes END OF TUPLE FFH 6EH 38H 8 C8H 4FH O 70H 46H F CAH 52H R 72H 4CH L CCH 50H P 20H 1EH CISTPL_DEVICEGEO TPL_LINK 07H 74H 46H F CEH 4FH O 22H 02H DGTPL_BUS 76H 30H 0 D0H 52H R 24H 12H DGTPL_EBS 78H 32H 2 D2H 41H A 26H 01H DGTPL_RBS 7AH 2DH - D4H 54H T 1CH 1EH 28H 01H DGTPL_WBS 7CH 2DH - D6H 45H E 2AH 01H DGTPL_PART 7EH 2DH - D8H 44H D 2CH 01H FLASH DEVICE 80H 32H 2 DAH 20H SPACE NON-INTERLEAVED 82H 35H 5 DCH 00H END TEXT 84H 20H SPACE DEH 31H 1 86H 00H END TEXT E0H 39H 9 43H C E2H 39H 9 E4H 38H 8 2EH FFH END OF TUPLE 30H 20H CISTPL_MANFID TPL_LINK(04H) 32H 34H 05H 88H 8AH 4FH O 8CH 50H P 8EH 59H Y 90H 52H R 92H 49H I 3CH F6H EDI TPLMID_MANF: LSB 01H EDI TPLMID_MANF: MSB 00H LSB: Number Not Assigned 00H MSB: Number Not Assigned END OF TUPLE FFH 3EH 1AH CISTPL_CONF 94H 47H G 40H 06H TPL_LINK 96H 48H H 42H 01H TPCC_SZ 98H 54H T 44H 00H TPCC_LAST 9AH 20H SPACE 46H 00H TPCC_RADR 9CH 45H E 48H 40H TPCC_RADR 9EH 4CH L 4AH 03H TPCC_RMSK A0H 45H E 36H 38H 3AH August 2000 Rev. 4 - ECO #13130 11 E6H 00H END TEXT E8H FFH END OF LIST EAH FFH PC Card Products PCMCIA Flash Memory Card FLF Series CIS data for 80MB card based on Intel 28F640J5 Address Value 00H 01H 02H 03H 04H 51H 06H FEH 08H Description CISTPL_DEVICE TPL_LINK Address Value 50H 20H 52H 04H Description CISTPL_MANFID TPL_LINK(04H) 54H F6H 56H 01H FFH FLASH = 250ns (device writable) CARD SIZE: 64MB(1st page) END OF TUPLE 58H 00H 0AH 09H CISTPL_EXTDEVICE 5AH 00H 0CH 06H TPL_LINK 5CH 15H 0EH 04H 5EH 47H 10H 51H Mem Paging Info: 1bit/COR/64M FLASH = 250ns EDI TPLMID_MANF: LSB EDI TPLMID_MANF: MSB LSB: Number Not Assigned MSB: Number Not Assigned CISTPL_VERS1 TPL_LINK 60H 05H 12H 14H 07H 01H Device Size Extender 1x64MB 62H 64H 00H 45H Address Value A0H 45H A2H 4CH A4H 45H A6H 43H A8H 54H AAH 52H Description E L E C T R ACH 4FH O AEH 4EH N B0H 49H I B2H 43H C B4H 20H SPACE TPLLV1_MAJOR B6H 44H D TPLLV1_MINOR B8H 45H E E BAH 53H S BCH BEH 49H 47H I G C0H 4EH N C2H 53H S C4H 20H SPACE C6H 49H I 4EH N 16H 3EH +16MB 66H 44H D 18H FFH END OF TUPLE 68H 49H I 1AH 1CH 1AH 06H CISTPL_CONF TPL_LINK 6AH 6CH 37H 50H 7 P 1EH 20H 01H 00H 6EH 70H 30H 38H 0 8 72H 30H 0 CAH 43H C 4FH O R 22H 00H TPCC_SZ TPCC_LAST(no index descript) TPCC_RADR: LSByte 24H 26H 40H 03H TPCC_RADR: MSByte TPCC_RMSK: 2 Reg 74H 76H 46H 4CH F L CCH CEH 52H 28H FFH END OF TUPLE 78H 46H F D0H 50H P 2AH 18H 7AH 30H 0 D2H 4FH O 2CH 03H CISTPL_JEDEC_C TPL_LINK 7CH 32H 2 D4H 52H R 2EH 89H INTEL - ID 7EH 2DH - D6H 41H A 30H 32H 28F640J5 - ID 15H INTEL END OF TUPLE FFH 80H 82H 2DH 2DH - D8H 54H T DAH 45H E 34H 17H 84H 32H 2 DCH 44H D 36H 03H 86H 35H 5 DEH 20H SPACE CISTPL_DEVICE_A TPL_LINK C8H 38H 42H EEPROM - 200ns 88H 20H SPACE E0H 00H END TEXT 3AH 01H Device Size = 2KBytes 8AH 00H END TEXT E2H 31H 1 3CH FFH END OF TUPLE 8CH 43H C E4H 39H 9 3EH 1EH 4FH O E6H 39H 9 07H CISTPL_DEVICEGEO TPL_LINK 8EH 40H 90H 50H P E8H 38H 8 42H 02H DGTPL_BUS 92H 59H Y EAH 00H END TEXT 44H 12H DGTPL_EBS 94H 52H R ECH FFH END OF LIST 46H 01H DGTPL_RBS 96H 49H I EEH FFH CISTPL_END 48H 4AH 01H 01H DGTPL_WBS DGTPL_PART 98H 9AH 47H 48H G H D2H FFH 4CH 01H 9CH 9EH 54H 20H T SPACE 4EH FFH FLASH DEVICE NON-INTERLEAVED END OF TUPLE August 2000 Rev. 4 - ECO #13130 12 PC Card Products PCMCIA Flash Memory Card FLF Series Date of revision 20-Mar-98 27-May-99 5-Jun-00 1-Aug-00 REVISION HISTORY Version Description -001 Initial release -002 Logo change -003 Added Page 10, changed page header -004 Corrected timing errors on pgs. 7&8 White Electronic Designs Corporation One Research Drive, Westborough, MA 01581, USA tel: (508) 366 5151 fax: (508) 836 4850 www.whiteedc.com August 2000 Rev. 4 - ECO #13130 13 PC Card Products