EL8200, EL8201, EL8401 ® Data Sheet March 9, 2006 200MHz Rail-to-Rail Amplifiers Features The EL8200, EL8201, and EL8401 represent rail-to-rail amplifiers with a -3dB bandwidth of 200MHz and slew rate of 200V/µs. Running off a very low supply current of 2mA per channel, the EL8200, EL8201, and EL8401 also feature inputs that go to 0.15V below the VS- rail. The EL8200 and EL8201 are dual channel amplifiers. The EL8401 is a quad channel amplifier. • 200MHz -3dB bandwidth The EL8200 includes a fast-acting disable/power-down circuit. With a 25ns disable and a 200ns enable, the EL8200 is ideal for multiplexing applications. • Input to 0.15V below VS- The EL8200, EL8201, and EL8401 are designed for a number of general purpose video, communication, instrumentation, and industrial applications. The EL8200 is available in a 10 Ld MSOP package, the EL8201 in an 8 Ld SO package, and the EL8401 in a 14 Ld SO and 16 Ld QSOP packages. All are specified for operation over the -40°C to +85°C temperature range. FN7105.3 • 200V/µs slew rate • Low supply current = 2mA per channel • Supplies from 3V to 5.5V • Rail-to-rail output • Fast 25ns disable (EL8200 only) • Low cost • Pb-free available Applications • Video amplifiers • Portable/hand-held products • Communications devices Pinouts EL8200 (10 LD MSOP) TOP VIEW EL8201 (8 LD SO) TOP VIEW OUTA 1 INA- 2 + INA+ 3 + VS- 4 8 VS+ INA+ 1 7 OUTB CEA 2 6 INB- VS- 3 5 INB+ CEB 4 10 INA+ 8 VS+ + - INB+ 5 INA- 2 14 OUTD A - + D + - INA+ 3 VS+ 4 INB- 6 - + B + C OUTB 7 INA- 2 12 IND+ INA+ 3 16 OUTD - + + - INB+ 5 9 INC- INB- 6 OUTB 7 NC 8 15 IND14 IND+ VS+ 4 10 INC+ 8 OUTC 1 6 INB- OUTA 1 13 IND- 11 VS- INB+ 5 7 OUTB EL8401 (16 LD QSOP) TOP VIEW EL8401 (14 LD SO) TOP VIEW OUTA 1 9 OUTA 13 VS12 INC+ - + + - 11 INC10 OUTC 9 NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004, 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL8200, EL8201, EL8401 Ordering Information PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. # EL8200IY j - 10 Ld MSOP MDP0043 EL8200IY-T7 j 7” 10 Ld MSOP MDP0043 EL8200IY-T13 j 13” 10 Ld MSOP MDP0043 EL8200IYZ (See Note) BAMAA - 10 Ld MSOP (Pb-free) MDP0043 EL8200IYZ-T7 (See Note) BAMAA 7” 10 Ld MSOP (Pb-free) MDP0043 EL8200IYZ-T13 (See Note) BAMAA 13” 10 Ld MSOP (Pb-free) MDP0043 EL8201IS 8201IS - 8 Ld SO MDP0027 EL8201IS-T7 8201IS 7” 8 Ld SO MDP0027 EL8201IS-T13 8201IS 13” 8 Ld SO MDP0027 EL8201ISZ (See Note) 8201ISZ - 8 Ld SO (Pb-free) MDP0027 EL8201ISZ-T7 (See Note) 8201ISZ 7” 8 Ld SO (Pb-free) MDP0027 EL8201ISZ-T13 (See Note) 8201ISZ 13” 8 Ld SO (Pb-free) MDP0027 EL8401IS 8401IS - 14 Ld SO MDP0027 EL8401IS-T7 8401IS 7” 14 Ld SO MDP0027 EL8401IS-T13 8401IS 13” 14 Ld SO MDP0027 EL8401ISZ (See Note) 8401ISZ - 14 Ld SO (Pb-free) MDP0027 EL8401ISZ-T7 (See Note) 8401ISZ 7” 14 Ld SO (Pb-free) MDP0027 EL8401ISZ-T13 (See Note) 8401ISZ 13” 14 Ld SO (Pb-free) MDP0027 EL8401IU 8401IU - 16 Ld QSOP MDP0040 EL8401IU-T7 8401IU 7” 16 Ld QSOP MDP0040 EL8401IU-T13 8401IU 13” 16 Ld QSOP MDP0040 EL8401IUZ (See Note) 8401IUZ - 16 Ld QSOP (Pb-free) MDP0040 EL8401IUZ-T7 (See Note) 8401IUZ 7” 16 Ld QSOP (Pb-free) MDP0040 EL8401IUZ-T13 (See Note) 8401IUZ 13” 16 Ld QSOP (Pb-free) MDP0040 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. 2 FN7105.3 March 9, 2006 EL8200, EL8201, EL8401 Absolute Maximum Ratings (TA = 25°C) Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Supply Voltage from VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS+ +0.3V to VS- -0.3V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = 5V, VS- = GND, TA = 25°C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified DESCRIPTION CONDITIONS MIN TYP MAX UNIT -6 -0.8 +6 mV INPUT CHARACTERISTICS VOS Offset Voltage TCVOS Offset Voltage Temperature Coefficient Measured from TMIN to TMAX IB Input Bias Current VIN = 0V IOS Input Offset Current VIN = 0V TCIOS Input Bias Current Temperature Coefficient Measured from TMIN to TMAX CMRR Common Mode Rejection Ratio VCM = -0.15V to +3.5V (EL8200,EL8201) VCM = -0.15V to +3.5V (EL8401) CMIR Common Mode Input Range RIN Input Resistance CIN Input Capacitance AVOL Open Loop Gain -2.5 3 µV/°C -1.6 µA 0.2 0.55 µA 2 nA/°C 70 90 dB 65 90 dB VS- -0.15 Common Mode VS+ -1.5 V 16 MΩ 0.5 pF 90 dB VOUT = +1.5V to +3.5V, RL = 150Ω to GND 80 dB 30 mΩ VOUT = +1.5V to +3.5V, RL = 1kΩ to GND 75 OUTPUT CHARACTERISTICS ROUT Output Resistance AV = +1 VOP Positive Output Voltage Swing RL = 1kΩ 4.85 4.9 V RL = 150Ω 4.6 4.7 V VON Negative Output Voltage Swing RL = 150Ω 100 150 mV RL = 1kΩ 35 50 mV IOUT Linear Output Current 65 mA ISC (source) Short Circuit Current RL = 10Ω 60 70 mA ISC (sink) Short Circuit Current RL = 10Ω 100 130 mA VS+ = 4.5V to 5.5V 70 100 dB POWER SUPPLY PSRR Power Supply Rejection Ratio IS-ON Supply Current 2 2.4 mA IS-OFF Supply Current - Disabled per Amplifier EL8200 only 40 90 µA ENABLE (EL8200 ONLY) tEN Enable Time 200 ns tDS Disable Time 25 ns VIH-ENB ENABLE Pin Voltage for Power-up 0.8 V 3 FN7105.3 March 9, 2006 EL8200, EL8201, EL8401 Electrical Specifications PARAMETER VS+ = 5V, VS- = GND, TA = 25°C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified (Continued) DESCRIPTION CONDITIONS VIL-ENB ENABLE Pin Voltage for Shut-down IIH-ENB IIL-ENB MIN TYP MAX UNIT 2 V ENABLE Pin Input Current High 8.6 µA ENABLE Pin Input for Current Low 0.01 µA AV = +1, RF = 0Ω, CL = 1.5pF 200 MHz AV = -1, RF = 1kΩ, CL = 1.5pF 90 MHz AV = +2, RF = 1kΩ, CL = 1.5pF 90 MHz AV = +10, RF = 1kΩ, CL = 1.5pF 10 MHz AC PERFORMANCE BW -3dB Bandwidth BW ±0.1dB Bandwidth AV = +1, RF = 0Ω, CL = 1.5pF 20 MHz Peak Peaking AV = +1, RF = 1kΩ, CL = 1.5pF 1 dB GBWP Gain Bandwidth Product 100 MHz PM Phase Margin RL = 1kΩ, CL = 1.5pF 55 ° SR Slew Rate AV = 2, RL = 100Ω, VOUT = 0.5V to 4.5V 200 V/µs tR Rise Time 2.5VSTEP, 20% - 80% 8 ns tF Fall Time 2.5VSTEP, 20% - 80% 7 ns OS Overshoot 200mV step 10 % tPD Propagation Delay 200mV step 2 ns tS 0.1% Settling Time 200mV step 20 ns dG Differential Gain AV = +2, RF = 1kΩ, RL = 150Ω 0.035 % dP Differential Phase AV = +2, RF = 1kΩ, RL = 150Ω 0.05 ° eN Input Noise Voltage f = 10kHz 10 nV/√Hz iN+ Positive Input Noise Current f = 10kHz 1 pA/√Hz iN- Negative Input Noise Current f = 10kHz 0.8 pA/√Hz eS Channel Separation f = 100kHz 95 dB 160 Pin Descriptions EL8200 EL8201 EL8401 (SO-14) EL8401 (QSOP-16) NAME 1, 5 3, 5 3, 5, 10, 12 3,5,12,14 IN+ Non-inverting input for each channel CE Enable and disable input for each channel 2, 4 FUNCTION 3 4 11 13 VS- Negative power supply 6, 10 2, 6 2, 6, 9, 13 2,6,11,15 IN- Inverting input for each channel 7, 9 1, 7 1, 7, 8, 14 1,7,10,16 OUT Amplifier output for each channel 8 8 4 4 VS+ Positive power supply 4 FN7105.3 March 9, 2006 EL8200, EL8201, EL8401 Typical Performance Curves 4 4 2 VOP-P=200mV GAIN (dB) GAIN (dB) 2 VS=5V AV=1 RL=1kΩ CL=1.5pF 0 VOP-P=1V -2 10M 0 RL=1kΩ -2 -4 -4 1M RL=330Ω RL=100Ω VOP-P=2V -6 100K VS=5V AV=1 CL=1.5pF 100M -6 100K 1G 1M 10M FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGE LEVELS FIGURE 2. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS RLOAD 4 VS=5V RL=1kΩ CL=1.5pF NORMALIZED GAIN (dB) 4 NORMALIZED GAIN (dB) 1G FREQUENCY (Hz) FREQUENCY (Hz) 2 100M AV=1 AV=2 0 -2 AV=5 -4 AV=10 -6 100K 1M 10M 100M 2 VS=5V RL=1kΩ CL=1.5pF RF=1kΩ 0 AV=-2 -2 AV=-10 -4 -6 100K 1G AV=-5 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS NON-INVERTING GAINS FIGURE 4. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS INVERTING GAINS 14 5 3 CL=10pF 12 CL=7pF 10 CL=56pF CL=35pF CL=5pF 1 CL=1.5pF -1 -3 GAIN (dB) GAIN (dB) 8 1M -2 -4 10M 100M 1G FREQUENCY (Hz) FIGURE 5. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS CL 5 CL=15pF 2 0 VS=5V AV=1 RL=1kΩ VOP-P=200mV -5 100K 6 4 VS=5V AV=2 RL=1kΩ RF=RG=1kΩ -6 100K 1M CL=1.5pF 10M 100M 1G FREQUENCY (Hz) FIGURE 6. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS CL FN7105.3 March 9, 2006 EL8200, EL8201, EL8401 Typical Performance Curves (Continued) 110 10 405 RL=1kΩ 70 8 RF=RG=500Ω 2 VS=5V AV=2 RL=1kΩ CL=1.5pF 0 100K 30 225 RL=150Ω -10 RL=1kΩ -50 1M 10M 100M 1G 135 -90 1K 10K PHASE (°) GAIN (dB) GAIN (dB) 6 4 315 RL=150Ω RF=RG=1kΩ RF=RG=2kΩ 45 100K 10M 1M 100M -45 1G FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 7. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS RF AND RG FIGURE 8. OPEN LOOP GAIN AND PHASE vs FREQUENCY -10 230 -30 190 BANDWIDTH (MHz) CMRR (dB) 210 -50 -70 -90 AV=1 170 150 130 110 90 RL=1kΩ CL=1.5pF 70 AV=2 50 -110 100K 1M 10M 3 100M 3.5 4.5 4 5 5.5 VS (V) FREQUENCY (Hz) FIGURE 9. COMMON-MODE REJECTION RATIO vs FREQUENCY FIGURE 10. SMALL SIGNAL BANDWIDTH vs SUPPLY VOLTAGE 2.5 100 PEAKING (dB) IMPEDANCE (Ω) 2 10 1 0.1 0.01 10K 1.5 1 AV=1 RL=1kΩ CL=1.5pF 0.5 0 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 11. OUTPUT IMPEDANCE vs FREQUENCY 6 3 3.5 4 4.5 5 5.5 VS (V) FIGURE 12. SMALL SIGNAL PEAKING vs SUPPLY VOLTAGE FN7105.3 March 9, 2006 EL8200, EL8201, EL8401 -10 -45 -30 -55 DISTORTION (dBc) PSRR (dB) Typical Performance Curves (Continued) PSRR- -50 -70 PSRR+ VS=5V RL=1kΩ CL=1.5pF AV=2 @ HD2 -65 HD -75 z HD2@5MH MHz @10 HD3 3@5MHz 1 HD2@ -85 -90 z 10MH MHz HD3@1MHz -95 -110 1K 100K 10K 1M 10M 2 1 100M 3 FREQUENCY (Hz) -10 VS=5V RL=1kΩ VO=1VP-P for AV=1 VO=2VP-P for AV=2 -40 DISTORTION (dBc) GAIN (dB) -30 VS=5V AV=1 RL=1kΩ CL=1.5pF -50 -70 -50 -60 -70 HD -80 2@ -90 -90 100K 10K 1M 10M 100M =1 AV 2 A V= 3@ HD HD3@AV=1 40 10 FREQUENCY (MHz) FIGURE 15. DISABLED OUTPUT ISOLATION FREQUENCY RESPONSE FIGURE 16. HARMONIC DISTORTION vs FREQUENCY 1K -60 HD -70 -75 HD -80 3@ AV = AV =2 VOLTAGE NOISE (nV/√Hz) CURRENT NOISE (pA/√Hz) H D 2@ -65 DISTORTION (dBc) HD 1 1G FREQUENCY (Hz) 2 HD2@A =1 V 3@ A V= 1 -85 -95 =2 AV 2@ -100 -110 1K -90 5 FIGURE 14. HARMONIC DISTORTION vs OUTPUT VOLTAGE FIGURE 13. POWER SUPPLY REJECTION RATIO vs FREQUENCY -30 4 VOP-P (V) VS=5V VO=1VP-P for AV=1 VO=2VP-P for AV=2 -100 100 1K 2K RLOAD (Ω) FIGURE 17. HARMONIC DISTORTION vs LOAD RESISTANCE 7 100 eN 10 IN+ 1 IN0.1 10 100 1K 10K 100K 1M 10M FREQUENCY (Hz) FIGURE 18. VOLTAGE AND CURRENT NOISE vs FREQUENCY FN7105.3 March 9, 2006 EL8200, EL8201, EL8401 0 0 -10 -10 CHANNEL SEPARATION (dB) CHANNEL SEPARATION (dB) Typical Performance Curves (Continued) -20 -30 -40 -50 CH1 <=> CH2 -60 -70 -80 -90 -100 100K 1M 10M 100M 1G -20 -30 -40 -50 CH1 <=> CH2 CH3 <=> CH4 -60 -70 -80 CH1 <=> CH3, CH4 CH2 <=> CH3, CH4 -90 -100 100K 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 19. CHANNEL SEPARATION vs FREQUENCY (EL8200 AND EL8201) 1M FIGURE 20. CHANNEL SEPARATION vs FREQUENCY (EL8401) VS=5V, AV=5, RL=1kΩ to 2.5V VS=5V, AV=1, RL=1kΩ to 2.5V 5 5 2.5 2.5 0 0 10ns/DIV 2µs/DIV FIGURE 21. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 22. OUTPUT SWING VS=5V, AV=1, RL=1kΩ to 2.5V CL=1.5pF VS=5V, AV=5, RL=1kΩ to 2.5V 5 2.6 2.5 2.5 2.4 0 10ns/DIV FIGURE 23. SMALL SIGNAL TRANSIENT RESPONSE 8 2µs/DIV FIGURE 24. OUTPUT SWING FN7105.3 March 9, 2006 EL8200, EL8201, EL8401 Typical Performance Curves (Continued) VS=±2.5V, AV=1, RL=1kΩ VS=±2.5V, AV=1, RL=1kΩ CH1 ENABLE INPUT ENABLE INPUT CH1 CH2 CH2 VOUT OUTPUT CH1, CH2, 1V/DIV, M=100ns CH1, CH2, 0.5V/DIV, M=20ns FIGURE 26. ENABLED RESPONSE (EL8200) FIGURE 25. DISABLED RESPONSE (EL8200) 1.136W 1.2 1 909mW θ JA 0.8 893mW 870mW MSOP10 θJA=115°C/W 0.6 0.4 SO =8 14 8° C/ W SO8 θJA=110°C/W QSOP16 θJA=112°C/W 0.2 0 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.4 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1 0.9 833mW 0.8 0.3 25 75 85 100 50 125 150 JA SO =1 14 20 °C /W MSOP10 θJA=206°C/W 0.2 SO8 θJA=160°C/W QSOP16 θJA=158°C/W 0.1 0 0 θ 0.7 625mW 0.6 633mW 0.5 0.4 486mW 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Simplified Schematic Diagram VS+ I1 I2 Q5 IN+ Q1 R8 VBIAS1 Q6 R3 R1 R7 R6 Q7 R2 Q2 DIFFERENTIAL TO SINGLE ENDED DRIVE GENERATOR IN- VBIAS2 Q3 OUT Q4 Q8 R4 R5 R9 VS- 9 FN7105.3 March 9, 2006 EL8200, EL8201, EL8401 Description of Operation and Application Information Product Description The EL8200, EL8201 and EL8401 are wide bandwidth, single supply, low power and rail-to-rail output voltage feedback operational amplifiers. The amplifiers are internally compensated for closed loop gain of +1 of greater. Connected in voltage follower mode and driving a 1kΩ load, they have a -3dB bandwidth of 200MHz. Driving a 150Ω load, the bandwidth is about 130MHz while maintaining a 200V/us slew rate. The EL8200 is available with a power down pin to reduce power to 30µA typically while the amplifier is disabled. Input, Output and Supply Voltage Range The EL8200, EL8201 and EL8401 have been designed to operate with a single supply voltage from 3V to 5.0V. Split supplies can also be used as long as their total voltage is within 3V to 5.0V. The amplifiers have an input common mode voltage range from 0.15V below the negative supply (VS- pin) to within 1.5V of the positive supply (VS+ pin). If the input signal is outside the above specified range, it will cause the output signal to be distorted. The output of the EL8200, EL8201 and EL8401 can swing rail to rail. As the load resistance becomes lower, the ability to drive close to each rail is reduced. For the load resistor 1kΩ, the output swing is about 4.9V at a 5V supply. For the load resistor 150Ω, the output swing is about 4.6V. Choice of Feedback Resistor and Gain Bandwidth Product For applications that require a gain of +1, no feedback resistor is required. Just short the output pin to the inverting input pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier’s phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few Pico farad range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. As far as the output stage of the amplifier is concerned, the output stage is also a gain stage with the load. RF and RG appear in parallel with RL for gains other than +1. As this combination gets smaller, the bandwidth falls off. Consequently, RF also has a minimum value that should not be exceeded for optimum performance. For gain of +1, RF=0 is optimum. For the gains other than +1, optimum response is obtained with RF between 300Ω to 1kΩ. 10 The EL8200, EL8201 and EL8401 have a gain bandwidth product of 100MHz. For gains ≥5, its bandwidth can be predicted by the following equation: Gain × BW = 100MHz Video Performance For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150Ω, because the change in output current with DC level. Special circuitry has been incorporated in the EL8200, EL8201 and EL8401 to reduce the variation of the output impedance with the current output. This results in dG and dP specifications of 0.03% and 0.05°, while driving 150Ω at a gain of 2. Driving high impedance loads would give a similar or better dG and dP performance. Driving Capacitive Loads and Cables The EL8200, EL8201 and EL8401 can drive 10pF loads in parallel with 1kΩ with less than 5dB of peaking at gain of +1. If less peaking is desired in applications, a small series resistor (usually between 5Ω to 50Ω) can be placed in series with the output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier’s output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. Disable/Power-Down The EL8200 can be disabled and placed its output in a high impedance state. The turn off time for each channel is about 25ns and the turn on time is about 200ns. When disabled, the amplifier’s supply current is reduced to 30µA typically, thereby effectively eliminating the power consumption. The amplifier’s power down can be controlled by standard TTL or CMOS signal levels at the ENABLE pin. The applied logic signal is relative to VS- pin. Letting the ENABLE pin float or applying a signal that is less than 0.8V above VS- will enable the amplifier. The amplifier will be disabled when the signal at ENABLE pin is 2V above VS-. Output Drive Capability The EL8200, EL8201 and EL8401 do not have internal short circuit protection circuitry. They have a typical short circuit current of 70mA sourcing and 140mA sinking for the output is connected to half way between the rails with a 10Ω resistor. If the output is shorted indefinitely, the power FN7105.3 March 9, 2006 EL8200, EL8201, EL8401 dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds ±40mA. This limit is set by the design of the internal metal interconnections. Power Dissipation With the high output drive capability of the EL8200, EL8201 and EL8401, it is possible to exceed the 125°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX – T AMAX PD MAX = -------------------------------------------θ JA normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier’s inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. Typical Applications Where: VIDEO SYNC PULSE REMOVER TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature θJA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: For sourcing: V OUTi PD MAX = V S × I SMAX + Σ ( V S – V OUTi ) × ----------------R Li For sinking: PD MAX = V S × I SMAX + Σ ( V OUTi – V S - ) × I LOADi Where: VS = Total supply voltage ISMAX = Maximum quiescent supply current VOUTi = Maximum output voltage of the application for each channel RLOADi = Load resistance tied to ground for each channel ILOADi = Load current for each channel By setting the two PDMAX equations equal to each other, we can solve the output current and RLOADi to avoid the device overheat. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For 11 Many CMOS analog to digital converters have a parasitic latch up problem when subjected to negative input voltage levels. Since the sync tip contains no useful video information and it is a negative going pulse, we can chop it off. Figure 29 shows a gain of 2 connections. Figure 30 shows the complete input video signal applied at the input, as well as the output signal with the negative going sync pulse removed. MULTIPLEXER Besides the normal power down usage, the ENABLE pin of the EL8200 can be used for multiplexing applications. Figure 31 shows two channels with the outputs tied together, driving a back terminated 75Ω video load. A 2VP-P 2MHz sine wave is applied to Amp A and a 1VP-P 2MHz sine wave is applied to Amp B. Figure 32 shows the ENABLE signal and the resulting output waveform at VOUT. Observe the break-before-make operation of the multiplexing. Amp A is on and VIN1 is passed through to the output when the ENABLE signal is low and turns off in about 25ns when the ENABLE signal is high. About 200ns later, Amp B turns on and VIN2 is passed through to the output. The break-beforemake operation ensures that more than one amplifier isn’t trying to drive the bus at the same time. 5V VIN + 75Ω VS+ 75Ω VS- VOUT 75Ω 1K 1K FIGURE 29. SYNC PULSE REMOVER FN7105.3 March 9, 2006 EL8200, EL8201, EL8401 set the AC gain. C2 isolates the virtual ground potential. RT and R3 are the termination resistors for the line. C1, C2 and C3 are selected big enough to minimize the droop of the luminance signal. 1V 0.5V VIN 0V 5V 1V VIN C1 47µF RT 75W R2 10K 0.5V VOUT 0V R1 10K R3 C3 470µF 75W + - VOUT 75W M = 10µs/DIV RG 1kW FIGURE 30. VIDEO SIGNAL RF 1kW C2 220µF +2.5V B 2MHz 1VP-P FIGURE 33. 5V SINGLE SUPPLY NON INVERTING VIDEO LINE DRIVER + 75W -2.5V 1K 1K 75W RF 1kΩ VOUT +2.5V A 2MHz 2VP-P 75W + - 75W -2.5V VIN C1 RG 47µF 500Ω 5V RT 75Ω - R3 C3 470µF 75Ω VOUT + R1 10K 1K 1K 5V R2 10K ENABLE 75Ω C2 220µF FIGURE 31. TWO TO ONE MULTIPLEXER FIGURE 34. 5V SINGLE SUPPLY INVERTING VIDEO LINE DRIVER 0V -0.5V ENABLE 5 -1.5V 1V 0V B A -1V M = 50ns/DIV FIGURE 32. ENABLE SIGNAL SINGLE SUPPLY VIDEO LINE DRIVER 4 NORMALIZED GAIN (dB) -2.5V 3 2 1 AV = 2 0 -1 AV = -2 -2 -3 -4 -5 100K 1M 10M FREQUENCY (Hz) 100M 200M FIGURE 35. VIDEO LINE DRIVER FREQUENCY RESPONSE The EL8200, EL8201 and EL8401 are wideband rail-to-rail output op amplifiers with large output current, excellent dG, dP, and low distortion that allow them to drive video signals in low supply applications. Figure 33 is the single supply non-inverting video line driver configuration and Figure 34 is the inverting video ling driver configuration. The signal is AC coupled by C1. R1 and R2 are used to level shift the input and output to provide the largest output swing. RF and RG 12 FN7105.3 March 9, 2006 EL8200, EL8201, EL8401 SO Package Outline Drawing 13 FN7105.3 March 9, 2006 EL8200, EL8201, EL8401 MSOP Package Outline Drawing 14 FN7105.3 March 9, 2006 EL8200, EL8201, EL8401 QSOP Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. 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For information regarding Intersil Corporation and its products, see www.intersil.com 15 FN7105.3 March 9, 2006