EM42BM1684RTC Revision History Revision 0.1 (Jun. 2010) - First release. Revision 0.2 (Sep. 2010) - Add [email protected]; 200MHz@3-3-3, page 2 - AC characteristics CL=2.5 & 3 for tAC, page 10 Revision 0.3 (Apr. 2012) - Add IDD7:four bank interleaving with BL=4 operating current Apr. 2012 1/23 www.eorex.com EM42BM1684RTC 512Mb (8M×4Bank×16) Double DATA RATE SDRAM Features • Internal Double-Date-Rate architecture with 2 Accesses per clock cycle. • VDD/VDDQ= 2.5V ± 0.2V • 2.5V SSTL-2 compatible I/O • Burst Length (B/L) of 2, 4, 8 • 2.5,3 Clock read latency • Bi- directional, intermittent data strobe (DQS) • All inputs except data and DM are sampled at the positive edge of the system clock. • Data Mask (DM) for write data Sequential & Interleaved Burst type available • Auto Precharge option for each burst accesses • DQS edge-aligned with data for Read cycles • DQS center-aligned with data for Write cycles • DLL aligns DQ/DQS transitions with CLK transition • Auto Refresh and Self Refresh • 8,192 Refresh Cycles / 64ms Description The EM42BM1684RTC is high speed Synchronous graphic RAM fabricated with ultra high performance CMOS process containing 536,870,912 bits which organized as 8Meg words x 4 banks by 16 bits. The 512Mb DDR SDRAM uses double data rate architecture to accomplish high-speed operation. The data path internally pre-fetches multiple bits and It transfers the data for both rising and falling edges of the system clock. It means the doubled data bandwidth can be achieved at the I/O pins. Available packages: TSOPII 66pin 400mil. Ordering Information Part No Organization Max. Freq Package Grade Pb EM42BM1684RTC-6F 32M X 16 166MHz @CL2.5-3-3 TSOPII-66 Commercial Free EM42BM1684RTC-5F 32M X 16 200MHz @CL3-3-3 TSOPII-66 Commercial Free EM42BM1684RTC-6FE 32M X 16 166MHz @CL2.5-3-3 TSOPII-66 Extended Free EM42BM1684RTC-5FE 32M X 16 200MHz @CL3-3-3 TSOPII-66 Extended Free Apr. 2012 2/23 www.eorex.com EM42BM1684RTC Parts Naming Rule * EOREX reserves the right to change products or specification without notice. Apr. 2012 3/23 www.eorex.com EM42BM1684RTC Pin Assignment 66pin TSOP-II Apr. 2012 4/23 www.eorex.com EM42BM1684RTC Pin Description (Simplified) Pin 45,46 24 Name CLK,/CLK /CS Function (System Clock) Clock input active on the Positive rising edge except for DQ and DM are active on both edge of the DQS. CLK and /CLK are differential clock inputs. (Chip Select) /CS enables the command decoder when”L” and disable the command decoder when “H”. The new commands are over- Looked when the command decoder is disabled but previous operation will still continue. CKE (Clock Enable) Activates the CLK when “H” and deactivates when “L”. When deactivate the clock, CKE low signifies the power down or self refresh mode. 28~32,35~42 A0~A12 (Address) Row address (A0 to A12) and Column address (CA0 to CA9) are multiplexed on the same pin. CA10 defines auto precharge at Column address. 26, 27 BA0, BA1 23 /RAS (Row Address Strobe) Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. 22 /CAS (Column Address Strobe) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. 21 /WE (Write Enable) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. 16/51 LDQS/UDQS (Data Input/Output) Data Inputs and Outputs are synchronized with both edges of DQS. 20/47 LDM/UDM (Data Input/Output Mask) DM controls data inputs. LDM corresponds to the data on DQ0~DQ7.UDM corresponds to the data on DQ8~DQ15. 2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65 DQ0~DQ15 (Data Input/Output) Data inputs and outputs are multiplexed on the same pin. VDD/VSS (Power Supply/Ground) VDD and VSS are power supply pins for internal circuits. 44 1,18,33/ 34,48,66 3, 9, 15, 55.61/ 6, 12, 52, 58,64 VDDQ/VSSQ 14,17,19,25,43, 50,53 NC/RFU 49 VREF Apr. 2012 (Bank Address) Selects which bank is to be active. (Power Supply/Ground) VDDQ and VSSQ are power supply pins for the output buffers. (No Connection/Reserved for Future Use) This pin is recommended to be left No Connection on the device. (Input) SSTL-2 Reference voltage for input buffer. 5/23 www.eorex.com EM42BM1684RTC Absolute Maximum Rating Symbol Item VIN, VOUT Input, Output Voltage VDD, VDDQ Power Supply Voltage TOP TSTG Operating Temperature Range Storage Temperature Range Rating Units -1 ~ +3.6 V -1 ~ +3.6 Commercial 0 ~ +70 Extended -25 ~ +85 -55 ~ +150 V °C °C PD Power Dissipation 1.6 W IOS Short Circuit Current 50 mA Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (VCC=2.5V, f=1MHz, TA=25°C) Symbol CCLK CI CO Parameter Clock Capacitance(CLK,/CLK) Input Capacitance for CKE, Address, /CS, /RAS, /CAS, /WE DM,Data&DQS Input/Output Capacitance Min. Typ. Max. Units 2 3 pF 2 - 3 pF 4 - 5 pF Recommended DC Operating Conditions (TA=-0°C ~+70°C) Symbol VDD VDDQ VREF VTT VIH VIL Apr. 2012 Parameter Power Supply Voltage Power Supply Voltage (for I/O Buffer) I/O Reference Voltage I/O Termination Voltage Input Logic High Voltage Input Logic Low Voltage 6/23 Min. Typ. Max. Units 2.3 2.3 0.49 VDDQ 2.7 2.7 0.51 VDDQ V V V VREF-0.04 - VREF+0.04 V VREF+0.15 - VDDQ+0.3 V -0.3 - VREF-0.15 V Note www.eorex.com EM42BM1684RTC Recommended DC Operating Conditions (VDD=2.5V±0.2V, TA=0°C ~ 70°C) Symbol Parameter Test Conditions Max. -5 -6 Units IDD1 Operating Current (Note 1) Burst length=2, tRC≥tRC(min.), IOL=0mA, One bank active 120 80 mA IDD2P Precharge Standby Current Power Down Mode CKE≤VIL(max.), tCK=min 10 10 mA IDD2N Precharge Standby Current (All banks idle) CKE≥VIL(min.), tCK=min, /CS≥VIH(min.) Input signals are changed once per clock cycle 50 45 mA IDD3P Active Standby Current (Power Down Mode) CKE≤VIL(max.), tCK=min 30 25 mA IDD3N Active Standby Current (Non-power Down Mode) CKE≥VIH(min.), tCK=min, /CS≥VIH(min.) Input signals are changed once per clock cycle 60 50 mA IDD4 Operating Current (Burst Mode) (Note 2) tCK ≥ tCK(min.), IOL=0mA, All banks active READ 100 85 WRITE 100 85 IDD5 Refresh Current (Note 3) tRC≥ tRFC (min.), All banks active 150 130 mA IDD6 Self Refresh Current CKE≤0.2V 5 5 mA IDD7 Operating Current Four bank linterleaving with BL=4 300 250 mA mA *All voltages referenced to VSS. Note 1: IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 2: IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 3: Min. of tRFC (Auto refresh Row Cycle Times) is shown at AC Characteristics. Apr. 2012 7/23 www.eorex.com EM42BM1684RTC Recommended DC Operating Conditions (Continued) Symbol Parameter Test Conditions Min. Max. Units IIL Input Leakage Current 0≤VI≤VDDQ, VDDQ=VDD All other pins not under test=0V -2 +2 uA IOL Output Leakage Current 0≤VO≤VDDQ, DOUT is disabled -5 +5 uA VOH High Level Output Voltage IO=-16.8mA 1.95 - V VOL Low Level Output Voltage IO=+16.8mA - 0.35 V Apr. 2012 8/23 www.eorex.com EM42BM1684RTC Block Diagram DM Auto/ Self Refresh Counter DQM Control A0 CLK, /CLK A1 A2 A6 A7 A8 A9 Row Decoder A5 Address Register A4 DQS Generator Row Add. Buffer A3 DLL Memory Array Driver S/ A & I/ O Gating A10 Write FIFO CLK, /CLK A11 Col. Decoder A12 BA0 BA1 Receiver Col. Add. Buffer Data In Mode Register Set Data Out Col Add. Counter Burst Counter DIO Timing Register DQS /CLK Apr. 2012 CLK CKE /CS / RAS 9/23 / CAS /WE DM DQS www.eorex.com EM42BM1684RTC AC Operating Test Conditions (VDD=2.5V±0.2V, TA=0°C ~70°C) AC Operating Test Characteristics (VDD=2.5V±0.2V, TA=0°C ~70°C) Symbol -6 tDQCK DQ output access from CLK,/CLK tDQSCK DQS output access from CLK,/CLK -0.55 0.55 -0.6 0.6 ns tCL,tCH CL low/high level width 0.45 0.55 0.45 0.55 tCK CL=3 5 10 - - CL=2.5 - - 6 12 DQ and DM hold/setup time 0.4 - 0.45 - ns tDIPW DQ and DM input pulse width for each input 1.75 - 1.75 - ns tHZ,tLZ Data out high/low impedance time from CLK,/CLK -0.7 0.7 -0.7 0.7 ns tDQSQ DQS-DQ skew for associated DQ signal - 0.4 - 0.4 ns tDQSS Write command to first latching DQS transition 0.72 1.25 0.75 1.25 tCK DQS input valid window 0.35 - 0.35 - tCK Mode Register Set command cycle time 2 - 2 - tCK tWPRES Write Preamble setup time 0 - 0 - ns tWPRE Write Preamble 0.25 - 0.25 - tCK tWPST Write Postamble 0.4 0.6 0.4 0.6 tCK tIH,tIS Address/control input hold/setup time (fast slew rate) 0.6 - 0.75 - ns tRPRE Read Preamble 0.9 1.1 tCK tDH,tDS tDSL,tDSH tMRD Clock Cycle Time 10/23 Max. 0.7 Min. -0.7 Max. 0.7 Units Min. -0.7 tCK Apr. 2012 -5 Parameter ns ns www.eorex.com EM42BM1684RTC AC Operating Test Characteristics (Continued) (VDD=2.5V±0.2V, TA=0°C ~70°C) Symbol -6 Min. Max. Min. Max. Units tRPST Read Postamble 0.4 0.6 0.4 0.6 tCK tRAS Active to Precharge command period 40 70k 42 70k ns tRC Active to Active command period 55 - 60 - ns tRFC Auto Refresh Row Cycle Time 70 - 72 - ns tRCD Active to Read or Write delay 15 - 18 - ns tRP Precharge command period 15 - 18 - ns tWR Write recover time 15 - 15 - ns tRRD Active bank A to B command period 10 - 12 - ns 2.2 - 2.2 - ns tIPW Apr. 2012 -5 Parameter Control & Address Input width tRAP Active to READ with Auto Precharge command 15 - 18 - ns tRPRE DQS read preamble 0.9 1.1 0.9 1.1 tCK tWTR Internal write to read command delay 2 - 1 - tCK tXSNR Exit self Refresh to non-read command 75 - 75 - ns tXSRD Exit self Refresh to read command 200 - 200 - tCK tREFI Average periodic refresh interval - 7.8 - 7.8 us 11/23 www.eorex.com EM42BM1684RTC Simplified State Diagram Apr. 2012 12/23 www.eorex.com EM42BM1684RTC 1. Command Truth Table Command Symbol CKE /CS /RAS /CAS /WE BA0, BA1 A10 A12~A0 n-1 N DESL H X H X X X X X X No Operation NOP H X L H H H X X X Burst Stop BSTH H X L H H L X X X Read Read with Auto Pre-charge Write Write with Auto Pre-charge Bank Activate Pre-charge Select Bank Pre-charge All Banks Mode Register Set READ H X L H L H V L V READA H X L H L H V H V WRIT H X L H L L V L V WRITA H X L H L L V H V ACT H X L L H H V V V PRE H X L L H L V L X PALL H X L L H L X H X MRS H X L L L L OP Code EMRS H X L L L L OP Code Ignore Command Extended MRS H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 2. CKE Truth Table Item Command Idle CBR Refresh Command Idle Self Refresh Entry Self Refresh Self Refresh Exit Idle Power Down Power Down Entry Power Down Exit Symbol CKE /CS /RAS /CAS /WE Addr. H L L L H X L L L L H X H L H H H X L H H X X X X H L X X X X X L H X X X X X n-1 n REF H SELF H L - H = High level, L = Low level, X = High or Low level (Don't care) Apr. 2012 13/23 www.eorex.com EM42BM1684RTC 3. Operative Command Table Current State Idle Row Active /CS /R /C /W Addr. Command H X X X X DESL NOP L H H H X NOP NOP L H H L X TERM NOP L H L X BA/CA/A10 READ/WRIT/BW L L H H BA/RA ACT L L H L BA, A10 PRE/PREA L L L H REFA Auto refresh(Note 4) L L L L MRS Mode register H L X H X H X H X Op-Code, Mode-Add X X DESL NOP L H H L BA/CA/A10 READ/READA NOP NOP Begin read,Latch CA, Determine auto-precharge L H L L BA/CA/A10 WRIT/WRITA L L H H BA/RA ACT L L H L BA/A10 PRE/PREA L L L H X REFA ILLEGAL MRS ILLEGAL ILLEGAL (Note 1) Bank active,Latch RA NOP(Note 3) Begin write,Latch CA, Determine auto-precharge ILLEGAL (Note 1) Precharge/Precharge all L L L L H L L X H H X H H X H L Op-Code, Mode-Add X X X L H L H BA/CA/A10 READ/READA L L H H BA/RA ACT L L H L BA, A10 PRE/PREA L L L H REFA ILLEGAL L L L L X Op-Code, Mode-Add MRS ILLEGAL H L L X H H X H H X H L X X X DESL NOP TERM L H L H BA/CA/A10 READ/READA L H L L BA/CA/A10 WRIT/WRITA L L H H BA/RA ACT DESL NOP TERM Read Write Apr. 2012 Action L L H L BA, A10 PRE/PREA L L L L L L H L X Op-Code, REFA MRS 14/23 NOP(Continue burst to end) NOP(Continue burst to end) Terminal burst Terminate burst,Latch CA, Begin new read, Determine Auto-precharge ILLEGAL (Note 1) Terminate burst, PrecharE NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL Terminate burst with DM=”H”,Latch CA,Begin read,Determine auto-precharge (Note 2) Terminate burst,Latch CA,Begin new write, Determine auto-precharge (Note 2) ILLEGAL (Note 1) Terminate burst with DM=”H”, Precharge ILLEGAL ILLEGAL www.eorex.com EM42BM1684RTC 3. Operative Command Table (Continued) Current State Read with AP Write with AP Pre-charging Row Activating /CS /R /C /W Addr. Command Action H X X X X DESL NOP(Continue burst to end) L H H H X NOP NOP(Continue burst to end) L H L H H L BA/CA/A10 TERM L X BA/RA READ/WRITE ILLEGAL ILLEGAL (Note 1) L L H H BA/A10 ACT ILLEGAL (Note 1) L L H L X PRE/PREA ILLEGAL (Note 1) L L L H REFA ILLEGAL L L L L MRS ILLEGAL H L L X H H X H H X H L X Op-Code, Mode-Add X X X DESL NOP TERM L H L X BA/CA/A10 READ/WRITE L L H H BA/RA ACT ILLEGAL (Note 1) L L H L BA/A10 PRE/PREA ILLEGAL (Note 1) L L L H REFA ILLEGAL L L L L MRS ILLEGAL H L L X H H X H H X H L X Op-Code, Mode-Add X X X DESL NOP TERM L H L X BA/CA/A10 READ/WRITE L L H H BA/RA ACT L L L L H L L H PRE/PREA REFA L L L L H L L X H H X H H X H L BA/A10 X Op-Code, Mode-Add X X X DESL NOP TERM L H L X BA/CA/A10 READ/WRITE L L H H BA/RA ACT ILLEGAL (Note 1) L L H L BA/A10 PRE/PREA ILLEGAL (Note 1) L L L H REFA ILLEGAL L L L L X Op-Code, Mode-Add MRS ILLEGAL MRS NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL ILLEGAL (Note 1) NOP(idle after tRP) NOP(idle after tRP) NOP ILLEGAL (Note 1) ILLEGAL (Note 1) NOP(idle after tRP) (Note 3) ILLEGAL ILLEGAL NOP(Row active after tRCD) NOP(Row active after tRCD) NOP ILLEGAL (Note 1) H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Apr. 2012 15/23 www.eorex.com EM42BM1684RTC 3. Operative Command Table (Continued) Current State Write Recovering Refreshing /CS /R /C /W Addr. Command Action H X X X X DESL NOP L H H H X NOP NOP L H H L L H L H X TERM BA/CA/A10 READ NOP ILLEGAL(Note 1) L H L L BA/CA/A10 WRIT/WRITA L L H H BA/RA L L H L BA/A10 PRE/PREA L L L H REFA ILLEGAL L L L L MRS ILLEGAL H L L L L L L X H H H L L L X H H L H H L X H L X H L H L L L L X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add ACT DESL NOP TERM READ/WRIT ACT PRE/PREA REFA MRS New write, Determine AP ILLEGAL (Note 1) ILLEGAL (Note 1) NOP(idle after tRP) NOP(idle after tRP) NOP ILLEGAL ILLEGAL NOP(idle after tRP) ILLEGAL ILLEGAL H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Note 1: ILLEGAL to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. Note 2: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Note 3: NOP to bank precharging or in idle state.May precharge bank indicated by BA. Note 4: ILLEGAL of any bank is not idle. Apr. 2012 16/23 www.eorex.com EM42BM1684RTC 4. Command Truth Table for CKE Current State Self Refresh Both bank precharge power down All Banks Idle C KE /CS /R /C /W Addr. H X X X X X X Action INVALID L H H X X X X Exist Self-Refresh L H L H H H X L H L H H L X L H L H L X X Exist Self-Refresh ILLEGAL ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP(Maintain self refresh) H X X X X X X INVALID L H H X X X X L L L H H H L L L H H H H H L H L X X X X L H L L X X X Exist Power down Exist Power down ILLEGAL ILLEGAL ILLEGAL L L X X X X X NOP(Maintain Power down) H H X X X X X H L H X X X X Refer to function true table Enter power down mode(Note 3) H L L H H H X Enter power down mode(Note 3) H L L H H L X H H L L L L L H L L H X H X RA L L L H X ILLEGAL ILLEGAL Row active/Bank active Enter self-refresh(Note 3) L L L L Op-Code Mode register access H L L L L L L Op-Code Special mode register access L X X X X X X Refer to current state H H X X X X X Refer to command truth table H H Any State Other than Listed above H = High level, L = Low level, X = High or Low level (Don't care) Notes 1: After CKE’s low to high transition to exist self refresh mode.And a time of tRC(min) has to be Elapse after CKE’s low to high transition to issue a new command. Notes 2: CKE low to high transition is asynchronous as if restarts internal clock. Notes 3: Power down and self refresh can be entered only from the idle state of all banks. Apr. 2012 17/23 www.eorex.com EM42BM1684RTC The Sequence of Power-Up and Initialization The following sequence is required for Power-Up and Initialization. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & VREF. 2. Start clock and maintain stable condition for a minimum of 200us. 3. The minimum of 200us after stable power and clock (CLK, CLK), apply NOP & take CKE high. 4. Precharge all banks. 5. Issue EMRS to enable DLL. (To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to all of the rest address pins, A1~A12 and BA1) 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL. (To issue DLL reset command, provide “High” to A8 and “Low” to BA0) 7. Issue precharge commands for all banks of the device. 8. Issue 2 or more auto-refresh commands. 9. Issue a mode register set command to initialize device operation. Note1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL. Apr. 2012 18/23 www.eorex.com EM42BM1684RTC Mode Register Definition Mode Register Set The mode register stores the data for controlling the various operating modes of DDR SDRAM which contains addressing mode, burst length, /CAS latency, test mode, DLL reset and various vendor＇s specific opinions. The defaults value of the register is not defined, so the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE and BA0 ( The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register. ) The state of the address pins A0-A12 in the same cycle as /CS, /RAS, /CAS, /WE and BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operating as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0-A2, addressing mode uses A3, /CAS latency (read latency from column address) uses A4-A6. A7 is used for test mode. A8 is used for DDR reset. A7 must be set to low for normal MRS operation. Apr. 2012 19/23 www.eorex.com EM42BM1684RTC Address input for Mode Register Set BA1 BA0 0 MRS A12 A11 A10 A9 RFU* A8 A7 DLL TM A6 A5 A4 CAS Latency A3 A2 BT A1 A0 Bust Length *RFU: Reserved for Future Use An ~ A0 BA0 DLL Rest A8 Mode A7 Burst Type A3 MRS cycle 0 No 0 Normal 0 Sequential 0 EMRS 1 Yes 1 Test 1 Interleave 1 Apr. 2012 CAS Latency A6 A5 A4 Reserve 0 0 0 Reserve 0 0 1 Reserve 0 1 0 3 0 1 1 Reserve 1 0 0 Reserve 1 0 1 2.5 1 1 0 Reserve 1 1 1 20/23 Burst Latency A2 A1 A0 Reserve 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 Reserve 1 0 0 Reserve 1 0 1 Reserve 1 1 0 Reserve 1 1 1 www.eorex.com EM42BM1684RTC Burst Type (A3) Burst Length 2 4 8 A2 A1 A0 Sequential Addressing Interleave Addressing X X 0 01 X X 0 10 X 0 0 0123 X 0 1 1230 1032 X 1 0 2301 2301 X 1 1 3012 3210 0 0 0 01234567 0 0 1 12345670 10325476 0 1 0 23456701 23016745 0 1 1 34567012 32107654 1 0 0 45670123 45670123 1 0 1 56701234 54761032 1 1 0 67012345 67452301 1 1 1 70123456 76543210 01 10 0123 01234567 *Page length is a function of I/O organization and column addressing DLL Enable / Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disable the DLL for the purpose of debug or evaluation ( upon existing Self Refresh Mode, the DLL is enable automatically. ) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Output Drive Strength The normal drive strength got all outputs is specified to be SSTL-2, Class II. Some vendors might also support a weak drive strength option, intended for lighter load and/or point to point environments. Apr. 2012 21/23 www.eorex.com EM42BM1684RTC Extended Mode Register Set ( EMRS ) The Extended mode register stores the data enabling or disabling DLL. The value of the extended mode register is not defined, so the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA0 ( The DDR SDRAM should be in all bank precharge with CKE already prior to writing into the extended mode register. ) The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE going low is written in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. High on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. BA1 BA0 0 MRS A12 A11 A10 A9 A8 A7 A6 A5 A4 RFU* A3 A2 A1 A0 0 I/O DLL *RFU: Reserved for Future Use Must be set to “0” An ~ A0 BA0 I/O Strength A1 DLL Enable A0 MRS cycle 0 Full 0 Enable 0 EMRS 1 Half 1 Disable 1 Apr. 2012 22/23 www.eorex.com EM42BM1684RTC Package Description Apr. 2012 23/23 www.eorex.com