128Mb SDRAM Ordering Information EM 48 8M 16 4 4 V T A – 55 L EOREX Logo EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM : : : : : : Power Blank : Standard L : Low power I : Industrial 40 41 42 43 46 48 F: PB free package Density 16M : 16 Mega Bits 8M : 8 Mega Bits 4M : 4 Mega Bits 2M : 2 Mega Bits 1M : 1 Mega Bit Min Cycle Time ( Max Freq.) -5 : 5ns ( 200MHz ) -55: 5.5ns ( 183MHz ) -6 : 6ns ( 167MHz ) -7 : 7ns ( 143MHz ) -75 : 7.5ns ( 133MHz ) -8 : 8ns ( 125MHz ) -10 : 10ns ( 100MHz ) Organization 8 : x8 9 : x9 16 : x16 18 : x18 32 : x32 Refresh 1 : 1K, 8 : 8K 2 : 2K, 6 :16K 4 : 4K Bank 2 : 2Bank 6 : 16Bank 4 : 4Bank 3 : 32Bank 8 : 8Bank Revision A : 1st B : 2nd C : 3rd D :4th Interface V: 3.3V R: 2.5V URL: http://www.eorex.com Email: [email protected] Package C: CSP B: uBGA T: TSOP Q: TQFP P: PQFP ( QFP ) Rev.02 1/18 128Mb SDRAM 128Mb ( 4Banks ) Synchronous DRAM EM488M1644VTA (8Mx16) Description The EM488M1644VTA, is Synchronous Dynamic Random Access Memory (SDRAM) organized as 2Meg words x 4 banks x 16 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 128Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL. Available packages: TSOPII 54P 400mil and TFBGA 54B 12mm x 8mm. Feature • Fully synchronous to positive clock edge 3.3V +/- 0.3V power supply • LVTTL compatible with multiplexed address • Programmable Burst Length (B/ L) - 1,2,4,8 or full page • Programmable CAS Latency (C/ L) - 2 or 3 • Data Mask (DQM) for Read / Write masking • Programmable wrap sequence - Sequential ( B/ L = 1/2/4/8/full page ) - Interleave ( B/ L = 1/2/4/8 ) • Burst read with single-bit write operation • All inputs are sampled at the rising edge of the system clock. • Auto refresh and self refresh • 4,096 refresh cycles / 64ms • Single * EOREX reserves the right to change products or specification without notice. Rev.02 2/18 128Mb SDRAM Pin Assignment ( Top View ) x16 VDD 1 54 VSS DQ0 2 53 DQ15 VDDQ 3 52 VSSQ DQ1 4 51 DQ14 DQ2 5 50 DQ13 VSSQ 6 49 VDDQ DQ3 7 48 DQ12 DQ4 8 47 DQ11 VDDQ 9 46 VSSQ DQ5 10 45 DQ10 DQ6 11 44 DQ9 VSSQ 12 43 VDDQ DQ7 13 42 DQ8 VDD 14 41 VSS LDQM 15 40 NC /WE 16 39 UDQM /CAS 17 38 CLK /RAS 18 37 CKE /CS 19 36 NC BA0 20 35 A11 BA1 21 34 A9 A10/AP 22 33 A8 A0 23 32 A7 A1 24 31 A6 A2 25 30 A5 A3 26 29 A4 VDD 27 28 VSS 54pin TSOP-II (400mil x 875mil) (0.8mm Pin pitch) 1 VSS DQ14 DQ12 DQ10 DQ8 UDQM NC A8 VSS 2 DQ15 DQ13 DQ11 DQ9 NC CLK A11 A7 A5 3 VSSQ VDDQ VSSQ VDDQ VSS CKE A9 A6 A4 A B C D E F G H J 7 VDDQ VSSQ VDDQ VSSQ VDD CAS BA0 A0 A3 8 DQ0 DQ2 DQ4 DQ6 LDQM RAS BA1 A1 A2 9 VDD DQ1 DQ3 DQ5 DQ7 WE CS A10 VDD Pin Configuration P-TFBGA-54 Rev.02 3/18 128Mb SDRAM Pin Descriptions ( Simplified ) Pin Name CLK System Clock /CS Chip select CKE Clock Enable Pin Function Master Clock Input(Active on the Positive rising edge) Selects chip when active Activates the CLK when “H” and deactivates when “L”. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row address (A0 to A11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. CA(CA0 to CA8) is determined by A0 to A8 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10 = High at the pre-charge command cycle, all banks are pre-charged. But when A10 = Low at the pre-charge command cycle, only the bank that is selected by BA0/BA1 is pre-charged. A0 ~ A11 Address BA0, BA1 Bank Address /RAS Row address strobe /CAS Column address strobe Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. /WE Write Enable Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. UDQM /LDQM Data input/output Mask DQ0 ~ 15 Data input/output VDD/VSS Power supply/Ground VDD and VSS are power supply pins for internal circuits. VDDQ/VSSQ Power supply/Ground VDDQ and VSSQ are power supply pins for the output buffers. NC No connection Selects which bank is to be active. Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. DQM controls I/O buffers. DQ pins have the same function as I/O pins on a conventional DRAM. This pin is recommended to be left No Connection on the device. Rev.02 4/18 128Mb SDRAM Block Diagram Auto/Self Refresh Counter A0 A1 DQM A2 A3 A7 A8 Memory Array Row Decoder A6 Address Register A5 Row Add. Buffer A4 Write DQM Control Data In A9 S/A & I/O gating A10 Col. Decoder DQi Data Out A11 BA0 Col. Add. Buffer Read DQM Control BA1 Col. Add. Counter Mode Register Set DQM Burst Counter Timing Register CLK CKE /CS /RAS /CAS Rev.02 /WE DQM 5/18 128Mb SDRAM Simplified State Diagram Self Refresh LF SE LF SE Mode Register Set MRS it Ex CBR Refresh REF IDLE CK E CK E ACT Power Down CKE Row Active Wr ite Read h WRITE Read READ Write CKE CKE POWER ON READA Precharge PR E WRITEA CKE READ Suspend CKE CKE E PR WRITEA Suspend CKE BS T Re ad Active Power Down w it WRITE Suspend ad Re w it h Write CKE CKE READA Suspend CKE Precharge Manual Input Automatic Sequence Rev.02 6/18 128Mb SDRAM Address Input for Mode Register Set BA1 BA0 A11 A10 A9 A8 A7 Operation Mode A6 A5 A4 A3 CAS Latency Sequential 1 2 4 8 Reserved Reserved Reserved Full Page BT BA1 0 0 BA1 0 0 BA0 0 0 A10 0 0 A9 0 1 A8 0 0 A7 0 0 A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A1 A0 Burst Length Burst Length Interleave A2 1 0 2 0 4 0 8 0 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Burst Type Interleave Sequential CAS Latency Reserved 2 3 Reserved Reserved Reserved Reserved Reserved A2 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 A3 0 1 A4 0 1 0 1 0 1 0 1 Operation Mode Normal Burst read with Single-bit Write Rev.02 7/18 128Mb SDRAM Burst Type ( A3 ) Burst Length 2 4 8 Full Page * A2 A1 A0 XX0 XX1 X0 0 X0 1 X1 0 X1 1 000 001 010 011 100 101 110 111 nnn Sequential Addressing 01 10 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456 Cn Cn+1 Cn+2 …... Interleave Addressing 01 10 0123 1032 2301 3210 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210 - * Page length is a function of I/O organization and column addressing x16 (CA0 ~ CA8) : Full page = 512bits Rev.02 8/18 128Mb SDRAM Truth Table 1. Command Truth Table Command Symbol CKE n-1 n /CS /RAS /CAS /WE BA0, BA1 A10 A11, A9~A0 Ignore Command DESL H X H X X X X X X No operation NOP H X L H H H X X X Burst stop BSTH H X L H H L X X X Read READ H X L H L H V L V Read with auto pre-charge READA H X L H L H V H V Write WRIT H X L H L L V L V Write with auto pre-charge WRITA H X L L H H V H V Bank activate ACT H X L L H H V V V Pre-charge select bank PRE H X L L H L V L X Pre-charge all banks PALL H X L L H L X H X Mode register set MRS H X L L L L L L V Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 2. DQM Truth Table Command Symbol CKE n-1 n /CS Data w rite / output enable ENB H X H Data mask / output disable MASK H X L Upper byte w rite enable / output enable BSTH H X L Read READ H X L Read w ith auto pre-charge READA H X L Write WRIT H X L Write w ith auto pre-charge WRITA H X L Bank activate ACT H X L Pre-charge select bank PRE H X L Pre-charge all banks PALL H X L Mode register set MRS H X L Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 3. CKE Truth Table Command Command Symbol CKE n-1 n /CS /RAS /CAS /WE Addr. Activating Clock suspend mode entry H L X X X X X Any Clock suspend mode L L X X X X X Clock suspend Clock suspend mode exit L H X X X X X Idle CBR refresh command REF H H L L L H X Idle Self refresh entry SELF H L L L L H X Self refresh Self refresh exit L H L H H H X L H H X X X X Idle Pow er dow n entry H L X X X X X Power down Pow er dow n exit L H X X X X X Re m ark H = High level, L = Low level, X = High or Low level (Don't care) Rev.02 9/18 128Mb SDRAM 4. Operative Command Table Current state Idle Row active Re ad Write /CS /R /C /W Addr. Command Action Notes X DESL Nop or pow er dow n 2 H X X X L H H X X NOP or BST Nop or pow er dow n 2 L H L H BA/CA/A10 READ/READA ILLEGAL 3 L H L L BA/CA/A10 WRIT/WRITA ILLEGAL 3 L L H H BA/RA ACT L L H L BA, A10 PRE/PALL Nop L L L H X REF/SELF Refresh or self refresh L L L L Op-Code MRS Mode register accessing H X X X X DESL Nop L H H X X NOP or BST Nop L H L H BA/CA/A10 READ/READA Begin read : Determine AP 5 L H L L BA/CA/A10 WRIT/WRITA Begin w rite : Determine AP 5 L L H H BA/RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Precharge 6 L L L H X REF/SELF ILLEGAL 4 Row activating 4 L L L L Op-Code MRS ILLEGAL H X X X X DESL Continue burst to end Row active L H H H X NOP Continue burst to end Row active L H H L X BST Burst stop Row active L H L H BA/CA/A10 READ/READA Terminate burst, new read : Determine AP 7 L L L L BA/CA/A10 WRIT/WRITA Terminate burst, start w rite : Determine AP 7, 8 L L H H BA/RA ACT L L H L BA/A10 L L L H L L L L H X X X L H H H L H H L H L L L L ILLEGAL 3 PRE/PALL Terminate burst, pre-charging 4 X REF/SELF ILLEGAL Op-Code MRS ILLEGAL X DESL Continue burst to end Write recovering X NOP Continue burst to end Write recovering L X BST Burst stop Row active L H BA/CA/A10 READ/READA Terminate burst, start read : Determine AP 7, 8 L L BA/CA/A10 WRIT/WRITA Terminate burst, new w rite : Determine AP 7 7 L H H BA/RA ACT ILLEGAL 3 L H L BA/A10 PRE/PALL Terminate burst, pre-charging 9 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL 7,8 Rem ark H = High level, L = Low level, X = High or Low level (Don't care) Rev.02 10/18 128Mb SDRAM Current state Re ad w ith AP Write w ith AP Precharging Row activating /CS /R /C /W Addr. Command Action Notes H X X X X DESL Continue burst to end Precharging L H H H X NOP Continue burst to end Precharging L H H L X BST ILLEGAL L H L H BA/CA/A10 READ/READA ILLEGAL 3 L H L L BA/CA/A10 WRIT/WRITA ILLEGAL 3 L L H H BA/RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H X X X X DESL burst to end Write recovering w ith auto precharge L H H H X NOP Continue burst to end Write recovering w ith auto precharge L H H L X BST ILLEGAL L H L H BA/CA/A10 READ/READA ILLEGAL 3 L H L L BA/CA/A10 WRIT/WRITA ILLEGAL 3 L L H H BA/RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H X X X X DESL Nop Enter idle af ter tRP L H H H X NOP Nop Enter idle af ter tRP L H H L X BST ILLEGAL L H L H BA/CA/A10 READ/READA ILLEGAL 3 L H L L BA/CA/A10 WRIT/WRITA ILLEGAL 3 L L H H BA/RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Nop Enter idle af ter tRP L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H X X X X DESL Nop Enter idle af ter tRCD L H H H X NOP Nop Enter idle af ter tRCD L H H L X BST ILLEGAL L H L H BA/CA/A10 READ/READA ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL 3 L L H H BA/RA ACT ILLEGAL 3,10 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL 3 Re m ark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge Rev.02 11/18 128Mb SDRAM Current state Write re cove ring Write re cove ring w ith AP Re fre shing M ode Re giste r Acces sing /CS /R /C /W Addr. Command Action Notes H X X X X DESL Nop Enter row active af ter tDPL L H H H X NOP Nop Enter row active af ter tDPL L H H L X BST Nop Enter row active af ter tDPL L H L H BA/CA/A10 READ/READA Start read, Determine AP L H L L BA/CA/A10 WRIT/WRITA New w rite, Determine AP 8 L L H H BA/RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H X X X X DESL Nop Enter precharge af ter tDPL L H H H X NOP Nop Enter precharge af ter tDPL L H H L X BST Nop Enter precharge af ter tDPL L H L H BA/CA/A10 READ/READA ILLEGAL 3,8 L H L L BA/CA/A10 WRIT/WRITA ILLEGAL 3 L L H H BA/RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H X X X X DESL Nop Enter idle after tRC L H H X X NOP/ BST Nop Enter idle after tRC L H L X X READ/WRIT ILLEGAL L L H X X ACT/PRE/PALL ILLEGAL ILLEGAL L L L X X REF/SELF/MRS H X X X X DESL Nop L H H H X NOP Nop L H H L X BST ILLEGAL L H L X X READ/WRIT ILLEGAL L L X X X ACT/PRE/PALL/ REF/SELF/MRS ILLEGAL Re m ark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge Notes 1. All entries assume that CKE w as active (High level) during the preceding clock cycle. 2. If all banks are idle, and CKE is inactive (Low level), SDRAM w ill enter Pow er dow n mode. All input buffers except CKE w ill be disabled. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If all banks are idle, and CKE is inactive (Low level), SDRAM w ill enter Self refresh mode. All input buffers except CKE w ill be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or w rite recovery requirements. 9. Must mask preceding data w hich don't satisfy tDPL. 10. Illegal if tRRD is not satisfied. Rev.02 12/18 128Mb SDRAM 5. Command Truth Table for CKE Current state Se lf re fre sh Se lf re fre sh re cove ry Pow er dow n Both banks idle Row active Any state other than liste d above CKE /CS /R /C /W Addr. Action n-1 n H X X X X X X INVALID, CLK (n – 1) w ould exit self refresh L H H X X X X Self refresh recovery L H L H H X X Self refresh recovery L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X Maintain self refresh H H H X X X X Idle after tRC H H L H H X X Idle after tRC H H L H L X X ILLEGAL H H L L X X X ILLEGAL H L H X X X X ILLEGAL H L L H H X X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL H X X X X X X INVALID, CLK(n-1) w ould exit pow er dow n L H X X X X X Exit pow er dow n Idle L L X X X X X Maintain pow er dow n mode H H H X X X Refer to operations in Operative Command Table H H L H X X Refer to operations in Operative Command Table H H L L H X Refer to operations in Operative Command Table H H L L L H X H H L L L L Op-Code H L H X X X Refer to operations in Operative Command Table H L L H X X Refer to operations in Operative Command Table H L L L H X Refer to operations in Operative Command Table H L L L L H X H L L L L L Op-Code L X X X X X X Pow er dow n H X X X X X X Refer to operations in Operative Command Table L X X X X X X Pow er dow n H H X X X X H L X X X X X Begin clock suspend next cycle L H X X X X X Exit clock suspend next cycle L L X X X X X Maintain clock suspend Notes Refresh Refer to operations in Operative Command Table Self refresh 1 Refer t o operations in Operative Command Table 1 1 Refer to operations in Operative Command Table 2 Rem ark : H = High level, L = Low level, X = High or Low level (Don't care) Notes 1. Self refresh can be entered only from the both banks idle state. Pow er dow n can be entered only from both banks idle or row active state. 2. Must be legal command as defined in Operative Command Table. Rev.02 13/18 128Mb SDRAM Absolute Maximum Ratings Symbol Item Rating Units VIN, VOUT Input, Output Voltage -0.3 ~ 4.6 V VDD, VDDQ Power Supply Voltage -0.3 ~ 4.6 V TOP Operating Temperature 0 ~ 70 °C TSTG Storage Temperature -55 ~ 150 °C PD Power Dissipation 1 W IOS Short Circuit Current 50 mA Note : Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operation Conditions ( Ta = 0 ~ 70 °C ) Symbol Parameter Min. Typical Max. Units VDD Power Supply Voltage 3.0 3.3 3.6 V VDDQ Power Supply Voltage (for I/O Buffer) 3.0 3.3 3.6 V VIH Input logic high voltage 2.0 VDD+0.3 V VIL Input logic low voltage -0.3 0.8 V Note : 1. All voltage referred to V SS. 2. V IH (max) = 5.6V for pulse w idth 3ns 3. V IL (min) = -2.0V for pulse w idth 3ns Capacitance ( Vcc =3.3V, f = 1MHz, Ta = 25 °C ) Symbol Parameter Min. Max. Units CCLK Clock capacitance 2.5 4.0 pF CI Input capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML,DQMU 2.5 5.0 pF CO Input/Output capacitance 4.0 6.5 pF Rev.02 14/18 128Mb SDRAM Recommended DC Operating Conditions ( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C ) MAX Parameter Operating current Precharge standby current in power down mode Precharge standby current in non-power down mode Active standby current in power down mode Active standby current in non-power down mode Symbol Test condition Units Notes -55 -6/6I -7/7L 95 90 80 ICC1 Burst length = 1, tRC tRC (min), IOL = 0 mA, One bank active ICC2P CKE V IL (max.), tCk = 15 ns 2 mA ICC2PS CKE V IL (max.), tCk = 1 mA ICC2N CKE V IL (min.), tCK = 15 ns, /CS V IH (min.) Input signals are changed one time during 30ns 20 mA ICC2NS CKE V IL (min.), tCK = Input signals are stable 20 mA mA ICC3P CKE VIL(max), tCK = 15ns 7 mA ICC3PS CKE VIL(max), tCK = 5 mA ICC3N CKE VIL(min), tCK = 15ns,/ CS VIH(min) Input signals are changed one time during 30ns 30 mA ICC3NS CKE VIL(min), tCK = Input signals are stable 35 mA operating current (Burst mode) ICC4 tCCD = 2CLKs , IOL = 0 mA Refresh current ICC5 tRC tRC(min.) Self Refresh current ICC6 CKE 0.2V CL=3 CL=2 130 120 110 150 140 130 2 0.8 1 mA 2 mA 3 mA 4 5 Note : 1. ICC1 depends on output loading and cycle rates. Specified values are obtained w ith the output open. Input signals are changed only one time during tCK(min) 2. ICC4 depends on output loading and cycle rates. Specified values are obtained w ith the output open. Input signals are changed only one time during tCK(min) 3. Input signals are changed only one time during tCK(min) 4. Standard pow er version. 5. Low pow er version. Rev.02 15/18 128Mb SDRAM Recommended DC Operating Conditions ( Continued ) Parameter Symbol Input leakage current IIL Output leakage current Test condition Min. Max. Unit 0 VI VDDQ, VDDQ=VDD All other pins not under test=0 V -0.5 +0.5 uA IOL 0 VO VDDQ, DOUT is disabled -0.5 +0.5 uA High level output voltage VOH Io = -4mA 2.4 Low level output voltage VOL Io = +4mA V 0.4 V AC Operating Test Conditions ( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70°C ) Output Reference Level 1.4V / 1.4V Output Load See diagram as below Input Signal Level 2.4V / 0.4V Transition Time of Input Signals 2ns Input Reference Level 1.4V Vtt = 1.4V 50 Output Z = 50 50pF Rev.02 16/18 128Mb SDRAM Operating AC Characteristics ( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C, Ta = -40 ~ 85 °C for 6I) Parameter Symbol CL = 3 Clock cycle time CL = 2 CL = 3 Access time from CLK tCK -55 Min. -6/6I Max. Min. -7/7L Max. Min. Max. Units Notes 5.5 6 7 ns 7.5 10 10 ns tAC CL = 2 5.2 5.5 6 ns 6 6 6 ns CLK high level width tCH 2.3 2.5 3 ns CLK low level width tCL 2.3 2.5 3 ns 2.2 2.5 2.5 ns 2.5 ns CL = 3 Data-out hold time CL = 2 CL = 3 Data-out high impedance time tOH tHZ 2 5 2.5 5 CL = 2 6 ns 6 ns Data-out low impedance time tLZ 0 0 1 ns Input hold time tIH 1 1 1 ns Input setup time tIS 1.5 2 2 ns ACTIVE to ACTIVE command period tRC 55 60 63 ns 2 ACTIVE to PRECHARGE command period tRAS 40 ns 2 PRECHARGE to ACTIVE command period tRP 18 18 18 ns 2 ACTIVE to READ/WRITE delay time tRCD 18 18 18 ns 2 ACTIVE(one) to ACTIVE(another) command tRRD 12 14 16 ns 2 READ/WRITE command to READ/WRITE command tCCD 1 1 1 CLK Data-in to PRECHARGE command tDPL 2 2 2 CLK Data-in to BURST stop command tBDL 1 1 1 CLK 3 3 3 CLK 2 CLK Data-out to high impedance from PRECHARGE command Refresh time(4,096 cycle) CL = 3 tROH 100k 42 100k CL = 2 tREF 64 64 42 100k 64 ms ＊ All voltages referenced to Vss. Note : 1. tHZ defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. 2. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows : The number of clock cycles = Specified value of timing/clock period (Count fractions as a whole number) Rev.02 17/18 128Mb SDRAM 0.8 15˚±5˚ 26x 0.8 = 20.8 3) 0.35 +0.1 -0.05 0.1 54x 0.5 ±0.1 11.76 ±0.2 0.2 M 54x 28 6 max 54 10.16 ±0.13 2) 0.15 +0.06 -0.03 1±0.05 15˚±5˚ 0.1±0.05 Package Dimension (Upper: TSOPII 54P; Lower: TFBGA 54B) 1 2.5 max 27 22.22 ±0.13 1) TSOPII-54 Index Marking 1) Does not include plastic or metal protrusion of 0.15 max per side Does not include plastic protrusion of 0.25 max per side 3) Does not include dambar protrusion of 0.13 max per side 2) FIG1. Upper: TSOPII 54P Drawing Lower: TFBGA 54B Drawing Rev.02 18