EM620FV8BS Series Low Power, 256Kx8 SRAM Document Title 256K x8 bit Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date 0.0 Initial Draft June 28, 2007 0.1 0.1 Revision Revised VOH(2.2v to 2.4v),tOH(15ns to 10ns), tOE-55(30ns to 25ns), tWP-55(45ns to 40ns), tWP-70(55ns to 50ns), tWHZ-70(25ns to 20ns), ICC(2mA to 3mA), ICC1(2mA to 3mA) July 2, 2007 0.2 0.2 Revision VIH level change from 2.0V to 2.2V Aug. 16, 2007 0.3 0.3 Revision Fix typo error Nov. 13, 2007 Emerging Memory & Logic Solutions Inc. 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Remark Zip Code : 690-719 The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 EM620FV8BS Series Low Power, 256Kx8 SRAM 256K x8 Bit Low Power and Low Voltage CMOS Static RAM GENERAL DESCRIPTION FEATURES The EM620FV8BS series are fabricated by EMLSI’s advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current. The EM620FV8BS series are available in KGD, JEDEC standard 32 pin 8mm x 13.4mm sTSOP package. - Process Technology : 0.15mm Full CMOS - Organization :256K x8 - Power Supply Voltage => EM620FV8BS Series : 2.7V~3.6V - Low Data Retention Voltage : 1.5V (MIN) - Three state output and TTL Compatible - Packaged product designed for 45/55/70ns - Package Type: 32-sTSOP1 PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby (ISB1, Typ.) Operating (ICC1.Max) PKG Type EM620FV8BS-45LF Industrial (-40 ~ 85oC) 2.7V~3.6V 45ns 1 µA 3mA 32-sTSOP EM620FV8BS-55LF Industrial (-40 ~ 85oC) 2.7V~3.6V 55ns 1 µA 3mA 32-sTSOP EM620FV8BS-70LF Industrial (-40 ~ 85oC) 2.7V~3.6V 70ns 1 µA 3mA 32-sTSOP FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION Pre-charge Circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EM620FV8BS-45LF 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 VSS I/O 2 I/O 1 I/O 0 A0 A1 A2 A3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 VCC VSS Row Select A11 A9 A8 A13 WE CS2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 I/O0 ~ I/O7 Data Cont Memory Array 1024 x 2048 I/O Circuit Column Select A10 A11 A12 A13 A14 A15 A16 A17 Name Function Name Function CS1,CS2 Chip select inputs Vcc Power Supply OE Output Enable input Vss Ground WE Write Enable input NC No Connection A0~A17 Address Inputs I/O0~I/O7 Data Inputs/Outputs WE OE CS1 CS2 2 Control Logic EM620FV8BS Series Low Power, 256Kx8 SRAM ABSOLUTE MAXIMUM RATINGS * Parameter Symbol Voltage on Any Pin Relative to Vss Minimum Unit VIN, VOUT -0.2 to 4.0V V Voltage on Vcc supply relative to Vss VCC -0.2 to 4.0V V Power Dissipation PD 1.0 W Operating Temperature TA -40 to 85 o C * Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional oper- ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION CS1 CS2 OE WE I/O0-7 Mode Power H X X X High-Z Deselected Stand by X L X X High-Z Deselected Stand by L H H H High-Z Output Disabled Active L H L H Data Out Read Active L H X L Data In Write Active Note: X means don’t care. (Must be low or high state) 3 EM620FV8BS Series Low Power, 256Kx8 SRAM RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Symbol Min Typ Max Unit Supply voltage VCC 2.7 3.3 3.6 V Ground VSS 0 0 0 V Input high voltage VIH 2.2 - VCC + 0.22) V Input low voltage VIL -0.23) - 0.6 V 1. 2. 3. 4. TA= -40 to 85oC, otherwise specified Overshoot: VCC +2.0 V in case of pulse width < 20ns Undershoot: -2.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f =1MHz, TA=25oC) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Ouput capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested. DC AND OPERATING CHARACTERISTICS Parameter Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIN=VSS to VCC -1 - 1 uA Output leakage current ILO CS1=VIH or CS2=VIL or OE=VIH or WE=VIL VIO=VSS to VCC -1 - 1 uA Operating power supply ICC IIO=0mA, CS1=VIL, CS2=WE=VIH, VIN=VIH or VIL - - 3 mA ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS1<0.2V, CS2>VCC-0.2V, VIN<0.2V or VIN>VCC-0.2V - - 3 mA 45ns - - 35 ICC2 Cycle time = Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, VIN=VIL or VIH 55ns - - 30 70ns - - 25 Average operating current mA Output low voltage VOL IOL = 2.1mA - - 0.4 V Output high voltage VOH IOH = -1.0mA 2.4 - - V Standby Current (TTL) ISB - - 0.3 mA - 11) 10 uA Standby Current (CMOS) ISB1 CS1=VIH, CS2=VIL, Other inputs=VIH or VIL CS1>VCC-0.2V, CS2>VCC-0.2V (CS1 controlled) or 0V<CS2<0.2V (CS2 controlled), Other inputs = 0~VCC (Typ. condition : VCC=3.3V @ 25oC) (Max. condition : VCC=3.6V @ 85oC) NOTES 1. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested. 4 LF EM620FV8BS Series Low Power, 256Kx8 SRAM AC OPERATING CONDITIONS VTM3) Test Conditions (Test Load and Test Input/Output Reference) R12) Input Pulse Level : 0.4 to 2.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL1) = 100pF + 1 TTL (70ns) CL1) = 30pF + 1 TTL (45ns/55ns) 1. Including scope and Jig capacitance 2. R1=3070 ohm, R2=3150 ohm 3. VTM=2.8V 4. CL = 5pF + 1 TTL (measurement with tLZ1,2, tHZ1,2, tOLZ, tOHZ, tWHZ) R22) CL1) READ CYCLE (Vcc = 2.7V to 3.6V, Gnd = 0V, TA = -40oC to +85oC) Parameter Symbol 45ns 55ns 70ns Min Max Min Max Min Max Unit Read cycle time tRC 45 - 55 - 70 - ns Address access time tAA - 45 - 55 - 70 ns Chip select to output tCO1, tCO2 - 45 - 55 - 70 ns tOE - 25 - 25 - 35 ns tLZ1, tLZ2 10 - 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - 5 - ns Chip disable to high-Z output tHZ1, tHZ2 0 20 0 20 0 25 ns Output disable to high-Z output tOHZ 0 15 0 20 0 25 ns Output hold from address change tOH 10 - 10 - 10 - ns Output enable to valid output Chip select to low-Z output WRITE CYCLE (Vcc = 2.7V to 3.6V, Gnd = 0V, TA = -40oC to +85oC) Parameter Symbol 45ns 55ns 70ns Unit Min Max Min Max Min Max tWC 45 - 55 - 70 - ns tCW1, tCW2 45 - 45 - 60 - ns Address setup time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 45 - 45 - 60 - ns Write pulse width tWP 35 - 40 - 50 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to ouput high-Z tWHZ 0 15 0 20 0 20 ns Data to write time overlap tDW 25 Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - ns Write cycle time Chip select to end of write 5 25 30 ns EM620FV8BS Series Low Power, 256Kx8 SRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH) tRC Address tAA tOH tCO1,2 CS1 CS2 tHZ1,2 tOE OE Data Out High-Z tOHZ tOLZ Data Valid tWHZ tLZ1,2 NOTES (READ CYCLE) 1. tHZ 1,2and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ1,2(Max.) is less than tLZ1,2(Min.) both for a given device and from device to device interconnection. 6 EM620FV8BS Series Low Power, 256Kx8 SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED) tWC Address tCW1,2(2) tWR(4) CS1 CS2 tAW tWP(1) WE tAS(3) Data in tDW High-Z High-Z Data Valid tWHZ Data out tDH tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED) tWC Address tAS(3) tCW1,2(2) tWR(4) CS1 CS2 tAW tWP(1) WE tDW Data in Data out Data Valid High-Z High-Z 7 tDH EM620FV8BS Series Low Power, 256Kx8 SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 CONTROLLED) tWC Address tCW1,2(2) tWR(4) CS1 tAS(3) CS2 tAW tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS1, a high CS2 and low WE. A write begins at the latest transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition among CS1 goes high, CS2 goes low and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE going high or CS2 going low. 8 EM620FV8BS Series Low Power, 256Kx8 SRAM DATA RETENTION CHARACTERISTICS Parameter Symbol VCC for Data Retention VDR Data Retention Current IDR Chip Deselect to Data Retention Time tSDR Operation Recovery Time tRDR Test Condition ISB1 Test Condition (Chip Disabled) 1) VCC=1.5V, ISB1 Test Condition (Chip Disabled) 1) See data retention wave form Min Typ2) Max Unit 1.5 - 3.6 V - 0.5 5.0 µA 0 - - tRC - - NOTES 1. See the ISB1 measurement condition of data sheet page 4. 2. Typical value is measured at TA=25oC and not 100% tested. DATA RETENTION WAVE FORM tSDR Data Retention Mode tRDR Vcc 3.0V 2.2V VDR CS1 > Vcc-0.2V CS1 GND Data Retention Mode Vcc 3.0V CS2 tRDR tSDR VDR 0.4V CS2 < 0.2V GND 9 ns EM620FV8BS Series Low Power, 256Kx8 SRAM PACKAGE DIMENSIONS 32Pin - sTSOP Type1 0.20 +0.10 - 0.05 0.008 -+0.004 0.002 Unit : millimeters/Inches 13.40 +/-0.20 0.528 +/- 0.008 0.10 0.004 MAX #1 #32 ( 0.25 ) 0.010 8.40 0.331MAX 0.50 0.0197 #16 0.25 TYP 0.010 8.00 0.315 #17 1.00 +/-0.10 0.039 +/- 0.004 11.80 +/-0.10 0.465 +/- 0.004 0.15 +0.10 - 0.05 0.006 -+0.004 0.002 0~8 0.50 ( 0.020 ) 0.45~0.75 0.018~0.030 10 1.20 MAX 0.047 0.05 0.002 MIN EM620FV8BS Series Low Power, 256Kx8 SRAM SRAM PART CODING SYSTEM EM X XX X X X XX X X - XX XX 1. EMLSI Memory 11. Power 2. Product Type 10. Speed 3. Density 4. Function 9. Package 5. Technology 8. Generation 6. Operating Voltage 7. Organization 1. Memory Component EM --------------------- Memory 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 2. Product Type 6 ------------------------ SRAM 8. Generation Blank ----------------- 1st generation A ----------------------- 2nd generation B ----------------------- 3rd generation C ----------------------- 4th generation D ----------------------- 5th generation E ----------------------- 6th generation F ----------------------- 7th generation G ---------------------- 8th generation 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 4. Function 0 ----------------------- Dual CS 1 ----------------------- Single CS 2 ----------------------- Multiplexed 3 ------------- Single CS / LBB, UBB(tBA=tOE) 4 ------------- Single CS / LBB, UBB(tBA=tCO) 5 ------------- Dual CS / LBB, UBB(tBA=tOE) 6 ------------- Dual CS / LBB, UBB(tBA=tCO) 9. Package Blank ---------------- KGD, 48&36FpBGA S ---------------------- 32 sTSOP1 T ---------------------- 32 TSOP1 U ---------------------- 44 TSOP2 V ---------------------- 32 SOP 5. Technology F ------------------------- Full CMOS 10. Speed 45 ---------------------55 ---------------------70 ---------------------85 ---------------------10 ---------------------12 ---------------------- 6. Operating Voltage T ------------------------- 5.0V V ------------------------- 3.3V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V 45ns 55ns 70ns 85ns 100ns 120ns 11. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power(Pb-Free & Green) L ---------------------- Low Power S ---------------------- Standard Power 11