merging Memory & Logic Solutions Inc. EM640FU8E Series Low Power, 512Kx8 SRAM Document Title 512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date 0.0 Initial Draft August 5 , 2002 0.1 2’nd Draft Changed Icc, Icc1 value & 55ns product tDW value November 11 , 2002 0.2 3’rd Draft tLZ1, tLZ2 value is changed from 5ns to 10ns March 13 , 2003 Remark tWP value is changed from 55ns to 50ns ( 70ns product ) tWP value is changed from 45ns to 40ns ( 55ns product ) VDR & IDR measurement condition change Changed ISB1 test conditions 0.3 4’th Draft Add Pb-free part number February 13 , 2004 Emerging Memory & Logic Solutions Inc. IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160 Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 EM640FU8E Series merging Memory & Logic Solutions Inc. Low Power, 512Kx8 SRAM FEATURES GENERAL DESCRIPTION • • • • • • The EM640FU8E families are fabricated by EMLSI’s advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current. Process Technology : 0.18µm Full CMOS Organization : 512K x 8 bit Power Supply Voltage : 2.7V ~ 3.3V Low Data Retention Voltage : 1.5V(Min) Three state output and TTL Compatible Package Type : 36-FPBGA 6.0x7.0 PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby (ISB1 , Typ) Operating (I CC1.Max) EM640FU8E Industrial (-40 ~ 85oC) 2.7V~3.3V 551) / 70ns 1 µA 2 mA PKG Type 36FPBGA 1. The parameter is measured with 30pF test load. PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM 1 2 3 4 5 6 A A0 A1 CS2 A3 A6 A8 B I/O 5 A2 WE A4 A7 I/O1 Pre-charge Circuit I/O 6 D V SS VCC E VC C V SS DNU A5 VCC Row S elect C A0 A1 A2 A3 A4 A5 A6 A7 I/O2 I/O 7 G I/O 8 H A9 A18 A17 OE CS1 A16 A15 I/O4 A10 A11 A12 A13 A14 I/O1 ~ I/O4 OE CS1 CS 1 ,CS 2 OE A 0 ~A18 I/O1 ~I/O 8 Name Function Chip select inputs WE Write Enable input Output Enable input Vcc Power Supply Address Inputs Vss Ground Data Inputs/outputs DNU Do Not Use I/O Circuit Column Select A11 A12 A13 A14 A15 A16 A17 A18 WE Function Data Cont Data Cont I/O3 36-FPBGA : Top view (ball down) Name 2048 x 2048 A8 A9 A10 I/O5 ~ I/O8 F VSS Memory Array CS2 2 Control Logic EM640FU8E Series merging Memory & Logic Solutions Inc. Low Power, 512Kx8 SRAM ABSOLUTE MAXIMUM RATINGS * Parameter Symbol Voltage on Any Pin Relative to Vss Ratings Unit VIN , VOUT -0.2 to Vcc+0.3 (Max. 4.0V) V VCC -0.2 to 4.0V V Power Dissipation PD 1.0 W Operating Temperature TA -40 to 85 oC Voltage on Vcc supply relative to Vss * Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION CS 1 CS 2 OE WE I/O Mode Power H X X X High-Z Deselected Stand by X L X X High-Z Deselected Stand by L H H H High-Z Output Disabled Active L H L H Data Out Read Active L H X L Data In Write Active Note: X means don’t care. (Must be low or high state) 3 EM640FU8E Series merging Memory & Logic Solutions Inc. Low Power, 512Kx8 SRAM RECOMMENDED DC OPERATING CONDITIONS 1) Parameter 1. 2. 3. 4. Symbol Min Typ Max Unit Supply voltage VCC 2.7 3.0 3.3 V Ground VSS 0 0 0 V Input high voltage VIH 2.2 - VCC + 0.22) V Input low voltage VIL -0.2 3) - 0.6 V TA= -40 to 85oC, otherwise specified Overshoot: V CC +2.0 V in case of pulse width < 20ns Undershoot: -2.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE 1) (f =1MHz, TA=25oC) Item Symbol Test Condition Min Max Unit Input capacitance C IN VIN=0V - 8 pF Input/Ouput capacitance CIO VIO =0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Parameter Symbol Test Conditions Min Typ Max Unit Input leakage current ILI V IN=V SS to V CC -1 - 1 µA Output leakage current ILO CS 1 = VIH , CS2 =VIL or OE=V IH or WE=VIL , VIO= VSS to V CC -1 - 1 µA Operating power supply ICC I IO=0mA, CS 1=V IL, CS 2=WE = VIH , VI N=VI H or VIL - - 2 mA - - 2 mA 55ns - - 20 70ns - - 15 Cycle time=1µs, 100% duty, I IO=0mA, I CC1 Average operating current CS 1< 0.2V, CS2 >V CC -0.2V, V IN< 0.2V or VIN >V CC-0.2V I CC2 Cycle time = Min, I IO =0mA, 100% duty, CS 1=V IL, CS2 =V IH, V IN=V IL or VI H Output low voltage VOL I OL = 2.1mA - - 0.4 V Output high voltage VOH I O H = -1.0mA 2.2 - - V - - 0.3 mA - 1 5 µA Standby Current (TTL) ISB CS 1 = VIH , CS2 =VIL , Other inputs=V IH or V IL CS 1 >V CC-0.2V, CS 2>V C C-0.2V (CS 1 controlled) or 0V<CS 2 <0.2V (CS 2 controlled), Standby Current (CMOS) ISB1 Other inputs=0~V CC o (Typ. condition : V C C=3.0V @ 25 C) (Max. condition : V CC=3.3V @ 85 o C) 4 LL LF mA EM640FU8E Series merging Memory & Logic Solutions Inc. Low Power, 512Kx8 SRAM VTM 3) AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) R12) Input Pulse Level : 0.4 to 2.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL = 100pF+ 1 TTL R22) CL1) CL 1) = 30pF + 1 TTL 1. Including scope and Jig capacitance 2. R1 =3070Ω, R 2 =3150Ω 3. VTM=2.8V READ CYCLE (V cc =2.7 to 3.3V, Gnd = 0V, T A = -40oC to +85oC) Parameter 55ns Symbol 70ns Min Max Min Max Unit Read cycle time tRC 55 - 70 - ns Address access time tAA - 55 - 70 ns Chip select to output tco1, tco2 - 55 - 70 ns tO E - 30 - 35 ns tLZ1, tLZ2 10 - 10 - ns tOLZ 5 - 5 - ns tHZ1, tHZ2 0 20 0 25 ns Output disable to high-Z output tOHZ 0 20 0 25 ns Output hold from address change tOH 10 - 10 - ns Output enable to valid output Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output WRITE CYCLE (Vcc =2.7 to 3.3V, Gnd = 0V, TA = -40oC to +85oC) Parameter 55ns Symbol 70ns Unit Min Max Min Max tWC 55 - 70 - ns tCW1, tCW2 45 - 60 - ns Address setup time tAs 0 - 0 - ns Address valid to end of write tAW 45 - 60 - ns Write pulse width tWP 40 - 50 - ns Write recovery time tWR 0 - 0 - ns Write to ouput high-Z tWHZ 0 20 0 25 ns Data to write time overlap tDW 30 Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns Write cycle time Chip select to end of write 5 30 ns merging Memory & Logic Solutions Inc. EM640FU8E Series Low Power, 512Kx8 SRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=VIL, CS2= WE=V IH ) tRC Address tAA tOH Data Out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH) tRC Address tAA tOH tCO CS1 CS2 tHZ tOE OE tOHZ tOLZ Data Out High-Z Data Valid tLZ NOTES (READ CYCLE) 1. t HZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels. 2. At any given temperature and voltage condition, t HZ(Max.) is less than t LZ(Min.) both for a given device and from device to device interconnection. 6 EM640FU8E Series merging Memory & Logic Solutions Inc. Low Power, 512Kx8 SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED) tWC Address tCW (2) tWR (4) CS1 CS2 tAW tWP (1) WE tAS(3) Data in tDH tDW High-Z High-Z Data Valid tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED) tWC Address tAS(3) tCW (2) tWR (4) CS1 CS2 tAW tWP (1) WE tDW Data in Data out Data Valid High-Z High-Z 7 tDH EM640FU8E Series merging Memory & Logic Solutions Inc. Low Power, 512Kx8 SRAM TIMING WAVEFORM OF WRITE CYCLE(3) ( CS2 CONTROLLED) tWC Address tCW(2) tW R(4) CS1 tAS(3) CS2 tAW tW P(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP ) of low CS1, a high CS2 and low WE. A write begins at the latest transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition when CS1 goes high, CS2 goes hagh and WE goes high. The t WP is measured from the beginning of write to the end of write. 2. t CW is measured from the CS1 going low to end of write. 3. t A S is measured from the address valid to the beginning of write. 4. t WR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE going high. 8 EM640FU8E Series merging Memory & Logic Solutions Inc. Low Power, 512Kx8 SRAM DATA RETENTION CHARACTERISTICS Parameter Symbol VCC for Data Retention VDR Data Retention Current I DR Chip Deselect to Data Retention Time tSDR Operation Recovery Time tRDR Test Condition ISB1 Test Condition (Chip Disabled) 1) VCC =1.5V, ISB1 Test Condition (Chip Disabled) 1) See data retention wave form Min Typ Max Unit 1.5 - 3.3 V - 0.5 - µA 0 - - t RC - - NOTES 1. See the IS B 1 measurement condition of datasheet page 4. DATA RETENTION WAVE FORM CS1 Controlled tSDR Data Retention Mode tRDR Vcc 2.7V 2.2V VDR CS 1 > Vcc-0.2V CS 1 GND CS2 Controlled Vcc 2.7V CS2 Data Retention Mode tRDR tSDR VDR 0.4V CS 2 < 0.2V GND 9 ns EM640FU8E Series merging Memory & Logic Solutions Inc. Low Power, 512Kx8 SRAM Unit: millimeters PACKAGE DIMENSION 36 Ball Fine Pitch BGA (0.75mm ball pitch) Bottom View Top View A1 index Mark B B1 6 5 4 3 0.5 0.5 B 2 1 A B #A1 C C1 C C D C1/2 E F G H B/2 E2 0.26 Side View Detail A D 0.25 Typ. E E1 A Min Typ Max A - 0.75 - B 5.93 6.00 6.03 B1 - 3.75 - C 6.93 7.00 7.03 C1 - 5.25 - D 0.30 0.35 0.40 E 1.00 1.04 1.10 E1 - 0.79 - E2 - 0.25 - Y - - 0.08 0.79 Typ. C Y NOTES. 1. Bump counts : 36(8row x 6column) 2. Bump pitch : (x,y)=(0.75x0.75) (typ.) 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity : 0.08(Max) 10 merging Memory & Logic Solutions Inc. EM640FU8E Series Low Power, 512Kx8 SRAM MEMORY FUNCTION GUIDE EM X XX X X X XX X X - XX XX 1. EMLSI Memory 11. Power 2. Device Type 10. Speed 3. Density 4. Option 9. Packages 5. Technology 8. Version 6. Operating Voltage 7. Organization 1. Memory Component 8. Version Blank ----------------- Mother Die A ----------------------- First revision B ----------------------- Second revision C ----------------------- Third revision D ----------------------- Fourth revision 2. Device Type 6 ------------------------ Low Power SRAM 7 ------------------------ STRAM 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 16 ----------------------- 16M 32 ----------------------- 32M 64 ----------------------- 64M 9. Package Blank ---------------------- Package W --------------------- Wafer 10. Speed 45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 10 --------------------- 100ns 12 --------------------- 120ns 4. Option 0 ----------------------- Dual CS 1 ----------------------- Single CS 5. Technology Blank ------------------ CMOS F ------------------------ Full CMOS 11. Power LL ---------------------- Low Low Power L ---------------------- Low Power S ---------------------- Standard Power LF ---------------------- Low Low Power (Pb-free) 6. Operating Voltage Blank ------------------- 5V V ------------------------- 3.3V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 11