ETRON EM6A9320BI-3.0

EtronTech
EM6A9320
4M x 32 DDR SDRAM
Preliminary (Rev 0.6 5/2006)
Features
Overview
• Fast clock rate: 350/333/300/285/250/200 MHz
• Differential Clock CK & CK# input
The EM6A9320 DDR SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 128
Mbits. It is internally configured as a quad 1M x 32
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal, CK).
• 4 Bi-directional DQS. Data transactions on both
edges of DQS (1DQS / Byte)
• DLL aligns DQ and DQS transitions
• Edge aligned data & DQS output
• Center aligned data & DQS input
• 4 internal banks, 1M x 32-bit for each bank
• Programmable mode and extended mode
registers
- CAS# Latency: 3, 4, 5
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleave
• Full page burst length for sequential type only
• Start address of full page burst should be even
• All inputs except DQ’s & DM are at the positive
edge of the system clock
• No Write-Interrupted by Read function
• 4 individual DM control for write masking only
• Auto Refresh and Self Refresh
• 4096 refresh cycles / 32ms
• Power supplies up to 350/333/300/285MHz:
VDD = 2.8V ± 5%
Data outputs occur at both rising edges of CK and CK#.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence.
Accesses begin with the registration of a BankActivate
command, which is then followed by a Read or Write
command.
The EM6A9320 provides programmable Read or Write
burst lengths of 2, 4, 8. An auto precharge function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.
The refresh functions, either Auto or Self Refresh are
easy to use.
In addition, EM6A9320 features programmable DLL
option. By having a programmable mode register and
extended mode register, the system can choose the
most suitable modes to maximize its performance.
These devices are well suited for applications requiring
high memory bandwidth, result in a device particularly
well suited to high performance main memory and
graphics applications.
VDDQ = 2.8V ± 5%
• Power supplies up to 250/200MHz:
VDD = 2.8V ± 5%
VDDQ = 2.8V ± 5%
• Interface : SSTL_2 I/O compatible
• Standard 144-ball FBGA package
Ordering Information
Part Number
EM6A9320BI-2.8
EM6A9320BI-3.0
EM6A9320BI-3.3
EM6A9320BI-3.5
EM6A9320BI-3.6
EM6A9320BI-4
EM6A9320BI-5
Frequency
350MHz
333MHz
300MHz
285MHz
275MHz
250MHz
200MHz
Power Supply
VDD 2.8V
VDDQ 2.8V
Package
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
EtronTech
EM6A9320
4Mx32 DDR SDRAM
Pin Assignment (FBGA 144Ball Top View)
Note: VSS pins for thermal balls are optional
1
2
3
4
5
6
7
8
9
10
11
12
A
DQS0
DM0
VSSQ
DQ3
DQ2
DQ0
DQ31
DQ29
DQ28
VSSQ
DM3
DQS3
B
DQ4
VDDQ
NC
VDDQ
DQ1
VDDQ
VDDQ
DQ30
VDDQ
NC
VDDQ
DQ27
C
DQ6
DQ5
VSSQ
VSSQ
VSSQ
VDD
VDD
VSSQ
VSSQ
VSSQ
DQ26
DQ25
D
DQ7
VDDQ
VDD
VSS
VSSQ
VSS
VSS
VSSQ
VSS
VDD
VDDQ
DQ24
E
DQ17
DQ16
VDDQ
VSSQ
VSS
VSS
VSS
VSS
VSSQ
VDDQ
DQ15
DQ14
F
DQ19
DQ18
VDDQ
VSSQ
VSS
VSS
VSS
VSS
VSSQ
VDDQ
DQ13
DQ12
G
DQS2
DM2
NC
VSSQ
VSS
VSS
VSS
VSS
VSSQ
NC
DM1
DQS1
H
DQ21
DQ20
VDDQ
VSSQ
VSS
VSS
VSS
VSS
VSSQ
VDDQ
DQ11
DQ10
J
DQ22
DQ23
VDDQ
VSSQ
VSS
VSS
VSS
VSS
VSSQ
VDDQ
DQ9
DQ8
K
CAS#
WE#
VDD
VSS
A10
VDD
VDD
NC
VSS
VDD
NC
NC
L
RAS#
NC
NC
BA1
A2
A11
A9
A5
NC
CK
CK#
NC
M
CS#
NC
BA0
A0
A1
A3
A4
A6
A7
A8
CKE
VREF
Pin Assignment by Name (FBGA 144Ball)
Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location
A0
M4
DQ6
C1 DQ24 D12
CK
L10 VDDQ B6
VSS
E5
VSS
J7 VSSQ G4
A1
M5
DQ7
D1 DQ25 C12
CK#
L11 VDDQ B7
VSS
E6
VSS
J8 VSSQ G9
A2
L5
DQ8
J12 DQ26 C11 CKE M11 VDDQ B9
VSS
E7
VSS
K4 VSSQ H4
A3
M6
DQ9
J11 DQ27 B12
CS#
M1 VDDQ B11
VSS
E8
VSS
K9 VSSQ H9
A4
M7 DQ10 H12 DQ28 A9
RAS#
L1 VDDQ D2
VSS
F5 VSSQ A3 VSSQ
J4
A5
L8
DQ11 H11 DQ29 A8
CAS# K1 VDDQ D11 VSS
F6 VSSQ A10 VSSQ
J9
A6
M8 DQ12 F12 DQ30 B8
WE#
K2 VDDQ E3
VSS
F7 VSSQ C3
NC
B3
A7
M9 DQ13 F11 DQ31 A7 VREF M12 VDDQ E10
VSS
F8 VSSQ C4
NC
B10
A8/AP M10 DQ14 E12 DQS0 A1
VDD
C6 VDDQ F3
VSS
G5 VSSQ C5
NC
G3
A9
L7
DQ15 E11 DQS1 G12 VDD
C7 VDDQ F10
VSS
G6 VSSQ C8
NC
G10
A10
K5 DQ16 E2 DQS2 G1
VDD
D3 VDDQ H3
VSS
G7 VSSQ C9
NC
K8
A11
L6
DQ17 E1 DQS3 A12 VDD D10 VDDQ H10 VSS
G8 VSSQ C10
NC
K11
DQ0
A6 DQ18
F2
DM0
A2
VDD
K3 VDDQ J3
VSS
H5 VSSQ D5
NC
K12
DQ1
B5 DQ19
F1
DM1 G11 VDD
K6 VDDQ J10
VSS
H6 VSSQ D8
NC
L2
DQ2
A5 DQ20 H2
DM2
G2
VDD
K7
VSS
D4
VSS
H7 VSSQ E4
NC
L3
DQ3
A4 DQ21 H1
DM3 A11 VDD K10
VSS
D6
VSS
H8 VSSQ E9
NC
L9
DQ4
B1 DQ22
J1
BA0
M3 VDDQ B2
VSS
D7
VSS
J5 VSSQ F4
NC
L12
DQ5
C2 DQ23
J2
BA1
L4 VDDQ B4
VSS
D9
VSS
J6 VSSQ F9
NC
M2
2
Rev 0.6
May. 2006
EtronTech
EM6A9320
4Mx32 DDR SDRAM
Block Diagram
Row Decoder
Column Decoder
4096 X 256 X 32
CELL ARRAY
(BANK #0)
Sense Amplifier
DLL
CLOCK
BUFFER
CK
CK#
CONTROL
SIGNAL
GENERATOR
CKE
CS#
RAS#
CAS#
WE#
Row Decoder
Sense Amplifier
COMMAND
DECODER
MODE
REGISTER
4096 X 256 X 32
CELL ARRAY
(BANK #1)
Column Decoder
COLUMN
COUNTER
A8/AP
A0
Row Decoder
Column Decoder
ADDRESS
BUFFER
A10
A11
BA0
BA1
4096 X 256 X 32
CELL ARRAY
(BANK #2)
Sense Amplifier
REFRESH
COUNTER
DQS0~3
Sense Amplifier
Row Decoder
DATA
STROBE
BUFFER
DQ
BUFFER
DQ0
│
DQ31
4096 X 256 X 32
CELL ARRAY
(BANK #3)
Column Decoder
DM0~3
3
Rev 0.6
May. 2006
EtronTech
4Mx32 DDR SDRAM
EM6A9320
Pin Descriptions
Table 1. Pin Details of EM6A9320
Symbol
CK, CK#
Type
Input
CKE
Input
BA0, BA1
Input
A0-A11
Input
CS#
Input
RAS#
Input
CAS#
Input
WE#
Input
DQS0-DQS3
Input /
Output
DM0 - DM3
Input
DQ0 - DQ31
Input /
Output
Supply
VDD
Description
Differential Clock: CK, CK# are driven by the system clock. All SDRAM input
commands are sampled on the positive edge of CK. Both CK and CK# increment the
internal burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE
goes low synchronously with clock, the internal clock is suspended from the next
clock cycle and the state of output and burst address is frozen as long as the CKE
remains low. When all banks are in the idle state, deactivating the clock controls the
entry to the Power Down and Self Refresh modes.
Bank Select: BA0 and BA1 defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied. They also define which Mode Register or
Extended Mode Register is loaded during a Mode Register Set command.
Address Inputs: A0-A11 are sampled during the Bank Activate command (row
address A0-A11) and Read/Write command (column address A0-A7 with A8 defining
Auto Precharge) to select one location out of the 256K available in the respective
bank. During a Precharge command, A8 is sampled to determine if all banks are to
be precharged (A8 = HIGH). The address inputs also provide the op-code during a
Mode Register Set or Extended Mode Register Set command.
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH. CS#
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges of
CK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH" either
the BankActivate command or the Precharge command is selected by the WE#
signal. When the WE# is asserted "HIGH," the BankActivate command is selected
and the bank designated by BS is turned on to the active state. When the WE# is
asserted "LOW," the Precharge command is selected and the bank designated by BS
is switched to the idle state after the precharge operation.
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CK. When RAS# is held "HIGH" and CS# is asserted "LOW" the column access is
started by asserting CAS# "LOW" Then, the Read or Write command is selected by
asserting WE# "HIGH " or “LOW".
Write Enable: The WE# signal defines the operation commands in conjunction with
the RAS# and CAS# signals and is latched at the positive edges of CK. The WE#
input is used to select the BankActivate or Precharge command and Read or Write
command.
Bidirectional Data Strobe: The DQSx signals are mapped to the following data
bytes: DQS0 to DQ0-DQ7, DQS1 to DQ8-DQ15, DQS2 to DQ16-DQ23, DQS3 to
DQ24-DQ31.
Data Input Mask: DM0-DM3 are byte specific. Input data is masked when DM is
sampled HIGH during a write cycle. DM3 masks DQ31-DQ24, DM2 masks DQ23DQ16, DM1 masks DQ15-DQ8, and DM0 masks DQ7-DQ0.
Data I/O: The DQ0-DQ31 input and output data are synchronized with the positive
edges of CK and CK#. The I/Os are byte-maskable during Writes.
Power Supply: Power for the input buffers and core logic.
4
Rev 0.6
May. 2006
EtronTech
VSS
4Mx32 DDR SDRAM
EM6A9320
Supply
Ground: Ground for the input buffers and core logic.
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
VDDQ
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
VSSQ
Supply Reference Voltage for Inputs: +0.5 x VDDQ
VREF
NC
No Connect: These pins should be left unconnected.
Note: The timing reference point for the differential clocking is the cross point of the CK and CK#. For any
applications using the single ended clocking, apply VREF to CK# pin.
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CK . Table 2
shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
BankActivate
BankPrecharge
PrechargeAll
Write
Write and AutoPrecharge
Read
Read and Autoprecharge
Mode Register Set
Extended Mode Register Set
No-Operation
Device Deselect
Burst Stop
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
State
CKEn-1 CKEn DM BA1 BA0
(3)
Idle
H
X
X
V
V
Any
H
X
X
V
V
Any
H
X
X
X
X
Active(3)
H
X
V
V
V
(3)
H
X
V
V
V
Active
(3)
Active
H
X
X
V
V
Active(3)
H
X
X
V
V
Idle
H
X
X
L
L
Idle
H
X
X
L
H
Any
H
X
X
X
X
Any
H
X
X
X
X
Active(4)
H
X
X
X
X
Idle
H
H
X
X
X
Idle
H
L
X
X
X
Idle
L
H
X
X
X
(Self Refresh)
Power Down Mode Entry Idle/Active(5)
H
L
X
X
X
A8 A11-A9, A7-0 CS# RAS# CAS# WE#
Row Address
L
L
H
H
L
X
L
L
H
L
H
X
L
L
H
L
L
L
H
L
L
Column
H
L
H
L
L
Address
L
L
H
L
H
A0~A7
H
L
H
L
H
L
L
L
L
OP code
L
L
L
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
H
H
L
X
X
L
L
L
H
X
X
L
L
L
H
H
X
X
X
X
X
L
H
H
H
H
X
X
X
X
X
L
H
H
H
H
X
X
X
X
X
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
Any
L
H
X
X
X
(Power Down)
Active
H
X
L
X
X
Data Write/Output Enable
Active
H
X
H
X
X
Data Mask/Output Disable
Note: 1. V = Valid data, X = Don't Care, L = Low level, H = High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA0, BA1signals.
4. Read burst stop with BST command for all burst types.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
Power Down Mode Exit
5
Rev 0.6
May. 2006
EtronTech
EM6A9320
4Mx32 DDR SDRAM
Mode Register Set (MRS)
The mode register is divided into various fields depending on functionality.
Burst Length Field (A2, A1, A0)
•
This field specifies the data length of column access and selects the Burst Length.
Addressing Mode Select Field (A3)
•
The Addressing Mode can be Interleave Mode or Sequential Mode. Both Sequential Mode and
Interleave Mode support burst length of 2, 4 and 8. Full page burst length is only for Sequential mode.
CAS# Latency Field (A6, A5, A4)
•
This field specifies the number of clock cycles from the assertion of the Read command to the first
read data. The minimum whole value of CAS# Latency depends on the frequency of CK. The
minimum whole value satisfying the following formula must be programmed into this field.
CAS# Latency X tCK
tCAC(min)
Test Mode field :A7; DLL Reset Mode field : A8
•
These two bits must be programmed to "00" in normal operation.
( BA0, BA1)
•
≦
Mode Resistor Bitmap
BA1
0
BA0
A11
A10
A9
Mode RFU must be set to “0”
BA0
0
1
A6
0
0
1
1
A5
1
1
0
0
Register Mode
MRS
EMRS
A8
DLL
A7
TM
A8
0
1
0
A7
0
0
1
A6
A5
A4
CAS Latency
Mode
Normal
Reset DLL
Test Mode
A4
CAS Latency
0
Reserved
1
3 clocks
0
4 clocks
1
5 clocks
All other Reserved
A2
0
0
0
1
A3
BT
A3
0
1
A1
0
1
1
1
A2
A1
A0
Burst Lenght
Type
Sequential
Interleave
A0
Burst Length
1
2
0
4
1
8
1
Full Page (Sequential)
All other Reserved
Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Burst Length
2
4
8
Start Address
A2
A1
A0
X
X
0
X
X
1
X
0
0
X
0
1
X
1
0
X
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Sequential
Interleave
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
6
Rev 0.6
May. 2006
EtronTech
EM6A9320
4Mx32 DDR SDRAM
Extended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore must be written after power
up for proper operation. The extended mode register is written by asserting low on CS#, RAS#, CAS#, and
WE#. The state of A0, A2 ~ A5, A7 ~ A11and BA1 is written in the mode register in the same cycle as CS#,
RAS#, CAS#, and WE# going low. The DDR SDRAM should be in all bank precharge with CKE already high
prior to writing into the extended mode register. A1 and A6 are used for setting driver strength to normal, weak
or matched impedance. Two clock cycles are required to complete the write operation in the extended mode
register. The mode register contents can be changed using the same command and clock cycle requirements
during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0
is used for EMRS. Refer to the table for specific codes.
Extended Mode Resistor Bitmap
BA1
0
BA0
1
BA0 Mode
0
MRS
1 EMRS
A11
A6
0
0
1
1
A10
A9
A8
RFU must be set to “0”
A7
A6
DS1
A5
A4
A3
A2
RFU must be set to “0”
A1
Drive Strength
Strength
Comment
0
Full
100%
1
SSTL-2 weak
60%
0
RFU
RFU Do not use
1 Matched impedance 30% Output driver matches impedance
A1
DS0
A0
DLL
A0
DLL
0
Enable
1 Disable
Power up Sequence
Power up must be performed in the following sequence.
1) Apply power to VDD before or at the same time as VDDQ, VTT and VREF when all input signals are held
"NOP" state and maintain CKE “LOW”.
2) Start clock and maintain stable condition for minimum 200us.
3) Issue a “NOP” command and keep CKE “HIGH”
4) Issue a “Precharge All” command.
5) Issue EMRS – enable DLL.
6) Issue MRS – reset DLL. (An additional 200 clock cycles are required to lock the DLL).
7) Precharge all banks of the device.
8) Issue two or more Auto Refresh commands.
9) Issue MRS – with A8 to low to initialize the mode register.
7
Rev 0.6
May. 2006
EtronTech
EM6A9320
4Mx32 DDR SDRAM
Absolute Maximum Rating
Symbol
VIN, VOUT
VDD, VDDQ
TA
TSTG
TSOLDER
PD
IOUT
Item
Input, Output Voltage
Power Supply Voltage
Ambient Temperature
Storage Temperature
Soldering Temperature (10s)
Power Dissipation
Short Circuit Output Current
Rating
- 0.3 ~ VDDQ+0.3
-0.3 ~ 3.6
0~70
- 55~150
240
2.0
50
Unit
V
V
°C
°C
°C
W
mA
Recommended D.C. Operating Conditions (SSTL_2 In/Out, TA = 0 ~ 70 °C)
Symbol
VDD
VDDQ
VREF
VTT
VIH(DC)
VIL(DC)
Parameter
Min.
Power Supply Voltage
2.66
Power Supply Voltage(for I/O )
2.66
Input Reference Voltage
0.49 x VDDQ
Termination Voltage
VREF – 0.04
Input High Voltage
VREF + 0.15
Input Low Voltage
Vssq - 0.3
VOH
Output High Voltage
VOL
IIL
IOL
Output Low Voltage
Input Leakage Current
Output Leakage Current
Note :
Typ.
2.8
2.8
VREF
-
Max.
Unit
2.94
V
2.94
V
0.51 x VDDQ
V
VREF + 0.04 V
VDDQ + 0.3
V
VREF- 0.15
V
Note
Vtt + 0.76
-
-
V
IOH = -15.2 mA
-5
-5
-
Vtt- 0.76
5
5
V
uA
uA
IOL = +15.2 mA
Under all conditions VDDQ must be less than or equal to VDD.
Capacitance (VDD = 2.8V, f = 1MHz, TA = 25 °C)
Parameter
Input Capacitance (A0~A11, BA0, BA1)
Input Capacitance (CK, CK#, CKE, CS#, RAS#, CAS#, WE#)
DQ & DQS input/output capacitance
DM0~DM3 input/output capacitance
Symbol
CIN1
CIN2
COUT
CIN3
Min.
4
3
6
6
Max.
5
5
8
8
Unit
pF
pF
pF
pF
Note: These parameters are periodically sampled and are not 100% tested.
8
Rev 0.6
May. 2006
EtronTech
EM6A9320
4Mx32 DDR SDRAM
D.C. Characteristics
(VDD = 2.8V ± 5%, TA = 0~70 °C)
Parameter & Test Condition
Symbol
OPERATING CURRENT : One bank; ActivePrecharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and
DQS inputs changing once per clock cycle; Address
and control inputs changing once every two clock
cycles.
OPERATING CURRENT : One bank; Active-ReadPrecharge; BL=4; CL=4; tRCDRD=4*tCK;
tRC=tRC(min); tCK=tCK(min); lout=0mA; Address and
control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY
CURRENT: All banks idle; power-down mode;
tCK=tCK(min); CKE=LOW
IDLE STANDLY CURRENT : CKE = HIGH;
CS#=HIGH(DESELECT); All banks idle; tCK=tCK(min);
Address and control inputs changing once per clock
cycle; VIN=VREF for DQ, DQS and DM
ACTIVE POWER-DOWN STANDBY CURRENT : one
bank active; power-down mode; CKE=LOW;
tCK=tCK(min)
ACTIVE STANDBY CURRENT :
CS#=HIGH;CKE=HIGH; one bank active ;
tRC=tRC(max);tCK=tCK(min);Address and control inputs
changing once per clock cycle; DQ,DQS,and DM
inputs changing twice per clock cycle
OPERATING CURRENT BURST READ : BL=2;
READS; Continuous burst; one bank active; Address
and control inputs changing once per clock cycle;
tCK=tCK(min); lout=0mA;50% of data changing on
every transfer
OPERATING CURRENT BURST Write : BL=2;
WRITES; Continuous Burst ;one bank active; address
and control inputs changing once per clock cycle;
tCK=tCK(min); DQ,DQS,and DM changing twice per
clock cycle; 50% of data changing on every transfer
AUTO REFRESH CURRENT : tRC=tRFC(min);
tCK=tCK(min)
SELF REFRESH CURRENT: Sell Refresh Mode ;
CKE<=0.2V;tCK=tCK(min)
BURST OPERATING CURRENT 4 bank operation:
Four bank interleaving READs; BL=4;with Auto
Precharge; tRC=tRC(min); tCK=tCK(min); Address and
control inputschang only during Active, READ , or
WRITE command
2.8 3.0 3.3 3.5 3.6
Max
4
5
Unit
IDD0
330 320 280 260 250 180 160 mA
IDD1
450 440 380 360 340 260 240 mA
IDD2P
50
50
45
40 mA
IDD2N 100 100 100 100 100
80
80 mA
IDD3P
45
40 mA
50
50
50
50
50
50
50
50
IDD3N 140 135 120 110 110 100 100 mA
IDD4R 560 540 480 450 450 440 420 mA
IDD4W 470 450 400 370 360 300 270 mA
IDD5
IDD6
IDD7
430 430 420 410 390 300 280 mA
4
4
4
4
4
3
3 mA
920 890 780 720 710 650 550 mA
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device.
2. All voltages are referenced to VSS.
3. Power-up sequence is described in previous page.
9
Rev 0.6
May. 2006
EtronTech
EM6A9320
4Mx32 DDR SDRAM
Decoupling Capacitance Guide Line
Symbol
Parameter
CDC1 Decouping Capacitance between VDD and VSS
CDC2 Decouping Capacitance between VDDQ and VSSQ
Value
0.1+0.01
0.1+0.01
Unit
uF
uF
AC Input Operating Conditions
(VDD = 2.8V ± 5%, Ta = 0~70 °C)
Symbol
VIH
VIL
VID
VIX
Parameter
Input High Voltage; DQ
Input Low Voltage; DQ
Clock Input Differential Voltage; Ck & CK#
Clock Input Crossing Point Voltage; Ck & CK#
Min
VREF+0.4
0.8
0.5xVDDQ-0.2
Max
VREF-0.4
VDDQ+0.6
0.5xVDDQ+0.2
Unit
V
V
V
V
AC Operating Test Conditions
(VDD = 2.8V ± 5%, Ta = 0~70 °C)
Reference Level of Output Signals (VRFE)
CK & CK# signal maximum peak swing
Output Load
Input Signal Levels
Input Signals Slew Rate
Input timing measurement reference level
Output timing measurement reference level
Reference Level of Input Signals
0.5 x VDDQ
1.5V
See Figure. A Test Load
VREF+0.4 V / VREF-0.4 V
1 V/ns
VREF
VTT
0.5 x VDDQ
Figure A. Test Load
VTT=0.5 x VDDQ
50 Ω
DQ,DQS
Z0=50 W
30pF VREF=0.5 x VDDQ
10
Rev 0.6
May. 2006
EtronTech
EM6A9320
4Mx32 DDR SDRAM
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 2.8V ± 5%, Ta = 0~70 °C)
Symbol
2.8
Parameter
CL = 3
CL = 4
CL = 5
3.0
3.3
3.5
Min
Max
Min
Max
Min
Max
Min
Max
3.3
2.86
2.86
10
10
5
3.3
3.0
3.0
10
10
5
3.3
3.3
3.3
10
10
5
3.5
3.5
3.5
10
10
5
tCK
Clock cycle time
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
tIH
tDS
tDH
Clock high level width
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
Clock low level width
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
ns
-
0.35
-
0.35
-
0.4
-
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
ns
tCK
tCK
tCK
ns
ns
ns
ns
tCLMIN
or
tCHMIN
-
tCLMIN
or
tCHMIN
-
tCLMIN
or
tCHMIN
-
tCLMIN
or
tCHMIN
-
ns
tHP 0.35
-
tHP 0.35
-
tHP 0.35
-
tHP 0.4
-
ns
-
20
-
17
-
16
-
DQS-out access time from CK,CK#
-0.6
0.6
-0.6
0.6
-0.6
0.6
-0.6
0.6
Output access time from CK,CK#
-0.6
0.6
-0.6
0.6
-0.6
0.6
-0.6
0.6
DQS-DQ Skew
-
0.35
-
0.35
-
0.35
-
0.4
Read preamble
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
Read postamble
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CK to valid DQS-in
0.85
1.15
0.85
1.15
0.85
1.15
0.85
1.15
DQS-in setup time
0
-
0
-
0
-
0
-
DQS-in hold time
0.35
-
0.35
-
0.35
-
0.35
-
DQS write postamble
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
DQS in high level pulse width
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
DQS in low level pulse width
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
Address and Control input setup time
0.9
-
0.9
-
0.9
-
0.9
-
Address and Control input hold time
0.9
-
0.9
-
0.9
-
0.9
-
DQ & DM setup time to DQS
0.35
-
0.35
-
0.35
-
0.4
-
0.35
DQ & DM hold time to DQS
Unit
tHP
Clock half period
tQH
Output DQS valid window
tRC
tRFC
tRAS
tRCDRD
tRCDWR
tRP
tRRD
twR
tCDLR
tCCD
tMRD
tDAL
tXSA
Row cycle time
20
Refresh row cycle time
22
-
22
-
19
-
18
-
Row active time
14
100K
14
100K
12
100K
11
100K
RAS# to CAS# Delay in Read
7
-
7
-
6
-
5
-
RAS# to CAS# Delay in Write
5
-
5
-
4
-
3
-
Row precharge time
6
-
6
-
5
-
3
-
Row active to Row active delay
4
-
4
-
3
-
3
-
Write recovery time
3
-
3
-
3
-
3
-
Last data in to Read command
2
-
2
-
2
-
2
-
Col. Address to Col. Address delay
1
-
1
-
1
-
1
-
Mode register set cycle time
1
-
1
-
1
-
1
-
Auto precharge write recovery + Precharge
9
-
9
-
9
-
9
-
Self refresh exit to read command delay
200
-
200
-
200
-
200
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tPDEX
Power down exit time
tIS +
2tCK
-
tIS +
2tCK
-
tIS +
2tCK
-
tIS +
2tCK
-
ns
tREF
Refresh interval time
-
7.8
-
7.8
-
7.8
7.8
us
11
Rev 0.6
May. 2006
EtronTech
Symbol
EM6A9320
4Mx32 DDR SDRAM
3.6
Parameter
CL = 3
CL = 4
CL = 5
Min
Max
Min
3.6
3.6
3.6
10
10
5
4
4
4
4.0
Max
5.0
Min
Max
10
10
5
5
5
5
10
10
10
tCK
Clock cycle time
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
tIH
tDS
tDH
Clock high level width
0.45
0.55
0.45
0.55
0.45
0.55
Clock low level width
0.45
0.55
0.45
0.55
0.45
0.55
DQS-out access time from CK,CK#
-0.6
0.6
-0.7
0.7
-0.7
0.7
Output access time from CK,CK#
tHP
Clock half period
tQH
Output DQS valid window
tRC
tRFC
tRAS
tRCDRD
tRCDWR
tRP
tRRD
twR
tCDLR
tCCD
tMRD
tDAL
tXSA
9
-
8
-
7
-
Self refresh exit to read command delay
200
-
200
-
200
tPDEX
Power down exit time
tIS +
2tCK
-
tIS +
2tCK
-
tIS +
2tCK
tREF
Refresh interval time
7.8
-
7.8
Unit
ns
DQ & DM setup time to DQS
0.4
-
0.45
-
0.5
-
DQ & DM hold time to DQS
0.4
-
0.45
-
0.5
-
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
ns
tCK
tCK
tCK
ns
ns
ns
ns
tCLMIN
or
tCHMIN
-
tCLMIN
or
tCHMIN
-
tCLMIN
or
tCHMIN
-
ns
tHP 0.4
-
tHP 0.45
-
tHP 0.5
-
ns
Row cycle time
16
-
15
-
12
-
Refresh row cycle time
18
-
17
-
14
-
Row active time
11
100K
10
100K
8
100K
RAS# to CAS# Delay in Read
5
-
5
-
4
-
RAS# to CAS# Delay in Write
3
-
3
-
2
-
Row precharge time
3
-
3
-
3
-
Row active to Row active delay
3
-
3
-
2
-
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
-
ns
7.8
us
-0.6
0.6
-0.7
0.7
-0.7
0.7
DQS-DQ Skew
-
0.4
-
0.4
-
0.45
Read preamble
0.9
1.1
0.9
1.1
0.9
1.1
Read postamble
0.4
0.6
0.4
0.6
0.4
0.6
CK to valid DQS-in
0.85
1.15
0.85
1.15
0.85
1.15
DQS-in setup time
0
-
0
-
0
-
DQS-in hold time
0.35
-
0.35
-
0.35
-
DQS write postamble
0.4
0.6
0.4
0.6
0.4
0.6
DQS in high level pulse width
0.4
0.6
0.4
0.6
0.4
0.6
DQS in low level pulse width
0.4
0.6
0.4
0.6
0.4
0.6
Address and Control input setup time
0.9
-
0.9
-
1.0
-
Address and Control input hold time
0.9
-
0.9
-
1.0
-
Write recovery time
3
-
3
-
2
-
Last data in to Read command
2
-
2
-
2
-
Col. Address to Col. Address delay
1
-
1
-
1
-
Mode register set cycle time
1
-
2
-
2
-
Auto precharge write recovery + Precharge
12
Rev 0.6
May. 2006
EtronTech
EM6A9320
4Mx32 DDR SDRAM
Timing Waveforms
Figure 1. AC Parameters for Read Timimg (Burst Length = 4)
0
tCH
tCK
CK#
1
tCL
tHP
2
tHP
3
4
5
6
7
8
tIS
CK
tIH
RD
CMD
tIS
tIH
A0-11,
BA0-1
Valid
“Preamble”
CAS Latency = 5
DQS
“Postmble”
tDQSCK
tRPRE
tAC
tRPST
tQHS
DQ
DQ0
DQ1
DQ2
tDQSQ
CAS Latency = 4
tQH
“Preamble”
DQS
“Postmble”
DQ
DQ0
CAS Latency = 3
“Preamble”
DQS
DQ
DQ3
DQ1
DQ2
DQ3
“Postmble”
DQ0
DQ1
DQ2
DQ3
Figure 2. AC Parameters for Write Timing (Burst Length=4)
0
CK#
1
2
3
4
5
6
7
8
CK
CMD
A0-11,
BA0-1
WR
WR
WR
Valid
Valid
Valid
“Preamble”
DQS
“Postmble”
tWPRES tWPREH
“Postmble”
“Preamble”
tWPST
tDQSS
tWPST
tDQSS
tDH
DM
tDH
tDS
tDS
Input Data Masked
tDS
DQ
tDH
DQ0
DQ1
DQ2
DQ0
DQ3
13
DQ1
DQ2
DQ3
DQ4 DQ5
Rev 0.6
DQ6
DQ7
May. 2006
EtronTech
EM6A9320
4Mx32 DDR SDRAM
Figure 3. Bank Activate Read or Write Command Timing
CK
tRCDRD
tRCDWR
tRAS
tRP
tRAS
tRC
CMD
ACT
RD
PRE
ROW ADR Active
A0-11
RA
ROW ADR
BA0-1
BA
tRRD
tRP
tRC
ACT
ACT
WR
RA
RA
CA
BA
BA
BA
PRE
ACT
Percharge
CA
RA
Column ADR
BA
BA
BA
BA
Bank ADR
Figure 4. Burst Stop for Read (CAS Letancy = 5, Burst Length = 4)
0
CK#
1
2
3
4
5
6
7
8
CK
CMD
RD
BST
CMD
Burst Stop for CAS Latency = 5
A0-11,
BA0-1
Valid
1x CK
After 1 x CK Command can be active
DQS
DQ
DQ0
DQ1
Figure 5. Read with Auto Precharge (CAS Letancy = 5, Burst Length = 4)
CK#
0
1
2
3
4
5
6
CK
Read with Auto Precharge
CMD
Bank can be Active after Auto Precharge
ACT
RDA
CAS Latency = 5
A0-11,
BA0-1
Valid
Valid
tRP
DQS
Begin of Auto Precharge
DQ
DQ0
14
DQ1
DQ2
DQ3
Rev 0.6
May. 2006
EtronTech
EM6A9320
4Mx32 DDR SDRAM
Figure 6. Write with Auto Precharge (Burst Length = 4)
CK#
0
1
2
3
4
5
6
CK
Write with Auto Precharge
Bank can be Active after Auto Precharge
CMD
WRA
ACT
A0-11,
BA0-1
Valid
Valid
tWR
DQS
tRP
Begin of Auto Precharge
DQ0
DQ
DQ1
DQ2
DQ3
Figure 7. Read Burst Interrupt by Read (CAS Letancy = 5, Burst Length = 4)
CK#
0
1
2
3
4
5
6
7
8
CK
tCCD
CMD
RDa
RDb
A0-11,
BA0-1
Valid
Valid
DQS
DQ
Da0
Da1
Db0
Db1
Db2
Db3
Figure 8. Write Interrupted by Write (Burst Length = 4)
CK#
0
1
2
3
4
CK
tCCD
CMD
WRa
WRb
A0-11,
BA0-1
Valid
Valid
DQS
DQ
Da0
Da1
Db0
Db1
Db2
Db3
Figure 9. Auto Refresh Timimg
CK
tRP
CMD
PRE
Precharge
tRFC
AFRF
CMD
Auto Refresh
E it
15
Rev 0.6
May. 2006
EtronTech
EM6A9320
4Mx32 DDR SDRAM
Figure 10. Self Refresh Timimg
CK
200xCK
tSREX
SREF
CMD
SREX
NOP
CMD
CKE
Self Refresh Entry
Self Refresh Exit
After 200 x CK, Command can be active
Figure 11. Precharge Command
CK
tRAS
tRP
tRC
CMD
ACT
A0-11
RA
BA0-1
BA
PRE
ACT
RA
BA
BA
Figure 12. Power Up Sequence
CK
200uS
CMD
NOP
tRP
NOP PREA
Power Up
wait 200uS
Precharge All
tMRD
200xCK
EMRS
MRS
EMRS set
MRS set
Reset DLL
with A8=H
tRP
PREA
Precharge All
tRFC
AREF AREF
2 or more
Auto Refresh
MRS
MRS set
with A8=L
Figure 13. Mode Register Set Timing
CK
tRP
CMD
PREA
1xCK
MRS
Precharge All
MRS set
tMRD
CMD
After 1 x CK, Command can be active
Figure 14. Power Down Mode
CK
CMD
PRE
NOP
NOP
NOP
CMD
tPDEX
CKE
Power Down Mode Entry
Power Down Mode Exit
16
Rev 0.6
May. 2006
EtronTech
EM6A9320
4Mx32 DDR SDRAM
BOTTOM VIEW
TOP VIEW
C
0.15 S
C
PIN A1 CORNER
A
B
0.40~0.50 (144X)
PIN A1 CORNER
1 2 3 4 5 6
0.08 S
12 11 10 9 8 7 6 5 4 3 2 1
7 8 9 10 11 12
L
L
0.80
-A-
8.80
1.60
0.20 C
-B0.15 (4x)
C
\\
Ball pitch : 0.80
0.15 C
-C-
Ball Diam eter : 0.45
SEATING PLANE
17
Rev 0.6
May. 2006