EM742SP16 256Kx16 Multiplexed STRAM Document Title 256K x 16Bit Multiplexed Single Transistor RAM Revision History Revision No. History Draft Date Remark December 21 , 2006 Preliminary 0.0 Initial Draft 0.1 1’st Revision Add to pad coordinate March 07, 2007 Preliminary 0.2 2’nd Revision Product code chang from EM742SP16AW to EM742SP16 March 20, 2007 Preliminary 0.3 3’rd Revision Valid address change from A18 to A17 March 28, 2007 Priliminary 0.4 4’ th Revision Remove configure register sets at functional descripition table May 9, 2007 Priliminary Emerging Memory & Logic Solutions Inc. 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Zip Code: 690-717 The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 EM742SP16 256Kx16 Multiplexed STRAM 256K x16 Bit Multiplexed Single Transistor RAM FEATURES - Process Technology : 0.13µm CMOS process - Organization :256K x16 - Power Supply Voltage : 1.7~1.9V - Multiplexed address and data bus - Three state outputs - Auto TCSR for power saving GENERAL WAFER SPECIFICATIONS - Deep trench process - 3 Metal layers including local inter-connection - Wafer diameter : 8-inch PAD DESCRIPTION Name Function Name Function /CS Chip select inputs /LB Lower byte (ADQ0~7) /OE Output enable input /UB Upper byte (ADQ8~15) /WE Write enable input VCC Power supply /AVD Address valid input VCCQ ADQi Address/Data In-out VSS(Q) Ground Ai Address inputs NC I/O Power supply No connection FUNCTION BLOCK DIAGRAM /AVD /CS /UB /LB /WE /OE CONTROL LOGIC A16~A17 ADDRESS DECODER ADQ0~ ADQ15 Self-Refresh CONTROL ROW SELECT COLUMN SELECT ADDRESS/DATA Multiplexer Din/Dout BUFFER Memory Array 256K X 16 I/O CIRCUIT 2 EM742SP16 256Kx16 Multiplexed STRAM ABSOLUTE MAXIMUM RATINGS 1) Parameter Symbol Minimum Unit Voltage on Any Pin Relative to Vss VIN, VOUT -0.2 to VCCQ+0.3V V Voltage on Vcc supply relative to Vss VCC, VCCQ -0.22) to 2.5V V Power Dissipation Storage Temperature Operating Temperature PD 1.0 W TSTG -65 to 150 oC TA -25 to 85 oC 1. Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Undershoot at power-off : -1.0V in case of pulse width < 20ns FUNCTIONAL DESCRIPTION CS OE WE LB UB AVD ADQ0~15 A16~A17 Mode Power H X X X X X High-Z X Deselected Stand by L H H X X H High-Z X Output Disabled Active L X X H H X High-Z X Output Disabled Active L H H H H L Add. Input Add. Input Address Input Active L L H L H H Data Out X Lower Byte Read Active L L H H L H Data Out X Upper Byte Read Active L L H L L H Data Out X Word Read Active L H L L H H Data In X Lower Byte Write Active L H L H L H Data In X Upper Byte Write Active L H L L L H Data In X Word Write Active Note: X means don’t care. (Must be low or high state) 3 EM742SP16 256Kx16 Multiplexed STRAM RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Symbol Min Typ Max Unit VCC 1.7 1.8 1.9 V VCCQ 1.7 1.8 1.9 V VSS, VSSQ 0 0 0 V Input high voltage VIH VCCQ - 0.4 - VCCQ + 0.22) V Input low voltage VIL - 0.4 V Supply voltage Ground 1. 2. 3. 4. -0.23) TA= -25 to 85oC, otherwise specified Overshoot: VCC +1.0 V in case of pulse width < 20ns Undershoot: -1.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f =1MHz, TA=25oC) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Parameter Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIN=VSS to VCCQ , VCC=VCCmax -1 - 1 uA Output leakage current ILO CS=VIH or OE=VIH or WE=VIL , VIO=VSS to VCCQ , VCC=VCCmax -1 - 1 uA ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS<0.2V, VIN<0.2V or VIN>VCCQ-0.2V - - 3 mA ICC2 Cycle time = Min, IIO=0mA, 100% duty, CS=VIL, VIN=VIL or VIH - - 25 mA Output low voltage VOL IOL = 0.1mA, VCC=VCCmin - - 0.1 V Output high voltage VOH IOH = -0.1mA, VCC=VCCmin VCCQ-0.1 - - V Standby Current (CMOS) ISB1 - - 60 uA Average operating current CS>VCCQ-0.2V, Other inputs = 0 ~ VCCQ (Typ. condition : VCC=1.8V @ 25oC) (Max. condition : VCC=1.9V @ 85oC) 1. Maximum Icc specifications are tested with VCC = VCCmax. 4 LL EM742SP16 256Kx16 Multiplexed STRAM AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) Dout Input Pulse Level : 0.2V to VCCQ-0.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : VCCQ/2 CL1) 1) Output Load (See right) : CL = 30pF 1. Including scope and Jig capacitance AC CHARACTERISTICS (Vcc = 1.7 to 1.9V, Gnd = 0V, TA = -25C to +85oC) Symbol Parameter List Common Read Write Speed Min Max Unit AVD Low pulse tAVD 15 1000 ns Address setup to AVD rising edge tAVDS 15 - ns Address hold from AVD rising edge tAVDH 5 - ns Chip enable setup to AVD rising edge tCSS 7 - ns AVD low to data valid time tACC1 - 70 ns Address access time tACC2 - 70 ns Chip enable to data output tACC3 - 70 ns Address disable to output enable tADOE 0 - ns Output enable to valid output tOE - 25 ns UB, LB enable to data output tUBLBA - 25 ns UB, LB enable to low-Z output tBLZ 5 - ns Output enable to low-Z output tOLZ 5 - ns Chip disable to high-Z output tHZ - 15 ns UB, LB disable to high-Z output tBHZ - 15 ns Output disable to high-Z output tOHZ - 15 ns AVD low to end of write tACW1 70 - ns Address valid to end of write tACW2 70 - ns Chip enable to end of write tACW3 70 - ns Write pulse low tWRL 45 - ns UB, LB valid to end of write tBW 50 - ns Data to write time overlap tDW 25 - ns Data hold from write time tDH 0 - ns 5 EM742SP16 256Kx16 Multiplexed STRAM Device Operaton The access is performed in two stages. The first stage is address latching. The first stage take place between point A and B in timing diagram. At this stage, the Chip Select(CS) to the device is asserted. The random access is enabled either from the point the address becomes stable, the falling edge of the AVD signal or from the falling edge of the last chip select signal. The second stage is the read or write access. This takes place between points B and C in timing diagram. In case of a read access, the multiplexed address/data bus (ADQ0 ~ ADQ15) changes its direction. It is important to notice tOE when it is dominant that the device gets into the read cycle since the address is available long before the device output is enabled. Read Access The read access is initiated by applying the address to the multiplexed address/data bus or to the address bus over A15 (A16 -> Axx). When the address is stable, the device chip select(CS) is set active low. At point A, the AVD signal is taken low and the latch becomes transparent. This allows the address to be propagated to the memory array. The address is stable at the rising edge of the AVD signal. The AVD signal goes high at point B in which the address latch is completed. At this point the read cycle is entered. The OE signal is set active low. This changes the direction of the bus. The status of control signals UB and LB are set according to the access. Data is read at point C. TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE (1) ( WE = VIH ) A C B tAVD AVD tAVDS Address/Data tACC1 tAVDH Address Valid Data Valid tACC2 tADOE tOLZ OE tOHZ tOE tCSS CS tHZ tACC3 tBLZ UB, LB tBHZ tUBLBA 6 EM742SP16 256Kx16 Multiplexed STRAM TIMING WAVEFORM OF READ CYCLE (2) ( WE = VIH ) A C B tAVD AVD tAVDS Address/Data tAVDH Address Valid tACC2 OE Data Valid tOLZ tOHZ tOE tCSS tHZ CS tBLZ tUBLBA tBHZ UB, LB NOTES (READ CYCLE) 1. tHZ and tBHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 7 EM742SP16 256Kx16 Multiplexed STRAM Write Access The write access is initiated by applying the address to the multiplexed address/data bus or to the address bus over A15 (A16 -> Axx). When the address is stable, the device chip select(CS) is set active low. At point A, the AVD signal is taken low and the latch becomes transparent. This allows the address to be propagated to the memory array. The address is stable at the rising edge of the AVD signal. The AVD signal goes high at point B in which the address latch is completed. At this point, the second stage of the write process is entered. Data is input to the multiplexed address/data bus. The WE signal is set low and control signal UB and LB are set according to the access. TIMING WAVEFORM OF WRITE CYCLE (1) (OE = VIH) A C B tAVD AVD tACW1 tAVDS Address/Data tAVDH Data Valid Address Valid tACW2 tDW tWRL tDH WE tCSS tACW3 CS tBW UB, LB TIMING WAVEFORM OF WRITE CYCLE (2) (OE = VIH) A C B tAVD AVD tAVDS Address/Data tAVDH Data Valid Address Valid tACW2 tWRL tDW tDH WE tCSS CS tBW UB, LB NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWRL) of low CS, low WE and low UB or LB. A write begins at the last transition among low CS and low WE with asserting UB or LB low for single byte operation or simultaneously asserting UB and LB low for word operation. A write ends at the earliest transition among high CS and high WE. The tWRL is measured from the beginning of write to the end of write. 8 EM742SP16 256Kx16 Multiplexed STRAM TIMING WAVEFORM OF POWER UP 200us VCC(Min.) VCC CS Power Up Mode Normal Operation NOTE . ( POWER UP ) 1. After Vcc reaches Vcc(Min.) , wait 200us with CS high. Then you get into the normal operation. TCSR (Temperature Cotrolled Self Refresh) The 4M STRAM can be operated with temperature controlled self-refresh. The device internal self-refresh period is controlled according as temperature change automatically. 9 EM742SP16 256Kx16 Multiplexed STRAM MEMORY FUNCTION GUIDE EM X XX X X X XX X X - XX XX 1. EMLSI Memory 11. Power 2. Device Type 10. Speed 3. Density 4. Option 9. Packages 5. Technology 8. Version 6. Operating Voltage 7. Organization 1. Memory Component 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 2. Device Type 6 ------------------------ Low Power SRAM 7 ------------------------ STRAM 8. Version Blank ----------------A ----------------------B ----------------------C ----------------------D ----------------------E ----------------------- 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 16 ----------------------- 16M 32 ----------------------- 32M 64 ----------------------- 64M Mother die First version Second version Third version Fourth version Fifth version 9. Package Blank ----------------- Package W ----------------------- Wafer 4. Function 0 ----------------------- Dual CS 1 ----------------------- Single CS 2 ----------------------- Multiplexed 10. Speed 45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 90 ---------------------- 90ns 10 --------------------- 100ns 12 --------------------- 120ns 5. Technology Blank ----------------- CMOS F ------------------------ Full CMOS S ------------------------ Single Transistor 6. Operating Voltage Blank ------------------ 5V V ------------------------- 3.3V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V O ------------------------- 1.5V 11. Power LL --------------------- Low Low Power L ---------------------- Low Power S ---------------------- Standard Power 10