EMLSI EM7645FV16BS-85LL 256k x16 bit low power and low voltage full cmos static ram Datasheet

EM640FV16FW Series
Low Power, 256Kx16 SRAM
Document Title
256K x16 bit Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
History
Draft Date
0.0
Initial Draft
August 13 , 2003
Remark
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Zip Code : 690-719
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM640FV16FW Series
Low Power, 256Kx16 SRAM
256K x16 Bit Low Power and Low Voltage CMOS Static RAM
FEATURES
- Process Technology : 0.18µm Full CMOS
- Organization :256K x16
- Power Supply Voltage
=> EM640FV16FW : 2.7~3.6V
- Three state output and TTL Compatible
- Packaged product designed for 55/70ns
GENERAL PHYSICAL SPECIFICATIONS
- Backside die surface of polished bare silicon
- Typical Die Thickness = 725um
- Typical top-level metalization :
=> Metal ( Ti/TiN/Al-Cu 0.5% ) : 5.7K Angstroms thickness
- Topside Passivation :
=> 7K Angstroms PE-SiN
- Typical Pad Size : 90.0um x 80.0um
- Wafer diameter : 8 inch
OPTIONS
- C1/W1 : DC Probed Die/Wafer @ Hot Temp
- C2/W2 : DC/AC Probed Die/Wafer @ Hot Temp
PAD DESCRIPTIONS
Name
Function
Name
Function
CS1, CS2
Chip select inputs
Vcc
Power Supply
OE
Output Enable input
Vss
Ground
WE
Write Enable input
UB
Upper Byte (I/O9~16)
A0~A17
Address Inputs
LB
Lower Byte (I/O1~8)
I/O1~I/O16
Data Inputs/Outpus
*NC
No Connection
2
EM640FV16FW Series
Low Power, 256Kx16 SRAM
FUNCTIONAL SPECIFICATIONS
There are 3 classifications for EMLSI die and wafers products, which are C1 and C2 for die and W1 and W2 for wafer, respectively.
Each die and wafer support dedicated charateristics and probe the eletrical parameters within their specifications. Followings are
brief information for die and wafer classifications. Please refer to packaged specifications for more information but these parameters
are not guaranteed at bare die and wafer.
− C1 LEVEL DIE OR W1 LEVEL WAFER
The DC parameters are measured by specification for C1 level die or W1 level wafer. The DC parameters measured at 70°C temperature, which called ‘Hot DC Sorting’ Other parameters are not guaranteed and warranted including device reliability. Please refer
to qualification report for device reliability and package level datasheets for electrical parameters.
− C2 LEVEL DIE OR W2 LEVEL WAFER
The DC parameters and selected AC parameters are measured with for C2 level die or W2 level wafer. The DC characteristics of C2
die and W2 wafer is tested based on DC specifications of C1 level die and W1 level wafer. The DC and specified AC parameters are
tested at 70°C temperature, which called ‘Hot DC & Selective AC Sorting’. Other parameters are not guaranteed and warranted
including device reliability. Please refer to qualification report for device reliability and package level datasheets for electrical parameters.
C2 level die and W2 level wafer probe following AC parameter.
− tRC, tAA, tCO
− tWC, tCW
PACKAGING
Individual device will be packed in anti-static trays.
− Chip Trays : A 2-inch square waffle style carrier for die with separate compartments for each die. Commonly referred to as a waffle
pack, each tray has a cavity size selected for the device that allows for easy loading and unloading and prevents
rotation. The tray itself is made of conductive material to reduce the danger of damage to the die from electrostatic
discharge. The chip carriers will be labeled with the following information :
− EMLSI wafer lot number
− EMLSI part number
− Quantity
− Jar Packing : Jar packing is made by EMLSI and used by many customers that we deliver the requested die as wafer. The pack is
consisted of clean paper to wrap the wafer, high cushioned sponge between wafers and hardly fragile plastic box with sponge. Each
pack has typically 25 wafers and then several packs are put into larger box depending on amounts of wafers.
Bond Pad #1 at Top
Die orientation in chip carriers
STORAGE AND HANDLING
EMLSI recommends the die stored in a controlled environment with filtered nitrogen. The carrier must be opened at ESD safe
environment when inspection and assembly.
3
EM640FV16FW Series
Low Power, 256Kx16 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Symbol
Ratings
Unit
VIN, VOUT
-0.2 to Vcc+0.3(Max.4.0V)
V
Voltage on Vcc supply relative to Vss
VCC
-0.2 to 4.0V
V
Power Dissipation
PD
1.0
W
Operating Temperature
TA
-40 to 85
Voltage on Any Pin Relative to Vss
o
C
* Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
LB
UB
I/O1-8
I/O9-16
Mode
Power
H
X
X
X
X
X
High-Z
High-Z
Deselected
Stand by
X
L
X
X
X
X
High-Z
High-Z
Deselected
Stand by
X
X
X
X
H
H
High-Z
High-Z
Deselected
Stand by
L
H
H
H
L
X
High-Z
High-Z
Output Disabled
Active
L
H
H
H
X
L
High-Z
High-Z
Output Disabled
Active
L
H
L
H
L
H
Data Out
High-Z
Lower Byte Read
Active
L
H
L
H
H
L
High-Z
Data Out
Upper Byte Read
Active
L
H
L
H
L
L
Data Out
Data Out
Word Read
Active
L
H
X
L
L
H
Data In
High-Z
Lower Byte Write
Active
L
H
X
L
H
L
High-Z
Data In
Upper Byte Write
Active
L
H
X
L
L
L
Data In
Data In
Word Write
Active
Note: X means don’t care. (Must be low or high state)
4
EM640FV16FW Series
Low Power, 256Kx16 SRAM
RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter
1.
2.
3.
4.
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
2.7
3.3
3.6
V
Ground
VSS
0
0
0
V
Input high voltage
VIH
2.2
-
VCC + 0.22)
V
Input low voltage
VIL
-0.23)
-
0.6
V
TA= -40 to 85oC, otherwise specified
Overshoot: VCC +2.0 V in case of pulse width < 20ns
Undershoot: -2.0 V in case of pulse width < 20ns
Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f =1MHz, TA=25oC)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Ouput capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
ILI
VIN=VSS to VCC
-1
-
1
uA
Output leakage current
ILO
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH
VIO=VSS to VCC
-1
-
1
uA
Operating power supply
ICC
IIO=0mA, CS1=VIL, CS2=WE=VIH, VIN=VIH or VIL
-
-
3
mA
ICC1
Cycle time=1µs, 100% duty, IIO=0mA,
CS1<0.2V, LB<0.2V or/and UB<0.2V, CS2>VCC-0.2V,
VIN<0.2V or VIN>VCC-0.2V
-
-
3
mA
Cycle time = Min, IIO=0mA, 100% duty,
CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL ,
VIN=VIL or VIH
55ns
-
-
30
mA
ICC2
70ns
-
-
25
mA
Output low voltage
VOL
IOL = 2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH = -1.0mA
2.4
-
-
V
Standby Current (TTL)
ISB
CS1=VIH, CS2=VIL, Other inputs=VIH or VIL
-
-
0.3
mA
ISB1
CS1>VCC-0.2V, CS2>VCC-0.2V (CS1 controlled)
or 0V<CS2<0.2V (CS2 controlled),
Other inputs = 0~VCC
-
11)
12
uA
Average operating current
Standby Current (CMOS)
(Typ. condition : VCC=3.3V @ 25oC)
(Max. condition : VCC=3.6V @ 85oC)
NOTES
1. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested.
5
LL
EM640FV16FW Series
Low Power, 256Kx16 SRAM
VTM3)
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
R12)
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL = 100pF+ 1 TTL
CL1) = 30pF + 1 TTL
1. Including scope and Jig capacitance
2. R1=3070 ohm,
R2=3150 ohm
3. VTM=2.8V
R22)
CL1)
READ CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
55ns
Symbol
70ns
Min
Max
Min
Max
Unit
Read cycle time
tRC
55
-
70
-
ns
Address access time
tAA
-
55
-
70
ns
Chip select to output
tco1, tco2
-
55
-
70
ns
Output enable to valid output
tOE
-
30
-
35
ns
UB, LB acess time
tBA
70
ns
Chip select to low-Z output
55
tLZ1, tLZ2
10
-
10
-
ns
UB, LB enable to low-Z output
tBLZ
10
-
10
-
ns
Output enable to low-Z output
tOLZ
5
-
5
-
ns
tHZ1, tHZ2
0
20
0
25
ns
UB, LB disable to high-Z output
tBHZ
0
20
0
25
ns
Output disable to high-Z output
tOHZ
0
20
0
25
ns
Output hold from address change
tOH
10
-
10
-
ns
Chip disable to high-Z output
WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
55ns
Symbol
70ns
Unit
Min
Max
Min
Max
tWC
55
-
70
-
ns
tCW1, tCW2
45
-
60
-
ns
Address setup time
tAs
0
-
0
-
ns
Address valid to end of write
tAW
45
-
60
-
ns
UB, LB valid to end of write
tBW
45
-
55
-
ns
Write pulse width
tWP
40
-
50
-
ns
Write recovery time
tWR
0
-
0
-
ns
Write to ouput high-Z
tWHZ
0
20
0
25
ns
Data to write time overlap
tDW
30
Data hold from write time
tDH
0
-
0
-
ns
End write to output low-Z
tOW
5
-
5
-
ns
Write cycle time
Chip select to end of write
6
30
ns
EM640FV16FW Series
Low Power, 256Kx16 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
tRC
Address
tAA
tOH
tCO
CS1
CS2
tHZ
tBA
UB,LB
tBHZ
tOE
OE
tOHZ
tOLZ
Data Out
High-Z
Data Valid
tBLZ
tWHZ
tLZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
7
EM640FV16FW Series
Low Power, 256Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
tWC
Address
tCW(2)
tWR(4)
CS1
CS2
tAW
tBW
UB,LB
tWP(1)
WE
tAS(3)
Data in
tDH
tDW
High-Z
High-Z
Data Valid
tWHZ
Data out
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
CS2
tAW
tBW
UB,LB
tWP(1)
WE
tDW
Data in
Data out
Data Valid
High-Z
High-Z
8
tDH
EM640FV16FW Series
Low Power, 256Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
tWC
Address
tCW(2)
tWR(4)
CS1
CS2
tAW
tBW
UB,LB
tWP(1)
tAS(3)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE
goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double
byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is
measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1
or WE going high.
9
EM640FV16FW Series
Low Power, 256Kx16 SRAM
DATA RETENTION CHARACTERISTICS
Parameter
Symbol
VCC for Data Retention
VDR
Data Retention Current
IDR
Chip Deselect to Data Retention Time
tSDR
Operation Recovery Time
Test Condition
ISB1 Test Condition
(Chip Disabled) 1)
VCC=1.5V, ISB1 Test Condition
(Chip Disabled) 1)
Min
Typ
Max
Unit
1.5
-
3.6
V
-
0.5
-
uA
0
-
-
tRC
-
-
See data retention wave form
tRDR
ns
NOTES
1. See the ISB1 measurement condition of datasheet page 5.
DATA RETENTION WAVE FORM
tSDR
Data Retention Mode
tRDR
Vcc
2.7V
2.2V
VDR
CS1 > Vcc-0.2V
CS1
GND
Data Retention Mode
Vcc
2.7V
CS2
tRDR
tSDR
VDR
0.4V
CS2 < 0.2V
GND
10
EM640FV16FW Series
Low Power, 256Kx16 SRAM
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
11. Power
2. Device Type
10. Speed
3. Density
9. Packages
4. Option
8. Version
5. Technology
7. Orgainzation
6. Operating Voltage
1. Memory Component
7. Orginzation
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
2. Device Type
6 ------------------------ Low Power SRAM
7 ------------------------ STRAM
8. Version
Blank ----------------- Mother Die
A ----------------------- First revision
B ----------------------- Second revision
C ----------------------- Third revision
D ----------------------- Fourth revision
E ----------------------- Fifth revision
F ----------------------- Sixth revision
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
16 ----------------------- 16M
32 ----------------------- 32M
64 ----------------------- 64M
9. Package
Blank ---------------------- FPBGA
S ---------------------------- 32 sTSOP1
T ---------------------------- 32 TSOP1
U ---------------------------- 44 TSOP2
W ---------------------------- Wafer
4. Mode Option
0 -------- Dual CS
1 -------- Single CS
2 -------- Multiplexed Address
3 -------- Single CS with LB,UB (tBA=tOE)
4 -------- Single CS with LB,UB (tBA=tCO)
5 -------- Dual CS with LB,UB (tBA=tOE)
6 -------- Dual CS with LB,UB (tBA=tCO)
10. Speed
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
10 --------------------- 100ns
12 --------------------- 120ns
5. Technology
Blank ------------------ CMOS
F ------------------------ Full CMOS
6. Operating Voltage
Blank ------------------- 5V
V ------------------------- 2.7V~3.6V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
11. Power
LL ---------------------- Low Low Power
L ---------------------- Low Power
S ---------------------- Standard Power
11
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