Actel EX128-CSG100I Ex family fpgas Datasheet

v4.3
eX Family FPGAs
FuseLock
Leading Edge Performance
•
•
•
•
•
240 MHz System Performance
350 MHz Internal Performance
3.9 ns Clock-to-Out (Pad-to-Pad)
•
•
•
Specifications
•
•
•
•
•
3,000 to 12,000 Available System Gates
Maximum 512 Flip-Flops (Using CC Macros)
0.22µm CMOS Process Technology
Up to 132 User-Programmable I/O Pins
•
•
•
Features
•
•
•
•
•
•
High-Performance, Low-Power Antifuse FPGA
LP/Sleep Mode for Additional Power Savings
Advanced Small-Footprint Packages
Hot-Swap Compliant I/Os
Single-Chip Solution
Nonvolatile
•
•
Live on Power-Up
No Power-Up/Down Sequence Required for Supply
Voltages
Configurable Weak-Resistor Pull-Up or Pull-Down
for Tristated Outputs during Power-Up
Individual Output Slew Rate Control
2.5 V, 3.3 V, and 5.0 V Mixed-Voltage Operation
with 5.0V Input Tolerance and 5.0V Drive Strength
Software Design Support with Actel Designer and
Libero™ Integrated Design Environment (IDE)
Tools
Up to 100% Resource Utilization with 100% Pin
Locking
Deterministic Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
Fuselock™ Secure Programming Technology
Prevents Reverse Engineering and Design Theft
Product Profile
Device
eX64
eX128
eX256
Capacity
System Gates
Typical Gates
3,000
2,000
6,000
4,000
12,000
8,000
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
64
128
128
256
256
512
Combinatorial Cells
128
256
512
Maximum User I/Os
84
100
132
Global Clocks
Hardwired
Routed
1
2
1
2
1
2
Speed Grades
–F, Std, –P
–F, Std, –P
–F, Std, –P
C, I, A
C, I, A
C, I, A
64, 100
49, 128
64, 100
49, 128
100
128, 180
Temperature Grades*
Package (by pin count)
TQFP
CSP
Note: *Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings.
June 2006
© 2006 Actel Corporation
i
eX Family FPGAs
Ordering Information
eX128
TQ
P
G
100
Application (Ambient Temperature Range)
Blank =
I=
A=
PP =
Commercial (0˚C to 70˚C)
Industrial (-40˚C to 85˚C)
Automotive (-40˚C to 125˚C)
Pre-production
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
TQ = Thin Quad Flat Pack (0.5 mm pitch)
CS = Chip-Scale Package (0.8 mm pitch)
Speed Grade
Blank= Standard Speed
P = Approximately 30% Faster than Standard
F = Approximately 40% Slower than Standard
Part Number
eX64 = 64 Dedicated Flip-Flops (3,000 System Gates)
eX128 = 128 Dedicated Flip-Flops (6,000 System Gates)
eX256 = 256 Dedicated Flip-Flops (12,000 System Gates)
Plastic Device Resources
Device
eX64
eX128
eX256
TQFP 64-Pin
41
46
—
User I/Os (Including Clock Buffers)
TQFP 100-Pin
CSP 49-Pin
CSP 128-Pin
56
36
84
70
36
100
81
—
100
CSP 180-Pin
—
—
132
Note: Package Definitions:TQFP = Thin Quad Flat Pack, CSP = Chip Scale Package
Temperature Grade Offerings
Device\Package
eX64
eX128
eX256
TQFP 64-Pin
C, I, A
C, I, A
C, I, A
TQFP 100-Pin
C, I, A
C, I, A
C, I, A
CSP 49-Pin
C, I, A
C, I, A
C, I, A
CSP 128-Pin
C, I, A
C, I, A
C, I, A
CSP 180-Pin
C, I, A
C, I, A
C, I, A
Notes:
C = Commercial
I = Industrial
A = Automotive
Speed Grade and Temperature Grade Matrix
C
I
A
–F
✓
Std
✓
✓
✓
Notes:
P = Approximately 30% faster than Standard
–F = Approximately 40% slower than Standard
Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings.
Contact your local Actel representative for device availability.
ii
v4.3
–P
✓
✓
eX Family FPGAs
Table of Contents
eX Family FPGAs
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
eX Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
2.5V/3.3V/5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
2.5V LVCMOS2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
5.0V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
eX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
C-Cell Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
eX Family Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
Package Pin Assignments
64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
49-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
128-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
180-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
v4.3
iii
eX Family FPGAs
eX Family FPGAs
General Description
impedance connection. Actel’s eX family provides two
types of logic modules, the register cell (R-cell) and the
combinatorial cell (C-cell).
The eX family of FPGAs is a low-cost solution for lowpower, high-performance designs. The inherent low
power attributes of the antifuse technology, coupled
with an additional low static power mode, make these
devices ideal for power-sensitive applications. Fabricated
with an advanced 0.22µm CMOS antifuse technology,
these devices achieve high performance with no power
penalty.
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and clock enable (using the
S0 and S1 lines) control signals (Figure 1-1). The R-cell
registers feature programmable clock polarity selectable
on a register-by-register basis. This provides additional
flexibility while allowing mapping of synthesized
functions into the eX FPGA. The clock source for the Rcell can be chosen from either the hard-wired clock or
the routed clock.
eX Family Architecture
The C-cell implements a range of combinatorial functions
up to five inputs (Figure 1-2 on page 1-2). Inclusion of
the DB input and its associated inverter function enables
the implementation of more than 4,000 combinatorial
functions in the eX architecture in a single module.
Actel's eX family is implemented on a high-voltage twinwell CMOS process using 0.22µm design rules. The eX
family architecture uses a “sea-of-modules” structure
where the entire floor of the device is covered with a
grid of logic modules with virtually no chip area lost to
interconnect elements or routing. Interconnection
among these logic modules is achieved using Actel’s
patented
metal-to-metal
programmable
antifuse
interconnect elements. The antifuse interconnect is
made up of a combination of amorphous silicon and
dielectric material with barrier metals and has an "on"
state resistance of 25Ω with a capacitance of 1.0fF for
low-signal impedance. The antifuses are normally open
circuit and, when programmed, form a permanent low-
S0
Two C-cells can be combined together to create a flipflop to imitate an R-cell via the use of the CC macro. This
is particularly useful when implementing non-timingcritical paths and when the design engineer is running
out of R-cells. More information about the CC macro can
be found in Actel’s Maximizing Logic Utilization in eX, SX
and SX-A FPGA Devices Using CC Macros application
note.
Routed
Data Input S1
PSET
DirectConnect
Input
D
Q
Y
HCLK
CLKA,
CLKB,
Internal Logic
CLR
CKS
CKP
Figure 1-1 • R-Cell
v4.3
1-1
eX Family FPGAs
Module Organization
C-cell and R-cell logic modules are arranged into horizontal banks called Clusters, each of which contains two C-cells
and one R-cell in a C-R-C configuration.
Clusters are further organized into modules called SuperClusters for improved design efficiency and device
performance, as shown in Figure 1-3. Each SuperCluster is a two-wide grouping of Clusters.
D0
D1
Y
D2
D3
Sa
Sb
DB
A1 B1
A0 B0
Figure 1-2 • C-Cell
R-Cell
S0
C-Cell
Routed
Data Input S1
D0
D1
PSET
Y
D2
DirectConnect
Input
Q
D
D3
Y
Sb
Sa
HCLK
CLKA,
CLKB,
Internal Logic
CLR
DB
CKS
CKP
A0
Cluster
Cluster
SuperCluster
Figure 1-3 • Cluster Organization
1 -2
v4.3
B0
A1
B1
eX Family FPGAs
Routing Resources
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters (Figure 1-4). This routing
architecture also dramatically reduces the number of
antifuses required to complete a circuit, ensuring the
highest possible performance.
FastConnect enables horizontal routing between any
two logic modules within a given SuperCluster and
vertical routing with the SuperCluster immediately
below it. Only one programmable connection is used in a
FastConnect path, delivering maximum pin-to-pin
propagation of 0.3 ns (–P speed grade).
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing
between SuperClusters. The exact combination of track
lengths and antifuses within each path is chosen by the
fully automatic place-and-route software to minimize
signal propagation delays.
DirectConnect is a horizontal routing resource that
provides connections from a C-cell to its neighboring Rcell in a given SuperCluster. DirectConnect uses a hardwired signal path requiring no programmable
interconnection to achieve its fast signal propagation
time of less than 0.1 ns (–P speed grade).
DirectConnect
• No antifuses
• 0.1 ns routing delay
SuperClusters
FastConnect
• One antifuse
• 0.5 ns routing delay
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Figure 1-4 • DirectConnect and FastConnect for SuperClusters
v4.3
1-3
eX Family FPGAs
Clock Resources
eX’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hardwired from
the HCLK buffer to the clock select MUX in each R-Cell.
HCLK cannot be connected to combinational logic. This
provides a fast propagation path for the clock signal,
enabling the 3.9 ns clock-to-out (pad-to-pad)
performance of the eX devices. The hard-wired clock is
tuned to provide a clock skew of less than 0.1 ns worst
case. If not used, the HCLK pin must be tied LOW or HIGH
and must not be left floating. Figure 1-5 describes the
clock circuit used for the constant load HCLK.
HCLK does not function until the fourth clock cycle each
time the device is powered up to prevent false output
levels due to any possible slow power-on-reset signal and
fast start-up clock circuit. To activate HCLK from the first
cycle, the TRST pin must be reserved in the Design
software and the pin must be tied to GND on the board.
(See the "TRST, I/O Boundary Scan Reset Pin" on page 126).
The remaining two clocks (CLKA, CLKB) are global routed
clock networks that can be sourced from external pins or
from internal logic signals (via the CLKINT routed clock
buffer) within the eX device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB is sourced from internal logic signals, the
external clock pin cannot be used for any other input
and must be tied LOW or HIGH and must not float.
Figure 1-6 describes the CLKA and CLKB circuit used in eX
devices.
Table 1-1 describes the possible connections of the
routed clock networks, CLKA and CLKB.
Unused clock pins must not be left floating and must be
tied to HIGH or LOW.
Constant Load
Clock Network
HCLKBUF
Figure 1-5 • eX HCLK Clock Pad
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
Figure 1-6 • eX Routed Clock Buffer
Table 1-1 • Connections of Routed Clock Networks, CLKA
and CLKB
Module
Pins
C-Cell
A0, A1, B0 and B1
R-Cell
CLKA, CLKB, S0, S1, PSET, and CLR
I/O-Cell
1 -4
EN
v4.3
eX Family FPGAs
Other Architectural Features
Performance
All unused I/Os are configured as tristate outputs by
Actel's Designer software, for maximum flexibility when
designing new boards or migrating existing designs. Each
I/O module has an available pull-up or pull-down resistor
of approximately 50 kΩ that can configure the I/O in a
known state during power-up. Just shortly before VCCA
reaches 2.5 V, the resistors are disabled and the I/Os will be
controlled by user logic.
The combination of architectural features described
above enables eX devices to operate with internal clock
frequencies exceeding 350 MHz for very fast execution
of complex logic functions. The eX family is an optimal
platform upon which the functionality previously
contained in CPLDs can be integrated. eX devices meet
the performance goals of gate arrays, and at the same
time, present significant improvements in cost and time
to market. Using timing-driven place-and-route tools,
designers can achieve highly deterministic device
performance.
Table 1-2 describes the I/O features of eX devices. For
more information on I/Os, refer to Actel eX, SX-A, and
RT54SX-S I/Os application note.
Table 1-2 • I/O Features
Function
User Security
The Actel FuseLock advantage ensures that unauthorized
users will not be able to read back the contents of an
Actel antifuse FPGA. In addition to the inherent
strengths of the architecture, special security fuses that
prevent internal probing and overwriting are hidden
throughout the fabric of the device. They are located
such that they cannot be accessed or bypassed without
destroying the rest of the device, making both invasive
and more-subtle noninvasive attacks ineffective against
Actel antifuse FPGAs.
Description
Input Buffer •
Threshold
•
Selection
•
5.0V TTL
Nominal
Output Drive
•
5.0V TTL/CMOS
•
3.3V LVTTL
•
2.5V LVCMOS 2
3.3V LVTTL
2.5V LVCMOS2
Output Buffer “Hot-Swap” Capability
Look for this symbol to ensure your valuable IP is secure.
•
I/O on an unpowered device does not sink
current
•
Can be used for “cold sparing”
Selectable on an individual I/O basis
Individually selectable low-slew option
Power-Up
Individually selectable pull ups and pull downs
during power-up (default is to power up in
tristate)
Enables deterministic power-up of device
FuseLock
VCCA and VCCI can be powered in any order
Figure 1-7 • Fuselock
For more information, refer to Actel's Implementation of
Security in Actel Antifuse FPGAs application note.
The eX family supports mixed-voltage operation and is
designed to tolerate 5.0 V inputs in each case.
I/O Modules
A detailed description of the I/O pins in eX devices can be
found in "Pin Description" on page 1-26.
Each I/O on an eX device can be configured as an input,
an output, a tristate output, or a bidirectional pin. Even
without the inclusion of dedicated I/O registers, these I/
Os, in combination with array registers, can achieve
clock-to-out (pad-to-pad) timing as fast as 3.9 ns. I/O cells
in eX devices do not contain embedded latches or flipflops and can be inferred directly from HDL code. The
device can easily interface with any other device in the
system, which in turn enables parallel design of system
components and reduces overall design time.
v4.3
1-5
eX Family FPGAs
Hot Swapping
Low Power Mode
eX I/Os are configured to be hot-swappable. During
power-up/down (or partial up/down), all I/Os are
tristated, provided VCCA ramps up within a diode drop of
VCCI. VCCA and VCCI do not have to be stable during
power-up/down, and they do not require a specific
power-up or power-down sequence in order to avoid
damage to the eX devices. In addition, all outputs can be
programmed to have a weak resistor pull-up or pulldown for output tristate at power-up. After the eX
device is plugged into an electrically active system, the
device will not degrade the reliability of or cause
damage to the host system. The device's output pins are
driven to a high impedance state until normal chip
operating conditions are reached. Please see the
application note, Actel SX-A and RT54SX-S Devices in
Hot-Swap and Cold-Sparing Applications, which also
applies to the eX devices, for more information on hot
swapping.
The eX family has been designed with a Low Power
Mode. This feature, activated with setting the special LP
pin to HIGH for a period longer than 800 ns, is
particularly useful for battery-operated systems where
battery life is a primary concern. In this mode, the core of
the device is turned off and the device consumes minimal
power with low standby current. In addition, all input
buffers are turned off, and all outputs and bidirectional
buffers are tristated when the device enters this mode.
Since the core of the device is turned off, the states of
the registers are lost. The device must be re-initialized
when returning to normal operating mode. I/Os can be
driven during LP mode. For details, refer to the Design
for Low Power in Actel Antifuse FPGAs application note
under the section Using the LP Mode Pin on eX Devices.
Clock pins should be driven either HIGH or LOW and
should not float; otherwise, they will draw current and
burn power. The device must be re-initialized when
exiting LP mode. To exit the LP mode, the LP pin must be
driven LOW for over 200µs to allow for the charge
pumps to power-up and device initialization can begin.
Table 1-3 illustrates the standby current of eX devices in
LP mode.
Power Requirements
Power consumption is extremely low for the eX family
due to the low capacitance of the antifuse interconnects.
The antifuse architecture does not require active circuitry
to hold a charge (as do SRAM or EPROM), making it the
lowest-power FPGA architecture available today.
Table 1-3 • Standby Power of eX Devices in LP Mode
Typical Conditions, VCCA, VCCI = 2.5 V, TJ = 25° C
Product
1 -6
v4.3
Low Power Standby Current
Units
eX64
100
µA
eX128
111
µA
eX256
134
µA
eX Family FPGAs
Figure 1-8 to Figure 1-11 on page 1-8 show some sample power characteristics of eX devices.
300
Power (mW)
250
200
eX64
150
eX128
100
eX256
50
0
50
100
150
200
Frequency (MHz)
Notes:
1. Device filled with 16-bit counters.
2. VCCA, VCCI = 2.7 V, device tested at room temperature.
Figure 1-8 • eX Dynamic Power Consumption – High Frequency
80
70
Power (mW)
60
50
eX64
40
eX128
30
eX256
20
10
0
0
10
20
30
40
50
Frequency (MHz)
Notes:
1. Device filled with 16-bit counters.
2. VCCA, VCCI = 2.7 V, device tested at room temperature.
Figure 1-9 • eX Dynamic Power Consumption – Low Frequency
v4.3
1-7
eX Family FPGAs
180
Total Dynamic Power (mW)
160
140
120
32-bit Decoder
100
8 x 8-bit Counters
80
SDRAM Controller
60
40
20
0
0
25
50
75
100
125
150
175
200
Frequency (MHz)
Figure 1-10 • Total Dynamic Power (mW)
12,000
System Power (uW)
10,000
8,000
5% DC
6,000
10% DC
15% DC
4,000
2,000
0
0
10
20
30
Frequency (MHz)
Figure 1-11 • System Power at 5%, 10%, and 15% Duty Cycle
1 -8
v4.3
40
50
60
eX Family FPGAs
Boundary Scan Testing (BST)
Flexible Mode
All eX devices are IEEE 1149.1 compliant. eX devices offer
superior diagnostic and testing capabilities by providing
Boundary Scan Testing (BST) and probing capabilities.
These functions are controlled through the special test
pins (TMS, TDI, TCK, TDO and TRST). The functionality of
each pin is defined by two available modes: Dedicated
and Flexible, and is described in Table 1-4. In the
dedicated test mode, TCK, TDI, and TDO are dedicated
pins and cannot be used as regular I/Os. In flexible mode
(default mode), TMS should be set HIGH through a pullup resistor of 10 kΩ. TMS can be pulled LOW to initiate
the test sequence.
In Flexible Mode, TDI, TCK and TDO may be used as
either user I/Os or as JTAG input pins. The internal
resistors on the TMS and TDI pins are disabled in flexible
JTAG mode, and an external 10 kΩ pull-resistor to VCCI is
required on the TMS pin.
To select the Flexible mode, users need to uncheck the
"Reserve JTAG" box in "Device Selection Wizard" in
Actel's Designer software. The functionality of TDI, TCK,
and TDO pins is controlled by the BST TAP controller. The
TAP controller receives two control inputs, TMS and TCK.
Upon power-up, the TAP controller enters the Test-LogicReset state. In this state, TDI, TCK, and TDO function as
user I/Os. The TDI, TCK, and TDO pins are transformed
from user I/Os into BST pins when the TMS pin is LOW at
the first rising edge of TCK. The TDI, TCK, and TDO pins
return to user I/Os when TMS is held HIGH for at least
five TCK cycles.
Table 1-4 • Boundary Scan Pin Functionality
Dedicated Test Mode
Flexible Mode
TCK, TDI, TDO are dedicated TCK, TDI, TDO are flexible and
BST pins
may be used as I/Os
No need for pull-up resistor for Use a pull-up resistor of 10 kΩ
TMS and TDI
on TMS
Table 1-5
describes
the
different
configuration
requirements of BST pins and their functionality in
different modes.
Dedicated Test Mode
Table 1-5 • Boundary-Scan Pin Configurations and
Functions
In Dedicated mode, all JTAG pins are reserved for BST;
designers cannot use them as regular I/Os. An internal
pull-up resistor is automatically enabled on both TMS
and TDI pins, and the TMS pin will function as defined in
the IEEE 1149.1 (JTAG) specification.
Designer
"Reserve JTAG"
Selection
TAP Controller
State
Dedicated (JTAG)
Checked
Any
Flexible (User I/O)
Unchecked
Test-Logic-Reset
Flexible (JTAG)
Unchecked
Any EXCEPT TestLogic-Reset
Mode
To select Dedicated mode, users need to reserve the JTAG
pins in Actel's Designer software by checking the
"Reserve JTAG" box in "Device Selection Wizard"
(Figure 1-12). JTAG pins comply with LVTTL/TTL I/O
specification regardless of whether they are used as a
user I/O or a JTAG I/O. Refer to the "3.3V LVTTL Electrical
Specifications" and "5.0V TTL Electrical Specifications"
on page 1-15 for detailed specifications.
TRST Pin
The TRST pin functions as a dedicated Boundary-Scan
Reset pin when the "Reserve JTAG Test Reset" option is
selected as shown in Figure 1-12. An internal pull-up
resistor is permanently enabled on the TRST pin in this
mode. It is recommended to connect this pin to GND in
normal operation to keep the JTAG state controller in
the Test-Logic-Reset state. When JTAG is being used, it
can be left floating or be driven HIGH.
When the "Reserve JTAG Test Reset" option is not
selected, this pin will function as a regular I/O. If unused
as an I/O in the design, it will be configured as a tristated
output.
Figure 1-12 • Device Selection Wizard
v4.3
1-9
eX Family FPGAs
JTAG Instructions
1. Load the .AFM file
Table 1-6 lists the supported instructions with the
corresponding IR codes for eX devices.
2. Select the device to be programmed
When the design is ready to go to production, Actel
offers device volume-programming services either
through distribution partners or via in-house
programming from the factory.
Table 1-6 • JTAG Instruction Code
Instructions (IR4: IR0)
Binary Code
EXTEST
00000
SAMPLE / PRELOAD
00001
INTEST
00010
USERCODE
00011
IDCODE
00100
HIGHZ
01110
CLAMP
01111
Diagnostic
10000
BYPASS
11111
Reserved
All others
For more details on programming eX devices, please
refer to the Programming Antifuse Devices application
note and the Silicon Sculptor II User's Guide.
Probing Capabilities
Table 1-7 lists the codes returned after executing the
IDCODE instruction for eX devices. Note that bit 0 is
always "1." Bits 11-1 are always "02F", which is Actel's
manufacturer code.
Table 1-7 • IDCODE for eX Devices
Device
Revision
Bits 31-28
Bits 27-12
eX64
0
8
40B2, 42B2
eX128
0
9
40B0, 42B0
eX256
0
9
40B5, 42B5
eX64
1
A
40B2, 42B2
eX128
1
B
40B0, 42B0
eX256
1
B
40B5, 42B5
eX devices provide internal probing capability that is
accessed with the JTAG pins. The Silicon Explorer II
Diagnostic hardware is used to control the TDI, TCK, TMS
and TDO pins to select the desired nets for debugging.
The user simply assigns the selected internal nets in the
Silicon Explorer II software to the PRA/PRB output pins
for observation. Probing functionality is activated when
the BST pins are in JTAG mode and the TRST pin is driven
HIGH or left floating. If the TRST pin is held LOW, the
TAP controller will remain in the Test-Logic-Reset state so
no probing can be performed. The Silicon Explorer II
automatically places the device into JTAG mode, but the
user must drive the TRST pin HIGH or allow the internal
pull-up resistor to pull TRST HIGH.
When you select the "Reserve Probe Pin" box as shown
in Figure 1-12 on page 1-9, the layout tool reserves the
PRA and PRB pins as dedicated outputs for probing. This
"reserve" option is merely a guideline. If the Layout tool
requires that the PRA and PRB pins be user I/Os to
achieve successful layout, the tool will use these pins for
user I/Os. If you assign user I/Os to the PRA and PRB pins
and select the "Reserve Probe Pin" option, Designer
Layout will override the "Reserve Probe Pin" option and
place your user I/Os on those pins.
Programming
Device programming is supported through Silicon
Sculptor series of programmers. In particular, Silicon
Sculptor II is a compact, robust, single-site and multi-site
device programmer for the PC.
With standalone software, Silicon Sculptor II allows
concurrent programming of multiple units from the
same PC, ensuring the fastest programming times
possible. Each fuse is subsequently verified by Silicon
Sculptor II to insure correct programming. In addition,
integrity tests ensure that no extra fuses are
programmed. Silicon Sculptor II also provides extensive
hardware self-testing capability.
The procedure for programming an eX device using
Silicon Sculptor II is as follows:
1 -1 0
3. Begin programming
v4.3
To allow for probing capabilities, the security fuse must
not be programmed. Programming the security fuse will
disable the probe circuitry. Table 1-8 on page 1-11
summarizes the possible device configurations for
probing once the device leaves the "Test-Logic-Reset"
JTAG state.
Silicon Explorer II Probe
Silicon Explorer II is an integrated hardware and
software solution that, in conjunction with Actel’s
Designer software tools, allow users to examine any of
the internal nets of the device while it is operating in a
prototype or a production system. The user can probe
into an eX device via the PRA and PRB pins without
changing the placement and routing of the design and
without using any additional resources. Silicon
eX Family FPGAs
Explorer II's noninvasive method does not alter timing or
loading effects, thus shortening the debug cycle.
Silicon Explorer II does not require re-layout or
additional MUXes to bring signals out to an external pin,
which is necessary when using programmable logic
devices from other suppliers.
Silicon Explorer II samples data at 100 MHz
(asynchronous) or 66 MHz (synchronous). Silicon Explorer
II attaches to a PC's standard COM port, turning the PC
into a fully functional 18-channel logic analyzer. Silicon
Explorer II allows designers to complete the design
verification process at their desks and reduces
verification time from several hours per cycle to a few
seconds.
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation. Figure 1-13 illustrates the
interconnection between Silicon Explorer II and the eX
device to perform in-circuit verification.
Design Considerations
The TDI, TCK, TDO, PRA, and PRB pins should not be used
as input or bidirectional ports. Since these pins are active
during probing, critical signals input through these pins
are not available while probing. In addition, the Security
Fuse should not be programmed because doing so
disables the probe circuitry. It is recommended to use a
series 70Ω termination resistor on every probe connector
(TDI, TCK, TMS, TDO, PRA, PRB). The 70Ω series
termination is used to prevent data transmission
corruption during probing and reading back the
checksum.
Table 1-8 • Device Configuration Options for Probe Capability (TRST pin reserved)
JTAG Mode
Dedicated
TRST1
Security Fuse Programmed
PRA, PRB2
TDI, TCK, TDO2
LOW
No
User I/O3
Probing Unavailable
3
User I/O3
Flexible
LOW
No
User I/O
Dedicated
HIGH
No
Probe Circuit Outputs
Probe Circuit Inputs
Flexible
HIGH
No
Probe Circuit Outputs
Probe Circuit Inputs
–
Yes
Probe Circuit Secured
Probe Circuit Secured
–
Notes:
1. If TRST pin is not reserved, the device behaves according to TRST = HIGH in the table.
2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input
signals will not pass through these pins and may cause contention.
3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by
Actel’s Designer software.
16 Pin
Connection
Serial
Connection Silicon Explorer II
TDI
TCK
TMS
TDO
eX FPGAs
PRA
PRB
22 Pin
Connection
Additional 16 Channels
(Logic Analyzer)
Figure 1-13 • Silicon Explorer II Probe Setup
v4.3
1-11
eX Family FPGAs
Development Tool Support
The eX family of FPGAs is fully supported by both Actel's
Libero™ Integrated Design Environment and Designer
FPGA Development software. Actel Libero IDE is a design
management environment that streamlines the design
flow. Libero IDE provides an integrated design manager
that seamlessly integrates design tools while guiding the
user through the design flow, managing all design and
log files, and passing necessary design data among tools.
Additionally, Libero IDE allows users to integrate both
schematic and HDL synthesis into a single flow and verify
the entire design in a single environment. Libero IDE
includes Synplify® for Actel from Synplicity®, ViewDraw
for Actel from Mentor Graphics, ModelSim™ HDL
Simulator from Mentor Graphics®, WaveFormer Lite™
from SynaptiCAD™, and Designer software from Actel.
Refer to the Libero IDE flow (located on Actel’s website)
diagram for more information.
Actel's Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
timing-driven place-and-route, and a world-class
integrated static timing analyzer and constraints editor.
With the Designer software, a user can lock his/her
design pins before layout while minimally impacting the
results of place-and-route. Additionally, the backannotation flow is compatible with all the major
simulators and the simulation results can be cross-probed
with Silicon Explorer II, Actel’s integrated verification
and logic analysis tool. Another tool included in the
Designer software is the SmartGen core generator, which
easily creates popular and commonly used logic
functions for implementation into your schematic or HDL
design. Actel's Designer software is compatible with the
most popular FPGA design entry and verification tools
from companies such as Mentor Graphics, Synplicity,
Synopsys, and Cadence Design Systems. The Designer
software is available for both the Windows and UNIX
operating systems.
1 -1 2
v4.3
Related Documents
Datasheet
eX Automotive Family FPGAs
http://www.actel.com/documents/eXAuto_DS.pdf
Application Notes
Maximizing Logic Utilization in eX, SX and SX-A FPGA
Devices Using CC Macros
http://www.actel.com/documents/CC_Macro_AN.pdf
Actel's Implementation of Security in Actel Antifuse FPGAs
http://www.actel.com/documents/
Antifuse_Security_AN.pdf
Actel eX, SX-A, and RT54SX-S I/Os
http://www.actel.com/documents/antifuseIO_AN.pdf
Actel SX-A and RT54SX-S Devices in Hot-Swap and ColdSparing Applications
http://www.actel.com/documents/
HotSwapColdSparing_AN.pdf
Design For Low Power in Actel Antifuse FPGAs
http://www.actel.com/documents/Low_Power_AN.pdf
Programming Antifuse Devices
http://www.actel.com/documents/
AntifuseProgram_AN.pdf
User Guides
Silicon Sculptor II User's Guide
http://www.actel.com/techdocs/manuals/
default.asp#programmers
Miscellaneous
Libero IDE flow
http://www.actel.com/products/tools/libero/flow.html
eX Family FPGAs
2.5 V / 3.3 V /5.0 V Operating Conditions
Table 1-9 • Absolute Maximum Ratings*
Symbol
Parameter
Limits
Units
VCCI
DC Supply Voltage for I/Os
–0.3 to +6.0
V
VCCA
DC Supply Voltage for Array
–0.3 to +3.0
V
VI
Input Voltage
–0.5 to +5.75
V
VO
Output Voltage
–0.5 to +VCCI
V
TSTG
Storage Temperature
–65 to +150
°C
Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
Table 1-10 • Recommended Operating Conditions
Parameter
Commercial
Industrial
Units
Temperature Range*
0 to +70
–40 to +85
°C
2.5V Power Supply
Range (VCCA, VCCI)
2.3 to 2.7
2.3 to 2.7
V
3.3V Power Supply
Range (VCCI)
3.0 to 3.6
3.0 to 3.6
V
5.0V Power Supply
Range (VCCI)
4.75 to 5.25
4.75 to 5.25
V
VCCA= 2.5 V
VCCI = 2.5 V
VCCA = 2.5 V
VCCI = 3.3 V
VCCA = 2.5 V
VCCI = 5.0 V
eX64
397 µA
49 7µA
700 µA
eX128
696 µA
795 µA
1,000 µA
eX256
698 µA
796 µA
2,000 µA
Note: *Ambient temperature (TA).
Table 1-11 • Typical eX Standby Current at 25°C
Product
v4.3
1-13
eX Family FPGAs
2.5 V LVCMOS2 Electrical Specifications
Commercial
Symbol
VOH
VOL
Parameter
Min.
Max.
Industrial
Min.
Max.
Units
VCCI = MIN, VI = VIH or VIL
(IOH = -100 µA)
2.1
2.1
V
VCCI = MIN, VI = VIH or VIL
(IOH = -1 mA)
2.0
2.0
V
VCCI = MIN, VI = VIH or VIL
(IOH = -2 mA)
1.7
1.7
V
VCCI = MIN, VI = VIH or VIL
(IOL= 100 µA)
0.2
0.2
V
VCCI = MIN, VI = VIH or VIL
(IOL= 1mA)
0.4
0.4
V
VCCI = MIN,VI = VIH or VIL
(IOL= 2 mA)
0.7
0.7
V
VIL
Input Low Voltage, VOUT ≤ VOL(max)
–0.3
0.7
-0.3
0.7
V
VIH
Input High Voltage, VOUT ≥ VOH(min)
1.7
VCCI + 0.3
1.7
VCCI +
0.3
V
IIL/ IIH
Input Leakage Current, VIN = VCCI or GND
–10
10
–10
10
µA
IOZ
3-State Output Leakage Current, VOUT = VCCI or GND
–10
10
–10
10
µA
tR, tF
1,2
Input Transition Time
10
10
ns
CIO
I/O Capacitance
10
10
pF
ICC3,4
Standby Current
1.0
3.0
mA
IV Curve
Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.
Notes:
1.
2.
3.
4.
1 -1 4
tR is the transition time from 0.7 V to 1.7 V.
tF is the transition time from 1.7 V to 0.7 V.
ICC max Commercial –F = 5.0 mA
ICC = ICCI + ICCA
v4.3
eX Family FPGAs
3.3 V LVTTL Electrical Specifications
Commercial
Symbol
Parameter
Min.
Max.
VOH
VCCI = MIN, VI = VIH or VIL
(IOH = –8 mA)
2.4
VOL
VCCI = MIN, VI = VIH or VIL
(IOL= 12 mA)
VIL
Input Low Voltage
VIH
Input High Voltage
2.0
VCCI +0.5
IIL/ IIH
Input Leakage Current, VIN = VCCI or GND
–10
IOZ
3-State Output Leakage Current, VOUT = VCCI or GND
–10
tR, tF1,2
Input Transition Time
CIO
ICC3,4
IV Curve
Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.
Industrial
Min.
Max.
2.4
Units
V
0.4
0.4
V
0.8
0.8
V
2.0
VCCI +0.5
V
10
–10
10
µA
10
–10
10
µA
10
10
ns
I/O Capacitance
10
10
pF
Standby Current
1.5
10
mA
Notes:
1.
2.
3.
4.
5.
tR is the transition time from 0.8 V to 2.0 V.
tF is the transition time from 2.0 V to 0.8 V.
ICC max Commercial –F = 5.0 mA
ICC = ICCI + ICCA
JTAG pins comply with LVTTL/TTL I/O specification regardless of whether they are used as a user I/O or a JTAG I/O.
5.0 V TTL Electrical Specifications
Commercial
Symbol
Parameter
Min.
Max.
VOH
VCCI = MIN, VI = VIH or VIL
(IOH = –8 mA)
2.4
VOL
VCCI = MIN, VI = VIH or VIL
(IOL= 12 mA)
VIL
Input Low Voltage
VIH
Input High Voltage
2.0
VCCI +0.5
IIL/ IIH
Input Leakage Current, VIN = VCCI or GND
–10
IOZ
3-State Output Leakage Current, VOUT = VCCI or GND
–10
tR, tF1,2
Input Transition Time
CIO
ICC3,4
IV Curve
Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.
Industrial
Min.
Max.
2.4
Units
V
0.4
0.4
V
0.8
0.8
V
2.0
VCCI +0.5
V
10
–10
10
µA
10
–10
10
µA
10
10
ns
I/O Capacitance
10
10
pF
Standby Current
15
20
mA
Note:
1.
2.
3.
4.
5.
tR is the transition time from 0.8 V to 2.0 V.
tF is the transition time from 2.0 V to 0.8 V.
ICC max Commercial –F=20mA
ICC = ICCI + ICCA
JTAG pins comply with LVTTL/TTL I/O specification regardless of whether they are used as a user I/O or a JTAG I/O.
v4.3
1-15
eX Family FPGAs
Power Dissipation
CEQ Values for eX Devices
Power consumption for eX devices can be divided into
two components: static and dynamic.
Combinatorial modules (Ceqcm)
Sequential modules (Ceqsm)
Input buffers (Ceqi)
Output buffers (Ceqo)
Routed array clocks (Ceqcr)
Static Power Component
The power due to standby current is typically a small
component of the overall power. Typical standby current
for eX devices is listed in the Table 1-11 on page 1-13. For
example, the typical static power for eX128 at 3.3 V VCCI
is:
1.70 pF
1.70 pF
1.30 pF
7.40 pF
1.05 pF
The variable and fixed capacitance of other device
components must also be taken into account when
estimating the dynamic power dissipation.
ICC * VCCA = 795 µA x 2.5 V = 1.99 mW
Table 1-12 shows the capacitance
components of eX devices.
Dynamic Power Component
Table 1-12 • Capacitance of Clock Components of eX
Devices
Power dissipation in CMOS devices is usually dominated
by the dynamic power dissipation. This component is
frequency-dependent and a function of the logic and the
external I/O. Dynamic power dissipation results from
charging internal chip capacitance due to PC board
traces and load device inputs. An additional component
of the dynamic power dissipation is the totem pole
current in the CMOS transistor pairs. The net effect can
be associated with an equivalent capacitance that can be
combined with frequency and voltage to represent
dynamic power dissipation.
2
Dynamic power dissipation = CEQ * VCCA x F
where:
CEQ = Equivalent capacitance
F
= switching frequency
Equivalent capacitance is calculated by measuring ICCA at
a specified frequency and voltage for each circuit
component of interest. Measurements have been made
over a range of frequencies at a fixed value of VCC.
Equivalent capacitance is frequency-independent, so the
results can be used over a wide range of operating
conditions. Equivalent capacitance values are shown
below.
1 -1 6
v4.3
of
the
clock
eX64
eX128
eX256
0.85 pF
0.85 pF
0.85 pF
Dedicated array clock – fixed 18.00 pF
(Ceqhf)
20.00 pF
25.00 pF
Routed array clock A (r1)
23.00 pF
28.00 pF
35.00 pF
Routed array clock B (r2)
23.00 pF
28.00 pF
35.00 pF
Dedicated array
variable (Ceqhv)
clock
–
The estimation of the dynamic power dissipation is a
piece-wise linear summation of the power dissipation of
each component.
Dynamic power dissipation
= VCCA2 * [(mc * Ceqcm * fmC)Comb Modules + (ms * Ceqsm *
fmS)Seq Modules + (n * Ceqi * fn)Input Buffers + (0.5 * (q1 *
Ceqcr * fq1) + (r1 * fq1))RCLKA + (0.5 * (q2 * Ceqcr * fq2) +
(r2 * fq2))RCLKB + (0.5 * (s1 * Ceqhv * fs1)+(Ceqhf *
fs1))HCLK] + VCCI2 * [(p * (Ceqo + CL) * fp)Output Buffers]
where:
mc
= Number of combinatorial cells switching at
frequency fm, typically 20% of C-cells
= Number of sequential cells switching at
ms
frequency fm, typically 20% of R-cells
n
= Number of input buffers switching at
frequency fn, typically number of inputs / 4
p
= Number of output buffers switching at
frequency fp, typically number of outputs / 4
q1
= Number of R-cells driven by routed array
clock A
q2
= Number of R-cells driven by routed array
clock B
r1
= Fixed capacitance due to routed array clock A
r2
= Fixed capacitance due to routed array clock B
s1
= Number of R-cells driven by dedicated array
clock
Ceqcm = Equivalent capacitance of combinatorial
modules
eX Family FPGAs
Thermal Characteristics
Ceqsm =
Equivalent capacitance of sequential
modules
Ceqi = Equivalent capacitance of input buffers
Ceqcr = Equivalent capacitance of routed array clocks
Ceqhv = Variable capacitance of dedicated array clock
Ceqhf = Fixed capacitance of dedicated array clock
Ceqo = Equivalent capacitance of output buffers
CL
=
Average output loading capacitance,
typically 10 pF
= Average C-cell switching frequency, typically
fmc
F/10
fms = Average R-cell switching frequency, typically
F/10
fn
= Average input buffer switching frequency,
typically F/5
fp
= Average output buffer switching frequency,
typically F/5
fq1
= Frequency of routed clock A
fq2
= Frequency of routed clock B
fs1
= Frequency of dedicated array clock
The eX, SX-A and RTSX-S Power Calculator can be used to
estimate the total power dissipation (static and dynamic)
of eX devices and can be found at
http://www.actel.com/products/rescenter/power/
calculators.asp.
The temperature variable in the Designer software refers
to the junction temperature, not the ambient
temperature. This is an important distinction because the
heat generated from dynamic power consumption is
usually hotter than the ambient temperature. EQ 1-1,
shown below, can be used to calculate junction
temperature.
EQ 1-1
Junction Temperature = ∆T + Ta(1)
Where:
Ta = Ambient Temperature
∆T = Temperature gradient between junction
(silicon) and ambient = θja * P
P = Power
θja = Junction to ambient of package. θja numbers are
located in the "Package Thermal Characteristics" section
below.
Package Thermal Characteristics
The device junction-to-case thermal characteristic is θjc,
and the junction-to-ambient air characteristic is θja. The
thermal characteristics for θja are shown with two
different air flow rates. θjc is provided for reference.
The maximum junction temperature is 150°C.
The maximum power dissipation allowed for eX devices
is a function of θja. A sample calculation of the absolute
maximum power dissipation allowed for a TQFP 100-pin
package at commercial temperature and still air is as
follows:
Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C – 70°C
Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------- = ----------------------------------- = 2.39W
θ ja (°C/W)
33.5°C/W
θja
Pin Count
θjc
Still Air
1.0 m/s
200 ft/min
2.5 m/s
500 ft/min
Units
Thin Quad Flat Pack (TQFP)
64
12.0
42.4
36.3
34.0
°C/W
Thin Quad Flat Pack (TQFP)
100
14.0
33.5
27.4
25.0
°C/W
Chip Scale Package (CSP)
49
72.2
59.5
54.1
°C/W
Chip Scale Package (CSP)
128
54.1
44.6
40.6
°C/W
Chip Scale Package (CSP)
180
57.8
47.6
43.3
°C/W
Package Type
v4.3
1-17
eX Family FPGAs
eX Timing Model
Input Delays
I/O Module
t INYH = 0.7 ns
Internal Delays
Combinatorial
Cell
t IRD1 = 0.3 ns
t IRD2 = 0.4 ns
t PD = 0.7 ns
Predicted
Routing
Delays
Output Delays
I/O Module
t DHL = 2.6 ns
t RD1 = 0.3 ns
t RD4 = 0.7 ns
t RD8 = 1.2 ns
I/O Module
Register
Cell
t ENZL= 1.9 ns
t SUD = 0.5 ns
t HD = 0.0 ns
Routed
Clock
t RCKH = 1.3 ns
t RD1 = 0.3 ns
t DHL = 2.6 ns
I/O Module
Register
Cell
t ENZL= 1.9 ns
t IRD1 = 0.3 ns
t SUD = 0.5 ns
t HD = 0.0 ns
Hard-Wired
Clock
Q
t RCO= 0.6 ns
(100% Load)
I/O Module
t INYH = 1.3 ns
D
t HCKH = 1.1 ns
D
Q
t RD1 = 0.3 ns
t DHL = 2.6 ns
t RCO= 0.6 ns
Note: Values shown for eX128–P, worst-case commercial conditions (5.0V, 35pF Pad Load).
Figure 1-14 • eX Timing Model
Hardwired Clock
Routed Clock
External Setup =
External Setup =
tINYH + tIRD2 + tSUD – tRCKH
=
0.7 + 0.4 + 0.5 – 1.3= 0.3 ns
=
tINYH + tIRD1 + tSUD – tHCKH
0.7 + 0.3 + 0.5 – 1.1 = 0.4 ns
Clock-to-Out (Pad-to-Pad), typical
Clock-to-Out (Pad-to-Pad), typical
=
tHCKH + tRCO + tRD1 + tDHL
=
tRCKH + tRCO + tRD1 + tDHL
=
1.1 + 0.6 + 0.3 + 2.6 = 4.6 ns
=
1.3+ 0.6 + 0.3 + 2.6 = 4.8 ns
1 -1 8
v4.3
eX Family FPGAs
Output Buffer Delays
E
D
In
Out
VOL
VCC
50% 50%
VOH
1.5 V
GND
1.5 V
tDHL
tDLH
En
Out
PAD To AC test loads (shown below)
TRIBUFF
VCC
50% 50%
GND
VCC
1.5 V
10%
V
OL
tENZL
tENLZ
En
VCC
50% 50%
VOH
1.5 V
Out
GND t
ENZH
GND
90%
tENHZ
Table 1-13 • Output Buffer Delays
AC Test Loads
Load 1
(used to measure
propagation delay)
Load 2
(Used to measure enable delays)
VCC
To the output
under test
35 pF
To the output
under test
GND
R to VCC for tPZL
R to GND for tPHZ
R = 1 kΩ
35 pF
Load 3
(Used to measure disable delays)
VCC
To the output
under test
GND
R to VCC for tPLZ
R to GND for tPHZ
R = 1 kΩ
5 pF
Figure 1-15 • AC Test Loads
v4.3
1-19
eX Family FPGAs
Input Buffer Delays
PAD
C-Cell Delays
S
A
B
Y
INBUF
S, A or B
3V
In
Out
GND
1.5 V
Out
GND
0V
1.5 V
VCC
50%
tPD
GND
50%
tPD
Out
50%
VCC
50%
tPD
tINY
tINY
VCC
50% 50%
VCC
50%
Y
Table 1-14 • Input Buffer Delays
GND
tPD
Table 1-15 • C-Cell Delays
Cell Timing Characteristics
D
CLK
Q
CLR
(Positive edge triggered)
tHD
D
t SUD
CLK
PRESET
tH P
t HPWH
,
t RPWH
tRCO
tHPWL, tRPWL
Q
tCLR
CLR
tWASYN
PRESET
Figure 1-16 • Flip-Flops
1 -2 0
v4.3
t PRESET
50%
eX Family FPGAs
Timing Characteristics
Long Tracks
Timing characteristics for eX devices fall into three
categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer
characteristics are common to all eX family members.
Internal routing delays are device-dependent. Design
dependency means actual delays are not determined
until after placement and routing of the user’s design are
complete. Delay values may then be determined by using
the Timer utility or performing simulation with postlayout delays.
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows,
columns, or modules. Long tracks employ three to five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, no more than six
percent of nets in a fully utilized device require long
tracks. Long tracks contribute approximately 4 ns to
8.4 ns delay. This additional delay is represented
statistically in higher fanout routing delays.
Critical Nets and Typical Nets
Timing Derating
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most timing
critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up
to six percent of the nets in a design may be designated
as critical.
eX devices are manufactured with a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case
processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating
temperature, and worst-case processing.
Temperature and Voltage Derating Factors
Table 1-16 • Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, TJ = 70°C, VCCA = 2.3V)
Junction Temperature (TJ)
VCCA
–55
–40
0
25
70
85
125
2.3
0.79
0.80
0.87
0.88
1.00
1.04
1.13
2.5
0.74
0.74
0.81
0.83
0.93
0.97
1.06
2.7
0.69
0.70
0.76
0.78
0.88
0.91
1.00
v4.3
1-21
eX Family FPGAs
eX Family Timing Characteristics
Table 1-17 • eX Family Timing Characteristics
(Worst-Case Commercial Conditions, VCCA = 2.3 V, TJ = 70°C)
‘–P’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
1
C-Cell Propagation Delays
tPD
Internal Array Module
Predicted Routing Delays
0.7
1.0
1.4
ns
0.1
0.1
0.2
ns
2
tDC
FO=1 Routing Delay, DirectConnect
tFC
FO=1 Routing Delay, FastConnect
0.3
0.5
0.7
ns
tRD1
FO=1 Routing Delay
0.3
0.5
0.7
ns
tRD2
FO=2 Routing Delay
0.4
0.6
0.8
ns
tRD3
FO=3 Routing Delay
0.5
0.8
1.1
ns
tRD4
FO=4 Routing Delay
0.7
1.0
1.3
ns
tRD8
FO=8 Routing Delay
1.2
1.7
2.4
ns
tRD12
FO=12 Routing Delay
1.7
2.5
3.5
ns
R-Cell Timing
tRCO
Sequential Clock-to-Q
0.6
0.9
1.3
ns
tCLR
Asynchronous Clear-to-Q
0.6
0.8
1.2
ns
tPRESET
Asynchronous Preset-to-Q
tSUD
Flip-Flop Data Input Set-Up
0.5
0.7
1.0
ns
tHD
Flip-Flop Data Input Hold
0.0
0.0
0.0
ns
tWASYN
Asynchronous Pulse Width
1.3
1.9
2.6
ns
tRECASYN
Asynchronous Recovery Time
0.3
0.5
0.7
ns
tHASYN
Asynchronous Hold Time
0.3
0.5
0.7
ns
0.7
0.9
1.3
ns
2.5 V Input Module Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
0.6
0.9
1.3
ns
tINYL
Input Data Pad-to-Y LOW
0.8
1.1
1.5
ns
3.3 V Input Module Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
0.7
1.0
1.4
ns
tINYL
Input Data Pad-to-Y LOW
0.9
1.3
1.8
ns
5.0 V Input Module Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
0.7
1.0
1.4
ns
tINYL
Input Data Pad-to-Y LOW
0.9
1.3
1.8
ns
Input Module Predicted Routing
Delays2
tIRD1
FO=1 Routing Delay
0.3
0.4
0.5
ns
tIRD2
FO=2 Routing Delay
0.4
0.6
0.8
ns
tIRD3
FO=3 Routing Delay
0.5
0.8
1.1
ns
tIRD4
FO=4 Routing Delay
0.7
1.0
1.3
ns
tIRD8
FO=8 Routing Delay
1.2
1.7
2.4
ns
tIRD12
FO=12 Routing Delay
1.7
2.5
3.5
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.
1 -2 2
v4.3
eX Family FPGAs
Table 1-18 • eX Family Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.3 V, VCCI = 4.75 V, TJ = 70°C)
‘–P’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Dedicated (Hard-Wired) Array Clock Networks
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
1.1
1.6
2.3
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
1.1
1.6
2.3
ns
tHPWH
Minimum Pulse Width HIGH
1.4
2.0
2.8
ns
tHPWL
Minimum Pulse Width LOW
1.4
2.0
2.8
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
<0.1
2.8
<0.1
4.0
<0.1
5.6
ns
ns
357
250
178
MHz
Routed Array Clock Networks
tRCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) MAX.
1.1
1.6
2.2
ns
tRCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) MAX.
1.0
1.4
2.0
ns
tRCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
2.4
ns
tRCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
2.4
ns
tRCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) MAX.
1.3
1.9
2.6
ns
tRCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) MAX.
1.3
1.9
2.6
ns
tRPWH
Min. Pulse Width HIGH
1.5
2.1
3.0
ns
tRPWL
Min. Pulse Width LOW
1.5
2.1
3.0
ns
tRCKSW*
Maximum Skew (Light Load)
0.2
0.3
0.4
ns
tRCKSW*
Maximum Skew (50% Load)
0.1
0.2
0.3
ns
tRCKSW*
Maximum Skew (100% Load)
0.1
0.1
0.2
ns
Note: *Clock skew improves as the clock network becomes more heavily loaded.
v4.3
1-23
eX Family FPGAs
Table 1-19 • eX Family Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.3V, VCCI = 2.3 V or 3.0V, TJ = 70°C)
‘–P’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Dedicated (Hard-Wired) Array Clock Networks
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
1.1
1.6
2.3
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
1.1
1.6
2.3
ns
tHPWH
Minimum Pulse Width HIGH
1.4
2.0
2.8
ns
tHPWL
Minimum Pulse Width LOW
1.4
2.0
2.8
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
<0.1
2.8
<0.1
4.0
<0.1
5.6
ns
ns
357
250
178
MHz
Routed Array Clock Networks
tRCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) MAX.
1.0
1.4
2.0
ns
tRCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) MAX.
1.0
1.4
2.0
ns
tRCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
2.4
ns
tRCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
2.4
ns
tRCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) MAX.
1.4
2.0
2.8
ns
tRCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) MAX.
1.4
2.0
2.8
ns
tRPWH
Min. Pulse Width HIGH
1.4
2.0
2.8
ns
tRPWL
Min. Pulse Width LOW
1.4
2.0
2.8
ns
tRCKSW*
Maximum Skew (Light Load)
0.2
0.3
0.4
ns
tRCKSW*
Maximum Skew (50% Load)
0.2
0.2
0.3
ns
tRCKSW*
Maximum Skew (100% Load)
0.1
0.1
0.2
ns
Note: *Clock skew improves as the clock network becomes more heavily loaded.
1 -2 4
v4.3
eX Family FPGAs
Table 1-20 • eX Family Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.3 V, TJ = 70°C)
‘–P’ Speed
Parameter
Description
2.5 V LVCMOS Output Module
Min.
Timing1
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
(VCCI = 2.3 V)
tDLH
Data-to-Pad LOW to HIGH
3.3
4.7
6.6
ns
tDHL
Data-to-Pad HIGH to LOW
3.5
5.0
7.0
ns
tDHLS
Data-to-Pad HIGH to LOW—Low Slew
11.6
16.6
23.2
ns
tENZL
Enable-to-Pad, Z to L
2.5
3.6
5.1
ns
tENZLS
Enable-to-Pad Z to L—Low Slew
11.8
16.9
23.7
ns
tENZH
Enable-to-Pad, Z to H
3.4
4.9
6.9
ns
tENLZ
Enable-to-Pad, L to Z
2.1
3.0
4.2
ns
tENHZ
Enable-to-Pad, H to Z
2.4
5.67
7.94
ns
dTLH
Delta Delay vs. Load LOW to HIGH
0.034
0.046
0.066
ns/pF
dTHL
Delta Delay vs. Load HIGH to LOW
0.016
0.022
0.05
ns/pF
dTHLS
Delta Delay vs. Load HIGH to LOW—Low Slew
0.05
0.072
0.1
ns/pF
1
3.3 V LVTTL Output Module Timing (VCCI = 3.0 V)
tDLH
Data-to-Pad LOW to HIGH
2.8
4.0
5.6
ns
tDHL
Data-to-Pad HIGH to LOW
2.7
3.9
5.4
ns
tDHLS
Data-to-Pad HIGH to LOW—Low Slew
9.7
13.9
19.5
ns
tENZL
Enable-to-Pad, Z to L
2.2
3.2
4.4
ns
tENZLS
Enable-to-Pad Z to L—Low Slew
9.7
13.9
19.6
ns
tENZH
Enable-to-Pad, Z to H
2.8
4.0
5.6
ns
tENLZ
Enable-to-Pad, L to Z
2.8
4.0
5.6
ns
tENHZ
Enable-to-Pad, H to Z
2.6
3.8
5.3
ns
dTLH
Delta Delay vs. Load LOW to HIGH
0.02
0.03
0.046
ns/pF
dTHL
Delta Delay vs. Load HIGH to LOW
0.016
0.022
0.05
ns/pF
dTHLS
Delta Delay vs. Load HIGH to LOW—Low Slew
0.05
0.072
0.1
ns/pF
*
5.0 V TTL Output Module Timing (VCCI = 4.75 V)
tDLH
Data-to-Pad LOW to HIGH
2.0
2.9
4.0
ns
tDHL
Data-to-Pad HIGH to LOW
2.6
3.7
5.2
ns
tDHLS
Data-to-Pad HIGH to LOW—Low Slew
6.8
9.7
13.6
ns
tENZL
Enable-to-Pad, Z to L
1.9
2.7
3.8
ns
tENZLS
Enable-to-Pad Z to L—Low Slew
6.8
9.8
13.7
ns
tENZH
Enable-to-Pad, Z to H
2.1
3.0
4.1
ns
tENLZ
Enable-to-Pad, L to Z
3.3
4.8
6.6
ns
Note: *Delays based on 35 pF loading.
v4.3
1-25
eX Family FPGAs
Pin Description
CLKA/B
Routed Clock A and B
TCK, I/O
These pins are clock inputs for clock distribution
networks. Input levels are compatible with standard TTL
or LVTTL specifications. The clock input is buffered prior
to clocking the R-cells. If not used, this pin must be set
LOW or HIGH on the board. It must not be left floating.
GND
Ground
HCLK
Dedicated (Hardwired)
Array Clock
This pin is the clock input for sequential modules. Input
levels are compatible with standard TTL or LVTTL
specifications. This input is directly wired to each R-cell
and offers clock speeds independent of the number of Rcells being driven. If not used, this pin must be set LOW
or HIGH on the board. It must not be left floating.
I/O
Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations,
input and output levels are compatible with standard
TTL or LVTTL specifications. Unused I/O pins are
automatically tristated by the Designer software.
LP
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active
when the TMS pin is set LOW (refer to Table 1-4 on
page 1-9). This pin functions as an I/O when the
boundary scan state machine reaches the “logic reset”
state.
TDI, I/O
LOW supply voltage.
Test Data Input
Serial input for boundary scan testing and diagnostic
probe. In flexible mode, TDI is active when the TMS pin is
set LOW (refer to Table 1-4 on page 1-9). This pin
functions as an I/O when the boundary scan state
machine reaches the “logic reset” state.
TDO, I/O
Test Data Output
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to
Table 1-4 on page 1-9). This pin functions as an I/O when
the boundary scan state machine reaches the "logic
reset" state. When Silicon Explorer is being used, TDO
will act as an output when the "checksum" command is
run. It will return to user I/O when "checksum" is
complete.
TMS
Low Power Pin
Test Clock
Test Mode Select
Controls the low power mode of the eX devices. The
device is placed in the low power mode by connecting
the LP pin to logic HIGH. In low power mode, all I/Os are
tristated, all input buffers are turned OFF, and the core
of the device is turned OFF. To exit the low power mode,
the LP pin must be set LOW. The device enters the low
power mode 800 ns after the LP pin is driven to a logic
HIGH. It will resume normal operation 200 µs after the LP
pin is driven to a logic LOW. LP pin should not be left
floating. Under normal operating condition it should be
tied to GND via 10 kΩ resistor.
The TMS pin controls the use of the IEEE 1149.1
Boundary scan pins (TCK, TDI, TDO, TRST). In flexible
mode when the TMS pin is set LOW, the TCK, TDI, and
TDO pins are boundary scan pins (refer to Table 1-4 on
page 1-9). Once the boundary scan pins are in test mode,
they will remain in that mode until the internal
boundary scan state machine reaches the “logic reset”
state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The “logic
reset” state is reached five TCK cycles after the TMS pin is
set HIGH. In dedicated test mode, TMS functions as
specified in the IEEE 1149.1 specifications.
NC
TRST, I/O
No Connection
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
PRA/PRB, I/O
Probe A/B
The Probe pin is used to output data from any userdefined design node within the device. This diagnostic
pin can be used independently or in conjunction with the
other probe pin to allow real-time diagnostic output of
any signal path within the device. The Probe pin can be
used as a user-defined I/O when verification has been
completed. The pin’s probe capabilities can be
permanently disabled to protect programmed design
confidentiality.
1 -2 6
v4.3
Boundary Scan Reset Pin
Once it is configured as the JTAG Reset pin, the TRST pin
functions as an active-low input to asynchronously
initialize or reset the boundary scan circuit. The TRST pin
is equipped with an internal pull-up resistor. This pin
functions as an I/O when the “Reserve JTAG Reset Pin” is
not selected in the Designer software.
VCCI
Supply Voltage
Supply voltage for I/Os.
VCCA
Supply Voltage
Supply voltage for Array.
eX Family FPGAs
Package Pin Assignments
64-Pin TQFP
64
1
64-Pin
TQFP
Figure 2-1 • 64-Pin TQFP
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v4.3
2-1
eX Family FPGAs
64-Pin TQFP
64-Pin TQFP
Pin Number
eX64
Function
eX128
Function
Pin Number
eX64
Function
eX128
Function
1
GND
GND
33
GND
GND
2
TDI, I/O
TDI, I/O
34
I/O
I/O
3
I/O
I/O
35
I/O
I/O
4
TMS
TMS
36
VCCA
VCCA
5
GND
GND
37
VCCI
VCCI
6
VCCI
VCCI
38
I/O
I/O
7
I/O
I/O
39
I/O
I/O
8
I/O
I/O
40
NC
I/O
9
NC
I/O
41
NC
I/O
10
NC
I/O
42
I/O
I/O
11
TRST, I/O
TRST, I/O
43
I/O
I/O
12
I/O
I/O
44
VCCA
VCCA
13
NC
I/O
45*
GND/LP
GND/ LP
14
GND
GND
46
GND
GND
15
I/O
I/O
47
I/O
I/O
16
I/O
I/O
48
I/O
I/O
17
I/O
I/O
49
I/O
I/O
18
I/O
I/O
50
I/O
I/O
19
VCCI
VCCI
51
I/O
I/O
20
I/O
I/O
52
VCCI
VCCI
21
PRB, I/O
PRB, I/O
53
I/O
I/O
22
VCCA
VCCA
54
I/O
I/O
23
GND
GND
55
CLKA
CLKA
24
I/O
I/O
56
CLKB
CLKB
25
HCLK
HCLK
57
VCCA
VCCA
26
I/O
I/O
58
GND
GND
27
I/O
I/O
59
PRA, I/O
PRA, I/O
28
I/O
I/O
60
I/O
I/O
29
I/O
I/O
61
VCCI
VCCI
30
I/O
I/O
62
I/O
I/O
31
I/O
I/O
63
I/O
I/O
32
TDO, I/O
TDO, I/O
64
TCK, I/O
TCK, I/O
Note: *Please read the LP pin descriptions for restrictions on their use.
2 -2
v4.3
eX Family FPGAs
100-Pin TQFP
100
1
100-Pin
TQFP
Figure 2-2 • 100-Pin TQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v4.3
2-3
eX Family FPGAs
100-Pin TQFP
100-Pin TQFP
Pin Number
eX64
Function
eX128
Function
eX256
Function
Pin Number
eX64
Function
eX128
Function
eX256
Function
1
GND
GND
GND
36
GND
GND
GND
2
TDI, I/O
TDI, I/O
TDI, I/O
37
NC
NC
NC
3
NC
NC
I/O
38
I/O
I/O
I/O
4
NC
NC
I/O
39
HCLK
HCLK
HCLK
5
NC
NC
I/O
40
I/O
I/O
I/O
6
I/O
I/O
I/O
41
I/O
I/O
I/O
7
TMS
TMS
TMS
42
I/O
I/O
I/O
8
VCCI
VCCI
VCCI
43
I/O
I/O
I/O
9
GND
GND
GND
44
VCCI
VCCI
VCCI
10
NC
I/O
I/O
45
I/O
I/O
I/O
11
NC
I/O
I/O
46
I/O
I/O
I/O
12
I/O
I/O
I/O
47
I/O
I/O
I/O
13
NC
I/O
I/O
48
I/O
I/O
I/O
14
I/O
I/O
I/O
49
TDO, I/O
TDO, I/O
TDO, I/O
15
NC
I/O
I/O
50
NC
I/O
I/O
16
TRST, I/O
TRST, I/O
TRST, I/O
51
GND
GND
GND
17
NC
I/O
I/O
52
NC
NC
I/O
18
I/O
I/O
I/O
53
NC
NC
I/O
19
NC
I/O
I/O
54
NC
NC
I/O
20
VCCI
VCCI
VCCI
55
I/O
I/O
I/O
21
I/O
I/O
I/O
56
I/O
I/O
I/O
22
NC
I/O
I/O
57
VCCA
VCCA
VCCA
23
NC
NC
I/O
58
VCCI
VCCI
VCCI
24
NC
NC
I/O
59
NC
I/O
I/O
25
I/O
I/O
I/O
60
I/O
I/O
I/O
26
I/O
I/O
I/O
61
NC
I/O
I/O
27
I/O
I/O
I/O
62
I/O
I/O
I/O
28
I/O
I/O
I/O
63
NC
I/O
I/O
29
I/O
I/O
I/O
64
I/O
I/O
I/O
30
I/O
I/O
I/O
65
NC
I/O
I/O
31
I/O
I/O
I/O
66
I/O
I/O
I/O
32
I/O
I/O
I/O
67
VCCA
VCCA
VCCA
33
I/O
I/O
I/O
68
GND/LP
GND/LP
GND/LP
34
PRB, I/O
PRB, I/O
PRB, I/O
69
GND
GND
GND
35
VCCA
VCCA
VCCA
70
I/O
I/O
I/O
Note: *Please read the LP pin descriptions for restrictions on their use.
2 -4
v4.3
eX Family FPGAs
100-Pin TQFP
Pin Number
eX64
Function
eX128
Function
eX256
Function
71
I/O
I/O
I/O
72
NC
I/O
I/O
73
NC
NC
I/O
74
NC
NC
I/O
75
NC
NC
I/O
76
NC
I/O
I/O
77
I/O
I/O
I/O
78
I/O
I/O
I/O
79
I/O
I/O
I/O
80
I/O
I/O
I/O
81
I/O
I/O
I/O
82
VCCI
VCCI
VCCI
83
I/O
I/O
I/O
84
I/O
I/O
I/O
85
I/O
I/O
I/O
86
I/O
I/O
I/O
87
CLKA
CLKA
CLKA
88
CLKB
CLKB
CLKB
89
NC
NC
NC
90
VCCA
VCCA
VCCA
91
GND
GND
GND
92
PRA, I/O
PRA, I/O
PRA, I/O
93
I/O
I/O
I/O
94
I/O
I/O
I/O
95
I/O
I/O
I/O
96
I/O
I/O
I/O
97
I/O
I/O
I/O
98
I/O
I/O
I/O
99
I/O
I/O
I/O
100
TCK, I/O
TCK, I/O
TCK, I/O
Note: *Please read the LP pin descriptions for restrictions on their use.
v4.3
2-5
eX Family FPGAs
49-Pin CSP
A1 Ball Pad Corner
1
2
3
4
5
6
A
B
C
D
E
F
G
Figure 2-3 • 49-Pin CSP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
2 -6
v4.3
7
eX Family FPGAs
49-Pin CSP
49-Pin CSP
Pin Number
eX64
Function
eX128
Function
Pin Number
eX64
Function
eX128
Function
A1
I/O
I/O
D5
VCCA
VCCA
A2
I/O
I/O
D6
I/O
I/O
A3
I/O
I/O
D7
I/O
I/O
A4
I/O
I/O
E1
I/O
I/O
A5
VCCA
VCCA
E2
TRST, I/O
TRST, I/O
A6
I/O
I/O
E3
VCCI
VCCI
A7
I/O
I/O
E4
GND
GND
B1
TCK, I/O
TCK, I/O
E5
I/O
I/O
B2
I/O
I/O
E6
I/O
I/O
B3
I/O
I/O
E7
VCCI
VCCI
B4
PRA, I/O
PRA, I/O
F1
I/O
I/O
B5
CLKA
CLKA
F2
I/O
I/O
B6
I/O
I/O
F3
I/O
I/O
B7*
GND/LP*
GND/LP*
F4
I/O
I/O
C1
I/O
I/O
F5
HCLK
HCLK
C2
TDI, I/O
TDI, I/O
F6
I/O
I/O
C3
VCCI
VCCI
F7
TDO, I/O
TDO, I/O
C4
GND
GND
G1
I/O
I/O
C5
CLKB
CLKB
G2
I/O
I/O
C6
VCCA
VCCA
G3
I/O
I/O
C7
I/O
I/O
G4
PRB, I/O
PRB, I/O
D1
I/O
I/O
G5
VCCA
VCCA
D2
TMS
TMS
G6
I/O
I/O
D3
GND
GND
G7
I/O
I/O
D4
GND
GND
Note: *Please read the LP pin descriptions for restrictions on their use.
v4.3
2-7
eX Family FPGAs
128-Pin CSP
A1 Ball Pad Corner
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
J
K
L
M
Figure 2-4 • 128-Pin CSP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
2 -8
v4.3
10
11
12
eX Family FPGAs
128-Pin CSP
128-Pin CSP
Pin Number
eX64
Function
eX128
Function
eX256
Function
Pin Number
eX64
Function
eX128
Function
eX256
Function
A1
I/O
I/O
I/O
C12
I/O
I/O
I/O
A2
TCK, I/O
TCK, I/O
TCK, I/O
D1
NC
I/O
I/O
A3
VCCI
VCCI
VCCI
D2
I/O
I/O
I/O
A4
I/O
I/O
I/O
D3
I/O
I/O
I/O
A5
I/O
I/O
I/O
D4
I/O
I/O
I/O
A6
VCCA
VCCA
VCCA
D5
I/O
I/O
I/O
A7
I/O
I/O
I/O
D6
GND
GND
GND
A8
I/O
I/O
I/O
D7
I/O
I/O
I/O
A9
VCCI
VCCI
VCCI
D8
GND
GND
GND
A10
I/O
I/O
I/O
D9
I/O
I/O
I/O
A11
I/O
I/O
I/O
D10
I/O
I/O
I/O
A12
I/O
I/O
I/O
D11
I/O
I/O
I/O
B1
TMS
TMS
TMS
D12
VCCI
VCCI
VCCI
B2
I/O
I/O
I/O
E1
NC
I/O
I/O
B3
I/O
I/O
I/O
E2
VCCI
VCCI
VCCI
B4
I/O
I/O
I/O
E3
I/O
I/O
I/O
B5
I/O
I/O
I/O
E4
GND
GND
GND
B6
PRA, I/O
PRA, I/O
PRA, I/O
E9
GND
GND
GND
B7
CLKB
CLKB
CLKB
E10
I/O
I/O
I/O
B8
I/O
I/O
I/O
E11*
GND/LP*
GND/LP*
GND/LP*
B9
I/O
I/O
I/O
E12
VCCA
VCCA
VCCA
B10
I/O
I/O
I/O
F1
NC
I/O
I/O
B11
GND
GND
GND
F2
NC
I/O
I/O
B12
I/O
I/O
I/O
F3
NC
I/O
I/O
C1
I/O
I/O
I/O
F4
I/O
I/O
I/O
C2
TDI, I/O
TDI, I/O
TDI, I/O
F9
GND
GND
GND
C3
I/O
I/O
I/O
F10
NC
I/O
I/O
C4
I/O
I/O
I/O
F11
I/O
I/O
I/O
C5
I/O
I/O
I/O
F12
I/O
I/O
I/O
C6
CLKA
CLKA
CLKA
G1
NC
I/O
I/O
C7
I/O
I/O
I/O
G2
TRST, I/O
TRST, I/O
TRST, I/O
C8
I/O
I/O
I/O
G3
I/O
I/O
I/O
C9
I/O
I/O
I/O
G4
GND
GND
GND
C10
NC
I/O
I/O
G9
GND
GND
GND
C11
NC
I/O
I/O
G10
NC
I/O
I/O
Note: *Please read the LP pin descriptions for restrictions on their use.
v4.3
2-9
eX Family FPGAs
128-Pin CSP
128-Pin CSP
Pin Number
eX64
Function
eX128
Function
eX256
Function
Pin Number
eX64
Function
eX128
Function
eX256
Function
G11
I/O
I/O
I/O
K8
I/O
I/O
I/O
G12
NC
I/O
I/O
K9
I/O
I/O
I/O
H1
GND
GND
GND
K10
I/O
I/O
I/O
H2
I/O
I/O
I/O
K11
TDO, I/O
TDO, I/O
TDO, I/O
H3
VCCI
VCCI
VCCI
K12
I/O
I/O
I/O
H4
GND
GND
GND
L1
I/O
I/O
I/O
H9
I/O
I/O
I/O
L2
I/O
I/O
I/O
H10
VCCI
VCCI
VCCI
L3
NC
I/O
I/O
H11
VCCA
VCCA
VCCA
L4
I/O
I/O
I/O
H12
NC
I/O
I/O
L5
I/O
I/O
I/O
J1
NC
NC
VCCA
L6
I/O
I/O
I/O
J2
I/O
I/O
I/O
L7
I/O
I/O
I/O
J3
VCCI
VCCI
VCCI
L8
I/O
I/O
I/O
J4
I/O
I/O
I/O
L9
I/O
I/O
I/O
J5
I/O
I/O
I/O
L10
I/O
I/O
I/O
J6
I/O
I/O
I/O
L11
NC
I/O
I/O
J7
GND
GND
GND
L12
VCCI
VCCI
VCCI
J8
I/O
I/O
I/O
M1
GND
GND
GND
J9
GND
GND
GND
M2
I/O
I/O
I/O
J10
I/O
I/O
I/O
M3
I/O
I/O
I/O
J11
I/O
I/O
I/O
M4
I/O
I/O
I/O
J12
NC
I/O
I/O
M5
I/O
I/O
I/O
K1
NC
I/O
I/O
M6
I/O
I/O
I/O
K2
I/O
I/O
I/O
M7
VCCA
VCCA
VCCA
K3
I/O
I/O
I/O
M8
I/O
I/O
I/O
K4
I/O
I/O
I/O
M9
I/O
I/O
I/O
K5
I/O
I/O
I/O
M10
I/O
I/O
I/O
K6
PRB, I/O
PRB, I/O
PRB, I/O
M11
I/O
I/O
I/O
K7
HCLK
HCLK
HCLK
M12
I/O
I/O
I/O
Note: *Please read the LP pin descriptions for restrictions on their use.
2 -1 0
v4.3
eX Family FPGAs
180-Pin CSP
A1 Ball Pad Corner
1
2
3
4
5
6
7
8
9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Figure 2-5 • 180-Pin CSP
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v4.3
2-11
eX Family FPGAs
180-Pin CSP
180-Pin CSP
180-Pin CSP
180-Pin CSP
Pin
Number
eX256
Function
Pin
Number
eX256
Function
Pin
Number
eX256
Function
Pin
Number
eX256
Function
A1
I/O
C8
CLKB
F1
I/O
J10
I/O
A2
I/O
C9
I/O
F2
I/O
J11
VCCI
A3
GND
C10
I/O
F3
VCCI
J12
VCCA
A4
NC
C11
I/O
F4
I/O
J13
I/O
A5
NC
C12
GND
F5
GND
J14
I/O
A6
NC
C13
I/O
F10
GND
K1
I/O
A7
NC
C14
I/O
F11
I/O
K2
VCCA
A8
NC
D1
I/O
F12*
GND/LP*
K3
I/O
A9
NC
D2
I/O
F13
VCCA
K4
VCCI
A10
NC
D3
TDI, I/O
F14
I/O
K5
I/O
A11
NC
D4
I/O
G1
VCCA
K6
I/O
A12
I/O
D5
I/O
G2
I/O
K7
I/O
A13
I/O
D6
I/O
G3
I/O
K8
GND
A14
I/O
D7
CLKA
G4
I/O
K9
I/O
B1
I/O
D8
I/O
G5
I/O
K10
GND
B2
I/O
D9
I/O
G10
GND
K11
I/O
B3
TCK, I/O
D10
I/O
G11
I/O
K12
I/O
B4
VCCI
D11
I/O
G12
I/O
K13
I/O
B5
I/O
D12
I/O
G13
I/O
K14
I/O
B6
I/O
D13
I/O
G14
VCCA
L1
I/O
B7
VCCA
D14
I/O
H1
I/O
L2
I/O
B8
I/O
E1
I/O
H2
I/O
L3
I/O
B9
I/O
E2
I/O
H3
TRST, I/O
L4
I/O
B10
VCCI
E3
I/O
H4
I/O
L5
I/O
B11
I/O
E4
I/O
H5
GND
L6
I/O
B12
I/O
E5
I/O
H10
GND
L7
PRB, I/O
B13
I/O
E6
I/O
H11
I/O
L8
HCLK
B14
I/O
E7
GND
H12
I/O
L9
I/O
C1
I/O
E8
I/O
H13
I/O
L10
I/O
C2
TMS
E9
GND
H14
I/O
L11
I/O
C3
I/O
E10
I/O
J1
I/O
L12
TDO, I/O
C4
I/O
E11
I/O
J2
GND
L13
I/O
C5
I/O
E12
I/O
J3
I/O
L14
I/O
C6
I/O
E13
VCCI
J4
VCCI
M1
I/O
C7
PRA, I/O
E14
I/O
J5
GND
M2
I/O
Note: *Please read the LP pin descriptions for restrictions on their use.
2 -1 2
v4.3
eX Family FPGAs
180-Pin CSP
180-Pin CSP
Pin
Number
eX256
Function
Pin
Number
eX256
Function
M3
I/O
P10
NC
M4
I/O
P11
NC
M5
I/O
P12
GND
M6
I/O
P13
I/O
M7
I/O
M8
I/O
M9
I/O
M10
I/O
M11
I/O
M12
I/O
M13
VCCI
M14
I/O
N1
I/O
N2
GND
N3
I/O
N4
I/O
N5
I/O
N6
I/O
N7
I/O
N8
VCCA
N9
I/O
N10
I/O
N11
I/O
N12
I/O
N13
I/O
N14
I/O
P1
I/O
P2
I/O
P3
I/O
P4
NC
P5
NC
P6
NC
P7
NC
P8
NC
P9
NC
Note: *Please read the LP pin descriptions for restrictions on their use.
v4.3
2-13
eX Family FPGAs
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version
v4.2
(June 2004)
Changes in current version (v4.3)
Page
The "Ordering Information" was updated with RoHS information. The TQFP measurement ii
was also updated.
The "Dedicated Test Mode" was updated.
1-9
Note 5 was added to the "3.3V LVTTL Electrical Specifications" and "5.0V TTL Electrical 1-15
Specifications" tables
The "LP Low Power Pin" description was updated.
1-26
v4.1
The "eX Timing Model" was updated.
1-18
v4.0
The "Development Tool Support" section was updated.
1-12
The "Package Thermal Characteristics" section was updated.
1-17
The "Product Profile" section was updated.
1-i
v3.0
The "Ordering Information" section was updated.
1-ii
The "Temperature Grade Offerings" section is new.
1-ii
The "Speed Grade and Temperature Grade Matrix" section is new.
1-ii
The "General Description" section was updated.
1-1
The "Clock Resources" section was updated.
1-4
Table 1-1 • Connections of Routed Clock Networks, CLKA and CLKB is new.
1-4
The "User Security" section was updated.
1-5
The "I/O Modules" section was updated.
1-5
The "Hot Swapping" section was updated.
1-6
The "Power Requirements" section was updated.
1-6
The "Low Power Mode" section was updated.
1-6
The "Boundary Scan Testing (BST)" section was updated.
1-9
The "Dedicated Test Mode" section was updated.
1-9
The "Flexible Mode" section was updated.
1-9
Table 1-5 • Boundary-Scan Pin Configurations and Functions is new.
1-9
The "TRST Pin" section was updated.
1-9
The "Probing Capabilities" section is new.
1-10
The "Programming" section was updated.
1-10
The "Probing Capabilities" section was updated.
1-10
The "Silicon Explorer II Probe" section was updated.
1-10
The "Design Considerations" section was updated.
1-11
The "Development Tool Support" section was updated.
1-12
The "Absolute Maximum Ratings*" section was updated.
1-13
The "Temperature and Voltage Derating Factors" section was updated.
1-21
The "TDI, I/O Test Data Input" section was updated.
1-26
v4.3
3-1
eX Family FPGAs
Previous version
Changes in current version (v4.3)
Page
v3.0
The "TDO, I/O Test Data Output" section was updated.
1-26
(continued)
The "TMS Test Mode Select" section was updated.
1-26
The "TRST, I/O Boundary Scan Reset Pin" section was updated.
1-26
All VSV pins were changed to VCCA. The change affected the following pins:
64-Pin TQFP –Pin 36
100-Pin TQFP –Pin 57
49-Pin CSP –Pin D5
128-Pin CSP–Pin H11 and Pin J1 for eX256
180-Pin CSP –Pins J12 and K2
v2.0.1
Advanced v0.4
The "Recommended Operating Conditions" section has been changed.
1-13
The "3.3V LVTTL Electrical Specifications" section has been updated.
1-15
The "5.0V TTL Electrical Specifications" section has been updated.
1-15
The "Total Dynamic Power (mW)" section is new.
1-8
The "System Power at 5%, 10%, and 15% Duty Cycle" section is new.
1-8
The "eX Timing Model" section has been updated.
1-18
The I/O Features table, Table 1-2 on page 1-5, was updated.
1-5
The table, "Standby Power of eX Devices in LP Mode Typical Conditions, VCCA, VCCI = 1-6
2.5V, TJ = 25× C" section, was updated.
"Typical eX Standby Current at 25°C" section is a new table.
1-13
The table in the section, "Package Thermal Characteristics" section has been updated for 1-17
the 49-Pin CSP.
The "eX Timing Model" section has been updated.
1-18
The timing numbers found in, "eX Family Timing Characteristics" section have been 1-22
updated.
The VSV pin has been added to the "Pin Description" section.
1-26
Please see the following pin tables for the VSV pin and an important footnote including the 2-1, 2-3, 2-6, 2-11
pin: "64-Pin TQFP","100-Pin TQFP",, ,"128-Pin CSP", and "180-Pin CSP".
Advanced v0.3
3 -2
The figure, "64-Pin TQFP" section has been updated.
2-1
In the Product Profile, the Maximum User I/Os for eX64 was changed to 84.
1-i
In the Product Profile table, the Maximum User I/Os for eX128 was changed to 100.
1-i
v4.3
eX Family FPGAs
Previous version
Advanced v0.2
Changes in current version (v4.3)
Page
The Mechanical Drawings section has been removed from the data sheet. The mechanical
drawings are now contained in a separate document, “Package Characteristics and
Mechanical Drawings,” available on the Actel web site.
A new section describing "Clock Resources"has been added.
1-4
A new table describing "I/O Features"has been added.
1-5
The "Pin Description"section has been updated and clarified.
1-26
The original Electrical Specifications table was separated into two tables (2.5V and 3.3/ Page 8 and 9
5.0V). In both tables, several different currents are specified for VOH and VOL.
A new table listing 2.5V low power specifications and associated power graphs were added. page 9
Pin functions for eX256 TQ100 have been added to the "100-Pin TQFP"table.
2-3
A CS49 pin drawing and pin assignment table including eX64 and eX128 pin functions have page 26
been added.
A CS128 pin drawing and pin assignment table including eX64, eX128, and eX256 pin pages 26-27
functions have been added.
A CS180 pin drawing and pin assignment table for eX256 pin functions have been added. pages 27, 31
Advanced v.1
The following table note was added to the eX Timing Characteristics table for clarification: pages 14-15
Clock skew improves as the clock network becomes more heavily loaded.
v4.3
3-3
eX Family FPGAs
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet
Supplement." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product
information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family
datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and
for specifications that do not differ between the two families.
Export Administration Regulations (EAR)
The product described in this datasheet is subject to the Export Administration Regulations (EAR). They could require
an approved export license prior to export from the United States. An export includes release of product or disclosure
of technology to a foreign national inside or outside the United States.
3 -4
v4.3
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
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