FINTEK F71889 Super hardware monitor lpc i/o Datasheet

F71889
F71889
Super Hardware Monitor + LPC I/O
Release Date: April, 2010
Version: V0.28P
April, 2010
V0.28P
F71889
F71889 Datasheet Revision History
Version
Date
Page
V0.10P
2007/11/23
-
Preliminary Version.
V0.11P
2008/1/16
-
Modify Pin25/26 description.
V0.12P
2008/1/29
-
Add function description and register description
V0.13P
2008/7/2
-
Add new functions by power on strapping
V0.14P
2008/8/15
-
Add application circuit and VID/GPIO new functions
V0.15P
2008/10/22
-
Modify typo.
V0.16P
2008/11/28
V0.17P
2008/12/3
V0.18P
2009/1/5
6,8
Modify the description of pin99, pin122
118
Update application circuit page 1.
38
Add VREF timing sequence sketch
118
Update application circuit page 1.
6
Rename pin99 AVCC to AVSB
83
Modify the description of Index 27h bit2
92
Remove Index F0h Clock Select Register
118
Update application circuit page 1. (Rename pin99)
-
V0.19P
2009/1/6
Modify KBC device config. register table (Blue Color)
83
Modify ROM address select register bit1-0 description.
85
Modify Wakeup control register bit2-1 description.
91
Modify default value of Index70/72 register.
92
Add “Powered by VSB3V” description on all GPIO register.
13
38, 76
from Version
E)
2009/2/5
Modify typo. (Blue Color) on page 8, 9, 10, 11, 12, 13, 14.
79
5
V0.20P (Start
Revision History
Revise pin configuration. The details can be referred in
P.13
Add IBX SCL/SDA pin description in pin 43, 44. Only
description updated, no function change
Move the description of VREF to P.75 from P.37, and
modify the contents
47
CR01, bit 5,TSI_EN, cleared by LRESET#
48
CR0A, bit 4,SST_EN, cleared by LRESET#
74
Change SPI clock default to 16.7MHz
Create a new bit “7” in Register 0x20 to choose the
81
conversion rate of the temperature from the digital
interface
85
Create a new bit “7” in Register 0x2C to choose GPIO1x
and GPIO2x clear condition
April, 2010
V0.28P
F71889
Create a new bit ”5” in Register 0x2D to set VREF_VSYS
and VREF_VTT status in the S3 state
V0.21P (Start
from Version
Rename:
2009/3/18
3
F)
VREF_VTT to VREF3, VREF_VSYS to VREF2,
VREF_VRAM to VREF1
Revise Pin Configuration
5
Pin 85: VREF_VTT Æ VREF3
Pin 86: VREF_VSYS Æ VREF2
Pin 87: VREF_VDRAM ÆVREF1
Pin-out rename:
Pin 85: VREF_VTT Æ VREF3
Pin 86: VREF_VSYS Æ VREF2
14
Pin 87: VREF_VDRAM ÆVREF1
Add dexcriptions for Pin84~87
Add pin 80 PWROK falling condition description
Modify pin 81 RSMRST# falling condition to VSB3V under
2.95V
16
Revise typo: PWMDUTY Æ FAN60_100
40
Remove Fig. 7-5/7-6
41
42
51
Remove Fig. 7-7/7-8
Revise Fig. 7-5, (original Fig. 7-10)
Revise Fig. 7-6, (original Fig. 7-11)
Rename V1~V6 to VIN1~VIN6
Revise CR20h, 27h, 28h to Reserved
Typo revised and pin-out rename:
The F71889 also supports 4 3 output voltages for VREF,
76
VRAM, VSYS and VTT.VREF1~3. The output is generated
Below is the timing sequence between
VFEF_VRAM/VREF_VSYS/VREF_VTT VREF1~3pins:
Revise VREF1~3 timing chart
79
Revise Section 7.11 SST Fuction description
Register 0xF0: Rename VREF_VTT to VREF3
83
Register 0xF1: Rename VREF_VSYS to VREF2
Register 0xF2: Rename VREF_VRAM to VREF1
Swap CR0x2C bit 6 and 4
88
Create a new bit ”6” in Register 0x2D to set VREF1~3 are
reset or not in the S3/S4/S5 state
April, 2010
V0.28P
F71889
Revise Register0x2D bit5 description: revise the reference
voltage output definition to VREF1~3
Register 0xF0: Rename VREF_VTT to VREF3 in the
relative description
115
Register 0xF1: Rename VREF_VSYS to VREF2 in the
relative description
Register 0xF2: Rename VREF_VRAM to VREF1 in the
relative description
Revise Register 0xF3 bit2~0 description: revise the
116
reference voltage output definition to VREF1~3
Revise Register 0xFF bit0 description: revise the reference
voltage output definition to VREF1~3
0.22P
0.23P
2009/05/04
2009/05/12
121
Revise Application circuit
16
Remove FDC, UART, Parallel port descriptions
51
Revise CR20h, 27h, 28h typo
55-57
Revise VREF timing chart
73
Revise Typo: (8) CTRL + Alt + user define key Space
66
Revise CR2Dh bit 6 description
93
Revise CRF6h bit 3 description
Revise CRF4h bit 5 description
0.24P
2009/5/19
92
10: DUAL_GATE_N tri-state in S5 state.
01: DUAL_GATE_N output low in S5 state.
Made Corrections & Clarification
0.25P
2009/8/3
Update Power Type for Pin 72
Revise Application circuit (Sheet 1)
Made Corrections & Clarification
Update Fan 1~3 Related Setting Index A6~A9, B6~B9, and
C6~C9
0.26P
2009/8/24
BUSIN Register Index 04h
GPIO0 and GPIO1 Pin Status Index F2h and E2h
TSI and SMBus Related Register Index E0h~EDh
Update Application Circuit (Add Intel IBX)
Made Corrections & Clarification
0.27P
2009
Update Electrical Characteristics
GPIO0 Drive Enable Register ⎯ Index F3h, bit 3
0.28P
2010/4/19
Made Corrections & Clarification
April, 2010
V0.28P
F71889
Please note that all data and specifications are subject to change without notice. All the trade marks of products
and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from
such improper use or sales.
April, 2010
V0.28P
F71889
Table of Content
1.
General Description ..................................................................................................................................... 1
2.
Feature List .................................................................................................................................................. 1
3.
Key Specification ......................................................................................................................................... 4
4.
Block Diagram.............................................................................................................................................. 4
5.
Pin Configuration ......................................................................................................................................... 5
6.
Pin Description............................................................................................................................................. 6
6.1
Power Pin ................................................................................................................................................ 6
6.2
LPC Interface........................................................................................................................................... 7
6.3
FDC ......................................................................................................................................................... 7
6.4
UART, SIR and 80-Port ........................................................................................................................... 8
6.5
Parallel Port ........................................................................................................................................... 10
6.6
Hardware Monitor, SPI Interface ........................................................................................................... 12
6.7
ACPI Function Pins ............................................................................................................................... 13
6.8
Bus Interface ......................................................................................................................................... 14
6.9
KBC Function ........................................................................................................................................ 15
7.
Function Description .................................................................................................................................. 16
7.1.
Power on Strapping Option ................................................................................................................... 16
7.2.
Hardware Monitor .................................................................................................................................. 16
7.3.
Keyboard Controller............................................................................................................................... 51
7.4.
SPI Interface.......................................................................................................................................... 54
7.5.
80 Port ................................................................................................................................................... 54
7.6.
ACPI Function ....................................................................................................................................... 54
7.7.
PECI Function ....................................................................................................................................... 58
7.8.
SST Function......................................................................................................................................... 59
7.9.
TSI Function .......................................................................................................................................... 59
7.10. FSB Bus Interface ................................................................................................................................. 59
7.11. VID Controller ........................................................................................................................................ 59
8.
Register Description .................................................................................................................................. 61
8.1
Global Control Registers ....................................................................................................................... 64
8.2
FDC Registers (CR00) .......................................................................................................................... 69
8.3
UART1 Registers (CR01) ...................................................................................................................... 71
8.4
UART 2 Registers (CR02) ..................................................................................................................... 72
8.5
Parallel Port Registers (CR03) .............................................................................................................. 73
8.6
Hardware Monitor Registers (CR04) ..................................................................................................... 73
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8.7
KBC Registers (CR05) .......................................................................................................................... 74
8.8
GPIO Registers (CR06) (All registers of GPIO are powered by VSB3V).............................................. 75
8.9
VID Registers (CR07)............................................................................................................................ 87
8.10 SPI Registers (CR08) ............................................................................................................................ 90
8.11 PME and ACPI Registers (CR0A) ......................................................................................................... 93
8.12 VREF Control Registers (CR0B) ........................................................................................................... 95
9.
Electrical Characteristics ........................................................................................................................... 96
10.
Ordering Information.................................................................................................................................. 99
11.
Package Dimensions ............................................................................................................................... 100
12.
Application Circuit .................................................................................................................................... 101
April, 2010
V0.28P
F71889
1. General Description
The F71889 which is the featured IO chip for new generational PC system is equipped
with one IEEE 1284 parallel port, two UART ports, KBC, Serial Peripheral Interface (SPI),
80-Port, SIR, VID controller and one FDC. The F71889 integrated with hardware monitor, 9
sets of voltage sensor, 3 sets of creative auto-controlling fans and 3 temperature sensor pins
for the accurate dual current type temp. measurement for CPU thermal diode or external
transistors 2N3906.
The F71889 provides flexible features for multi-directional application. For instance,
supports Bus Interface pins, provides 59 GPIO pins (multi-pin), IRQ sharing function also
designed in UART feature for particular usage and accurate current mode H/W monitor will be
worth in measurement of temperature, provides 3 modes fan speed control mechanism
included Manual Mode/Speed Mode/Temperature Mode for users’ selection.
Additionally, integrated SPI interface, 80-Port, and 5VDUAL voltage switch switch and
adjustable voltage reference outputs related functions. The SPI interface is for BIOS usage
including bridge function (Supports up to 16M), and the 80-Port is for engineering and
debuging usage. F71889 also provides 5V dual controller and some voltage reference outputs
for system application. Others, the F71889 supports newest AMD new interface TSI and Intel
PECI 1.1/SST interfaces for temperature reading. These features will help you more and
improve product value. Finally, the F71889 is powered by 3.3V voltage, with the LPC interface
in the package of 128-QFP green package.
2. Feature List
General Functions
¾ Comply with LPC Spec. 1.1
¾ Support DPM (Device Power Management), ACPI
¾ Bus Interface for CPU use
¾ Provides one FDC, two UARTs, KBC and Parallel Port
¾ 16 pins VID controller for VRM 11.x and OTF
¾ Serial VID controller with CORE_TYPE input for AMD Processor
¾ H/W monitor functions
¾ Reference voltage outputs support
¾ 5VDUAL voltage switch
¾ SPI interface for BIOS Bridge
¾ 80-Port interface from LPT or COM2
¾ Support AMD TSI interface and Intel SST/PECI interface
¾ PECI Spec.1.1 ready
-1-
April, 2010
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F71889
¾ Support Ibex protocol SMBus interface
¾ 59 GPIO Pins for flexible application
¾ 24/48 MHz clock input
¾ Packaged in 128-PQFP green package and powered by 3.3VCC
FDC
¾ Compatible with IBM PC AT disk drive systems
¾ Variable write pre-compensation with track selectable capability
¾ Support vertical recording format
¾ DMA enable logic
¾ 16-byte data FIFOs
¾ Support floppy disk drives and tape drives
¾ Detects all overrun and under run conditions
¾ Built-in address mark detection circuit to simplify the read electronics
¾ Completely compatible with industry standard 82077
¾ 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate
UART
¾ Two high-speed 16C550 compatible UART with 16-byte FIFOs
¾ Fully programmable serial-interface characteristics
¾ Baud rate up to 115.2K
¾ Support IRQ sharing
Infrared
¾ Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
Parallel Port
¾ One PS/2 compatible bi-directional parallel port
¾ Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification
¾ Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 specification
¾ Enhanced printer port back-drive current protection
Keyboard Controller
¾ Compatibility with the 8042
¾ Support PS/2 mouse
¾ Support both interrupt and polling modes
¾ Hardware Gate A20 and Hardware Keyboard Reset
-2-
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F71889
Hardware Monitor Functions
¾ 3 dual current type (±3ºC) thermal inputs for CPU thermal diode and 2N3906 transistors
¾ Temperature range -40ºC ~127ºC
¾ 9 sets voltage monitoring (6 external and 3 internal powers)
¾ High limit signal (PME#) for Vcore level
¾ 3 fan speed monitoring inputs
¾ 3 fan speed PWM/DC control outputs(support 3 wire and 4 wire fans)
¾ Issue PME# and OVT# hardware signals output
¾ Case intrusion detection circuit
¾ WATCHDOG# comparison of all monitored values
Serial Peripheral Interface Compatible
¾ Support SPI bridge function for BIOS use
¾ Up to 16M bit Support
80-Port Interface
¾ Monitor 0x80 Port and output the value via signals defined for 7-segment display.
¾ High nibble and low nibble are outputted interleaved at 1KHz frequency.
¾ 80-Port output by LPT or COM2 interface.
8-IN and 8-OUT VID Controller for VRM11.x and OTF
Serial VID Controller with CORE_TYPE Input for AMD CPU application
Integrate AMD TSI interface
Integrate Intel PECI 1.1 /SST interface
Support Ibex Protocol SMBus interface
Support FSB over clocking control bus
5V Dual Voltage Switch
¾ Provide ACPI-compliant 5VDUAL voltage switch
¾ 5VDUAL for USB/Keyboard/Mouse application
Adjustable Voltage Reference Outputs
¾ Enable pin for VREF2 and 3 Voltage Reference Output control
¾ 0.9V default output on VREF1~3 pins
¾ Adjustable voltage range from 0~2.295V
Package
¾ 128-pin PQFP green package
-3-
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V0.28P
F71889
Noted: Patented TW207103 TW207104 TW220442 US6788131 B1 TWI235231 TW237183 TWI263778
3. Key Specification
Supply Voltage
3.0V to 3.6V
Operating Supply Current
10mA typ.
4. Block Diagram
CPU
Chipset
(NB+SB)
Super H/W Monitor +
F71889
IDE
USB
AC’97
I/O
Temperature
KBC
LED (GPIO)
Voltage
IrDA
COM
Fan
Parallel
Floppy
ACPI
IBX Bus
Interface
SPI
80-Port
AMDTSI
PECI
A
SST
5V Dual Controller
VID Controller
-4-
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F71889
5. Pin Configuration
Figure1. F71889 pin configuration
-5-
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6. Pin Description
I/O12t
I/OD12t
I/OOD12t
I/OOD12st,lv
I/OD16st,5v
OD16,u10-5v
I/OD12st,5v
I/OD8,st,lv
I/Os1,D8st,lv
I/OD12st,lv
O8,u47,5v
O12
O30
AOUT
OD12
OD12,5v
OD24
OD14
I/OD14t
INt,5v
INst
INst,5v
INst,lv
AIN
P
6.1
- TTL level bi-directional pin with 12 mA source-sink cap ability.
- TTL level bi-directional pin and schmitt trigger, Open-drain output with 12 mA sink
- TTL level bi-directional pin, can select to OD or OUT by register, with 12 mA
source-sink capability.
- Low level bi-directional pin with schmitt trigger, can select to OD or OUT by register,
with 12 mA source-sink capability.
- TTL level bi-directional pin and schmitt trigger, Open-drain output with 16 mA sink
capability, 5V tolerance.
- Open-drain output pin with 16 mA sink capability, pull-up 10k ohms, 5V tolerance.
- TTL level bi-directional pin and schmitt trigger, Open-drain output with 12 mA sink
capability, 5V tolerance.
- Low level bi-directional pin (VIH Æ 0.9V, VIL Æ 0.6V.) with schmitt trigger. Output
with 8mA drive
- Low level bi-directional pin (VIH Æ 0.9V, VIL Æ 0.6V.) with schmitt trigger. Output
with 8mA drive and 1mA sink capability.
- Low level bi-directional pin with schmitt trigger. Open-drain output with 12mA sink
capability.
- Open-drain pin with 8 mA source-sink capability, pull-up 47k ohms, 5V tolerance.
- Output pin with 12 mA source-sink capability.
- Output pin with 30 mA source-sink capability.
- Output pin(Analog).
- Open-drain output pin with 12 mA sink capability.
- Open-drain output pin with 12 mA sink capability, 5V tolerance.
- Open-drain output pin with 24 mA sink capability.
- Open-drain output pin with 14 mA sink capability.
- TTL level bi-directional pin, Open-drain output with 14 mA sink capability.
- TTL level input pin,5V tolerance.
- TTL level input pin and schmitt trigger.
- TTL level input pin and schmitt trigger, 5V tolerance.
- TTL low level input pin (VIH Æ 0.9V, VIL Æ 0.6V.)
- Input pin(Analog).
- Power.
Power Pin
Pin No.
1,35
Pin Name
VCC
Type
P
99
AVSB
P
65
82
88
20, 50, 70, 117
VSB
VBAT
AGND(D-)
GND
P
P
P
P
-6-
Description
Power supply voltage input with 3.3V
Analog power supply voltage input with 3.3V
stand-by power.
Stand-by power supply voltage input 3.3V
Battery voltage input
Analog GND
Digital GND
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6.2
LPC Interface
Pin No.
Pin Name
Type
PWR
27
LRESET#
INst,5v
VCC
LDRQ#
O12
BSGPIO_TRAP
INt,5v
29
SERIRQ
I/O12t
VCC
30
LFRAME#
INst
VCC
31-34
LAD[0:3]
I/O12t
VCC
36
PCICLK
INst
VCC
37
CLKIN
INst
VCC
Pin Name
Type
PWR
DENSEL#
OD14
GPIO40
I/OD14t
MOA#
OD14
GPIO41
I/OD14t
28
6.3
FDC
Pin No.
7
8
9
10
11
12
13
14
VCC
Description
Reset signal. It can connect to PCIRST# signal on the
host.
Encoded DMA Request signal.
Power on strapping : (Default internal pull high)
1(Default): Pin 51-56 are Bus Interface functions
0
: Pin 51-56 are GPIO pins
Serial IRQ input/Output.
Indicates start of a new cycle or termination of a broken
cycle.
These signal lines communicate address, control, and
data information over the LPC bus between a host and a
peripheral.
33MHz PCI clock input.
System clock input. According to the input frequency
24/48MHz.
DRVA#
OD14
GPIO42
I/OD14t
WDATA#
OD14
GPIO43
I/OD14t
DIR#
OD14
GPIO44
I/OD14t
STEP#
OD14
GPIO45
I/OD14t
HDSEL#
OD14
GPIO46
WGATE#
I/OD14t
OD14
Description
VCC
Drive Density Select.
Set to 1 - High data rate.(500Kbps, 1Mbps)
Set to 0 – Low data rate. (250Kbps, 300Kbps)
General purpose IO. (Select by Register)
Motor A On. When set to 0, this pin enables disk drive 0.
This is an open drain output.
VCC
Drive Select A. When set to 0, this pin enables disk drive
A. This is an open drain output.
VCC
General purpose IO. (Select by Register)
General purpose IO. (Select by Register)
VCC
VCC
VCC
VCC
VCC
Write data. This logic low open drain writes
pre-compensation serial data to the selected FDD. An
open drain output.
General purpose IO. (Select by Register)
Direction of the head step motor. An open drain output.
Logic 1 = outward motion
Logic 0 = inward motion
General purpose IO. (Select by Register)
Step output pulses. This active low open drain output
produces a pulse to move the head to another track.
General purpose IO. (Select by Register)
Head select. This open drain output determines which
disk drive head is active.
Logic 1 = side 0
Logic 0 = side 1
General purpose IO. (Select by Register)
Write enable. An open drain output.
-7-
April, 2010
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F71889
15
16
17
18
19
6.4
GPIO47
RDATA#
GPIO50
I/OD14t
INst,5v
I/OOD12t
TRK0#
INst,5v
GPIO51
I/OOD12t
INDEX#
INst,5v
GPIO52
I/OOD12t
WPT#
INst,5v
GPIO53
I/OOD12t
DSKCHG#
INst,5v
GPIO54
I/OOD12t
VCC
VCC
VCC
VCC
This Schmitt-triggered input from the disk drive is active
low when the head is positioned over the beginning of a
track marked by an index hole.
General purpose IO. (Select by Register)
Write protected. This active low Schmitt input from the
disk drive indicates that the diskette is write-protected.
General purpose IO. (Select by Register)
VCC
Diskette change. This signal is active low at power on
and whenever the diskette is removed.
General purpose IO. (Select by Register)
UART, SIR and 80-Port
Pin No.
Pin Name
Type
PWR
118
DCD1#
INt,5v
VCC
119
RI1#
INt,5v
VCC
120
CTS1#
INt,5v
VCC
DTR1#
O8,u47,5v
121
VCC
FAN60_100
INt,5v
RTS1#
O8,u47,5v
122
123
General purpose IO. (Select by Register)
The read data input signal from the FDD.
General purpose IO. (Select by Register)
Track 0. This Schmitt-triggered input from the disk drive
is active low when the head is positioned over the
outermost track.
General purpose IO. (Select by Register)
VCC
80_TRAP
INt,5v
DSR1#
INt,5v
SOUT1
O8,u47,5v
124
VCC
VCC
Config4E_2E
INt,5v
Description
Data Carrier Detect. An active low signal indicates the
modem or data set has detected a data carrier.
Ring Indicator. An active low signal indicates that a ring
signal is being received from the modem or data set.
Clear To Send is the modem control input.
UART 1 Data Terminal Ready. An active low signal
informs the modem or data set that controller is ready to
communicate. Internal 47k ohms pulled high and disable
after power on strapping.
Power on strapping pin:
1(Default): (Internal pull high)
Power on fan speed default duty is 60%.(PWM)
0: (External pull down)
Power on fan speed default duty is 100%.(PWM)
UART 1 Request To Send. An active low signal informs
the modem or data set that the controller is ready to send
data. Internal 47k ohms pulled high and disable after
power on strapping.
Power on strapping pin:
1(Default) : Default 80-port enable (Internal pull high) 80
port decode output from COM2 interface
0
: Disable 80-port function
Data Set Ready. An active low signal indicates the
modem or data set is ready to establish a communication
link and transfer data to the UART.
UART 1 Serial Output. Used to transmit serial data out
to the communication link. Internal 47k ohms pulled high
and disable after power on strapping.
Power on strapping: (Internal pull high)
1(Default): Configuration register Æ4E
0
: Configuration register Æ2E
-8-
April, 2010
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F71889
125
126
127
128
2
3
SIN1
INt,5v
DCD2#
INt,5v
SEGG
O12
GPIO30
I/OOD12t
RI2#
INt,5v
SEGF
O12
GPIO31
CTS2#
I/OOD12t
INt,5v
SEGA
O12
GPIO32
I/OOD12t
DTR2#
O8,u47,5v
SEGD
O12
GPIO33
I/OOD12t
FWH_TRAP
INt,5v
VCC
VCC
VCC
VCC
VCC
Serial Input. Used to receive serial data through the
communication link.
Data Carrier Detect. An active low signal indicates the
modem or data set has detected a data carrier.
SEGG for 7-segment display. (Select by pin 122 power
on strapping)
General purpose IO. (Select by register)
Ring Indicator. An active low signal indicates that a ring
signal is being received from the modem or data set.
SEGF for 7-segment display. (Select by pin 122 power
on strapping)
General purpose IO. (Select by register)
Clear To Send is the modem control input.
SEGA for 7-segment display. (Select by pin 122 power
on strapping)
General purpose IO. (Select by register)
UART 2 Data Terminal Ready. An active low signal
informs the modem or data set that controller is ready to
communicate. Internal 47k ohms pulled high and disable
after power on strapping.
SEGD for 7-segment display. (Select by pin 122 power
on strapping)
General purpose IO. (Select by register)
Power on strapping :
1(Default): FWH as a primary BIOS
0
: SPI as a primary BIOS
UART 2 Request To Send. An active low signal informs
the modem or data set that the controller is ready to send
data. Internal 47k ohms pulled high and disable after
power on strapping.
SEGC for 7-segment display. (Select by pin 122 power
on strapping)
General purpose IO. (Select by register)
RTS2#
O8,u47,5v
SEGC
O12
GPIO34
I/OOD12t
PWM_DC
INt,5v
DSR2#
INt,5v
L#
O30
GPIO35
I/OOD12t
SOUT2
O8,u47,5v
SEGB
O12
GPIO36
I/OOD12t
SPI_TRAP
INt,5v
1(Default) : SPI function disable
INt,5v
0
: SPI function enable
Serial Input. Used to receive serial data through the
communication link.
VCC
Power on strapping :
VCC
4
5
VCC
1 (Default): Fan control method will be PWM Mode
0 Drive :Fan control method will be Linear Mode
Data Set Ready. An active low signal indicates the
modem or data set is ready to establish a communication
link and transfer data to the UART.
L# for 7-segment display. (Select by pin 122 power on
strapping)
General purpose IO. (Select by register)
UART 2 Serial Output. Used to transmit serial data out
to the communication link. Internal 47k ohms pulled
high and disable after power on strapping.
SEGB for 7-segment display. (Select by pin 122 power
on strapping)
General purpose IO. (Select by register)
Power on strapping: (Internal pull high)
6
SIN2
VCC
-9-
April, 2010
V0.28P
F71889
6.5
O12
GPIO37
I/OOD12t
Pin Name
Type
SLCT
INst,5v
VIDIN0
INst,lv
GPIO60
I/OOD12t
PE
INst,5v
VIDIN1
INst,lv
GPIO61
I/OOD12t
BUSY
INst,5v
VIDIN2
(SVD_IN)
INst,lv
GPIO62
I/OOD12t
ACK#
INst,5v
103
Description
An active high input on this pin indicates that the printer
is selected. Refer to the description of the parallel port
for definition of this pin in ECP and EPP mode.
VCC
CPU VID input pin. (Select by pin 104 power on
strapping) Special Level input VIH Æ 0.9V, VIL Æ 0.6V
General purpose IO. (Select by pin 104 power on
strapping)
An active high input on this pin indicates that the printer
has detected the end of the paper. Refer to the
description of the parallel port for the definition of this pin
in ECP and EPP mode.
CPU VID input pin. (Select by pin 104 power on
strapping) Special Level input VIH Æ 0.9V, VIL Æ 0.6V
General purpose IO. (Select by pin 104 power on
strapping)
An active high input indicates that the printer is not ready
to receive data. Refer to the description of the parallel
port for definition of this pin in ECP and EPP mode.
VCC
VCC
VIDIN3
(SVC_IN)
INst,lv
GPIO63
I/OOD12t
SLIN#
OD12-5v
CoreTP
INst,lv
104
105
PWR
VCC
101
102
SEGE for 7-segment display. (Select by pin 122 power
on strapping)
General purpose IO. (Select by register)
Parallel Port
Pin No.
100
SEGE
VIDIO_TRAP
INt,5v
INIT#
OD12-5v
VIDIN4
INst,lv
VCC
VCC
CPU VID input pin. (Select by pin 104 power on
strapping) Special Level input VIH Æ 0.9V, VIL Æ 0.6V
General purpose IO. (Select by pin 104 power on
strapping)
An active low input on this pin indicates that the printer
has received data and is ready to accept more data.
Refer to the description of the parallel port for the
definition of this pin in ECP and EPP mode.
CPU VID input pin. (Select by pin 104 power on
strapping) Special Level input VIH Æ 0.9V, VIL Æ 0.6V
General purpose IO. (Select by pin 104 power on
strapping)
Output line for detection of printer selection. Refer to the
description of the parallel port for the definition of this pin
in ECP and EPP mode.
Processor Core_Type pin for AMD CPU identification.
Power on strapping :
Pull high 1K : Pin 100-116 as LPT interfaces
Pull high 20K : Pin 100-116 as PVID Controller
Pull down 1K: Pin 102/103/111/112 as SVID Controller
Pull down 47K:Pin 100-103 and pin 105-116 as GPIO pins
Output line for the printer initialization. Refer to the
description of the parallel port for the definition of this pin
in ECP and EPP mode.
CPU VID input pin. (Select by pin 104 power on
strapping) Special Level input VIH Æ 0.9V, VIL Æ 0.6V
-10-
April, 2010
V0.28P
F71889
GPIO64
I/OOD12t
ERR#
INst,5v
VIDIN5
INst,lv
GPIO65
I/OOD12t
AFD#
OD12,5v
H#
O30
VIDIN6
INst,lv
GPIO66
I/OOD12t
VCC
106
107
108
109
110
111
112
STB#
OD12,5v
L#
O30
VIDIN7
INtslv
GPIO67
I/OOD12t
PD0
I/O12st,5v
SEGA
O12
VIDOUT0
OD12
GPIO70
I/OOD12t
PD1
I/O12st,5v
SEGB
O12
VIDOUT1
OD12
GPIO71
I/OOD12t
PD2
SEGC
VIDOUT2
(SVD_OUT)
I/O12st,5v
O12
GPIO72
I/OOD12t
PD3
I/O12st,5v
SEGD
VIDOUT3
(SVC_OUT)
O12
GPIO73
OD12
OD12
I/OOD12t
VCC
VCC
VCC
General purpose IO. (Select by pin 104 power on
strapping)
An active low input on this pin indicates that the printer
has encountered an error condition. Refer to the
description of the parallel port for the definition of this pin
in ECP and EPP mode.
CPU VID input pin. (Select by pin 104 power on
strapping) Special Level input VIH Æ 0.9V, VIL Æ 0.6V
General purpose IO. (Select by pin 104 power on
strapping)
An active low output from this pin causes the printer to
auto feed a line after a line is printed. Refer to the
description of the parallel port for the definition of this pin
in ECP and EPP mode.
H# signal of 80-port for 7-segment display.
CPU VID input pin. (Select by pin 104 power on
strapping) Special Level input VIH Æ 0.9V, VIL ( 0.6V
General purpose IO. (Select by pin 104 power on
strapping)
An active low output is used to latch the parallel data into
the printer. Refer to the description of the parallel port for
the definition of this pin in ECP and EPP mode
L# signal of 80-port for 7-segment display.
CPU VID input pin. (Select by pin 104 power on
strapping) Special Level input VIH ( 0.9V, VIL ( 0.6V
General purpose IO. (Select by pin 104 power on
strapping)
Parallel port data bus bit 0. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP
mode.
SEGA signal of 80-port for 7-segment display.
CPU VID output pin. (Select by pin 104 power on
strapping)
General purpose IO. (Select by pin 104 power on
strapping)
Parallel port data bus bit 1.
SEGB signal of 80-port for 7-segment display.
VCC
VCC
VCC
CPU VID output pin. (Select by pin 104 power
strapping)
General purpose IO. (Select by pin 104 power
strapping)
Parallel port data bus bit 2.
SEGC signal of 80-port for 7-segment display.
CPU VID output pin. (Select by pin 104 power
strapping)
General purpose IO. (Select by pin 104 power
strapping)
Parallel port data bus bit 3.
on
on
on
on
SEGD signal of 80-port for 7-segment display.
CPU VID output pin. (Select by pin 104 power on
strapping)
General purpose IO. (Select by pin 104 power on
strapping)
-11-
April, 2010
V0.28P
F71889
113
114
115
116
6.6
PD4
SEGE
I/O12st,5v
O12
VIDOUT4
OD12
GPIO74
I/OOD12t
PD5
I/O12st,5v
SEGF
O12
VIDOUT5
OD12
GPIO75
I/OOD12t
PD6
SEGG
I/O12st,5v
O12
VIDOUT6
OD12
GPIO76
I/OOD12t
PD7
I/O12st,5v
VIDOUT7
OD12
GPIO77
I/OOD12t
Parallel port data bus bit 4.
SEGE signal of 80-port for 7-segment display.
CPU VID output pin. (Select by pin 104 power on
strapping)
General purpose IO. (Select by pin 104 power on
strapping)
Parallel port data bus bit 5.
VCC
SEGF signal of 80-port for 7-segment display.
CPU VID output pin. (Select by pin 104 power
strapping)
General purpose IO. (Select by pin 104 power
strapping)
Parallel port data bus bit 6.
SEGG signal of 80-port for 7-segment display.
CPU VID output pin. (Select by pin 104 power
strapping)
General purpose IO. (Select by pin 104 power
strapping)
Parallel port data bus bit 7.
CPU VID output pin. (Select by pin 104 power
strapping)
General purpose IO. (Select by pin 104 power
strapping)
VCC
VCC
VCC
on
on
on
on
on
Hardware Monitor, SPI Interface
Pin No.
93-97
98
21
Pin Name
VIN6~VIN2
Vcore(VIN1)
FANIN1
22
FANCTL1
23
FANIN2
24
FANCTL2
25
FANIN3
GPIO10
Type
AIN
AIN
INs t , 5 v
OD12,5v
AOUT
INs t , 5 , 4 v
OD12,5v
AOUT
INs t , 5 v
I/OOD12t
IRRX1
INst
PWR
AVSB
AVSB
VCC
VCC
VCC
VCC
VCC
Description
Voltage Input 2 ~ 6.
Voltage Input for Vcore.
Fan 1 tachometer input.
Fan 1 control output. This pin provides PWM duty-cycle
output or a voltage output.
Fan 2 tachometer input.
Fan 2 control output. This pin provides PWM duty-cycle
output or a voltage output.
Fan 3 speed input.
General purpose IO. (Select by Register)
Infrared Receiver input. (Select by Register)
GPIO11
IRTX1
OD12,5v
AOUT
I/OOD12t
O12
VCC
89
D3+(System)
AIN
AVSB
90
D2+
AIN
AVSB
91
D1+(CPU)
AIN
AVSB
92
VREF
AOUT
AVSB
75
PME#
OD12,5v
VSB
45
GPIO20
I/OOD12t
VCC
FANCTL3
26
on
Fan 3 control output.
General purpose IO. (Select by Register)
Infrared Transmitter Output. (Select by Register)
Thermal diode/transistor temperature sensor input for
system use.
Thermal diode/transistor temperature sensor input.
CPU thermal diode/transistor temperature sensor input.
This pin is for CPU use.
Voltage sensor output.
Generated PME event. It supports the PCI PME#
interface. This signal allows the peripheral to request
the system to wake up from the S3 state.
General purpose IO.
-12-
April, 2010
V0.28P
F71889
46
47
48
49
SPI_SLK
O12
GPIO21
I/OOD12t
SPI_CS0#
O12
GPIO22
I/OOD12t
SPI_MISO
INt , 5 v
GPIO23
I/OOD12t
SPI_MOSI
O12
GPIO24
I/OOD12t
Serial clock output pin for SPI device. (Select by pin 2/5
power on strapping)
General purpose IO.
Connect this pin to primary BIOS chip select pin.
(Select by pin 2/5 power on strapping)
General purpose IO.
VCC
VCC
SPI master in/slave out pin. (Select by pin 2/5 power on
strapping)
General purpose IO.
VCC
SPI master out/slave in pin. (Select by pin 2/5 power on
strapping)
VCC
General purpose IO.
Firmware hub disable (Select by pin 2/5 power on
strapping)
Over temperature signal output.
General purpose IO.
Watch dog timer signal output. (Selecty by register)
FWH_DIS
O12
OVT#
GPIO12
WDTRST#
OD12,5v
I/OOD12t
OD12,5v
41
PECI_REQ#
IRTX
OD12
O12
42
GPIO13
PECI_AVL
IRRX
I/OOD12t
INst,lv
INst
GPIO14
SST
TSI_CLK
I/OOD12t
I/OD8,st,lv
I/OD12st,lv
IBX_CLK
I/OD12st,lv
GPIO15
I/OOD12st,lv
General purpose IO. (Selecty by register)
PECI
I/Os1,D8st,lv
Intel PECI hardware monitor interface. (Default)
TSI_DAT
I/OD12st,lv
61
40
43
44
6.7
IBX_SDA
I/OD12st,lv
GPIO16
I/OOD12st,lv
VSB3V
VCC
VCC
PECI REQUEST signal (Default)
Infrared Transmitter Output. (Selecty by register)
VCC
General purpose IO. (Selecty by register)
PECI AVAILABLE signal (Default)
Infrared Receiver input. (Selecty by register)
General purpose IO. (Selecty by register)
Intel SST hardware monitor interface. (Default)
Clock output for AMD TSI interface. (Select by register)
Clock output for INTEL PCH (IBex Peak) interface.
(Select by register)
VCC
AMD TSI data interface. (Select by register)
VCC
INTEL PCH (IBex Peak) data interface pin. (Select by
register)
General purpose IO. (Selecty by register)
ACPI Function Pins
Pin No.
62
63
64
Pin Name
PCIRST1#
PCIRST2#
PCIRST3#
Type
OD12,5v
O24
O24
PWR
VSB3V
VSB3V
VSB3V
71
VCCGATE
O12
VSB3V
72
DUALGATE
OD12
VSB3V
73
S5#
INst,5v
VSB3V
74
ATXPG_IN
INst,5v
VSB3V
Description
It is an output buffer of LRESET#.
It is an output buffer of LRESET#.
It is an output buffer of LRESET#.
Driver output for 5VCC. Connect this pin to the gate of a
suitable NMOS.
Driver output for 5VSB. Connect this pin to the gate of a
suitable PMOS.
S3# input. This pin companies with S3# to indicate operating
state from S0 to S3 and S4/S5 sleep states.
ATX Power Good input.
-13-
April, 2010
V0.28P
F71889
76
PWSIN#
INst,5v
VSB3V
Main power switch button input.
77
PWSOUT#
OD12,5v
VSB3V
Panel Switch Output. This pin is low active and pulse
output. It is power on request output#.
78
S3#
INst,5v
VSB3V
79
PSON#
OD12,5v
VSB3V
80
PWROK
OD12,5v
VBAT
81
RSMRST#
OD12,5v
VBAT
83
COPEN#
INst,5v
VBAT
84
VREF_EN
INst,5v
AVSB
85
VREF3
AOUT
AVSB
86
VREF2
AOUT
AVSB
87
VREF1
AOUT
AVSB
Pin Name
Type
PWR
BUSIN[0:2]
INst,lv
6.8
Bus Interface
Pin No.
51-53
54-56
57
58
59
60
S3# Input is Main power on-off switch input.
Power supply on-off control output. Connect to ATX
power supply PS_ON# signal.
PWROK function, It is power good signal of VCC, which
is delayed 400ms (default) as VCC arrives at 2.8V. It
falls when S3# gets low.
Resume Reset# function, It is power good signal of
VSB, which is delayed 66ms as VSB arrives at 2.95V.
There is an option to set RSMRST# falls wheb VSB
drops to 2.3V.
Case Open Detection #. This pin is connected to a
specially designed low power CMOS flip-flop back by
the battery for case open state preservation during
power loss.
Reference Voltage DAC output enable pin. Input high to
this pin to enable VREF2 and VREF3. On the contrary,
VREF2 and VREF3 will be disabled when input low to
this pin. The specific timing can be referred in Figure
Deafault 0.9V reference voltage output. The on/off
sequence of this pin can be controlled by S3#, S5#, and
VREF_EN. The specific timing can be referred in Figure
Deafault 0.9V reference voltage output. The on/off
sequence of this pin can be controlled by S3#, S5#, and
VREF_EN. The specific timing can be referred in Figure
Deafault 0.9V reference voltage output. Deafault 0.9V
reference voltage output. The on/off sequence of this
pin can be controlled by S3# and S5#. The specific
timing can be referred in Figure
VCC
GPIO2[5:7]
I/OOD12st,lv
BUSOUT[0:2]
OD12
GPIO0[0:2]
I/OOD12t
SLOTOCC#
GPIO03
GPIO04
LED_VSB
GPIO05
LED_VCC
INst,5v
I/OD12t
I/OOD12t
OD12
I/OOD12t
OD12
GPIO06
BEEP
ALERT#
I/OOD12t
OD12
OD12
VSB3V
VSB3V
VSB3V
VSB3V
VSB3V
Description
BUSIN input pins.
Special level input VIHÆ 0.9, VIL Æ 0.6
General purpose pin. (Select by pin 28 power on
strapping)
BUS OUT output pins.
General purpose pin. (Select by pin 28 power on
strapping)
CPU SLOTOCC# input.
General purpose pin.
General purpose pin.
Power LED for VSB
General purpose pin.
Power LED for VCC
General purpose pin.
Beep pin.
Alert a signal when something issues
-14-
April, 2010
V0.28P
F71889
6.9
KBC Function
Pin No.
Pin Name
Type
PWR
38
KBRST#
OD16,u10,5v
VCC
39
GA20
OD16,u10,5v
VCC
66
KDATA
I/OD16st,5v
VSB3V
Description
Keyboard reset. This pin is high after system reset.
Internal pull high 3.3V with 10k ohms. (KBC P20)
Gate A20 output. This pin is high after system reset.
Internal pull high 3.3V with 10k ohms. (KBC P21)
Keyboard Data.
67
KCLK
I/OD16st,5v
VSB3V
Keyboard Clock.
68
MDAT
I/OD16st,5v
VSB3V
PS2 Mouse Data.
69
MCLK
I/OD16st,5v
VSB3V
PS2 Mouse Clock.
-15-
April, 2010
V0.28P
F71889
7. Function Description
7.1. Power on Strapping Option
The F71889 provides eight pins for power on hardware strapping to select functions. Power on
strapping value follows TTL voltage level. Below table describes how to set the functions you want.
Table1. Power on trap configuration
Pin No.
2
3
5
28
104
121
122
124
Symbol
Value
1
FWH_TRAP
0
1
PWM_DC
0
1
SPI_TRAP
0
1
BSGPIO_TRAP
0
Pull high 1K
Pull
high 20K
VIDIO_TRAP
Pull down 1K
Pull down 47K
1
FAN60_100
0
1
80PORT_TRAP
0
1
Config4E_2E
0
Description
FWH as a primary BIOS (Default)
SPI as a primary BIOS
Fan control mode: PWM mode. ( Default)
Fan control mode: DAC mode.
SPI function disable(Default)
SPI function enable
Pin 51-56 are Bus Interface functions (Default)
Pin 51-56 are GPIO pins
Pin 100-116 as LPT interfaces
Pin 100-116 as PVID Controller
Pin 102/103/111/112 as SVID Controller
Pin 100-103 and pin 105-116 as GPIO pins
Fan full duty is 60%.(Default)
Fan full duty is 100%.
Enable the 80 port function. (Default)
Disable the 80 port function.
Configuration Register I/O port is 4E/4F. (Default)
Configuration Register I/O port is 2E/2F.
7.2. Hardware Monitor
For the 8-bit ADC has the 8mv LSB, the maximum input voltage of the analog pin is 2.04V.
Therefore the voltage under 2.04V (ex:1.5V) can be directly connected to these analog inputs. The
voltage higher than 2.04V should be reduced by a factor with external resistors so as to obtain the input
range. Only 3Vcc is an exception for it is main power of the F71889. Therefore 3Vcc can directly
connect to this chip’s power pin and need no external resistors. There are two functions in this pin with
3.3V. The first function is to supply internal analog power of the F71889 and the second function is that
voltage with 3.3V is connected to internal serial resistors to monitor the +3.3V voltage. The internal
serial resistors are two 150K ohm, so that the internal reduced voltage is half of +3.3V.
There are four voltage inputs in the F71889 and the voltage divided formula is shown as follows:
-16-
April, 2010
V0.28P
F71889
VIN = V+12 V ×
R2
R1 + R 2
where V+12V is the analog input voltage, for example.
If we choose R1=27K, R2=5.1K, the exact input voltage for V+12v will be 1.907V, which is within
the tolerance. As for application circuit, it can be refer to the figure shown as follows.
Voltage Inputs
3Vcc
(directly connect to the chip)
VIN (< 2.04V)
(directly connect to the chip)
VIN (> 2.04V)
R
1
150K
150K
R2
8-bit ADC
with
8 mV LSB
VREF
R
Typical BJT
Connection
2N3906
VIN3.3
10K, 1%
R
Typical Thermister
THM Connection
10K, 25 C
D+
D-
Figure 2. Hardware monitor configuration
SMI# interrupt for voltage is shown as figure. Voltage exceeding or going below high limit will
cause an interrupt if the previous interrupt has been reset by writing “1” all the interrupt Status Register.
Voltage exceeding or going below low limit will result the same condition as voltage exceeding or going
below high limit.
(pulse mode)
(level mode)
*
*
*
*
*
*
*
*
*Interrupt Reset when Interrupt Status Registers are written 1
Voltage SMI# Mode
Figure 3
The F71889 monitors three remote temperature sensors. These sensors can be measured from -40°C to
127°C. More detail please refer to register description.
-17-
April, 2010
V0.28P
F71889
Table 2. Remote-sensor transistor manufacturers
Manufacturer
Model Number
Panasonic
2SB0709 2N3906
Philips
PMBT3906
Monitor Temperature from “thermistor”
The F71889 can connect three thermistors to measure environment temperature or remote
temperature. The specification of thermistor should be considered to (1) value is 3435K (2) resistor
value is 10K ohm at 25°C. In the Figure 7-1, the thermistor is connected by a serial resistor with 10K
ohm, thenand then connected to VREF.
Monitor Temperature from “thermal diode”
Also, if the CPU, GPU or external circuits provide thermal diode for temperature
measurement, the F71889 is capable to these situations. The build-in reference table is for
PNP 2N3906 transistor, and each different kind of thermal diode should be matched with
specific offset and BJT gain. In the Figure 7-1, the transistor is directly connected into
temperature pins.
ADC Noise Filtering
The ADC is integrating type with inherently good noise rejection. Micro-power operation places
constraints on high-frequency noise rejection; therefore, careful PCB board layout and suitable external
filtering are required for high-accuracy remote measurement in electronically noisy environment. High
frequency EMI is best filtered at D+ and D- with an external 2200pF or 3300pF capacitor. Too high
capacitance may introduce errors due to the rise time of the switched current source. Nearly all noise
sources tested cause the ADC measurement to be higher than the actual temperature, depending on
the frequency and amplitude.
Over Temperature Signal (OVT#)
OVT# alert for temperature is shown as figure 7-4. When monitored temperature exceeds the
over-temperature threshold value, OVT# will be asserted until the temperature goes below the hysteresis
temperature.
-18-
April, 2010
V0.28P
F71889
To
T
HYST
OVT#
Figure 4
Temperature PME#
PME# interrupt for temperature is shown as figure 7-5. Temperature exceeding high limit or going
below hysteresis will cause an interrupt if the previous interrupt has been reset by writing “1” all the
interrupt Status Register.
To
T HYST
SMI#
(pulse mode)
*
*
*
(level mode
active low)
*
*Interrupt Reset when Interrupt Status Registers are written 1
Figure 5
Fan speed count
Inputs are provided by the signals from fans equipped with tachometer outputs. The level of these
signals should be set to TTL level, and maximum input voltage cannot be over 5V. If the input signals
from the tachometer outputs are over the 5V, the external trimming circuit should be added to reduce
the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as
follows:
Determine the fan counter according to:
-19-
April, 2010
V0.28P
F71889
Count =
1.5 × 10 6
RPM
In other words, the fan speed counter has been read from register, the fan speed can be
evaluated by the following equation. As for fan, it would be best to use 2 pulses tachometer output per
round.
RPM =
1.5 × 10 6
Count
Fan speed control
The F71889 provides 2 fan speed control methods:
1. DAC FAN CONTROL
2. PWM DUTY CYCLE
DAC Fan Control
The range of DC output is 0~VCC, controlled by 8-bit register. 1 LSB is about 0.013V (VCC=3.3V).
The output DC voltage is amplified by external OP circuit, thus to reach maximum FAN OPERATION
VOLTAGE, 12V. The output voltage will be given as followed:
Output_vol tage (V) = Vcc ×
Programmed 8bit Register Value
256
And the suggested application circuit for linear fan control would be:
+12V
8
R
4.7K
3
2
+
PMOS
Q1
D1
1N4148
1
4
DC OUTPUT VOLTAGE
U1A
R
4.7K
LM358
JP1
R
10K
C
47u
3
2
1
CON3
R
3.6K
R
C
0.1u
27K
FANIN MONITOR
R
10K
Figure 6 DAC fan control application circuit
-20-
April, 2010
V0.28P
F71889
PWM duty Fan Control
The duty cycle of PWM can be programmed by an 8-bit register. The default duty cycle is set to
100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as
follows.
Duty_cycle(%) =
Programmed 8bit Register Value
× 100%
255
+12V
R1
R2
G
PNP Transistor
D
NMOS
S
+
-
C
FAN
Figure 7 +12/5V PWM fan control application circuit
Fan speed control mechanism
There are some modes to control fan speed and they are 1.Manual mode, 2.Stage auto mode, 3.
Linear auto mode. More detail, please refer to the description of registers.
Manual mode
For manual mode, it generally acts as software fan speed control.
Stage auto mode
At this mode, the F71889 provides automatic fan speed control related to temperature variation of
CPU/GPU or the system. The F71889 can provide four temperature boundaries and five intervals, and
each interval has its related fan speed count. All these values should be set by BIOS first.
There are some examples as below:
A. Stage auto mode (PWM Duty)
Set temperature as 60°C, 50°C, 40°C, 30°C and Duty as 100%, 90%, 80%, 70%, 60%
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PWM duty
60 Degree C
50 Degree C
hysteresis 47 Degree C
40 Degree C
30 Degree C
Temp.
Fan Speed
a
b
c
100%
0xFF
90%
0xE5
80%
0xCC
70%
0xB2
60%
0x99
d
Figure 8 Stage mode fan control illustration-2
a. Once temp. is under 30°C, the lowest fan speed keeps 60% PWM duty
b. Once temp. is over 30°C,40°C,50°C, the fan speed will vary from 60% to 90% PWM duty and
increase with temp. level.
c.
Once temp. keeps in 55°C, fan speed keeps in 90% PWM duty
d. If set the hysteresis as 3°C (default 4°C), once temp reduces under 47°C, fan speed reduces to 80%
PWM duty and stays there.
B. Stage auto mode (RPM%)
Set temperature as 60°C, 50°C, 40°C, 30°C and assume the Full Speed is 6000rpm, set 90% of full
speed RPM(5400rpm), 80%(4800rpm), 70%(4200rpm), 60%(3600rpm) of full speed RPM
6000RPM
60 Degree C
90%(5400RPM)
50 Degree C
hysteresis 47 Degree C
80%(4800RPM)
40 Degree C
70%(4200RPM)
30 Degree C
60%(3600RPM)
Temp.
Fan Speed
a
b
c
d
Figure 9 Stage mode fan control illustration-3
a. Once temp. is under 30°C, the lowest fan speed keeps 60% of full speed (3600RPM).
b. Once temp. is over 30°C,40°C,50°C, the fan speed will vary from 3600RPM to 5400RPM and
increase with temp. level.
c. Once temp. keeps in 55°C, fan speed keeps in 90% of full speed (5400RPM)
d. If set the hysteresis as 3°C (default 4°C), once temp reduces under 47°C, fan speed reduces to
4800RPM and stays there.
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Linear auto mode
Otherwise, F71889 supports linear auto mode. Below has two examples to describe this mode. More
detail, please refer the register description.
A. Linear auto mode (PWM Duty I)
Set temperature as 70°C, 60°C, 50°C, 40°C and Duty as 100%, 70%, 60%, 50%, 40%
PWM duty
100%
70 Degree C
hysteresis 65 Degree C
70%
60 Degree C
60%
50 Degree C
50%
40 Degree C
40%
Temp.
Fan Speed
a
b
c
d
Figure 10 Linear mode fan control illustration-1
a. Once temp. is under 40°C, the lowest fan speed keeps 40% PWM duty
b. Once temp. is over 40°C,50°C,60°C, the fan speed will vary from 40% to 70% PWM duty and
linearly increase with temp. variation. The temp.-fan speed monitoring and flash interval is 1sec.
c.
Once temp. goes over 70°C, fan speed will directly increase to 100% PWM duty (full speed)
d. If set the hysteresis as 5°C (default is 4°C), once temp reduces under 65°C (not 70°C), fan speed
reduces from 100% PWM duty and decrease linearly with temp..
B. Linear auto mode (RPM%)
Set temperature as 70°C, 60°C, 50°C, 40°C and if full speed is 6000RPM, setting 100%, 70%, 60%,
50%, 40% of full speed.
6000RPM
70 Degree C
hysteresis 65 Degree C
70%(4200RPM)
60 Degree C
60%(3600
50 Degree C
50%(3000
40 Degree C
Temp.
Fan Speed
40%(2400R
a
b
c
d
Figure 11 Linear mode fan control illustration-2
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a. Once temp. is under 40°C, the lowest fan speed keeps 40% of full speed (2400RPM)
b. Once temp. is over 40°C,50°C,60°C, the fan speed will vary from 40% to 70% of full speed and
almost linearly increase with temp. variation.
The temp.-fan speed monitoring and flash interval
is 1sec.
c.
Once temp. goes over 70°C, fan speed will directly increase to full speed 6000RPM.
d. If set the hysteresis as 5°C, once temp reduces under 65°C (not 70°C), fan speed reduces from
full speed and decrease linearly with temp..
PWMOUT Duty-cycle operating process
In both “Manual RPM” and “Temperature RPM” modes, the F71889 adjust PWMOUT duty-cycle
according to current fan count and expected fan count. It will operate as follows:
(1). When expected count is 0xFFF, PWMOUT duty-cycle will be set to 0x00 to turn off
fan.
(2). When expected count is 0x000, PWMOUT duty-cycle will be set to 0xFF to turn on fan with
full speed.
(3). If both (1) and (2) are not true,
(4). When PWMOUT duty-cycle decrease to MIN_DUTY(≠ 00h), obviously the duty-cycle will
decrease to 00h next, the F71889 will keep duty-cycle at 00h for 1.6 seconds. After that, the
F71889 starts to compare current fan count and expected count in order to increase or
decrease its duty-cycle. This ensures that if there is any glitch during the period, the
F71889 will ignore it.
Start Duty
Stop Duty
Figure 12
FAN_FAULT#
Fan_Fault# will be asserted when the fan speed doesn’t meet the expected fan speed within a
programmable period (default is 11 seconds) or when fan stops with respect to PWM duty-cycle which
should be able to turn on the fan. There are two conditions may cause the FAN_FAULT# event.
(1). When PWM_Duty reaches 0xFF, the fan speed count can’t reach the fan expected count in
time. (Figure 7-13)
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11 sec(default)
Current Fan Count
Expected Fan Count
100%
Duty-cycle
Fan_Fault#
Figure 13 FAN_FAULT# event
(2). After the period of detecting fan full speed, when PWM_Duty > Min. Duty, and fan count still in
0xFFF.
T1 Architecture
The F71889 implement the Intel PECI/SST interface and AMD TSI interface to collect the CPU
temperature for fan control. The CPU temperature source could be programmed to be from external
diode, Intel PECI interface or AMD TSI interface.
Device registers, the following is a register map order which shows a summary of all registers. Please refer
each one register if you want more detail information.
Register CR01 ~ CR03 Æ Configuration Registers
Register CR0A ~ CR0F Æ PECI/SST/TSI Control Register
Register CR10 ~ CR4F Æ Voltage Setting Register
Register CR60 ~ CR8E Æ Temperature Setting Register
Register CR90 ~ CRDF Æ Fan Control Setting Register
ÆFan1 Detail Setting CRA0 ~ CRAF
ÆFan2 Detail Setting CRB0 ~ CRBF
ÆFan3 Detail Setting CRC0 ~ CRCF
Register CR5A ~ CR5D Æ HW Chip ID and Vender ID Register
7.5.1
Configuration Register ⎯ Index 01h
Bit
Name
R/W Default
Description
7
BETA_EN
R/W
1
0: disable the T1 beta compensation.
1: enable the T1 beta compensation.
6
INTEL_MODEL
R/W
1
0: AMD model.
1: Intel model.
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0: Disable the TSI function via PECI/SST pins.
1: Enable the TSI function via PECI/SST pins.
This bit accompanying with INTEL_MODEL and SST_EN will determine the
availability of AMD TSI, Intel PCH SMBus, PECI and SST.
Setting
INTEL_
TSI_EN
SST_EN
(CR01,
(CR0A,
bit5)
bit4)
0
0
0
MODEL
5
TSI_EN
R/W
Intel PCH
PECI
SST
AMD TSI
X
N
N
N
N
1
X
N
N
Y
N
1
0
0
Y
N
N
N
1
0
1
Y
Y
N
N
1
1
X
N
N
N
Y
(CR01,
0
Results
bit6)
SMBus
This bit is cleared by LRESET#.
4-3
Reserved
-
-
Reserved
2
POWER_DOWN
R/W
0
Hardware monitor function power down.
1
FAN_START
R/W
1
Set one to enable startup of fan monitoring operations; a zero puts the part in
standby mode.
0
V_T_START
R/W
1
Set one to enable startup of temperature and voltage monitoring operations;
a zero puts the part in standby mode.
7.5.2 Configuration Register ⎯ Index 02h
Bit
Name
7
Reserved
R/W
0
6
CASE_BEEP_EN
R/W
0
R/W
0
5-4
OVT_MODE
R/W Default
3
Reserved
R/W
0
2
CASE_SMI_EN
R/W
0
1-0
ALERT_MODE
R/W
0
Description
Dummy register.
0: Disable case open event output via BEEP.
1: Enable case open event output via BEEP.
00: The OVT# will be low active level mode.
01: The OVT# will be high active level mode.
10: The OVT# will indicate by 1Hz LED function.
11: The OVT# will indicate by (400/800HZ) BEEP output.
Dummy register.
0: Disable case open event output via PME.
1: Enable case open event output via PME.
00: The ALERT# will be low active level mode.
01: The ALERT# will be high active level mode.
10: The ALERT# will indicate by 1Hz LED function.
11: The ALERT# will indicate by (400/800HZ) BEEP output.
7.5.3 Case Status Register ⎯ Index 03h
Bit
Name
R/W Default
Description
7-1
Reserved
R/W
0
Return 0 when read.
0
CASE_STS
R/W
0
Case open event status, write 1 to clear if case open event cleared.
7.5.4 Debut Port Temp Register ⎯ Index 04h
Bit
7-2
Name
Reserved
R/W Default
R/W
0
Description
Return 0 when read.
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1-0
DPORT_TEMP_SEL R/W
01
Debug port temperature source select:
00: 0xff.
01: T1 reading.
10: T2 reading.
11: T3 reading.
7.5.5 SST and VTT_SEL Register ⎯ Index 0Ah
Bit
Name
R/W Default
7-5
Reserved
-
0
4
SST_EN_REG
R/W
0
3-2
VTT_SEL
R/W
0
1
DIG_T1_EN
R/W
0
0
DIODE_T1_EN
R/W
1
Description
Reserved.
Set this bit “1” and select Intel model will enable SST interface.
Otherwise will disable SST interface
This bit is cleared by LRESET#.
PECI (Vtt) voltage select.
00: Vtt is 1.23V
01: Vtt is 1.13V
10: Vtt is 1.00V
11: Vtt is 1.00V
0: Disable the digital interface of T1 (PECI/TSI).
1: Enable the digital interface of T1.
0: Disable the D1+ measurement.
1: Enable the D1+ measurement.
7.5.6 PECI Address Register ⎯ Index 0Bh
Bit
Name
R/W Default
7-4
CPU_SEL
R/W
0
3-1
Reserved
-
0
0
DOMAIN1_EN
R/W
0
Description
Select the Intel CPU socket number.
0000: no CPU presented. PECI host will use Ping() command to find CPU
address.
0001: CPU is in socket 0, i.e. PECI address is 0x30.
0010: CPU is in socket 0, i.e. PECI address is 0x31.
0100: CPU is in socket 0, i.e. PECI address is 0x32.
1000: CPU is in socket 0, i.e. PECI address is 0x33.
Otherwise are reserved.
Reserved.
If the CPU selected is dual core. Set this register 1 to read the temperature
of domain1.
7.5.7 TCC TEMP Register ⎯ Index 0Ch
Bit
7-0
Name
R/W Default
TCC_TEMP/TSI_OFF
R/W
SET
Description
TCC Activation Temperature/TSI Offset.
When PECI is enabled, the absolute value of CPU temperature is calculated
by the equation:
8’h55 CPU_TEMP = TCC_TEMP + PECI Reading.
The range of this register is -128 ~ 127.
When AMD TSI or Intel PCH SMBus is enabled, this byte is used as the
offset to be added to the reading.
7.5.8 SST ADDR Register ⎯ Index 0Dh
Bit
Name
7-0
SST_ADDR/
SMBUS_ADDR
R/W Default
R/W
Description
When AMD TSI or Intel PCH SMBus is enabled, this byte is used as
SMBUS_ADDR. SMBUS_ADDR[7:1] is the slave address sent by the
8’h4C
embedded master to fetch the temperature.
Otherwise, this byte is used as SST_ADDR if SST is enabled.
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7.5.9 Voltage DIV Register ⎯ Index 0Eh
Bit
Name
R/W Default
7-6
VIN4_DIV
R/W
0
5-4
VIN3_DIV
R/W
0
3-2
VIN2_DIV
R/W
0
1-0
VIN1_DIV
R/W
0
Description
The value indicates the divisor of the voltage source.
00: voltage source is directly connected to VIN4.
01: voltage source is divided by 2 and connect to VIN4.
10: voltage source is divided by 4 and connect to VIN4.
11: voltage source is divided by 16 and connect to VIN4.
The value indicates the divisor of the voltage source.
00: voltage source is directly connected to VIN3.
01: voltage source is divided by 2 and connect to VIN3.
10: voltage source is divided by 4 and connect to VIN3.
11: voltage source is divided by 16 and connect to VIN3.
The value indicates the divisor of the voltage source.
00: voltage source is directly connected to VIN2.
01: voltage source is divided by 2 and connect to VIN2.
10: voltage source is divided by 4 and connect to VIN2.
11: voltage source is divided by 16 and connect to VIN2.
The value indicates the divisor of the voltage source.
00: voltage source is directly connected to VIN1.
01: voltage source is divided by 2 and connect to VIN1.
10: voltage source is divided by 4 and connect to VIN1.
11: voltage source is divided by 16 and connect to VIN1.
Above is available only if SST is enabled. Otherwise, bit 7-1 will be used as
I2C_ADDR if Intel PCH SMBus is enabled.
7.5.10 PECI Config. and Voltage Register ⎯ Index 0Fh
Bit
Name
R/W Default
7
PECI_ERR
R
-
6
PECI_NOT_AVL
R
-
5
PECI_REQ_EN
R/W
1
4
PECI_AVL_EN
R/W
1
3-2
VIN6_DIV
R/W
0
Description
0: no PECI error occurred.
1: PECI error occurred..
The condition of PECI_ERR is the PECI return all 0’s if PECI_AVL asserts at
start of PECI message and during PECI message for continuous three
times.
0: PECI is available.
1: PECI is not available.
The condition of PECI_ERR is the PECI return all 0’s if PECI_AVL asserts at
start of PECI message and de-asserts during PECI message for continuous
three times.
0: disable the PECI_REQ# function.
1: Enable the PECI_REQ# function.
0: disable the PECI_AVL function.
1: Enable the PECI_AVL function.
The value indicates the divisor of the voltage source.
00: voltage source is directly connected to VIN6.
01: voltage source is divided by 2 and connect to VIN6.
10: voltage source is divided by 4 and connect to VIN6.
11: voltage source is divided by 16 and connect to VIN6.
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The value indicates the divisor of the voltage source.
00: voltage source is directly connected to VIN5.
01: voltage source is divided by 2 and connect to VIN5.
10: voltage source is divided by 4 and connect to VIN5.
11: voltage source is divided by 16 and connect to VIN5.
VIN6_DIV[0] and VIN5_DIV are used as TSI_TEMP_SEL[2:0] if Intel PCH SMBus is
enabled. TSI_TEMP_SEL is used to select the temperature source for fan control.
1-0
VIN5_DIV
R/W
TSI_TEMP_SEL
0
000
Temperature Source
Maximum of MCH or
001
CPU
PCH
010
CPU
011
MCH
100
DIMM0
101
DIMM1
110
DIMM2
111
DIMM3
Voltage Setting
7.5.11 Voltage1 PME# Enable Register ⎯ Index 10h
Bit
Name
7-2
Reserved
EN_V1_PME
1
Reserved
0
R/W Default
Description
--
0
Reserved
R/W
0
--
0
A one enables the corresponding interrupt status bit for PME# interrupt.
Set this bit 1 to enable PME# function for VIN1.
Reserved
7.5.12 Voltage1 Interrupt Status Register ⎯ Index 11h
Bit
Name
R/W Default
Description
7-2
Reserved
--
0
Reserved
1
V1_ EXC _STS
R/W
0
0
Reserved
--
0
This bit is set when the VIN1 is over the high limit. Write 1 to clear this bit,
write 0 will be ignored.
Reserved
7.5.13 Voltage1 Exceeds Real Time Status Register 1 ⎯ Index 12h
Bit
Name
R/W Default
Description
7-2
Reserved
--
0
Reserved
1
V1_EXC
RO
0
A one indicates VIN1 exceeds the high or low limit. A zero indicates VIN1 is
in the safe region.
0
Reserved
--
0
Reserved
7.5.14 Voltage1 BEEP Enable Register ⎯ Index 13h
Bit
Name
R/W Default
Description
7-2
Reserved
--
0
Reserved
1
EN_V1_BEEP
R/W
0
0
Reserved
--
0
A one enables the corresponding interrupt status bit for BEEP output of
VIN1.
Reserved
7.5.15 Voltage reading and limit⎯ Index 20h- 4Fh
Address
20h
Attribute
RO
Default
Value
--
Description
VCC3V reading. The unit of reading is 8mV.
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21h
22h
23h
24h
25h
26h
27h
28h
29~2Fh
30~31h
32h
33~4Fh
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
RO
--------FF
FF
FF
FF
VIN1 (Vcore) reading. The unit of reading is 8mV.
VIN2 reading. The unit of reading is 8mV.
VIN3 reading. The unit of reading is 8mV.
VIN4 reading. The unit of reading is 8mV.
VIN5 reading. The unit of reading is 8mV.
VIN6 reading. The unit of reading is 8mV.
VSB3V reading. The unit of reading is 8mV.
VBAT reading. The unit of reading is 8mV.
Reserved
Reserved
V1 High Limit setting register. The unit is 8mV.
Reserved
Temperature Setting
7.5.16 Temperature PME# Enable Register ⎯ Index 60h
Bit
Name
R/W Default
7
EN_ T3_OVT_PME
R/W
0
6
EN_ T2_ OVT_PME
R/W
0
5
EN_ T1_ OVT_PME
R/W
0
4
Reserved
R/W
0
3
EN_ T3_EXC_PME
R/W
0
2
EN_ T2_EXC_PME
R/W
0
1
EN_ T1_EXC_PME
R/W
0
0
Reserved
R/W
0
Description
If set this bit to 1, PME# signal will be issued when TEMP3 exceeds OVT
limit setting.
If set this bit to 1, PME# signal will be issued when TEMP2 exceeds OVT
setting.
If set this bit to 1, PME# signal will be issued when TEMP1 exceeds OVT
setting.
Reserved
If set this bit to 1, PME# signal will be issued when TEMP3 exceeds high
limit setting.
If set this bit to 1, PME# signal will be issued when TEMP2 exceeds high
limit setting.
If set this bit to 1, PME# signal will be issued when TEMP1 exceeds high
limit setting.
Reserved
7.5.17 Temperature Interrupt Status Register ⎯ Index 61h
Bit
Name
R/W Default
7
T3_OVT_STS
R/W
0
6
T2_OVT _STS
R/W
0
5
T1_OVT _STS
R/W
0
4
Reserved
R/W
0
3
T3_EXC _STS
R/W
0
2
T2_EXC _STS
R/W
0
Description
A one indicates TEMP3 temperature sensor
below the “OVT limit –hysteresis”. Write 1 to
ignored.
A one indicates TEMP2 temperature sensor
below the “OVT limit –hysteresis”. Write 1 to
ignored.
A one indicates TEMP1 temperature sensor
below the “OVT limit –hysteresis”. Write 1 to
ignored.
Reserved
has exceeded OVT limit or
clear this bit, write 0 will be
has exceeded OVT limit or
clear this bit, write 0 will be
has exceeded OVT limit or
clear this bit, write 0 will be
A one indicates TEMP3 temperature sensor has exceeded high limit or
below the “high limit –hysteresis”. Write 1 to clear this bit, write 0 will be
ignored.
A one indicates TEMP2 temperature sensor has exceeded high limit or
below the “high limit –hysteresis” limit. Write 1 to clear this bit, write 0 will
be ignored.
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T1_EXC _STS
R/W
0
0
Reserved
R/W
0
A one indicates TEMP1 temperature sensor has exceeded high limit or
below the “high limit –hysteresis” limit. Write 1 to clear this bit, write 0 will
be ignored.
Reserved
7.5.18 Temperature Real Time Status Register ⎯ Index 62h
Bit
Name
R/W Default
7
T3_OVT
R/W
0
6
T2_OVT
R/W
0
5
T1_OVT
R/W
0
4
Reserved
R/W
0
3
T3_EXC
R/W
0
2
T2_EXC
R/W
0
1
T1_EXC
R/W
0
0
Reserved
R/W
0
Description
Set when the TEMP3 exceeds the OVT limit. Clear when the TEMP3 is
below the “OVT limit –hysteresis” temperature.
Set when the TEMP2 exceeds the OVT limit. Clear when the TEMP2 is
below the “OVT limit –hysteresis” temperature.
Set when the TEMP1 exceeds the OVT limit. Clear when the TEMP1 is
below the “OVT limit –hysteresis” temperature.
Reserved
Set when the TEMP3 exceeds the high limit. Clear when the TEMP3 is
below the “high limit –hysteresis” temperature.
Set when the TEMP2 exceeds the high limit. Clear when the TEMP2 is
below the “high limit –hysteresis” temperature.
Set when the TEMP1 exceeds the high limit. Clear when the TEMP1 is
below the “high limit –hysteresis” temperature.
Reserved
7.5.19 Temperature BEEP Enable Register ⎯ Index 63h
Bit
Name
R/W Default
7
EN_ T3_OVT_BEEP R/W
0
6
EN_ T2_ OVT_BEEP R/W
0
5
EN_ T1_ OVT_BEEP R/W
0
4
R/W
0
3
EN_ T3_EXC_BEEP R/W
0
2
EN_ T2_EXC_BEEP R/W
0
1
EN_ T1_EXC_BEEP R/W
0
0
Reserved
Reserved
R/W
0
Description
If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds OVT
limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds OVT
limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds OVT
limit setting.
Reserved
If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds high
limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds high
limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds high
limit setting.
Reserved
7.5.20 OVT Output Enable Register 1 ⎯ Index 66h
Bit
Name
R/W Default
Description
7
EN_T3_ALERT
R
0
6
EN_T2_ALERT
R
0
5
EN_T1_ALERT
R
0
4
Reserved
R
0
Enable temperature 3 alert event (asserted when temperature over high
limit)
Enable temperature 2 alert event (asserted when temperature over high
limit)
Enable temperature 1 alert event (asserted when temperature over high
limit)
Reserved.
3
EN_T3_OVT
R/W
0
Enable over temperature (OVT) mechanism of temperature3.
2
EN_T2_OVT
R/W
0
Enable over temperature (OVT) mechanism of temperature2.
1
EN_T1_OVT
R/W
1
Enable over temperature (OVT) mechanism of temperature1.
0
Reserved
R
0h
Reserved.
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7.5.21 Temperature Sensor Type Register ⎯ Index 6Bh
Bit
Name
R/W Default
7-4
Reserved
RO
0
3
T3_MODE
R/W
1
2
T2_MODE
R/W
1
1
T1_MODE
R/W
1
0
Reserved
R
0h
Description
-0: TEMP3 is connected to a thermistor
1: TEMP3 is connected to a BJT.(default)
0: TEMP2 is connected to a thermistor.
1: TEMP2 is connected to a BJT. (default)
0: TEMP1 is connected to a thermistor
1: TEMP1 is connected to a BJT.(default)
--
7.5.22 TEMP1 Limit Hystersis Select Register -- Index 6Ch
Bit
Name
R/W Default
7-4
TEMP1_HYS
R/W
4h
3-0
Reserved
R
0h
Description
Limit hysteresis. (0~15ºC)
Temperature and below the (boundary – hysteresis).
--
7.5.23 TEMP2 and TEMP3 Limit Hystersis Select Register -- Index 6Dh
Bit
Name
R/W Default
Description
º
7-4
TEMP3_HYS
R/W
2h
3-0
TEMP2_HYS
R/W
4h
Limit hysteresis. (0~15 C)
Temperature and below the (boundary – hysteresis).
Limit hysteresis. (0~15ºC)
Temperature and below the (boundary – hysteresis).
7.5.24 DIODE OPEN Status Register -- Index 6Fh
Bit
Name
R/W Default
Description
7-4
Reserved
RO
0h
Reserved
3
T3_DIODE_OPEN
RO
0h
External diode 3 is open
2
T2_DIODE_OPEN
RO
0h
External diode 2 is open
1
T1_DIODE_OPEN
RO
0h
This register indicates the abnormality of temperature 1 measurement.
When TSI interface is enabled, it indicates the error of not receiving NACK
bit or a timeout occurred.
When PECI interface is enabled, it indicates an error code (0x0080 or
0x0081) is received from PECI slave.
When external diode is used, it indicates the BJT is open or short.
0
Reserved
R
0h
--
Temperature ⎯ Index 70h- 8Fh
Address
Attribute
Default
Value
70h
Reserved
FFh
Reserved
71h
Reserved
FFh
Reserved
72h
RO
--
Temperature 1 reading. The unit of reading is 1ºC.At the moment of reading this
register.
73h
RO
--
Reserved
74h
RO
--
Temperature 2 reading. The unit of reading is 1ºC.At the moment of reading this
register.
75h
RO
--
Reserved
Description
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April, 2010
V0.28P
F71889
76h
RO
--
Temperature 3 reading. The unit of reading is 1ºC.At the moment of reading this
register.
77-79h
RO
--
Reserved
7Ah
RO
--
7Bh
RO
--
7Ch
RO
--
The raw data of T1 read from digital interface.
7Dh
RO
--
The raw data of T1 read from D1+.
7Eh
R/W
00h-
T1 Slope Adjust.
7Fh
R/W
00h
T1 Source Select.
80h
Reserved
FFh
Reserved
81h
Reserved
FFh
Reserved
82h
R/W
64h
Temperature sensor 1 OVT limit. The unit is 1ºC.
83h
R/W
55h
Temperature sensor 1 high limit. The unit is 1ºC.
84h
R/W
64h
Temperature sensor 2 OVT limit. The unit is 1ºC.
85h
R/W
55h
Temperature sensor 2 high limit. The unit is 1ºC.
86h
R/W
55h
Temperature sensor 3 OVT limit. The unit is 1ºC.
87h
R/W
46h
Temperature sensor 3 high limit. The unit is 1ºC.
88-8Bh
RO
--
Reserved
8C~8Dh
RO
FFH
Reserved
The raw data of T3 read from digital interface. (Only available if Intel IBX interface
is enabled)
The raw data of T2 read from digital interface. (Only available if Intel IBX interface
is enabled)
7.5.25 T1 Slope Adjust Register -- Index 7Eh
Bit
7
Name
DIG_T1_ADD
R/W Default
R/W
0h
Description
This bit is the sign bit for digital T1 reading slope adjustment.
See DIG_T1_SCALE below for detail.
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April, 2010
V0.28P
F71889
6-4
DIG_T1_SCALE
R/W
0h
3
DIODE_T1_ADD
R/W
0h
DIODE_T1_SCALE
R/W
0h
2-0
Accompanying with DIG_T1_ADD, the slope adjustment of digital T1 is
listed.
DIG_T1_ADD
DIG_T1_SCALE
Slope
0
000
No adjustment
0
001
1/2
0
010
3/4
0
011
7/8
0
100
15/16
0
101
31/32
0
110
63/64
0
111
127/128
1
000
No adjustment
1
001
3/2
1
010
5/4
1
011
9/8
1
100
17/16
1
101
33/32
1
110
65/64
1
111
129/128
The function of this bit is the same as DIG_T1_ADD expect that it is for D1+
reading.
The function of this bit is the same as DIG_T1_SCALE expect that it is for
D1+ reading.
7.5.26 Temperature Filter Select Register -- Index 7Fh
Bit
7-2
1-0
Name
Reserved
T1_SRC_SEL_REG
R/W Default
-
R/W
-
00
Description
Reserved.
The bits are used when DIODE_T1_EN and DIG_T1_EN are both enabled.
The real select bits T1_SCR_SEL are fixed to 2’b01 if DIODE_T1_EN is “0”
and 2’b00 if DIG_T1_EN is “0”. The T1 source is listed.
T1_SRC_SEL
T1 source
00
From D1+ only
01
From Digital reading (PECI/TSI)
10
Average
11
Maximum
7.5.27 Temperature Filter Select Register -- Index 8Eh
Bit
Name
R/W Default
7-6
IIR-QUEUR3
R/W
0h
5-4
IIR-QUEUR2
R/W
0h
3-2
IIR-QUEUR1
R/W
0h
0
Reserved
R
0h
Description
The queue time for second filter to quickly update values.
00: 8 times.
01: 12 times.
10: 16 times. (default)
11: 24 times.
The queue time for second filter to quickly update values.
00: 8 times.
01: 12 times.
10: 16 times. (default)
11: 24 times.
The queue time for second filter to quickly update values.
00: 8 timers.
01: 12 times.
10: 16 times. (default)
11: 24 times.
--
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April, 2010
V0.28P
F71889
Fan Control Setting
7.5.28 FAN PME# Enable Register ⎯ Index 90h
Bit
Name
7-3
Reserved
2
R/W Default
RO
0h
EN_FAN3_PME
R/W
0h
1
EN_FAN2_PME
R/W
0h
0
EN_FAN1_PME
R/W
0h
Description
Reserved
A one enables the corresponding interrupt status bit for PME# interrupt.
Set this bit 1 to enable PME# function for Fan3.
A one enables the corresponding interrupt status bit for PME# interrupt.
Set this bit 1 to enable PME# function for Fan2.
A one enables the corresponding interrupt status bit for PME# interrupt.
Set this bit 1 to enable PME# function for Fan1.
7.5.29 FAN Interrupt Status Register ⎯ Index 91h
Bit
Name
R/W Default
7-3
Reserved
2
FAN3_STS
R/W
--
1
FAN2_STS
R/W
--
0
FAN1_STS
R/W
--
RO
0
Description
Reserved
This bit is set when the fan3 count exceeds the count limit. Write 1 to clear
this bit, write 0 will be ignored.
This bit is set when the fan2 count exceeds the count limit. Write 1 to clear
this bit, write 0 will be ignored.
This bit is set when the fan1 count exceeds the count limit. Write 1 to clear
this bit, write 0 will be ignored.
7.5.30 FAN Real Time Status Register ⎯ Index 92h
Bit
Name
R/W Default
7-3
Reserved
--
0
2
FAN3_EXC
RO
--
1
FAN2_EXC
RO
--
0
FAN1_EXC
RO
--
Description
Reserved
This bit set to high mean that fan3 count can’t meet expect count over than
SMI time(CR9F) or when duty not zero but fan stop over then 3 sec.
This bit set to high mean that fan2 count can’t meet expect count over than
SMI time(CR9F) or when duty not zero but fan stop over then 3 sec.
This bit set to high mean that fan1 count can’t meet expect count over than
SMI time(CR9F) or when duty not zero but fan stop over then 3 sec.
7.5.31 FAN BEEP# Enable Register ⎯ Index 93h
Bit
Name
R/W Default
Description
7
FULL_WITH_T3_EN R/W
0
Set one will enable FAN to force full speed when T3 over high limit.
6
FULL_WITH_T2_EN R/W
0
Set one will enable FAN to force full speed when T2 over high limit.
5
FULL_WITH_T1_EN R/W
0
Set one will enable FAN to force full speed when T1 over high limit.
4
Reserved
R/W
0
Reserved for local temperature.
3
Reserved
-
-
Reserved.
2
EN_FAN3_ BEEP
R/W
0
A one enables the corresponding interrupt status bit for BEEP.
1
EN_FAN2_ BEEP
R/W
0
A one enables the corresponding interrupt status bit for BEEP.
0
EN_FAN1_ BEEP
R/W
0
A one enables the corresponding interrupt status bit for BEEP.
7.5.32 Fan Type Select Register -- Index 94h
Bit
Name
7-6
Reserved
R/W Default
-
-
Description
Reserved.
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April, 2010
V0.28P
F71889
5-4
FAN3_TYPE
R/W
3-2
FAN2_TYPE
R/W
1-0
FAN1_TYPE
R/W
00: Output PWM mode (pushpull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s power
terminal.
10: Output PWM mode (open drain) to control Intel 4-wire fans.
2’b 0S
11: Reserved.
Bit 0 is power on trap by RTS2#
0: RTS2# is pull up by internal 47K resistor.
1: RTS2# is pull down by external resistor.
00: Output PWM mode (pushpull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s power
terminal.
10: Output PWM mode (open drain) to control Intel 4-wire fans.
2’b 0S
11: Reserved.
Bit 0 is power on trap by RTS2#
0: RTS2# is pull up by internal 47K resistor.
1: RTS2# is pull down by external resistor.
00: Output PWM mode (push pull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s power
terminal.
10: Output PWM mode (open drain) to control Intel 4-wire fans.
2’b 0S
11: Reserved.
Bit 0 is power on trap by RTS2#
0: RTS2# is pull up by internal 47K resistor.
1: RTS2# is pull down by external resistor.
S: Register default values are decided by trapping.
7.5.33 Fan mode Select Register -- Index 96h
Bit
Name
7-6
Reserved
R/W Default
-
-
5-4
FAN3_MODE
R/W
1h
3-2
FAN2_MODE
R/W
1h
Description
Reserved.
00: Auto fan speed control, fan speed will follow different temperature by
different RPM that defines in 0xC6-0xCE.
01: Auto fan speed control, fan speed will follow different temperature by
different duty cycle that defines in 0xC6-0xCE.
10: Manual mode fan control, user can write expect RPM count to
0xC2-0xC3, and F71889 will auto control duty cycle (PWM fan type) or
voltage(linear fan type) to control fan speed.
11: Manual mode fan control, user can write expect duty cycle (PWM fan
type) or voltage(linear fan type) to 0xC3, and F71889 will output this value
duty or voltage to control fan speed.
00: Auto fan speed control, fan speed will follow different temperature by
different RPM that defines in 0xB6-0xBE.
01: Auto fan speed control, fan speed will follow different temperature by
different duty cycle (voltage) that defines in 0xB6-0xBE.
10: Manual mode fan control, user can write expect RPM count to
0xB2-0xB3, and F71889 will auto control duty cycle (PWM fan type) or
voltage (linear fan type) to control fan speed.
11: Manual mode fan control, user can write expect duty cycle (PWM fan
type) or voltage (linear fan type) to 0xB3, and F71889 will output this value
duty or voltage to control fan speed.
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April, 2010
V0.28P
F71889
1-0
FAN1_MODE
R/W
1h
00: Auto fan speed control, fan speed will follow different temperature by
different RPM that defines in 0xA6-0xAE.
01: Auto fan speed control, fan speed will follow different temperature by
different duty cycle that defines in 0xA6-0xAE.
10: Manual mode fan control, user can write expect RPM count to
0xA2-0xA3, and F71889 will auto control duty cycle (PWM fan type) or
voltage(linear fan type) to control fan speed.
11: Manual mode fan control, user can write expect duty cycle (PWM fan
type) or voltage(linear fan type) to 0xA3, and F71889 will output this value
duty or voltage to control fan speed.
7.5.34 Auto Fan1 and Fan2 Boundary Hystersis Select Register -- Index 98h
Bit
Name
R/W Default
Description
º
7-4
FAN2_HYS
R/W
4h
3-0
FAN1_HYS
R/W
4h
0000: Boundary hysteresis. (0~15 C)
Segment will change when the temperature over the boundary temperature
and below the (boundary – hysteresis).
º
0000: Boundary hysteresis. (0~15 C)
Segment will change when the temperature over the boundary temperature
and below the (boundary – hysteresis).
7.5.35 Auto Fan3 Boundary Hystersis Select Register -- Index 99h
Bit
Name
7-4
Reserved
R/W Default
-
-
Description
Reserved.
º
3-0
FAN3_HYS
R/W
2h
0000: Boundary hysteresis. (0~15 C)
Segment will change when the temperature over the boundary temperature
and below the (boundary – hysteresis).
7.5.36 Auto Fan Up Speed update Rate Select Register -- Index 9Bh (FAN_RATE_PROG_SEL = 0)
Bit
7-6
Name
Reserved
R/W Default
-
-
5-4
FAN3_UP_RATE
R/W
1h
3-2
FAN2_UP_RATE
R/W
1h
1-0
FAN1_UP_RATE
R/W
1h
Description
Reserved.
Fan3 duty update rate:
00: 2Hz
01: 5Hz (default)
10: 10Hz
11: 20Hz
Fan2 duty update rate:
00: 2Hz
01: 5Hz (default)
10: 10Hz
11: 20Hz
Fan1 duty update rate:
00: 2Hz
01: 5Hz (default)
10: 10Hz
11: 20Hz
7.5.37 Auto Fan Down Speed update Rate Select Register -- Index 9Bh (FAN_RATE_PROG_SEL = 1)
Bit
Name
7-6
Reserved
5-4 FAN3_DOWN_RATE
R/W Default
-
R/W
-
1h
Description
Reserved.
Fan3 duty update rate:
00: 2Hz
01: 5Hz (default)
10: 10Hz
11: 20Hz
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April, 2010
V0.28P
F71889
3-2 FAN2_DOWN_RATE
R/W
1h
1-0 FAN1_DOWN_RATE
R/W
1h
Fan2 duty update rate:
00: 2Hz
01: 5Hz (default)
10: 10Hz
11: 20Hz
Fan1 duty update rate:
00: 2Hz
01: 5Hz (default)
10: 10Hz
11: 20Hz
7.5.38 FAN1 and FAN2 START UP DUTY-CYCLE/VOLTAGE ⎯ Index 9Ch
Bit
Name
R/W Default
7-4
FAN2_STOP_DUTY
R/W
5h
3-0
FAN1_STOP_DUTY
R/W
5h
Description
When fan start, the FAN_CTRL2 will increase duty-cycle from 0 to this (value
x 8) directly. And if fan speed is down, the FAN_CTRL 2 will decrease
duty-cycle to 0 when the PWM duty cycle is less than this (value x 4).
When fan start, the FAN_CTRL 1 will increase duty-cycle from 0 to this
(value x 8 directly. And if fan speed is down, the FAN_CTRL 1 will decrease
duty-cycle to 0 when the PWM duty cycle is less than this (value x 4).
7.5.39 FAN3 START UP DUTY-CYCLE/VOLTAGE ⎯ Index 9Dh
Bit
Name
R/W Default
7-4
Reserved
-
-
3-0
FAN3_STOP_DUTY
R/W
5h
Description
Reserved.
When fan start, the FAN_CTRL 3 will increase duty-cycle from 0 to this
(value x 8 directly. And if fan speed is down, the FAN_CTRL 3 will decrease
duty-cycle to 0 when the PWM duty cycle is less than this (value x 4).
7.5.40 Fan Fault Time Register -- Index 9Fh
Bit
Name
R/W Default
7
FAN_RATE_PROG_SEL
R/W
0
6-5
Reserved
--
--
4
FULL_DUTY_SEL
R/W
--
3-0
F_FAULT_TIME
R/W
Ah
Description
0: Index 9Bh is the fan up speed update rate select register.
1: Index 9Bh is the fan down speed update rate select register.
Reservd
0: the full duty is 100%. (pull down by external resistor)
1: the full duty is 60% (default, pull up by internal 47K resistor).
This register is power on trap by DTR1#.
This register determines the time of fan fault. The condition to cause fan fault
event is:
When PWM_Duty reaches FFh, if the fan speed count can’t reach the fan
expect count in time.
The unit of this register is 1 second. The default value is 11 seconds.
(Set to 0 , means 1 seconds. ; Set to 1, means 2 seconds.
Set to 2, means 3 seconds. …. )
Another condition to cause fan fault event is fan stop and the PWM duty is
greater than the minimum duty programmed by the register index 9C-9Dh.
-38-
April, 2010
V0.28P
F71889
Fan1 Index A0h- AFh
Address
Attribute
Default
Value
A0h
RO
8’h0f
A1h
RO
8’hff
A2h
R/W
8’h00
A3h
R/W
8’h01
A4h
R/W
8’h03
A5h
R/W
8’hff
Description
FAN1 count reading (MSB). At the moment of reading this register, the LSB will
be latched. This will prevent from data updating when reading. To read the fan
count correctly, read MSB first and followed read the LSB.
FAN1 count reading (LSB).
RPM mode(CR96 bit0=0):
FAN1 expect speed count value (MSB), in auto fan mode (CR96 bit1Î0) this
register is auto updated by hardware.
Duty mode(CR96 bit0=1):
This byte is reserved byte.
RPM mode(CR96 bit0=0):
FAN1 expect speed count value (LSB) or expect PWM duty, in auto fan mode this
register is auto updated by hardware and read only.
Duty mode(CR96 bit0=1):
The Value programming in this byte is duty value. In auto fan mode (CR96
bit1Î0) this register is updated by hardware.
Ex: 5Î 5*100/255 %
255 Î 100%
FAN1 full speed count reading (MSB). At the moment of reading this register, the
LSB will be latched. This will prevent from data updating when reading. To read
the fan count correctly, read MSB first and followed read the LSB.
FAN1 full speed count reading (LSB).
7.5.41 VT1 BOUNDARY 1 TEMPERATURE – Index A6h
Bit
7-0
Name
BOUND1TMP1
R/W Default
R/W
Description
The 1st BOUNDARY temperature for VT1 in temperature mode.
When VT1 temperature is exceed this boundary, FAN1 expect value will load
from segment 1 register (index AAh).
3Ch
When VT1 temperature is below this boundary – hysteresis, FAN1 expect
º
(60 C)
value will load from segment 2 register (index ABh).
This byte is a 2’s complement value ranging from -128ºC ~ 127ºC. Bit 7 will
always be “0” (always positive) if FAN_NEG_TEMP_EN is “0”.
7.5.42 VT1 BOUNDARY 2 TEMPERATURE – Index A7
Bit
7-0
Name
BOUND2TMP1
R/W Default
R/W
Description
The 2st BOUNDARY temperature for VT1 in temperature mode.
When VT1 temperature is exceed this boundary, FAN1 expect value will load
from segment 2 register (index ABh).
32
When VT1 temperature is below this boundary – hysteresis, FAN1 expect
º
(50 C)
value will load from segment 3 register (index ACh).
This byte is a 2’s complement value ranging from -128ºC ~ 127ºC. Bit 7 will
always be “0” (always positive) if FAN_NEG_TEMP_EN is “0”.
7.5.43 VT1 BOUNDARY 3 TEMPERATURE – Index A8h
Bit
Name
7-0 BOUND3TMP1
R/W Default
R/W
Description
The 3st BOUNDARY temperature for VT1 in temperature mode.
When VT1 temperature is exceed this boundary, FAN1 expect value will load
from segment 3 register (index ACh).
28h
When VT1 temperature is below this boundary – hysteresis, FAN1 expect
º
(40 C)
value will load from segment 4 register (index ADh).
This byte is a 2’s complement value ranging from -128ºC ~ 127ºC. Bit 7 will
always be “0” (always positive) if FAN_NEG_TEMP_EN is “0”.
-39-
April, 2010
V0.28P
F71889
7.5.44 VT1 BOUNDARY 4 TEMPERATURE – Index A9
Bit
7-0
Name
BOUND4TMP1
R/W Default
R/W
Description
The 4st BOUNDARY temperature for VT1 in temperature mode.
When VT1 temperature is exceed this boundary, FAN1 expect value will load
from segment 4 register (index ADh).
1Eh
When VT1 temperature is below this boundary – hysteresis, FAN1 expect
º
(30 C)
value will load from segment 5 register (index AEh).
This byte is a 2’s complement value ranging from -128ºC ~ 127ºC. Bit 7 will
always be “0” (always positive) if FAN_NEG_TEMP_EN is “0”.
7.5.45 FAN1 SEGMENT 1 SPEED COUNT – Index AAh
Bit
7-0
Name
SEC1SPEED1
R/W Default
The meaning of this register is depending on the FAN1_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
the full speed in this temperature section.
Ex:
FFh
100%: full speed: User must set this register to 0.
R/W
(100%)
60% full speed: (100-60)*32/60, so user must program 21 to this reg.
X% full speed: The value programming in this byte is Î (100-X)*32/X
2’b01: The value that set in this byte is mean the expect PWM duty-cycle in
this temperature section.
7.5.46 FAN1 SEGMENT 2 SPEED COUNT
Bit
7-0
Name
SEC2SPEED1
7-0
Name
SEC3SPEED1
R/W
7-0
Name
SEC4SPEED1
7-0
Name
SEC5SPEED1
– Index ACh
R/W Default
R/W
Description
The meaning of this register is depending on the FAN1_MODE(CR96)
B2h 2’b00: The value that set in this byte is the relative expect fan speed % of
(70%) the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle in
this temperature section.
– Index ADh
R/W Default
R/W
Description
The meaning of this register is depending on the FAN1_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
99h
the full speed in this temperature section.
(60%)
2’b01: The value that set in this byte is mean the expect PWM duty-cycle in
this temperature section.
7.5.49 FAN1 SEGMENT 5 SPEED COUNT
Bit
Description
The meaning of this register is depending on the FAN1_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
D9h
the full speed in this temperature section.
(85%)
2’b01: The value that set in this byte is mean the expect PWM duty-cycle in
this temperature section.
7.5.48 FAN1 SEGMENT 4 SPEED COUNT
Bit
– Index ABh
R/W Default
7.5.47 FAN1 SEGMENT 3 SPEED COUNT
Bit
Description
– Index AEh
R/W Default
R/W
Description
The meaning of this register is depending on the FAN1_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
80h
the full speed in this temperature section.
(50%)
2’b01: The value that set in this byte is mean the expect PWM duty-cycle in
this temperature section.
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April, 2010
V0.28P
F71889
7.5.50 FAN1 Temperature Mapping Select
– Index AFh
Bit
Name
7
FAN1_TEMP_SEL
_DIG
R/W
0
6
Reserved
--
0
This bit companying with FAN1_TEMP_SEL select the temperature source
for controlling FAN1.
Reserved
5
FAN1_UP_T_EN
R/W
0
Set 1 to force FAN1 to full speed if any temperature over its high limit.
FAN1_INTERPOLATION_
R/W
EN
0
4
R/W Default
3
FAN1_JUMP_HIGH_EN R/W
0
2
FAN1_JUMP_LOW_EN R/W
0
FAN1_TEMP_SEL
1
1-0
R/W
Description
Set 1 will enable the interpolation of the fan expect table.
This register controls the FAN1 duty movement when temperature over
highest boundary.
0: The FAN1 duty will increases with the slope selected by
FAN1_RATE_SEL register.
1: The FAN1 duty will directly jumps to the value of SEC1SPEED1 register.
This bit only activates in duty mode.
This register controls the FAN1 duty movement when temperature under
(highest boundary – hysteresis).
0: The FAN1 duty will decreases with the slope selected by
FAN1_RATE_SEL register.
1: The FAN1 duty will directly jumps to the value of SEC2SPEED1 register.
This bit only activates in duty mode.
This registers companying with FAN1_TEMP_SEL_DIG select the
temperature source for controlling FAN1. The following value is comprised
by {FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL}
001: fan1 follows temperature 1 (CR72h).
010: fan1 follows temperature 2 (CR74h).
011: fan1 follows temperature 3 (CR76h).
101: fan1 follows digital temperature 1 (CR7Ch).
110: fan1 follows digital temperature 2 (CR7Bh).
111: fan1 follows digital temperature 3 (CR7Ah).
Otherwise: reserved.
Fan2 Index B0h- BFh
Address
Attribute
Default
Value
B0h
RO
8’h0f
B1h
RO
8’hff
B2h
R/W
8’h00
B3h
R/W
8’h01
B4h
R/W
8’h03
Description
FAN2 count reading (MSB). At the moment of reading this register, the LSB will
be latched. This will prevent from data updating when reading. To read the fan
count correctly, read MSB first and followed read the LSB.
FAN2 count reading (LSB).
RPM mode(CR96 bit2=0):
FAN2 expect speed count value (MSB), in auto fan mode (CR96 bit3Î0) this
register is auto updated by hardware.
Duty mode(CR96 bit2=1):
This byte is reserved byte.
RPM mode(CR96 bit2=0):
FAN2 expect speed count value (LSB) or expect PWM duty, in auto fan mode this
register is auto updated by hardware and read only.
Duty mode(CR96 bit2=1):
The Value programming in this byte is duty value. In auto fan mode (CR96
bit3Î0) this register is updated by hardware.
Ex: 5Î 5*100/255 %
255Î 100%
FAN2 full speed count reading (MSB). At the moment of reading this register, the
LSB will be latched. This will prevent from data updating when reading. To read
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B5h
R/W
8’hff
the fan count correctly, read MSB first and followed read the LSB.
FAN2 full speed count reading (LSB).
7.5.51 VT2 BOUNDARY 1 TEMPERATURE – Index B6h
Bit
7-0
Name
BOUND1TMP2
R/W Default
R/W
Description
The 1st BOUNDARY temperature for VT2 in temperature mode.
When VT2 temperature is exceed this boundary, FAN2 expect value will load
from segment 1 register (index BAh).
3Ch
When VT2 temperature is below this boundary – hysteresis, FAN2 expect
º
(60 C)
value will load from segment 2 register (index BBh).
This byte is a 2’s complement value ranging from -128ºC ~ 127ºC. Bit 7 will
always be “0” (always positive) if FAN_NEG_TEMP_EN is “0”.
7.5.52 VT2 BOUNDARY 2 TEMPERATURE – Index B7
Bit
7-0
Name
BOUND2TMP2
R/W Default
R/W
Description
The 2st BOUNDARY temperature for VT2 in temperature mode.
When VT2 temperature is exceed this boundary, FAN2 expect value will load
from segment 2 register (index BBh).
32
When VT2 temperature is below this boundary – hysteresis, FAN2 expect
º
(50 C)
value will load from segment 3 register (index BCh).
This byte is a 2’s complement value ranging from -128ºC ~ 127ºC. Bit 7 will
always be “0” (always positive) if FAN_NEG_TEMP_EN is “0”.
7.5.53 VT2 BOUNDARY 3 TEMPERATURE – Index B8h
Bit
7-0
Name
BOUND3TMP2
R/W Default
R/W
Description
The 3st BOUNDARY temperature for VT2 in temperature mode.
When VT2 temperature is exceed this boundary, FAN2 expect value will load
from segment 3 register (index BCh).
28h
When VT2 temperature is below this boundary – hysteresis, FAN2 expect
º
(40 C)
value will load from segment 4 register (index BDh).
This byte is a 2’s complement value ranging from -128ºC ~ 127ºC. Bit 7 will
always be “0” (always positive) if FAN_NEG_TEMP_EN is “0”.
7.5.54 VT2 BOUNDARY 4 TEMPERATURE – Index B9
Bit
7-0
Name
BOUND4TMP2
R/W Default
R/W
7.5.55 FAN2 SEGMENT 1 SPEED COUNT
Bit
7-0
Name
SEC1SPEED2
Description
The 4st BOUNDARY temperature for VT2 in temperature mode.
When VT2 temperature is exceed this boundary, FAN2 expect value will load
from segment 4 register (index BDh).
1Eh
When VT2 temperature is below this boundary – hysteresis, FAN2 expect
º
(30 C)
value will load from segment 5 register (index BEh).
This byte is a 2’s complement value ranging from -128ºC ~ 127ºC. Bit 7 will
always be “0” (always positive) if FAN_NEG_TEMP_EN is “0”.
– Index BAh
R/W Default
Description
The meaning of this register is depending on the FAN2_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
the full speed in this temperature section.
Ex:
FFh
100%: full speed: User must set this register to 0.
R/W
(100%)
60% full speed: (100-60)*32/60, so user must program 21 to this reg.
X% full speed: The value programming in this byte is Î (100-X)*32/X
2’b01: The value that set in this byte is mean the expect PWM duty-cycle in
this temperature section.
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7.5.56 FAN2 SEGMENT 2 SPEED COUNT – Index BBh
Bit
7-0
Name
SEC2SPEED2
R/W Default
R/W
Description
The meaning of this register is depending on the FAN2_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
D9h
the full speed in this temperature section.
(85%)
2’b01: The value that set in this byte is mean the expect PWM duty-cycle in
this temperature section.
7.5.57 FAN2 SEGMENT 3 SPEED COUNT
Bit
7-0
Name
SEC3SPEED2
R/W Default
R/W
Description
The meaning of this register is depending on the FAN2_MODE(CR96)
B2h 2’b00: The value that set in this byte is the relative expect fan speed % of
(70%) the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle in
this temperature section.
7.5.58 FAN2 SEGMENT 4 SPEED COUNT
Bit
7-0
Name
SEC4SPEED2
7-0
Name
SEC5SPEED2
– Index BDh
R/W Default
R/W
Description
The meaning of this register is depending on the FAN2_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
99h
the full speed in this temperature section.
(60%)
2’b01: The value that set in this byte is mean the expect PWM duty-cycle in
this temperature section.
7.5.59 FAN2 SEGMENT 5 SPEED COUNT
Bit
– Index BCh
– Index BEh
R/W Default
R/W
Description
The meaning of this register is depending on the FAN2_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
80h
the full speed in this temperature section.
(50%)
2’b01: The value that set in this byte is mean the expect PWM duty-cycle in
this temperature section.
7.5.60 FAN2 Temperature Mapping Select
– Index BFh
Bit
Name
7
FAN2_TEMP_SEL
_DIG
R/W
0
6
Reserved
--
0
This bit companying with FAN2_TEMP_SEL select the temperature source
for controlling FAN2.
Reserved
5
FAN2_UP_T_EN
R/W
0
Set 1 to force FAN2 to full speed if any temperature over its high limit.
FAN2_INTERPOLATION_
R/W
EN
0
4
R/W Default
3
FAN2_JUMP_HIGH_EN R/W
0
2
FAN2_JUMP_LOW_EN R/W
0
Description
Set 1 will enable the interpolation of the fan expect table.
This register controls the FAN2 duty movement when temperature over
highest boundary.
0: The FAN2 duty will increases with the slope selected by
FAN2_RATE_SEL register.
1: The FAN2 duty will directly jumps to the value of SEC1SPEED2 register.
This bit only activates in duty mode.
This register controls the FAN2 duty movement when temperature under
(highest boundary – hysteresis).
0: The FAN2 duty will decreases with the slope selected by
FAN2_RATE_SEL register.
1: The FAN2 duty will directly jumps to the value of SEC2SPEED2 register.
This bit only activates in duty mode.
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1-0
FAN2_TEMP_SEL
R/W
1
This registers companying with FAN2_TEMP_SEL_DIG select the
temperature source for controlling FAN2. The following value is comprised
by {FAN2_TEMP_SEL_DIG, FAN2_TEMP_SEL}
001: fan1 follows temperature 1 (CR72h).
010: fan1 follows temperature 2 (CR74h).
011: fan1 follows temperature 3 (CR76h).
101: fan1 follows digital temperature 1 (CR7Ch).
110: fan1 follows digital temperature 2 (CR7Bh).
111: fan1 follows digital temperature 3 (CR7Ah).
Otherwise: reserved.
Fan3 Index C0h- CFh
Address
Attribute
Default
Value
C0h
RO
8’h0F
C1h
RO
8’hff
C2h
R/W
8’h00
C3h
R/W
8’h01
C4h
R/W
8’h03
C5h
R/W
8’hff
Description
FAN3 count reading (MSB). At the moment of reading this register, the LSB will
be latched. This will prevent from data updating when reading. To read the fan
count correctly, read MSB first and followed read the LSB.
FAN3 count reading (LSB).
RPM mode(CR96 bit4=0):
FAN3 expect speed count value (MSB), in auto fan mode (CR96 bit5Î0) this
register is auto updated by hardware.
Duty mode(CR96 bit4=1):
This byte is reserved byte.
RPM mode(CR96 bit4=0):
FAN3 expect speed count value (LSB) or expect PWM duty, in auto fan mode this
register is auto updated by hardware and read only.
Duty mode(CR96 bit4=1):
The Value programming in this byte is duty value. In auto fan mode (CR96
bit5Î0) this register is updated by hardware.
Ex: 5Î 5*100/255 %
255 Î 100%
FAN3 full speed count reading (MSB). At the moment of reading this register, the
LSB will be latched. This will prevent from data updating when reading. To read
the fan count correctly, read MSB first and followed read the LSB.
FAN3 full speed count reading (LSB).
7.5.61 VT3 BOUNDARY 1 TEMPERATURE – Index C6h
Bit
7-0
Name
BOUND1TMP3
R/W Default
R/W
Description
The 1st BOUNDARY temperature for VT3 in temperature mode.
When VT3 temperature is exceed this boundary, FAN3 expect value will load
from segment 1 register (index CAh).
3Ch
When VT3 temperature is below this boundary – hysteresis, FAN3 expect
o
(60 C)
value will load from segment 2 register (index CBh).
This byte is a 2’s complement value ranging from -128 oC ~ 127 oC. Bit 7 will
always be “0” (always positive) if FAN_NEG_TEMP_EN is “0”.
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7.5.62 VT3 BOUNDARY 2 TEMPERATURE – Index C7
Bit
7-0
Name
BOUND2TMP3
R/W Default
R/W
Description
The 2st BOUNDARY temperature for VT3 in temperature mode.
When VT3 temperature is exceed this boundary, FAN3 expect value will load
from segment 2 register (index CBh).
32
When VT3 temperature is below this boundary – hysteresis, FAN3 expect
o
(50 C)
value will load from segment 3 register (index CCh).
This byte is a 2’s complement value ranging from -128 oC ~ 127 oC. Bit 7 will
always be “0” (always positive) if FAN_NEG_TEMP_EN is “0”.
7.5.63 VT3 BOUNDARY 3 TEMPERATURE – Index C8h
Bit
7-0
Name
BOUND3TMP3
R/W Default
R/W
Description
The 3st BOUNDARY temperature for VT3 in temperature mode.
When VT3 temperature is exceed this boundary, FAN3 expect value will load
from segment 3 register (index CCh).
28h
When VT3 temperature is below this boundary – hysteresis, FAN3 expect
o
(40 C)
value will load from segment 4 register (index CDh).
This byte is a 2’s complement value ranging from -128 oC ~ 127 oC. Bit 7 will
always be “0” (always positive) if FAN_NEG_TEMP_EN is “0”.
7.5.64 VT3 BOUNDARY 4 TEMPERATURE – Index C9
Bit
7-0
Name
BOUND4TMP3
R/W Default
R/W
The 4st BOUNDARY temperature for VT3 in temperature mode.
When VT3 temperature is exceed this boundary, FAN3 expect value will load
from segment 4 register (index CDh).
1Eh
When VT3 temperature is below this boundary – hysteresis, FAN3 expect
o
(30 C)
value will load from segment 5 register (index CEh).
This byte is a 2’s complement value ranging from -128ºC ~ 127ºC. Bit 7 will
always be “0” (always positive) if FAN_NEG_TEMP_EN is “0”.
7.5.65 FAN3 SEGMENT 1 SPEED COUNT
Bit
7-0
Name
SEC1SPEED3
Description
– Index CAh
R/W Default
Description
The meaning of this register is depending on the FAN3_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
the full speed in this temperature section.
Ex:
FFh
100%: full speed: User must set this register to 0.
R/W
(100%)
60% full speed: (100-60)*32/60, so user must program 21 to this reg.
X% full speed: The value programming in this byte is ( (100-X)*32/X
2’b01: The value that set in this byte is mean the expect PWM duty-cycle in
this temperature section.
7.5.66 FAN3 SEGMENT 2 SPEED COUNT – Index CBh
Bit
7-0
Name
SEC2SPEED3
R/W Default
R/W
Description
The meaning of this register is depending on the FAN3_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of the
D9h
full speed in this temperature section.
(85%)
2’b01: The value that set in this byte is mean the expect PWM duty-cycle in
this temperature section.
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7.5.67 FAN3 SEGMENT 3 SPEED COUNT
Bit
7-0
Name
SEC3SPEED3
R/W Default
R/W
Description
The meaning of this register is depending on the FAN3_MODE(CR96)
B2h 2’b00: The value that set in this byte is the relative expect fan speed % of
(70%) the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle in
this temperature section.
7.5.68 FAN3 SEGMENT 4 SPEED COUNT
Bit
7-0
Name
SEC4SPEED3
7-0
Name
SEC5SPEED3
– Index CDh
R/W Default
R/W
Description
The meaning of this register is depending on the FAN3_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
99h
the full speed in this temperature section.
(60%)
2’b01: The value that set in this byte is mean the expect PWM duty-cycle in
this temperature section.
7.5.69 FAN3 SEGMENT 5 SPEED COUNT
Bit
– Index CCh
– Index CEh
R/W Default
R/W
Description
The meaning of this register is depending on the FAN3_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
80h
the full speed in this temperature section.
(50%)
2’b01: The value that set in this byte is mean the expect PWM duty-cycle in
this temperature section.
7.5.70 FAN3 Temperature Mapping Select
– Index CFh
Bit
Name
7
FAN3_TEMP_SEL
_DIG
R/W
0
6
Reserved
--
0
This bit companying with FAN3_TEMP_SEL select the temperature source
for controlling FAN3.
Reserved
5
FAN3_UP_T_EN
R/W
0
Set 1 to force FAN3 to full speed if any temperature over its high limit.
FAN3_INTERPOLATION_
R/W
EN
0
Set 1 will enable the interpolation of the fan expect table.
4
R/W Default
3
FAN3_JUMP_HIGH_EN R/W
0
2
FAN3_JUMP_LOW_EN R/W
0
1-0
FAN3_TEMP_SEL
R/W
1
Description
This register controls the FAN3 duty movement when temperature over
highest boundary.
0: The FAN3 duty will increases with the slope selected by
FAN3_RATE_SEL register.
1: The FAN3 duty will directly jumps to the value of SEC1SPEED3 register.
This bit only activates in duty mode.
This register controls the FAN3 duty movement when temperature under
(highest boundary – hysteresis).
0: The FAN3 duty will decreases with the slope selected by
FAN3_RATE_SEL register.
1: The FAN3 duty will directly jumps to the value of SEC2SPEED3 register.
This bit only activates in duty mode.
This registers companying with FAN3_TEMP_SEL_DIG select the
temperature source for controlling FAN3. The following value is comprised
by {FAN3_TEMP_SEL_DIG, FAN3_TEMP_SEL}
001: fan1 follows temperature 1 (CR72h).
010: fan1 follows temperature 2 (CR74h).
011: fan1 follows temperature 3 (CR76h).
101: fan1 follows digital temperature 1 (CR7Ch).
110: fan1 follows digital temperature 2 (CR7Bh).
111: fan1 follows digital temperature 3 (CR7Ah).
Otherwise: reserved.
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7.5.71 TSI Temperature 0
Bit
Name
– Index E0h
R/W Default
Description
This byte is used as multi-purpose as follows:
TSI_TEMP0
R/W
8’h00
1.
AMD TSI reading if AMD TSI enable (0~255 o C).
2.
Highest temperature among CPU, MCH and PCH if Intel IBex enable
o
(0~255 C).
3.
7-0
SMB_DATA0
7.5.72 TSI Temperature 1
Bit
Name
R/W
The 1st byte of read block protocol. To access this byte,
MCH_BANK_SEL must set to “0”.
This byte is used as multi-purpose:
1. The received data of receive protocol.
2. The first received byte of read word protocol.
3. The 10th received byte of read block protocol.
8’h00
4. The sent data for send byte protocol and write byte protocol.
5. The first send byte for write word protocol.
6. The first send byte for write block protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
– Index E1h
R/W Default
Description
This byte is used as multi-purpose as follows:
1.
TSI_TEMP1
R
Intel IBex is enabled.
8’h00
2.
The 2nd byte of read block protocol.
To access this byte, MCH_BANK_SEL should be set to “0”.
7-0
SMB_DATA1
R/W
This byte is used as multi-purpose:
1. The second received byte of read word protocol.
2. The 11th received byte of read block protocol.
8’h00
3. The second send byte for write word protocol.
4. The second send byte for write block protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
7.5.73 TSI Temperature 2 Low Byte
Bit
The PCH temperature reading (0~255 o C). This byte is only valid if
Name
– Index E2h
R/W Default
Description
This byte is used as multi-purpose as follows:
1.
The low byte of Intel temperature interface CPU reading. The reading
is the fraction part of CPU temperature. Bit 0 indicates the error
TSI_TEMP2_LO
R
8’h00
status. Logic “1” indicates an error code. This byte is only valid if Intel
Ibex is enabled.
7-0
2.
The 3rd byte of the block read protocol.
To access this byte, MCH_BANK_SEL should be set to “0”.
SMB_DATA2
R/W
This is the 12th byte of the block read protocol.
8’h00 This byte is also used as the 3rd byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
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7.5.74 TSI Temperature 2 High Byte – Index E3h
Bit
Name
R/W Default
Description
This byte is used as multi-purpose as follows:
1.
TSI_TEMP2_HI
R
The high byte of Intel temperature interface CPU reading. The reading
is the decimal part of CPU temperature. This byte is only valid if Intel
8’h00
Ibex is enabled.
7-0
2.
The 4th byte of the block read protocol.
To access this byte, MCH_BANK_SEL should be set to “0”.
SMB_DATA3
7.5.75 TSI Temperature 3
Bit
Name
R/W
This is the 13th byte of the block read protocol.
8’h00 This byte is also used as the 4th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
– Index E4h
R/W Default
Description
This byte is used as multi-purpose as follows:
1.
TSI_TEMP3
R
8’h00
Intel Ibex is enabled.
2.
7-0
The MCH temperature reading (0~255 o C). This byte is only valid if
The 5th byte of the block read protocol.
To access this byte, MCH_BANK_SEL should be set to “0”.
SMB_DATA4
7.5.76 TSI Temperature 4
Bit
Name
R/W
This is the 14th byte of the block read protocol.
8’h00 This byte is also used as the 5th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
– Index E5h
R/W Default
Description
This byte is used as multi-purpose as follows:
1.
TSI_TEMP4
R
Intel Ibex is enabled.
8’h00
2.
7-0
The DIMM0 temperature reading (0~255 o C). This byte is only valid if
The 6th byte of the block read protocol.
To access this byte, MCH_BANK_SEL should be set to “0”.
SMB_DATA5
7.5.77 TSI Temperature 5
Bit
Name
R/W
This is the 15th byte of the block read protocol.
8’h00 This byte is also used as the 6th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
– Index E6h
R/W Default
Description
This byte is used as multi-purpose:
1.
7-0
TSI_TEMP5
R
8’h00
The DIMM1 temperature reading (0~255 o C). This byte is only valid if
Intel Ibex is enabled.
2.
The 7th byte of the block read protocol.
To access this byte, MCH_BANK_SEL should be set to “0”.
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SMB_DATA6
7.5.78 TSI Temperature 6
Bit
Name
R/W
This is the 16th byte of the block read protocol.
8’h00 This byte is also used as the 7th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
– Index E7h
R/W Default
Description
This byte is used as multi-purpose as follows:
1.
TSI_TEMP6
R
8’h00
Intel Ibex is enabled.
2.
7-0
The DIMM2 temperature reading (0~255 o C). This byte is only valid if
The 8th byte of the block read protocol.
To access this byte, MCH_BANK_SEL should be set to “0”.
SMB_DATA7
7.5.79 TSI Temperature 7
Bit
Name
R/W
This is the 17th byte of the block read protocol.
8’h00 This byte is also used as the 8th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
– Index E8h
R/W Default
Description
This byte is used as multi-purpose:
1.
TSI_TEMP7
R
8’h00
Intel Ibex is enabled.
2.
7-0
The DIMM3 temperature reading (0~255 o C). The byte is only valid if
The 9th byte of block read protocol.
To access this byte, MCH_BANK_SEL should be set to “0”.
SMB_DATA8
7.5.80 SMB Data Buffer 9
Bit
Name
R/W
This is the 18th byte of the block read protocol.
8’h00 This byte is also used as the 9th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
– Index E9h (MCH_BANK_SEL = 1)
R/W Default
Description
th
This is the 19 byte of the block read protocol.
7-0
SMB_DATA9
R/W
0
This byte is also used as the 10th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
7.5.81 SMB Data Buffer 10
Bit
Name
– Index EAh (MCH_BANK_SEL = 1)
R/W Default
Description
This is the 20th byte of the block read protocol.
7-0
SMB_DATA10
R/W
0
This byte is also used as the 11th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
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7.5.82 Block Write Count Register
Bit
Name
– Index ECh
R/W Default
Description
7
MCH_BANK_SEL
R/W
0
This bit is used to select the register in index E0h to E9h.
Set “0” to read the temperature bank and “1” to access the data bank.
6
Reserved
-
0
Reserved
5-0
BLOCK_WR_CNT
R/W
0
Use the register to specify the byte count of block write protocol. Support up
to 10 bytes.
7.5.83 SMB Command Byte/TSI Comamdn Byte
Bit
Name
7-0
SMB_CMD
R/W Default
R/W
8’h0
Description
Command code for write byte/word, read byte/word, block write/read and
process call protocol.
7.5.84 SMB Command Byte/TSI Comamdn Byte
Bit
Name
7-0
TSI_CMD
7.5.85 SMB Status
Bit
– Index EDh (TSI_CMD_PROG = 0)
– Index EDh (TSI_CMD_PROG = 1)
R/W Default
R/W
8’h1
Description
The command code for Intel temperature interface block read protocol and
the data byte for AMD TSI send byte protocol.
– Index EEh
Name
R/W Default
Description
7
TSI_PENDING
R/W
0
Set 1 to pending auto TSI accessing. (In AMD model, auto accessing will
issue a send-byte followed a receive-byte; In Intel model, auto accessing will
issue a block read).
To use the TSI_SCL/TSI_SDA as a SMBus master, set this bit to “1” first.
6
TSI_CMD_PROG
R/W
0
Set 1 to program TSI_CMD.
5
PROC_KILL
R/W
0
Kill the current SMBus transfer and return the state machine to idle. It will set
an fail status if the current transfer is not completed.
4
FAIL_STS
R
0
This is set when PROC_KI LL kill an un-completed transfer. It will be auto
cleared by next SMBus transfer.
3
SMB_ABT_ERR
R
0
This is the arbitration lost status if a SMBus command is issued. Auto
cleared by next SMBus command.
2
SMB_TO_ERR
R
0
This is the timeout status if a SMBus command is issued. Auto cleared by
next SMBus command.
1
SMB_NAC_ERR
R
0
This is the NACK error status if a SMBus command is issued. Auto cleared
by next SMBus command.
0
SMB_READY
R
1
0: a SMBus transfer is in process.
1: Ready for next SMBus command.
7.5.86 SMB Protocol Select – Index EFh
Bit
Name
R/W Default
7
SMB_START
W
0
6-4
Reserved
-
-
Description
Write “1” to trigger a SMBus transfer with the protocol specified by
SMB_PROTOCOL.
Reserved.
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3-0
SMB_PROTOCOL
R/W
0
Select what protocol if SMBus transfer is triggered.
0001b: send byte.
0010b: write byte.
0011b: write word.
0100b: process call.
0101b: block write.
0111b: quick command (write).
1001b: receive byte.
1010b: read byte.
1011b: read word.
1101b: block read.
1111b: quick command (read).
Otherwise: reserved.
HW Chip ID and Vender ID Information
7.5.87 HM Chip ID 1 Register ⎯ Index 5Ah
Bit
7-0
Name
HM_CHIP_ID1
R/W Default
R
03h
Description
Chip ID 1 of HM Device.
7.5.88 HM Chip ID 2 Register ⎯ Index 5Bh
Bit
7-0
Name
HM_CHIP_ID2
R/W Default
R
04h
Description
Chip ID 2 of HM Device.
7.5.89 HM Vendor ID 1 Register ⎯ Index 5Dh
Bit
7-0
Name
HM_VENDOR_ID1
R/W Default
R
19h
Description
Chip ID 1 of HM Device.
7.5.90 HM Vendor ID 2 Register ⎯ Index 5Eh
Bit
7-0
Name
HM_VENDOR_ID2
R/W Default
R
34h
Description
Chip ID 2 of HM Device.
7.3. Keyboard Controller
The KBC provides the functions included a keyboard and a PS/2 mouse, and can be used with
IBM-compatible personal computers or PS/2-based systems. The controller receives serial data from
the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a
byte of data in its output buffer. The controller will assert an interrupt to the system when data are
placed in its output buffer.
The below content is about the KBC device register descriptions. All the registers are for software
porting reference.
Status Register
The status register is an 8 bits register at I/O address 64h that provides information about the
status of the KBC
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Bit
Name
R/W Default
Description
7
Parity error
R
0
0:odd parity
1:even parity
6
Time out
R
0
0:no time out error
1:time out error
5
Auxiliary device
OBF
R
0
0: Auxiliary output buffer empty
1: Auxiliary output buffer full
4
Inhinit
R
0
0:keyboard is inhibited
1: keyboard is not inhibited
3
Command/data
R
0
0:data byte
1:command byte
2
SYSTEM_FLAG
R
0
This bit is set or clear by command byte of KBC
1
IBF
R
0
0:input buffer empty
1: input buffer full
0
OBF
R
0
0:output buffer empty
1: output buffer full
Command register
The internal KBC operation is controlled by the KBC command byte (KCCB). The KCCB resides in I/O
address 64h that is read with a 20h command and written with a 60h command data.
Bit
Name
R/W Default
Description
7
Reserved
-
-
Reserved
6
Translate code
R/W
1
0: Pass un-translated scan code.
1: Translate scan code to IBM PC standard.
5
Disable Auxiliary
Device
R/W
0
4
Disable Keyboard
R/W
0
1: Disable keyboard inhibit function.
3
Reserved
-
-
Reserved
2
System flag
R/W
1
0: The system is executing POST as a result of a cold boot.
1: The system is executing POST as a result of a shutdown or warm boot.
1
Enable Auxiliary
Interrupt
R/W
1
0: Ao interrupt
1: A system interrupt is generated when a byte is placed in output buffer
(IRQ12).
0
Enable keyboard
Interrupt
R/W
1
0:No interrupt
1: A system interrupt is generated when a byte is placed in output buffer
(IRQ1).
1: Disable Auxiliary inhibit function.
DATA register
The DATA register is an 8 bits register at I/O address 60h. the KBC used the output buffer to send the
scan code received from keyboard and data byte replay by command to the system.
Power on default <7:0> = 00000000 binary
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Commands
COMMAND
20h
FUNCTION
Read Command Byte
Write Command Byte
60h
BIT
DESCRIPTION
0
Enable Keyboard Interrupt
1
Enable Mouse Interrupt
2
System flag
3
Reserve
4
Disable Keyboard Interface
5
Disable Mouse interface
6
IBM keyboard Translate Mode
7
Reserve
A7h
Disable Auxiliary Device Interface
A8h
Enable Auxiliary Device Interface
Auxiliary Interface Test
8’h00: indicate Auxiliary interface is ok.
A9h
8’h01: indicate Auxiliary clock is low.
8’h02: indicate Auxiliary clock is high
8’h03: indicate Auxiliary data is low
8’h04: indicate Auxiliary data is high
AAh
Self-test
Returns 055h if self test succeeds
keyboard
Interface Test
8’h00: indicate keyboard interface is ok.
ABh
8’h01: indicate keyboard clock is low.
8’h02: indicate keyboard clock is high
8’h03: indicate keyboard data is low
8’h04: indicate keyboard data is high
ADh
Disable Keyboard Interface
AEh
Enable Keyboard Interface
C0h
Read Input Port(P1) and send data to the system
C1h
Continuously puts the lower four bits of Port1 into STATUS register
C2h
Continuously puts the upper four bits of Port1 into STATUS register
CAh
Read the data written by CBh command.
CBh
Written a scratch data. This byte could be read by CAh command.
D0h
Send Port2 value to the system
D1h
Only set/reset GateA20 line based on the system data bit 1
D2h
Send data back to the system as if it came from Keyboard
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D3h
Send data back to the system as if it came from Muse
D4h
Output next received byte of data from system to Mouse
FEh
Pulse only RC(the reset line) low for 6μS if Command byte is even
KBC Command Description
PS2 wakeup function
The KBC supports keyboard and mouse wakeup function, keyboard wakeup function has 4
kinds of conditions, when key is pressed combinational key (1) CTRL +ESC (2) CTRL+F1 (3)
CTRL+SPACE (4) ANY KEY (5) windows 98 wakeup up key (6) windows 98 Power key (7) CTRL + ALT
+ Backspace (8) CTRL + Alt + Space, KBC will assert PME signal. Mouse wakeup function has 2 kinds
of conditions, when mouse (1) BUTTON CLICK or (2) BUTTON CLICK AND MOVEMENT, KBC will
assert PME signal. Those wakeup conditions are controlled by configuration register.
7.4. SPI Interface
Communication between the two devices is handling the serial peripheral interface (SPI). Every
SPI system consist of one master and one or more slaves, where a master provides the SPI clock and
slave receives clock from the master.
This
design
is
only
master
function,
for
basic
signal,
master-out/slave-in
(MOSI),
master-in/slave-out (MISO), serial clock (SCK), and 4 slaves select (CS#), are needed for SPI interface.
Each of slave select supports from 1Mbits to 16Mbits flash is decided by configuration register. Serial
clock (SCK) signal is optional 16.7 or 33MHz, and the default is 16.7MHz. The serial data (MOSI) for
SPI interface translates to depend on SCK rising edge or falling edge is decided by configuration
register.
7.5. 80 Port
Monitor the value of 0x80 port and output the value via the signals defined for 7-segment display.
High nibble and low nibble are outputted interleaved at 1KHz frequency. The 80 Port could also be
output to LPT pins if all the input pins of LPT is “0” during power on.
7.6. ACPI Function
The Advanced Configuration and Power Interface (ACPI) is a system for controlling the use of power
in a computer. It lets computer manufacturer and user to determine the computer’s power usage
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dynamically.
There are three ACPI states that are of primary concern to the system designer and they are
designated S0, S3 and S5. S0 is a full-power state; the computer is being actively used in this state. The
other two are called sleep states and reflect different power consumption when power-down. S3 is a state
that the processor is powered down but the last procedural state is being stored in memory which is still
active. S5 is a state that memory is off and the last procedural state of the processor has been stored to
the hard disk. Take S3 and S5 as comparison, since memory is fast, the computer can quickly come back
to full-power state, the disk is slower than the memory and the computer takes longer time to come back to
full-power state. However, since the memory is off, S5 draws the minimal power comparing to S0 and S3.
It is anticipated that only the following state transitions may happen:
S0→S3, S0→S5, S5→S0, S3→S0 and S3→S5.
Among them, S3→S5 is illegal transition and won’t be allowed by state machine. It is necessary to enter
S0 first in order to get to S5 from S3. As for transition S5→S3 will occur only as an immediate state during
state transition from S5→S0. It isn’t allowed in the normal state transition.
The below diagram described the timing, the always on and always off, keep last state could be set in
control register. In keep last state mode, one register will keep the status of before power loss. If it is power
on before power loss, it will remain power on when power is resumed, otherwise, if it is power off before
power loss, it will remain power off when power is resumed.
VBAT
VSB
RSMRST#
S3#
PS_ON#
PSIN#
PSOUT#
VCC3V
Figure 14 Default timing: Always off
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VBAT
VSB
RSMRST#
S3#
PS_ON#
PSIN#
PSOUT#
VCC3V
Figure 15 Optional timing: Always on
PCI Reset and PWROK Signals
The F71889 supports 3 output buffers for 3 reset signals. The result of PCIRST# outcome will
be affected by conditions as below:
PCIRST1# Æ Output buffer of LRESET#.
PCIRST2# Æ Output buffer of LRESET#.
PCIRST3# Æ Output buffer of LRESET#.
+3.3V
Delay
PWROK
LRESET#
PCIRST1~3#
ATXPG
So far as the PWROK issue is as the figure above. PWROK is delayed 400ms (default) as
VCC arrives 2.8V, and the delay timing can be programmed by register. (100ms ~ 400ms)
The F71889 also supports 3 output voltages for VREF1~3. The output is generated from DACs
which is powered by trimmed 2.304V reference voltage. One LSB is 2.304V/512.
Below is the timing sequence between VREF1~3 pins:
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Figure 16 VREF timing: S5ÆS0
Figure 17 VREF timing: S0ÆS3
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Figure 18 VREF timing: S3ÆS0
Figure 19 VREF timing: S0ÆS5
7.7. PECI Function
The Platform Environment Control Interface (PECI) uses a single wire for self-clocking and
data transfer. The bus requires no additional control lines. The physical layer is a self-clocked
on-wire bus that begins each bit with a driven, rising edge from an idle level near zero volts. The
duration of the signal driven high depends on whether the bit value is a logic ‘0’ or login ‘1’. PECI
also includes variable data transfer rate established with every message. In this way, it is highly
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flexible even though underlying logic is simple.
The interface design was optimized for interfacing to Intel processor and chipset components
in both single processor and multiple processor environments. The single wire interface provides
low board routing overhead for the multiple load connections in the congested routing area near
the processor and chipset components. Bus speed, error checking, and low protocol overhead
provides adequate link bandwidth and reliability to transfer critical device operating conditions and
configuration information.
7.8. SST Function
The Simple Serial Transfer (SST) temperature sensor provides a means to digitize an analog
signal and send that information over a digital bus enabling remote temperature sensing in areas
previously not monitored in the PC. The temperature sensor supports an internal and external
thermal diode.
The Simple Serial Transfer (SST) interface provides sensed temperatures and voltages. The
sensed temperatures are T1, T2, and T3 whose reading values stored in CR72h, CR74h, and
CR76h. The sensed voltages are V1~V6 whose reading values stored in CR21h~26h.
7.9. TSI Function
The Temperature Sensor Interface (TSI) was a simple SMBUS master to communicate with
AMD CPU or Intel CPU to getting the temperature of CPU. It supports byte sending, byte reveiving,
read/write byte, read/write block and quick command of SMBus protocol. When power on the
hardware automatically fetch the temperature use the protocol per the specification of AMD/Intel.
User can use the provided registers to control the SCL/SDA as a SMBus master. For Intel platform,
the SMBUS supports next generational IBX protocol for temperature reading.
7.10. FSB Bus Interface
The Bus interface is simply GPIs and GPIOs. There are two modes supported: bypass mode
and manual mode. Default is the bypass mode, BUSIN will bypass to BUSOUT. In manual mode,
BUSOUT is controlled by registers. Nomally this function is for FSB over/under colcking
application.
7.11. VID Controller
VID Controller provides two types of interface parallel to parallel and serial to serial (AMD only).
There are three modes for each type: bypass, manual and on the fly. It’s used to over-voltage
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control. In bypass mode, the hardware monitors the input and bypass to the output. In manual
mode, the input is monitored but the output is controlled by registers. In on-the-fly mode, user
programs the offset, the hardware monitors the input, adds the offset and then pass to the output.
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8. Register Description
The configuration register is used to control the behavior of the corresponding devices. To
configure the register, using the index port to select the index and then writing data port to alter the
parameters. The default index port and data port are 0x4E and 0x4F respectively. Pull down the
SOUT1 pin to change the default value to 0x2E/0x2F. To enable configuration, the entry key 0x87
must be written to the index port. To disable configuration, write exit key 0xAA to the index port.
Following is a example to enable configuration and disable configuration by using debug.
-o 4e 87
-o 4e 87
( enable configuration )
-o 4e aa
( disable configuration )
The Following is a register map (total devices) grouped in hexadecimal address order, which
shows a summary of all registers and their default value. Please refer each device chapter if you
want more detail information.
“-“ Reserved or Tri-State
Global Control Registers
Register
0x[HEX]
02
07
20
21
23
24
25
26
27
28
2A
2B
2C
2D
Default Value
Register Name
MSB
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0/1
1
1
0
0
0
0
-
Software Reset Register
Logic Device Number Register (LDN)
Chip ID Register
Chip ID Register
Vender ID Register
Vender ID Register
Software Power Down Register
UART IRQ Sharing Register
ROM Address Select Register
80 Port Enable Register
Multi Function Select 1 Register
Multi Function Select 2 Register
Multi Function Select 3 Register
Wakeup Control Register
0
0
1
0
1
0
0
1/0
0/1
1
1
0
-
0
0
0
1
1
0
0
1/0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
1/0
0
0
0
0
LSB
0
0
0
1
1
1
1
0
1
0
0
0
0
0
0
1/0 1/0
0
0
0
0
0
0
0
0
“-“ Reserved or Tri-State
FDC Device Configuration Registers (LDN CR00)
Register
0x[HEX]
30
60
61
70
74
Default Value
Register Name
MSB
0
1
-
FDC Device Enable Register
Base Address High Register
Base Address Low Register
IRQ Channel Select Register
DMA Channel Select Register
-61-
0
1
-
0
1
-
0
1
-
0
0
0
-
0
0
1
0
LSB
1
0
1
1
1
1
0
0
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F0
F2
F4
FDD Mode Register
FDD Drive Type Register
FDD Selection Register
-
-
-
0
0
1
0
1
-
1
1
0
0
1
0
0
0
1
-
LSB
1
0
0
-
1
1
0
0
-
0
0
0
0
1
LSB
1
0
1
0
1
0
0
1
0
UART1 Device Configuration Registers (LDN CR01)
Register
0x[HEX]
30
60
61
70
F0
Default Value
Register Name
MSB
0
1
-
UART1 Device Enable Register
Base Address High Register
Base Address Low Register
IRQ Channel Select Register
RS485 Enable Register
0
1
-
0
1
-
0
1
0
0
1
0
-
UART2 Device Configuration Registers (LDN CR02)
Default Value
Register
0x[HEX]
30
60
61
70
F0
F1
UART2 Device Enable Register
Base Address High Register
Base Address Low Register
IRQ Channel Select Register
RS485 Enable Register
SIR Mode Control Register
Register
0x[HEX]
30
60
61
70
74
F0
Parallel Port Device Configuration Registers (LDN CR03)
Default Value
Register Name
MSB
Parallel Port Device Enable Register
Base Address High Register
0
0
0
0
0
Base Address Low Register
0
1
1
1
1
IRQ Channel Select Register
0
DMA Channel Select Register
0
PRT Mode Select Register
0
1
0
0
0
0
0
1
0
0
LSB
1
0
1
1
1
1
1
0
1
1
0
Register
0x[HEX]
30
60
61
70
Hardware Monitor Device Configuration Registers (LDN CR04)
Default Value
Register Name
MSB
H/W Monitor Device Enable Register
Base Address High Register
0
0
0
0
0
Base Address Low Register
1
0
0
1
0
IRQ Channel Select Register
0
0
1
0
LSB
1
0
0
1
0
1
0
Register Name
MSB
0
1
-
0
1
-
0
1
-
0
1
0
0
0
1
0
0
0
KBC Device Configuration Registers (LDN CR05)
Register
0x[HEX]
30
60
61
70
72
F0
FE
Default Value
Register Name
MSB
0
0
1
KBC Device Enable Register
Base Address High Register
Base Address Low Register
KB IRQ Channel Select Register
Mouse IRQ Channel Select Register
Clock Select Register
Swap Register
1
0
1
0
0
1
-
0
0
-
0
0
0
1
-
0
0
0
1
-
LSB
0
0
0
0
1
1
0
0
1
0
1
-
-
0
0
0
0
1
0
1
0
LSB
0
1
0
0
1
0
GPIO Device Configuration Registers (LDN CR06)
Register
0x[HEX]
F0
F1
F2
F3
Default Value
Register Name
MSB
-
GPIO Output Enable Register
GPIO Output Data Register
GPIO Pin Status Register
GPIO Drive Enable Register
-62-
0
1
0
0
1
0
0
1
0
0
1
0
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FE
FF
E0
E1
E2
E3
D0
D1
D2
D3
C0
C1
C2
C3
B0
B1
B2
A0
A1
A2
A3
90
91
92
93
80
81
82
83
LED_VSB Control Register
LED_VCC Control Register
GPIO1 Output Enable Register
GPIO1 Output Data Register
GPIO1 Pin Status Register
GPIO1 Drive Enable Register
GPIO2 Output Enable Register
GPIO2 Output Data Register
GPIO2 Pin Status Register
GPIO2 Drive Enable Register
GPIO3 Output Enable Register
GPIO3 Output Data Register
GPIO3 Pin Status Register
GPIO3 Drive Enable Register
GPIO4 Output Enable Register
GPIO4 Output Data Register
GPIO4 Pin Status Register
GPIO5 Output Enable Register
GPIO5 Output Data Register
GPIO5 Pin Status Register
GPIO5 Drive Enable Register
GPIO6 Output Enable Register
GPIO6 Output Data Register
GPIO6 Pin Status Register
GPIO6 Drive Enable Register
GPIO7 Output Enable Register
GPIO7 Output Data Register
GPIO7 Pin Status Register
GPIO7 Drive Enable Register
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
LSB
0
0
0
VID Device Configuration Registers (LDN CR07)
Register
0x[HEX]
30
60
61
F0
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
Default Value
Register Name
MSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID Device Enable Register
Base Address High Register
Base Address Low Register
Watchdog Timer Enable Register
BUS Manual Register
Key Data Register
BUSIN Status Register
WDT Unit Select Register
WDT Count Register
NB Offset Register
VDD0 Offset Register
VDD1 Offset Register
Watchdog Timer PME Register
NB Manaul Register
VDD0 Manaul Register
VDD1 Manaul Register
PSI Control Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
SPI Device Configuration Registers (LDN CR08)
Register
0x[HEX]
F0
F1
Default Value
Register Name
MSB
0
SPI Control Register
SPI Timeout Value Register
-63-
0
0
0
0
0
0
April, 2010
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F2
F3
F4
F5
F6
F7
F8
FA
FB
FC
FD
FE
FF
SPI Baud Rate Divisor Register
SPI Status Register
SPI High Byte Data Register
SPI Command Data Register
SPI Chip Select Register
SPI Memory Mapping Register
SPI Operate Register
SPI Low Byte Data Register
SPI Address High Byte Register
SPI Address Medium Byte Register
SPI Address Low Byte Register
SPI Program Byte Register
SPI Write Data Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register
0x[HEX]
30
F0
F1
F4
F5
F6
PME and ACPI Device Configuration Registers (LDN CR0A)
Default Value
Register Name
MSB
PME Device Enable Register
PME Event Enable Register
0
0
0
0
PME Event Status Register
ACPI Control Register1
0
0
1
0
0
ACPI Control Register2
0
0
0
1
1
ACPI Control Register3
0
0
0
0
0
0
1
1
1
LSB
0
1
0
1
0
0
0
0
1
Register
0x[HEX]
F0
F1
F2
F3
FF
Vref Control Device Configuration Registers (LDN CR0B)
Default Value
Register Name
MSB
VREF3 output value
0
1
1
0
0
VREF2output value
0
1
1
0
0
VREF1 output value
0
1
1
0
0
Voltage LSB
WDT Reset Enable
-
1
1
1
0
-
LSB
0
0
0
0
-
0
0
0
0
0
8.1 Global Control Registers
8.1.1
Bit
Software Reset Register ⎯ Index 02h
Name
R/W Default
Description
7
Temp_Update_Rate
R/W
0
0: Digital interface (PECI/TSI/IBX) transmits when every temperature
updates
1: Digital interface (PECI/TSI/IBX) transmits when every four times
temperature updates
6-1
Reserved
-
-
Reserved
0
SOFT_RST
R/W
0
Write 1 to reset the register and device powered by VDD (VCC).
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8.1.2
Bit
7-0
8.1.3
Logic Device Number Register (LDN) ⎯ Index 07h
Name
LDN
Name
7-0
CHIP_ID1
00h
00h: Select FDC device configuration registers.
01h: Select UART 1 device configuration registers.
02h: Select UART 2 device configuration registers.
03h: Select Parallel Port device configuration registers.
04h: Select Hardware Monitor device configuration registers.
05h: Select KBC device configuration registers.
06h: Select GPIO device configuration registers.
07h: Select VID device configuration registers.
08h: Select SPI device configuration registers.
0ah: Select PME & ACPI device configuration registers.
0bh: Select VREF Control device configuration registers.
R/W Default
R
07h
Description
Chip ID 1.
Chip ID Register ⎯ Index 21h
Bit
Name
7-0
CHIP_ID2
8.1.5
R/W
Description
Chip ID Register ⎯ Index 20h
Bit
8.1.4
R/W Default
R/W Default
R
23h
Description
Chip ID2.
Vendor ID Register ⎯ Index 23h
Bit
Name
R/W Default
7-0
VENDOR_ID1
8.1.6
Vendor ID Register ⎯ Index 24h
R
19h
Description
Vendor ID 1 of Fintek devices.
Bit
Name
R/W Default
7-0
VENDOR_ID2
8.1.7
Software Power Down Register ⎯ Index 25h
R
34h
Description
Vendor ID 2 of Fintek devices.
Bit
Name
7-6
Reserved
R/W Default
-
-
Reserved
Description
5
SOFTPD_KBC
R/W
0
Power down the KBC device. This will stop the KBC clock. (Reserved for
future use)
4
SOFTPD_HM
R/W
0
Power down the Hardware Monitor device. This will stop the Hardware
Monitor clock.
3
SOFTPD_PRT
R/W
0
Power down the Parallel Port device. This will stop the Parallel Port clock.
2
SOFTPD_UR2
R/W
0
Power down the UART 2 device. This will stop the UART 2 clock.
1
SOFTPD_UR1
R/W
0
Power down the UART 1 device. This will stop the UART 1 clock.
0
SOFTPD_FDC
R/W
0
Power down the FDC device. This will stop the FDC clock.
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8.1.8
UART IRQ Sharing Register ⎯ Index 26h
Bit
Name
R/W Default
7
CLK24M_SEL
R/W
0
6
Reserved
-
-
5
DPORT_DEC_SEL
R/W
0
Description
0: CLKIN is 48MHz
1: CLKIN is 24MHz
Reserved.
0: The 80 Port address is decoded as 0x0080.
1: The 80 port address is decoded as the SCR of UART2.
This bit is powered by VBAT.
0: The SPI timeout status is reset by internal VDD3VOK.
4
SPI_TM_RST_SEL
R/W
0
1: The SPI timeout status is reset by internal VSB3VOK.
This bit is powered by VBAT.
3-2
Reserved
-
-
1
IRQ_MODE
R/W
0
0
IRQ_SHAR
R/W
0
8.1.9
Name
7
ROM_WR_EN
R/W
0
0: disable IRQ sharing of two UART devices.
1: enable IRQ sharing of two UART devices.
SPI_EN
SPI_BIOS_EN
3
Reserved
-
BSEL_EN
0: use SPI bridge for BIOS
1: Reserved
This register is power on trapped by DTR2#/FWH_TRAP. Pull down to
enable SPI bridge for BIOS.
R/W
0: SPI disable
This register is power on trapped by SOUT2/SPI_TRAP. Pull down to enable
SPI.
R/W
PORT_4E_EN
0: disable ROM writing
1: SPI enable
R/W
4
Description
1: enable ROM writing
-
2
1: ISA IRQ sharing mode (low pulse).
R/W Default
-
5
0: PCI IRQ sharing mode (low level).
ROM Address Select Register ⎯ Index 27h
Bit
6
Reserved.
0: The configuration register port is 2E/2F.
1: The configuration register port is 4E/4F.
This register is power on trapped by SOUT1/ Config4E_2E. Pull down to
select port 2E/2F.
-
Reserved.
-
0: The BUSIN/BUSOUT functions as GPIOs.
1: The BUSIN/BUSOUT functions as BUS interface.
R/W
This register is power on trapped by BSGPIO_TRP. Pull down to select
GPIO function.
-
00: The parallel port pins function as LPT.
x1: The parallel port pins function as VID control.
1-0
LPT_FUNC_SEL
R/W
10: The parallel port pins function as GPIOs.
This register is power on trapped by VIDIO_TRAP. Different resistor will
determine these three functions.
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8.1.10
80 Port Enable Register ⎯ Index 28h
Bit
Name
7
LPT_DPORT_EN
R/W
-
6
Reserved
-
-
5
DPORT_EN
R/W
-
4
TEMP_OUT_EN
R/W
0
Set this bit to “1” will output the CPU temperature to the 7-segment LED.
3-0
Reserved
-
-
Reserved.
8.1.11
Bit
R/W Default
Description
0: The 80 port data could not be output to LPT pins.
1: The 80 port data could be output to LPT pins in DPORT_EN is set to “1”.
Reserved.
0: The 80 port function is disabled.
1: The 80 port function is enabled.
Multi Function Select 1 Register ⎯ Index 2Ah (Powered by VSB3V)
Name
R/W Default
Description
GPIO06/BEEP/ALERT# function select.
00: The pin function is ALERT#.
7-6
GPIO06_SEL
R/W
2’b11 01: The pin function is BEEP.
10: Reserved.
11: The pin function is GPIO06.
GPIO05/LED_VCC function select.
5
GPIO05_SEL
R/W
1
0: The pin function is LED_VCC.
1: The pin function is GPIO05.
GPIO04/LED_VSB function select.
4
GPIO04_SEL
R/W
1
0: The pin function is LED_VSB.
1: The pin function is GPIO04.
SLOTOCC#/GPIO03 function select.
3
GPIO03_SEL
R/W
0
0: The pin function is SLOTOCC#.
1: The pin function is GPIO03.
2
Reserved
R/W
0
Reserved
1
Reserved
R/W
0
Reserved
0
Reserved
R/W
0
Reserved
8.1.12
Bit
Multi Function Select 2 Register ⎯ Index 2Bh (Powered by VSB3V)
Name
R/W Default
Description
PECI_REQ#/IRTX/GPIO13 function select.
00: The pin function is PECI_REQ#
7-6
GPIO13_SEL
R/W
00b
01: The pin function is IRTX.
10: Reserved.
11: The pin function is GPIO13
GPIO12/WDTRST# function select.
00: The pin function is WDTRST#.
5-4
GPIO12_SEL
R/W
11b
01: reserved.
10: reserved.
11: The pin function is GPIO12.
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FANCTRL3/GPIO11/IRTX1 function select.
00: The pin function is FANCTRL3.
3-2
GPIO11_SEL
R/W
00b
01: The pin function is IRTX1.
10: Reserved.
11: The pin function is GPIO11.
FANIN3/GPIO10/IRRX1 function select.
00: The pin function is FANIN3.
1-0
GPIO10_SEL
R/W
00b
01: The pin function is IRRX1.
10: Reserved.
11: The pin function is GPIO10.
8.1.13
Multi Function Select 3 Register ⎯ Index 2Ch (Powered by VSB3V)
Bit
Name
R/W Default
7
GPIO1/2_Clear
R/W
0
6
UR2_GP_EN2
R/W
0
5
UR2_GP_EN1
R/W
0
4
FDC_GP_EN
R/W
0
Description
0: Cleared by 3VSB
1: Cleared by LRESET#
0: Pin2~4 and pin126~128 function as UART2 modem control.
1: Pin2~4 and pin126~128 function as GPIO3x.
0: Pin5, 6 function as UART2 SOUT2/SIN2.
1: Pin5, 6 function as GPIO3x.
0: Pin 7 ~ 19 function as FDC.
1: Pin 7 ~19 function as GPIOs.
PECI/TSI_DAT/IBX_SDA/GPIO16 function select.
3
GPIO16_SEL
R/W
0
0: The pin function is PECI/TSI_DAT/IBX_SDA decided by INTEL_MODEL
register.
1: The pin function is GPIO16.
SST/TSI_CLK/IBX_CLK/GPIO15 function select.
2
GPIO15_SEL
R/W
0
0: The pin function is SST/TSI_CLK/IBX_CLK decided by INTEL_MODEL
register.
1: The pin function is GPIO15.
PECI_AVL/IRRX/GPIO14 function select.
00: The pin function is PECI_AVL.
1-0
GPIO14_SEL
R/W
00b
01: The pin function is IRRX.
10: Reserved.
11: The pin function is GPIO14.
8.1.14
Wakeup Control Register ⎯ Index 2Dh (Powered by VBAT)
Bit
Name
7
SLOT_PWR_SEL
R/W Default
R/W
0
Description
0: SLOTOCC# is pull-up to VSB3V.
1: SLOTOCC# is pull-up to VBAT.
0: RSMRST# will sink low when VSB3V is below 2.6V.
6
VSBOK_HYS_DIS
R/W
0
1: RSMRST# will sink low when VSB3V is below 2.95V.
VSB3V power good level is 2.95V.
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S3_Reset
R/W
0
5
VREF_S3
R/W
0
4
KEY_SEL_ADD
R/W
0
3
WAKEUP_EN
R/W
1
0: VREF1~3 settings are kept when S3# becomes low
1: VREF1~3 will be reset to default when S3# becomes low
1: VREF2 and 3 keep power on In the S3 state
0: VREF2 and 3 are power down In the S3 state
This bit is added to add more wakeup key function.
0: disable keyboard/mouse wake up.
1: enable keyboard/mouse wake up.
This registers select the keyboard wake up key. Accompanying with
KEY_SEL_ADD, there are eight wakeup keys:
2-1
KEY_SEL
R/W
00
KEY_SEL_ADD
KEY_SEL
Wakeup Key
0
00
Ctrl + Esc
0
01
Ctrl + F1
0
10
Ctrl + Space
0
11
Any Key
1
00
Windows Wakeup
1
01
Windows Power
1
10
Ctrl + Alt + Space
1
11
Space
This register selects the mouse wake up key.
0
MO_SEL
R/W
0
0: Wake up by click.
1: Wake up by click and movement.
8.2 FDC Registers (CR00)
FDC Device Enable Register ⎯ Index 30h
Bit
Name
R/W Default
Description
7-1
Reserved
-
-
Reserved
0
FDC_EN
R/W
1
0: disable FDC.
1: enable FDC.
Base Address High Register ⎯ Index 60h
Bit
Name
7-0
BASE_ADDR_HI
R/W Default
R/W
03h
Description
The MSB of FDC base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
7-0
BASE_ADDR_LO
R/W Default
R/W
F0h
Description
The LSB of FDC base address.
IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Default
7-4
Reserved
-
-
3-0
SELFDCIRQ
R/W
06h
Description
Reserved.
Select the IRQ channel for FDC.
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DMA Channel Select Register ⎯ Index 74h
Bit
Name
R/W Default
7-3
Reserved
-
-
2-0
SELFDCDMA
R/W
010
Description
Reserved.
Select the DMA channel for FDC.
FDD Mode Register ⎯ Index F0h
Bit
Name
R/W Default
Description
7-5
Reserved
-
-
Reserved.
4
FDC_SW_WP
R/W
0
Write “1” to this bit will force FDC to write protect. Otherwise, write protect is
controlled by hardware pin WP#.
3-2
IF_MODE
R/W
11
00: Model 30 mode.
01: PS/2 mode.
10: Reserved.
11: AT mode (default).
1
FDMAMODE
R/W
1
0: enable burst mode.
1: non-busrt mode (default).
0
Reserved
R/W
0
Reserved
FDD Drive Type Register ⎯ Index F2h
Bit
Name
R/W Default
7-2
Reserved
-
-
1-0
FDD_TYPE
R/W
11
Description
Reserved.
FDD drive type.
FDD Selection Register ⎯ Index F4h
Bit
Name
7-5
Reserved
R/W Default
-
-
4-3
FDD_DRT
R/W
00
2
Reserved
-
-
1-0
FDD_DT
R/W
00
TABLE A
Data Rate Table Select
FDD_DRT[1]
0
0
1
FDD_DRT[0]
0
1
0
Description
Reserved.
Data rate table select, refer to table A.
00: select regular drives and 2.88 format.
01: Reserved.
10: 2 mega tape.
11: reserved.
Reserved.
Drive type select, refer to table B.
Data Rate
Selected Data Rate
DENSEL
DATARATE1
DATARATE0
MFM
FM
0
0
500K
250K
1
0
1
300K
150K
0
1
0
250K
125K
0
1
1
1Meg
---
1
0
0
500K
250K
1
0
1
500K
250K
0
1
0
250K
125K
0
1
1
1Meg
---
1
0
0
500K
250K
1
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0
1
2Meg
---
0
1
0
250K
125K
0
1
1
1Meg
---
1
TABLE B
Drive Type
FDD_DT1
DRVDEN0
FDD_DT0
0
DENSEL
0
1
DATARATE1
1
0
DENSEL#
1
1
DATARATE0
Remark
4/2/1 MB 3.5”
2/1 MB 5.25”
0
8.3 UART1 Registers (CR01)
UART 1 Device Enable Register ⎯ Index 30h
Bit
Name
R/W Default
Description
7-1
Reserved
-
-
Reserved
0
UR1_EN
R/W
1
0: disable UART 1.
1: enable UART 1.
Base Address High Register ⎯ Index 60h
Bit
Name
7-0
BASE_ADDR_HI
R/W Default
R/W
03h
Description
The MSB of UART 1 base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
7-0
BASE_ADDR_LO
R/W Default
R/W
F8h
Description
The LSB of UART 1 base address.
IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Default
7-4
Reserved
-
-
3-0
SELUR1IRQ
R/W
4h
Description
Reserved.
Select the IRQ channel for UART 1.
RS485 Enable Register ⎯ Index F0h
Bit
Name
R/W Default
Description
7-5
Reserved
-
-
Reserved.
4
RS485_EN
R/W
0
0: RS232 driver.
1: RS485 driver. Auto drive RTS# low when transmitting data.
3-0
Reserved
-
-
Reserved.
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8.4 UART 2 Registers (CR02)
UART 2 Device Enable Register ⎯ Index 30h
Bit
Name
R/W Default
Description
7-1
Reserved
-
-
Reserved
0
UR2_EN
R/W
1
0: disable UART 2.
1: enable UART 2.
Base Address High Register ⎯ Index 60h
Bit
Name
7-0
BASE_ADDR_HI
R/W Default
R/W
02h
Description
The MSB of UART 2 base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
7-0
BASE_ADDR_LO
R/W Default
R/W
F8h
Description
The LSB of UART 2 base address.
IRQ Channel Select Register ⎯ Index 70h
Bit
Name
7-4
Reserved
R/W Default
-
-
3-0
SELUR2IRQ
R/W
3h
Description
Reserved.
Select the IRQ channel for UART 2.
RS485 Enable Register ⎯ Index F0h
Bit
Name
R/W Default
Description
7-5
Reserved
-
-
Reserved.
4
RS485_EN
R/W
0
0: RS232 driver.
1: RS485 driver. Auto drive RTS# low when transmitting data.
3
RXW4C_IR
R/W
0
0: No reception delay when SIR is changed form TX to RX.
1: Reception delays 4 characters time when SIR is changed form TX to RX.
2
TXW4C_IR
R/W
0
0: No transmission delay when SIR is changed form RX to TX.
1: Transmission delays 4 characters time when SIR is changed form RX to
TX.
1-0
Reserved
-
-
Reserved.
SIR Mode Control Register ⎯ Index F1h
Bit
Name
R/W Default
Description
7
Reserved
-
-
Reserved.
6
Reserved
-
-
Reserved.
5
Reserved
-
-
Reserved.
4-3
IRMODE
R/W
00
00: disable IR function.
01: disable IR function.
10: IrDA function, active pulse is 1.6uS.
11: IrDA function, active pulse is 3/16 bit time.
2
HDUPLX
R/W
1
0: SIR is in full duplex mode for loopbak test. TXW4C_IR and RXW4C_IR
are of no use.
1: SIR is in half duplex mode.
1
TXINV_IR
R/W
0
0: IRTX1 is in normal condition.
1: inverse the IRTX1.
0
RXINV_IR
R/W
0
0: IRRX1is in normal condition.
1: inverse the IRRX1.
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8.5 Parallel Port Registers (CR03)
Parallel Port Device Enable Register ⎯ Index 30h
Bit
Name
R/W Default
Description
7-1
Reserved
-
-
Reserved
0
PRT_EN
R/W
1
0: disable Parallel Port.
1: enable Parallel Port.
Base Address High Register ⎯ Index 60h
Bit
Name
7-0
BASE_ADDR_HI
R/W Default
R/W
03h
Description
The MSB of Parallel Port base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
7-0
BASE_ADDR_LO
R/W Default
R/W
78h
Description
The LSB of Parallel Port base address.
IRQ Channel Select Register ⎯ Index 70h
Bit
Name
7-5
Reserved
R/W Default
-
-
3-0
SELPRTIRQ
R/W
7h
Description
Reserved.
Select the IRQ channel for Parallel Port.
DMA Channel Select Register ⎯ Index 74h
Bit
Name
R/W Default
Description
7-5
Reserved
-
-
Reserved.
4
ECP_DMA_MODE
R/W
0
0: non-burst mode DMA.
1: enable burst mode DMA.
3
Reserved
-
-
Reserved.
2-0
SELPRTDMA
R/W
011
Select the DMA channel for Parallel Port.
PRT Mode Select Register ⎯ Index F0h
Bit
Name
R/W Default
Description
Interrupt mode in non-ECP mode.
0: Level mode.
1: Pulse mode.
7
SPP_IRQ_MODE
R/W
0
6-3
ECP_FIFO_THR
R/W
1000
ECP FIFO threshold.
010
000: Standard and Bi-direction (SPP) mode.
001: EPP 1.9 and SPP mode.
010: ECP mode (default).
011: ECP and EPP 1.9 mode.
100: Printer mode.
101: EPP 1.7 and SPP mode.
110: Reserved.
111: ECP and EPP1.7 mode.
2-0
PRT_MODE
R/W
8.6 Hardware Monitor Registers (CR04)
8.6.1
Hardware Monitor Configuration Registers
Hardware Monitor Device Enable Register ⎯ Index 30h
Bit
Name
7-1
Reserved
R/W Default
-
-
Description
Reserved
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HM_EN
R/W
1
0: disable Hardware Monitor.
1: enable Hardware Monitor.
Base Address High Register ⎯ Index 60h
Bit
Name
7-0
BASE_ADDR_HI
R/W Default
R/W
02h
Description
The MSB of Hardware Monitor base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
7-0
BASE_ADDR_LO
R/W Default
R/W
95h
Description
The LSB of Hardware Monitor base address.
IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Default
7-4
Reserved
-
-
3-0
SELHMIRQ
R/W
0000
Description
Reserved.
Select the IRQ channel for Hardware Monitor.
8.7 KBC Registers (CR05)
KBC Device Enable Register ⎯ Index 30h
Bit
Name
R/W Default
Description
7-1
Reserved
-
-
Reserved
0
KBC_EN
R/W
1
0: disable KBC.
1: enable KBC.
Base Address High Register ⎯ Index 60h
Bit
Name
7-0
BASE_ADDR_HI
R/W Default
R/W
00h
Description
The MSB of KBC command port address. The address of data port is
command port address + 4;
Base Address Low Register ⎯ Index 61h
Bit
Name
7-0
BASE_ADDR_LO
R/W Default
R/W
60h
Description
The LSB of KBC command port address. The address of data port is
command port address + 4.
KB IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Default
7-4
Reserved
-
-
3-0
SELKIRQ
R/W
1h
Description
Reserved.
Select the IRQ channel for keyboard interrupt.
Mouse IRQ Channel Select Register ⎯ Index 72h
Bit
Name
R/W Default
7-4
Reserved
-
-
3-0
SELMIRQ
R/W
Ch
Description
Reserved.
Select the IRQ channel for PS/2 mouse interrupt.
Auto Swap Register ⎯ Index FEh (Powered by VBAT)
Bit
Name
R/W Default
7
AUTO_DET_EN
R/W
1b
6-5
Reserved
-
-
Description
0: disable auto detect keyboard/mouse swap.
1: enable auto detect keyboard/mouse swap.
Reserved.
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KB_MO_SWAP
R/W
0b
0: Keyboard/mouse not swap.
1: Keyboard/mouse swap.
This bit is set/clear by hardware if AUTO_DET_EN is set to “1”. Users could
also program this bit manually.
3-0
Reserved
R/W
1h
Reserved
8.8 GPIO Registers (CR06) (All registers of GPIO are powered by VSB3V)
GPIO0 Output Enable Register ⎯ Index F0h
Bit
Name
R/W Default
Description
7
Reserved
-
-
Reserved.
6
GPIO06_OE
R/W
0
0: GPIO06 is in input mode.
1: GPIO06 is in output mode.
5
GPIO05_OE
R/W
0
0: GPIO05 is in input mode.
1: GPIO05 is in output mode.
4
GPIO04_OE
R/W
0
0: GPIO04 is in input mode.
1: GPIO04 is in output mode.
3
GPIO03_OE
R/W
0
0: GPIO03 is in input mode.
1: GPIO03 is in output mode.
2
GPIO02_OE
R/W
0
0: GPIO02 is in input mode.
1: GPIO02 is in output mode.
1
GPIO01_OE
R/W
0
0: GPIO01 is in input mode.
1: GPIO01 is in output mode.
0
GPIO00_OE
R/W
0
0: GPIO00 is in input mode.
1: GPIO00 is in output mode.
GPIO0 Output Data Register ⎯ Index F1h
Bit
Name
R/W Default
Description
7
Reserved
-
-
Reserved.
6
GPIO06_VAL
R/W
1
0: GPIO06 outputs 0 when in output mode.
1: GPIO06 outputs1 when in output mode.
5
GPIO05_VAL
R/W
1
0: GPIO05 outputs 0 when in output mode.
1: GPIO05 outputs 1 when in output mode.
4
GPIO04_VAL
R/W
1
0: GPIO04 outputs 0 when in output mode.
1: GPIO04 outputs 1 when in output mode.
3
GPIO03_VAL
R/W
1
0: GPIO03 outputs 0 when in output mode.
1: GPIO03 outputs 1 when in output mode.
2
GPIO02_VAL
R/W
1
0: GPIO02 outputs 0 when in output mode.
1: GPIO02 outputs 1 when in output mode.
1
GPIO01_VAL
R/W
1
0: GPIO01 outputs 0 when in output mode.
1: GPIO01 outputs 1 when in output mode.
0
GPIO00_VAL
R/W
1
0: GPIO00 outputs 0 when in output mode.
1: GPIO00 outputs 1 when in output mode.
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GPIO0 Pin Status Register ⎯ Index F2h
Bit
Name
R/W Default
Description
7
Reserved
-
-
Reserved.
6
GPIO06_IN
R
-
The pin status of GPIO06/Beep/Alert#.
5
GPIO05_IN
R
-
The pin status of GPIO05/LED_VCC.
4
GPIO04_IN
R
-
The pin status of GPIO04/LED_VSB.
3
GPIO03_IN
R
-
The pin status of SLOTCC#/GPIO03.
2
GPIO02_IN
R
-
The pin status of BUSOUT2/GPIO02.
1
GPIO01_IN
R
-
The pin status of BUSOUT1/GPIO01.
0
GPIO00_IN
R
-
The pin status of BUSOUT0/GPIO00.
GPIO0 Drive Enable Register ⎯ Index F3h
Bit
Name
R/W Default
Description
7
Reserved
-
-
Reserved.
6
GPIO06_DRV_EN
R/W
0
0: GPIO06 is open drain in output mode.
1: GPIO06 is push pull in output mode.
5
GPIO05_DRV_EN
R/W
0
0: GPIO05 is open drain in output mode.
1: GPIO05 is push pull in output mode.
4
GPIO04_DRV_EN
R/W
0
0: GPIO04 is open drain in output mode.
1: GPIO04 is push pull in output mode.
3
GPIO03_DRV_EN
R/W
0
0: GPIO03 is open drain in output mode.
1: Reserved.
2
GPIO02_DRV_EN
R/W
0
0: GPIO02 is open drain in output mode.
1: GPIO02 is push pull in output mode.
1
GPIO01_DRV_EN
R/W
0
0: GPIO01 is open drain in output mode.
1: GPIO01 is push pull in output mode.
0
GPIO00_DRV_EN
R/W
0
0: GPIO00 is open drain in output mode.
1: GPIO00 is push pull in output mode.
LED_VSB Control Register ⎯ Index FEh
Bit
Name
7-6
Reserved
5-4
3-2
LED_VSB_S5_MODE
LED_VSB_S3_MODE
R/W Default
-
R/W
R/W
Description
-
Reserved.
0
These bits control the LED_VSB output mode in S5 state.
00: Sink 0
01: Tri-state.
10: 0.5Hz clock
11: 1Hz clock.
0
These bits control the LED_VSB output mode in S3 state.
00: Sink 0
01: Tri-state.
10: 0.5Hz clock
11: 1Hz clock.
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LED_VSB_S0_MODE
R/W
0
These bits control the LED_VSB output mode in S0 state.
00: Sink 0
01: Tri-state.
10: 0.5Hz clock
11: 1Hz clock.
LED_VCC Control Register ⎯ Index FFh
Bit
Name
7-6
Reserved
5-4
3-2
1-0
LED_VCC_S5_MODE
LED_VCC_S3_MODE
LED_VCC_S0_MODE
R/W Default
-
R/W
R/W
R/W
Description
-
Reserved.
0
These bits control the LED_VCC output mode in S5 state.
00: Sink 0
01: Tri-state.
10: 0.5Hz clock
11: 1Hz clock.
0
These bits control the LED_VCC output mode in S3 state.
00: Sink 0
01: Tri-state.
10: 0.5Hz clock
11: 1Hz clock.
0
These bits control the LED_VCC output mode in S0 state.
00: Sink 0
01: Tri-state.
10: 0.5Hz clock
11: 1Hz clock.
GPIO1 Output Enable Register ⎯ Index E0h
Bit
Name
R/W Default
Description
7
Reserved
-
-
Reserved.
6
GPIO16_OE
R/W
0
0: GPIO16 is in input mode.
1: GPIO16 is in output mode.
5
GPIO15_OE
R/W
0
0: GPIO15 is in input mode.
1: GPIO15 is in output mode.
4
GPIO14_OE
R/W
0
0: GPIO14 is in input mode.
1: GPIO14 is in output mode.
3
GPIO13_OE
R/W
0
0: GPIO13 is in input mode.
1: GPIO13 is in output mode.
2
GPIO12_OE
R/W
0
0: GPIO12 is in input mode.
1: GPIO12 is in output mode.
1
GPIO11_OE
R/W
0
0: GPIO11 is in input mode.
1: GPIO11 is in output mode.
0
GPIO10_OE
R/W
0
0: GPIO10 is in input mode.
1: GPIO10 is in output mode.
GPIO1 Output Data Register ⎯ Index E1h
Bit
Name
7
Reserved
R/W Default
-
-
Description
Reserved.
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GPIO16_VAL
R/W
1
0: GPIO16 outputs 0 when in output mode.
1: GPIO16 outputs1 when in output mode.
5
GPIO15_VAL
R/W
1
0: GPIO15 outputs 0 when in output mode.
1: GPIO15 outputs 1 when in output mode.
4
GPIO14_VAL
R/W
1
0: GPIO14 outputs 0 when in output mode.
1: GPIO14 outputs 1 when in output mode.
3
GPIO13_VAL
R/W
1
0: GPIO13 outputs 0 when in output mode.
1: GPIO13 outputs 1 when in output mode.
2
GPIO12_VAL
R/W
1
0: GPIO12 outputs 0 when in output mode.
1: GPIO12 outputs 1 when in output mode.
1
GPIO11_VAL
R/W
1
0: GPIO11 outputs 0 when in output mode.
1: GPIO11 outputs 1 when in output mode.
0
GPIO10_VAL
R/W
1
0: GPIO10 outputs 0 when in output mode.
1: GPIO10 outputs 1 when in output mode.
GPIO1 Pin Status Register ⎯ Index E2h
Bit
Name
R/W Default
Description
7
Reserved
-
-
Reserved.
6
GPIO16_IN
R
-
The pin status of PECI/TSI_DAT/IBX_SDA/GPIO16
5
GPIO15_IN
R
-
The pin status of SST/TSI_CLK/IBX_CLK/GPIO15.
4
GPIO14_IN
R
-
The pin status of PECI_AVL/IRRX/GPIO14.
3
GPIO13_IN
R
-
The pin status of PECI_REQ#/IRTX/GPIO13.
2
GPIO12_IN
R
-
The pin status of GPIO12/WDTRST#
1
GPIO11_IN
R
-
The pin status of FANCTL3/GPIO11/IRTX1.
0
GPIO10_IN
R
-
The pin status of FANIN3/GPIO10/IRRX1.
GPIO1 Drive Enable Register ⎯ Index E3h
Bit
Name
R/W Default
Description
7
Reserved
-
-
Reserved.
6
GPIO16_DRV_EN
R/W
0
0: GPIO16 is open drain in output mode.
1: GPIO16 is push pull in output mode.
5
GPIO15_DRV_EN
R/W
0
0: GPIO15 is open drain in output mode.
1: GPIO15 is push pull in output mode.
4
GPIO14_DRV_EN
R/W
0
0: GPIO14 is open drain in output mode.
1: GPIO14 is push pull in output mode.
3
GPIO13_DRV_EN
R/W
0
0: GPIO13 is open drain in output mode.
1: GPIO13 is push pull in output mode.
2
GPIO12_DRV_EN
R/W
0
0: GPIO12 is open drain in output mode.
1: GPIO12 is push pull in output mode.
1
GPIO11_DRV_EN
R/W
0
0: GPIO11 is open drain in output mode.
1: GPIO11 is push pull in output mode.
0
GPIO10_DRV_EN
R/W
0
0: GPIO10 is open drain in output mode.
1: GPIO10 is push pull in output mode.
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GPIO2 Output Enable Register ⎯ Index D0h
Bit
Name
R/W Default
Description
7
GPIO27_OE
R/W
0
0: GPIO27 is in input mode.
1: GPIO27 is in output mode.
6
GPIO26_OE
R/W
0
0: GPIO26 is in input mode.
1: GPIO25 is in output mode.
5
GPIO25_OE
R/W
0
0: GPIO25 is in input mode.
1: GPIO25 is in output mode.
4
GPIO24_OE
R/W
0
0: GPIO24 is in input mode.
1: GPIO24 is in output mode.
3
GPIO23_OE
R/W
0
0: GPIO23 is in input mode.
1: GPIO23 is in output mode.
2
GPIO22_OE
R/W
0
0: GPIO22 is in input mode.
1: GPIO22 is in output mode.
1
GPIO21_OE
R/W
0
0: GPIO21 is in input mode.
1: GPIO21 is in output mode.
0
GPIO20_OE
R/W
0
0: GPIO20 is in input mode.
1: GPIO20 is in output mode.
GPIO2 Output Data Register ⎯ Index D1h
Bit
Name
R/W Default
Description
7
GPIO27_VAL
R/W
1
0: GPIO27 outputs 0 when in output mode.
1: GPIO27 outputs 1 when in output mode.
6
GPIO26_VAL
R/W
1
0: GPIO26 outputs 0 when in output mode.
1: GPIO26 outputs 1 when in output mode.
5
GPIO25_VAL
R/W
1
0: GPIO25 outputs 0 when in output mode.
1: GPIO25 outputs 1 when in output mode.
4
GPIO24_VAL
R/W
1
0: GPIO24 outputs 0 when in output mode.
1: GPIO24 outputs 1 when in output mode.
3
GPIO23_VAL
R/W
1
0: GPIO23 outputs 0 when in output mode.
1: GPIO23 outputs 1 when in output mode.
2
GPIO22_VAL
R/W
1
0: GPIO22 outputs 0 when in output mode.
1: GPIO22 outputs 1 when in output mode.
1
GPIO21_VAL
R/W
1
0: GPIO21 outputs 0 when in output mode.
1: GPIO21 outputs 1 when in output mode.
0
GPIO20_VAL
R/W
1
0: GPIO20 outputs 0 when in output mode.
1: GPIO20 outputs 1 when in output mode.
GPIO2 Pin Status Register ⎯ Index D2h
Bit
Name
R/W Default
Description
7
GPIO27_IN
R
-
The pin status of BSUIN2/GPIO27.
6
GPIO26_IN
R
-
The pin status of BUSIN1/GPIO26.
5
GPIO25_IN
R
-
The pin status of BUSIN0/GPIO25.
4
GPIO24_IN
R
-
The pin status of GPIO24/FWH_DIS.
3
GPIO23_IN
R
-
The pin status of GPIO23/SPI_MOSI.
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GPIO22_IN
R
-
The pin status of GPIO22/SPI_MISO.
1
GPIO21_IN
R
-
The pin status of GPIO21/SPI_CS0#.
0
GPIO20_IN
R
-
The pin status of GPIO20/SPI_SLK#.
GPIO2 Drive Enable Register ⎯ Index D3h
Bit
Name
R/W Default
Description
7
GPIO27_DRV_EN
R/W
0
0: GPIO27 is open drain in output mode.
1: GPIO27 is push pull in output mode.
6
GPIO26_DRV_EN
R/W
0
0: GPIO26 is open drain in output mode.
1: GPIO26 is push pull in output mode.
5
GPIO25_DRV_EN
R/W
0
0: GPIO25 is open drain in output mode.
1: GPIO25 is push pull in output mode.
4
GPIO24_DRV_EN
R/W
0
0: GPIO24 is open drain in output mode.
1: GPIO24 is push pull in output mode.
3
GPIO23_DRV_EN
R/W
0
0: GPIO23 is open drain in output mode.
1: GPIO23 is push pull in output mode.
2
GPIO22_DRV_EN
R/W
0
0: GPIO22 is open drain in output mode.
1: GPIO22 is push pull in output mode.
1
GPIO21_DRV_EN
R/W
0
0: GPIO21 is open drain in output mode.
1: GPIO21 is push pull in output mode.
0
GPIO20_DRV_EN
R/W
0
0: GPIO20 is open drain in output mode.
1: GPIO20 is push pull in output mode.
GPIO3 Output Enable Register ⎯ Index C0h
Bit
Name
R/W Default
Description
7
GPIO37_OE
R/W
0
0: GPIO37 is in input mode.
1: GPIO37 is in output mode.
6
GPIO36_OE
R/W
0
0: GPIO36 is in input mode.
1: GPIO35 is in output mode.
5
GPIO35_OE
R/W
0
0: GPIO35 is in input mode.
1: GPIO35 is in output mode.
4
GPIO34_OE
R/W
0
0: GPIO34 is in input mode.
1: GPIO34 is in output mode.
3
GPIO33_OE
R/W
0
0: GPIO33 is in input mode.
1: GPIO33 is in output mode.
2
GPIO32_OE
R/W
0
0: GPIO32 is in input mode.
1: GPIO32 is in output mode.
1
GPIO31_OE
R/W
0
0: GPIO31 is in input mode.
1: GPIO31 is in output mode.
0
GPIO30_OE
R/W
0
0: GPIO30 is in input mode.
1: GPIO30 is in output mode.
GPIO3 Output Data Register ⎯ Index C1h
Bit
Name
7
GPIO37_VAL
R/W Default
R/W
1
Description
0: GPIO37 outputs 0 when in output mode.
1: GPIO37 outputs 1 when in output mode.
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GPIO36_VAL
R/W
1
0: GPIO36 outputs 0 when in output mode.
1: GPIO36 outputs 1 when in output mode.
5
GPIO35_VAL
R/W
1
0: GPIO35 outputs 0 when in output mode.
1: GPIO35 outputs 1 when in output mode.
4
GPIO34_VAL
R/W
1
0: GPIO34 outputs 0 when in output mode.
1: GPIO34 outputs 1 when in output mode.
3
GPIO33_VAL
R/W
1
0: GPIO33 outputs 0 when in output mode.
1: GPIO33 outputs 1 when in output mode.
2
GPIO32_VAL
R/W
1
0: GPIO32 outputs 0 when in output mode.
1: GPIO32 outputs 1 when in output mode.
1
GPIO31_VAL
R/W
1
0: GPIO31 outputs 0 when in output mode.
1: GPIO31 outputs 1 when in output mode.
0
GPIO30_VAL
R/W
1
0: GPIO30 outputs 0 when in output mode.
1: GPIO30 outputs 1 when in output mode.
GPIO3 Pin Status Register ⎯ Index C2h
Bit
Name
R/W Default
Description
7
GPIO37_IN
R
-
The pin status of SIN2/SEGE/GPIO37.
6
GPIO36_IN
R
-
The pin status of SOUT2/SEGB/GPIO36/SPI_TRAP.
5
GPIO35_IN
R
-
The pin status of DSR2#/L#/GPIO35.
4
GPIO34_IN
R
-
The pin status of RTS2#/SEGC/GPIO34/PWM_DC.
3
GPIO33_IN
R
-
The pin status of DTR2#/SEGD/GPIO33/FWH_TRAP.
2
GPIO32_IN
R
-
The pin status of CTS2#/SEGA/GPIO32.
1
GPIO31_IN
R
-
The pin status of RI2#/GPIO31.
0
GPIO30_IN
R
-
The pin status of DCD2#/GPIO30.
GPIO3 Drive Enable Register ⎯ Index C3h
Bit
Name
R/W Default
Description
7
GPIO37_DRV_EN
R/W
0
0: GPIO37 is open drain in output mode.
1: GPIO37 is push pull in output mode.
6
GPIO36_DRV_EN
R/W
0
0: GPIO36 is open drain in output mode.
1: GPIO36 is push pull in output mode.
5
GPIO35_DRV_EN
R/W
0
0: GPIO35 is open drain in output mode.
1: GPIO35 is push pull in output mode.
4
GPIO34_DRV_EN
R/W
0
0: GPIO34 is open drain in output mode.
1: GPIO34 is push pull in output mode.
3
GPIO33_DRV_EN
R/W
0
0: GPIO33 is open drain in output mode.
1: GPIO33 is push pull in output mode.
2
GPIO32_DRV_EN
R/W
0
0: GPIO32 is open drain in output mode.
1: GPIO32 is push pull in output mode.
1
GPIO31_DRV_EN
R/W
0
0: GPIO31 is open drain in output mode.
1: GPIO31 is push pull in output mode.
0
GPIO30_DRV_EN
R/W
0
0: GPIO30 is open drain in output mode.
1: GPIO30 is push pull in output mode.
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GPIO4 Output Enable Register ⎯ Index B0h
Bit
Name
R/W Default
Description
7
GPIO47_OE
R/W
0
0: GPIO47 is in input mode.
1: GPIO47 is in output mode.
6
GPIO46_OE
R/W
0
0: GPIO46 is in input mode.
1: GPIO45 is in output mode.
5
GPIO45_OE
R/W
0
0: GPIO45 is in input mode.
1: GPIO45 is in output mode.
4
GPIO44_OE
R/W
0
0: GPIO44 is in input mode.
1: GPIO44 is in output mode.
3
GPIO43_OE
R/W
0
0: GPIO43 is in input mode.
1: GPIO43 is in output mode.
2
GPIO42_OE
R/W
0
0: GPIO42 is in input mode.
1: GPIO42 is in output mode.
1
GPIO41_OE
R/W
0
0: GPIO41 is in input mode.
1: GPIO41 is in output mode.
0
GPIO40_OE
R/W
0
0: GPIO40 is in input mode.
1: GPIO40 is in output mode.
GPIO4 Output Data Register ⎯ Index B1h
Bit
Name
R/W Default
Description
7
GPIO47_VAL
R/W
1
0: GPIO47 outputs 0 when in output mode.
1: GPIO47 outputs 1 when in output mode.
6
GPIO46_VAL
R/W
1
0: GPIO46 outputs 0 when in output mode.
1: GPIO46 outputs 1 when in output mode.
5
GPIO45_VAL
R/W
1
0: GPIO45 outputs 0 when in output mode.
1: GPIO45 outputs 1 when in output mode.
4
GPIO44_VAL
R/W
1
0: GPIO44 outputs 0 when in output mode.
1: GPIO44 outputs 1 when in output mode.
3
GPIO43_VAL
R/W
1
0: GPIO43 outputs 0 when in output mode.
1: GPIO43 outputs 1 when in output mode.
2
GPIO42_VAL
R/W
1
0: GPIO42 outputs 0 when in output mode.
1: GPIO42 outputs 1 when in output mode.
1
GPIO41_VAL
R/W
1
0: GPIO41 outputs 0 when in output mode.
1: GPIO41 outputs 1 when in output mode.
0
GPIO40_VAL
R/W
1
0: GPIO40 outputs 0 when in output mode.
1: GPIO40 outputs 1 when in output mode.
GPIO4 Pin Status Register ⎯ Index B2h
Bit
Name
R/W Default
Description
7
GPIO47_IN
R
-
The pin status of WGATE#/GPIO47.
6
GPIO46_IN
R
-
The pin status of HDSEL#/GPIO46.
5
GPIO45_IN
R
-
The pin status of STEP#/GPIO45.
4
GPIO44_IN
R
-
The pin status of DIR#/GPIO44.
3
GPIO43_IN
R
-
The pin status of WDATA#/GPIO43.
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GPIO42_IN
R
-
The pin status of DRVA#/GPIO42.
1
GPIO41_IN
R
-
The pin status of MOA#/GPIO41.
0
GPIO40_IN
R
-
The pin status of DENSEL#/GPIO40.
GPIO5 Output Enable Register ⎯ Index A0h
Bit
Name
R/W Default
Description
7-5
Reserved
-
-
Reserved.
4
GPIO54_OE
R/W
0
0: GPIO54 is in input mode.
1: GPIO54 is in output mode.
3
GPIO53_OE
R/W
0
0: GPIO53 is in input mode.
1: GPIO53 is in output mode.
2
GPIO52_OE
R/W
0
0: GPIO52 is in input mode.
1: GPIO52 is in output mode.
1
GPIO51_OE
R/W
0
0: GPIO51 is in input mode.
1: GPIO51 is in output mode.
0
GPIO50_OE
R/W
0
0: GPIO50 is in input mode.
1: GPIO50 is in output mode.
GPIO5 Output Data Register ⎯ Index A1h
Bit
Name
R/W Default
Description
7-5
Reserved
-
-
Reserved.
4
GPIO54_VAL
R/W
1
0: GPIO54 outputs 0 when in output mode.
1: GPIO54 outputs 1 when in output mode.
3
GPIO53_VAL
R/W
1
0: GPIO53 outputs 0 when in output mode.
1: GPIO53 outputs 1 when in output mode.
2
GPIO52_VAL
R/W
1
0: GPIO52 outputs 0 when in output mode.
1: GPIO52 outputs 1 when in output mode.
1
GPIO51_VAL
R/W
1
0: GPIO51 outputs 0 when in output mode.
1: GPIO51 outputs 1 when in output mode.
0
GPIO50_VAL
R/W
1
0: GPIO50 outputs 0 when in output mode.
1: GPIO50 outputs 1 when in output mode.
GPIO5 Pin Status Register ⎯ Index A2h
Bit
Name
R/W Default
Description
7-5
Reserved
-
-
Reserved.
4
GPIO54_IN
R
-
The pin status of DSKCHG#/GPIO54.
3
GPIO53_IN
R
-
The pin status of WPT#/GPIO53.
2
GPIO52_IN
R
-
The pin status of INDEX#/GPIO52.
1
GPIO51_IN
R
-
The pin status of TRK0#/GPIO51.
0
GPIO50_IN
R
-
The pin status of RDDATA#/GPIO50.
GPIO5 Drive Enable Register ⎯ Index A3h
Bit
Name
7-5
Reserved
R/W Default
-
-
Description
Reserved.
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GPIO54_DRV_EN
R/W
0
0: GPIO54 is open drain in output mode.
1: GPIO54 is push pull in output mode.
3
GPIO53_DRV_EN
R/W
0
0: GPIO53 is open drain in output mode.
1: GPIO53 is push pull in output mode.
2
GPIO52_DRV_EN
R/W
0
0: GPIO52 is open drain in output mode.
1: GPIO52 is push pull in output mode.
1
GPIO51_DRV_EN
R/W
0
0: GPIO51 is open drain in output mode.
1: GPIO51 is push pull in output mode.
0
GPIO50_DRV_EN
R/W
0
0: GPIO50 is open drain in output mode.
1: GPIO50 is push pull in output mode.
GPIO6 Output Enable Register ⎯ Index 90h
Bit
Name
R/W Default
Description
7
GPIO67_OE
R/W
0
0: GPIO67 is in input mode.
1: GPIO67 is in output mode.
6
GPIO66_OE
R/W
0
0: GPIO66 is in input mode.
1: GPIO65 is in output mode.
5
GPIO65_OE
R/W
0
0: GPIO65 is in input mode.
1: GPIO65 is in output mode.
4
GPIO64_OE
R/W
0
0: GPIO64 is in input mode.
1: GPIO64 is in output mode.
3
GPIO63_OE
R/W
0
0: GPIO63 is in input mode.
1: GPIO63 is in output mode.
2
GPIO62_OE
R/W
0
0: GPIO62 is in input mode.
1: GPIO62 is in output mode.
1
GPIO61_OE
R/W
0
0: GPIO61 is in input mode.
1: GPIO61 is in output mode.
0
GPIO60_OE
R/W
0
0: GPIO60 is in input mode.
1: GPIO60 is in output mode.
GPIO6 Output Data Register ⎯ Index 91h
Bit
Name
R/W Default
Description
7
GPIO67_VAL
R/W
1
0: GPIO67 outputs 0 when in output mode.
1: GPIO67 outputs 1 when in output mode.
6
GPIO66_VAL
R/W
1
0: GPIO66 outputs 0 when in output mode.
1: GPIO66 outputs 1 when in output mode.
5
GPIO65_VAL
R/W
1
0: GPIO65 outputs 0 when in output mode.
1: GPIO65 outputs 1 when in output mode.
4
GPIO64_VAL
R/W
1
0: GPIO64 outputs 0 when in output mode.
1: GPIO64 outputs 1 when in output mode.
3
GPIO63_VAL
R/W
1
0: GPIO63 outputs 0 when in output mode.
1: GPIO63 outputs 1 when in output mode.
2
GPIO62_VAL
R/W
1
0: GPIO62 outputs 0 when in output mode.
1: GPIO62 outputs 1 when in output mode.
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GPIO61_VAL
R/W
1
0: GPIO61 outputs 0 when in output mode.
1: GPIO61 outputs 1 when in output mode.
0
GPIO60_VAL
R/W
1
0: GPIO60 outputs 0 when in output mode.
1: GPIO60 outputs 1 when in output mode.
GPIO6 Pin Status Register ⎯ Index 92h
Bit
Name
R/W Default
Description
7
GPIO67_IN
R
-
The pin status of STB#/L#/VIDIN7/GPIO67.
6
GPIO66_IN
R
-
The pin status of AFD#/H#/VIDIN6/GPIO66.
5
GPIO65_IN
R
-
The pin status of ERR#/VIDIN5/GPIO65.
4
GPIO64_IN
R
-
The pin status of INIT#/VIDIN4/GPIO64.
3
GPIO63_IN
R
-
The pin status of ACK#/VIDIN3 (SVC_IN)/GPIO63.
2
GPIO62_IN
R
-
The pin status of BUSY/VIDIN2 (SVD_IN)/GPIO62.
1
GPIO61_IN
R
-
The pin status of PE/VIDIN1/GPIO61.
0
GPIO60_IN
R
-
The pin status of SLCT/VIDIN0/GPIO60.
GPIO6 Drive Enable Register ⎯ Index 93h
Bit
Name
R/W Default
Description
7
GPIO67_DRV_EN
R/W
0
0: GPIO67 is open drain in output mode.
1: GPIO67 is push pull in output mode.
6
GPIO66_DRV_EN
R/W
0
0: GPIO66 is open drain in output mode.
1: GPIO66 is push pull in output mode.
5
GPIO65_DRV_EN
R/W
0
0: GPIO65 is open drain in output mode.
1: GPIO65 is push pull in output mode.
4
GPIO64_DRV_EN
R/W
0
0: GPIO64 is open drain in output mode.
1: GPIO64 is push pull in output mode.
3
GPIO63_DRV_EN
R/W
0
0: GPIO63 is open drain in output mode.
1: GPIO63 is push pull in output mode.
2
GPIO62_DRV_EN
R/W
0
0: GPIO62 is open drain in output mode.
1: GPIO62 is push pull in output mode.
1
GPIO61_DRV_EN
R/W
0
0: GPIO61 is open drain in output mode.
1: GPIO61 is push pull in output mode.
0
GPIO60_DRV_EN
R/W
0
0: GPIO60 is open drain in output mode.
1: GPIO60 is push pull in output mode.
GPIO7 Output Enable Register ⎯ Index 80h
Bit
Name
R/W Default
Description
7
GPIO77_OE
R/W
0
0: GPIO77 is in input mode.
1: GPIO77 is in output mode.
6
GPIO76_OE
R/W
0
0: GPIO76 is in input mode.
1: GPIO75 is in output mode.
5
GPIO75_OE
R/W
0
0: GPIO75 is in input mode.
1: GPIO75 is in output mode.
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GPIO74_OE
R/W
0
0: GPIO74 is in input mode.
1: GPIO74 is in output mode.
3
GPIO73_OE
R/W
0
0: GPIO73 is in input mode.
1: GPIO73 is in output mode.
2
GPIO72_OE
R/W
0
0: GPIO72 is in input mode.
1: GPIO72 is in output mode.
1
GPIO71_OE
R/W
0
0: GPIO71 is in input mode.
1: GPIO71 is in output mode.
0
GPIO70_OE
R/W
0
0: GPIO70 is in input mode.
1: GPIO70 is in output mode.
GPIO7 Output Data Register ⎯ Index 81h
Bit
Name
R/W Default
Description
7
GPIO77_VAL
R/W
1
0: GPIO77 outputs 0 when in output mode.
1: GPIO77 outputs 1 when in output mode.
6
GPIO76_VAL
R/W
1
0: GPIO76 outputs 0 when in output mode.
1: GPIO76 outputs 1 when in output mode.
5
GPIO75_VAL
R/W
1
0: GPIO75 outputs 0 when in output mode.
1: GPIO75 outputs 1 when in output mode.
4
GPIO74_VAL
R/W
1
0: GPIO74 outputs 0 when in output mode.
1: GPIO74 outputs 1 when in output mode.
3
GPIO73_VAL
R/W
1
0: GPIO73 outputs 0 when in output mode.
1: GPIO73 outputs 1 when in output mode.
2
GPIO72_VAL
R/W
1
0: GPIO72 outputs 0 when in output mode.
1: GPIO72 outputs 1 when in output mode.
1
GPIO71_VAL
R/W
1
0: GPIO71 outputs 0 when in output mode.
1: GPIO71 outputs 1 when in output mode.
0
GPIO70_VAL
R/W
1
0: GPIO70 outputs 0 when in output mode.
1: GPIO70 outputs 1 when in output mode.
GPIO7 Pin Status Register ⎯ Index 82h
Bit
Name
R/W Default
Description
7
GPIO77_IN
R
-
The pin status of PD7/VIDOUT7/GPIO77.
6
GPIO76_IN
R
-
The pin status of PD6/SEGG/VIDOUT6/GPIO76.
5
GPIO75_IN
R
-
The pin status of PD5/SEGF/VIDOUT5/GPIO75.
4
GPIO74_IN
R
-
The pin status of PD4/SEGE/VIDOUT4/GPIO74.
3
GPIO73_IN
R
-
The pin status of PD3/SEGD/VIDOUT3 (SVC_OUT)/GPIO73.
2
GPIO72_IN
R
-
The pin status of PD2/SEGC/VIDOUT2 (SVD_OUT)/GPIO72.
1
GPIO71_IN
R
-
The pin status of PD1/SEGB/VIDOUT1/GPIO71.
0
GPIO70_IN
R
-
The pin status of PD0/SEGA/VIDOUT0/GPIO70.
GPIO7 Drive Enable Register ⎯ Index 83h
Bit
Name
7
GPIO77_DRV_EN
R/W Default
R/W
0
Description
0: GPIO77 is open drain in output mode.
1: GPIO77 is push pull in output mode.
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GPIO76_DRV_EN
R/W
0
0: GPIO76 is open drain in output mode.
1: GPIO76 is push pull in output mode.
5
GPIO75_DRV_EN
R/W
0
0: GPIO75 is open drain in output mode.
1: GPIO75 is push pull in output mode.
4
GPIO74_DRV_EN
R/W
0
0: GPIO74 is open drain in output mode.
1: GPIO74 is push pull in output mode.
3
GPIO73_DRV_EN
R/W
0
0: GPIO73 is open drain in output mode.
1: GPIO73 is push pull in output mode.
2
GPIO72_DRV_EN
R/W
0
0: GPIO72 is open drain in output mode.
1: GPIO72 is push pull in output mode.
1
GPIO71_DRV_EN
R/W
0
0: GPIO71 is open drain in output mode.
1: GPIO71 is push pull in output mode.
0
GPIO70_DRV_EN
R/W
0
0: GPIO70 is open drain in output mode.
1: GPIO70 is push pull in output mode.
8.9
VID Registers (CR07)
8.9.1
VID Configuration Registers
VID Device Enable Register ⎯ Index 30h
Bit
Name
R/W Default
Description
7-1
Reserved
-
0
Reserved
0
VID_EN
R/W
0
0: disable VID.
1: enable VID.
Base Address High Register ⎯ Index 60h
Bit
Name
7-0
BASE_ADDR_HI
R/W Default
R/W
00h
Description
The MSB of VID base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
7-0
BASE_ADDR_LO
8.9.2
R/W Default
R/W
00h
Description
The LSB of VID base address.
Device Registers
Configuration Register ⎯ Index 00h ( * cleared by slotocc_n and watch dog timeout)
Bit
Name
R/W Default
7
WDOUT_EN
R/W
0
If this bit is set to 1 and watchdog timeout event occurs, WDTRST# output is
enabled.
6-1
Reserved
-
0
Reserved
0
WD_RST_EN
0
0: Disable WDT to reset the VID register marked with *.
1: Enable WDT to reset the VID register marked with *.
R/W
Description
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BUSOUT Manual Register ⎯ Index 02h
Bit
Name
7*
MANUAL_MODE
R/W
0
6
KEY_OK
R
-
0: BUSIN2-0 is bypassed to BUSOUT2-0.
1: BUSOUT2-0 is controlled by BUSOUT_MANUAL.
This bit is reset by SLOTOCC# falling edge or WDT (with WD_RT_EN set).
This bit is 1 represents that the serial key is entered correctly.
5-3
Reserved
R/W
0
Dummy register for future use.
BUSOUT_MANUAL R/W
0
The output value for BUSOUT2-0 if MANUAL_MODE is set.
2-0
R/W Default
Description
Serial Key Data Register ⎯ Index 03h
Bit
7-0
Name
KEY_DATA
R/W Default
R/W
0
Description
Write serial data to this register correctly, the KEY_OK bit will be set to 1.
Hence, users are able to write key protected registers. The sequence to
enable KEY_OK is 0x32, 0x5D, 0x42, 0xAC. When KEY_OK is set, write this
register 0x35 will clear KEY_OK.
BUSIN Register ⎯ Index 04h
Bit
Name
7-3
Reserved
2:0
BUSIN
R/W Default
R
R
Description
0
Reserved
-
The value of this register depends on the BUSIN_MODE register:
BUSIN_MODE is 1: the register indicates the BUS reading from CPU (the
pin status of BUS_IN [2:0]).
BUSIN_MODE is 0: the register latches the value of BUS_IN [2:0] when
BUSIN_MODE changed from 1 to 0.
Watchdog Timer Configuration Register 1⎯ Index 05h
Bit
Name
R/W Default
Description
7
Reserved
R
0
6
WDTMOUT_STS
R/W
0
5
WD_EN
R/W
0
If watchdog timeout event occurs, this bit will be set to 1. Write a 1 to this bit
will clear it to 0.
If this bit is set to 1, the counting of watchdog time is enabled.
4
WD_PULSE
R/W
0
Select output mode (0: level, 1: pulse) of RSTOUT# by setting this bit.
3
WD_UNIT
R/W
0
Select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit.
2
WD_HACTIVE
R/W
0
1:0
WD_PSWIDTH
R/W
0
Reserved
Select output polarity of RSTOUT# (1: high active, 0: low active) by setting
this bit.
Select output pulse width of RSTOUT#
0: 1 ms
1: 25 ms
2: 125 ms
3: 5 sec
Watchdog Timer Configuration Register 2 ⎯ Index 06h
Bit
Name
7:0
WD_TIME
R/W Default
R/W
0
Description
Time of watchdog timer
NB Offset Register ⎯ Index 07h
Bit
Name
7:0
*NB_OFFSET
R/W Default
R/W
0
Description
Program this byte to add offset to VDDNB in AMD SVID interface. The value
will be “0” before PWROK.
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VDD0 Offset Register ⎯ Index 08h
Bit
Name
R/W Default
Description
Program this byte to add offset to
7:0
*VDD0_OFFSET
R/W
0
1.
VDD0 in AMD SVID interface.
2.
VININ in AMD PVID interface (LSB is not used, VDD0_OFFSET[1] is
the smallest step).
3.
VIDIN in Intel VRM11.
The value will be “0” before PWROK.
VDD1 Offset Register ⎯ Index 09h
Bit
Name
7:0
*VDD1_OFFSET
R/W Default
R/W
0
Description
Program this byte to add offset to VDD1 in AMD SVID interface.
The value will be “0” before PWROK.
WDT PME Register ⎯ Index 0Ah
Bit
7
Name
WDT_PME
R/W Default
R
0
6
WDT_PME_EN
R/W
0
5-1
Reserved
R
0
0
CPU_CHANGE
R/W
0
Description
0: No WDT PME occurred.
1: WDT PME occurred.
The WDT PME is occurred one unit before WDT timeout.
0: Disable WDT PME.
1: Enable WDT PME.
Reserved
This bit will be set at SLOTOCC# rise edge. Internal 1us de-bounce circuit is
implemented. Write “1” to this bit will clear the status.
VDDNB Manual Register ⎯ Index 0Bh
Bit
Name
R/W Default
VDDNB_MANUAL
R/W
0
VDDNB_IN
R
-
7:0
Description
This byte is used to program the manual value for VDDNB of AMD SVID
interface in manual mode. Set VID_BANK_SEL “1” to access this byte.
The value of VDDNB from CPU (AMD SVID interface only).
Set VID_BANK_SEL “0” to read this byte.
VDD0 Manual Register ⎯ Index 0Ch
Bit
Name
R/W Default
VDD0_MANUAL
R/W
0
VDD0_IN
R
-
7:0
Description
This byte is used to program the manual value for
1. VDD0 of AMD SVID interface in manual mode.
2. VIDOUT of AMD PVID interface in manual mode (The output is
controlled by VDD0_MANUAL [6:1] since AMD PVID only has 6 pins).
3. VIDOUT of Intel VRM11 in manual mode.
Set VID_BANK_SEL “1” to access this byte.
This byte has three functions:
1. VDD0 read from CPU in AMD SVID interface.
2. {1’b0, VIDIN [5:0], 1’b0} in AMD PVID interface.
3. VIDIN in Intel VRM11.
Set VID_BANK_SEL “0” to read this byte.
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VDD1 Manual Register ⎯ Index 0Dh
Bit
Name
R/W Default
VDD1_MANUAL
R/W
0
VDD1_IN
R
-
7:0
Description
This byte is used to program the manual value for VDD1 of AMD SVID
interface in manual mode. Set VID_BANK_SEL “1” to access this byte.
The value of VDD1 from CPU (AMD SVID interface only).
Set VID_BANK_SEL “0” to read this byte.
PSI Control Register ⎯ Index 0Eh
Bit
Name
R/W Default
7
VID_BANK_SEL
R/W
0
6-5
Reserved
-
0
4
VRM_SEL
R/W
0
3
PSI_VDD1
R/W
1
2
PSI_VDD0
R/W
1
1
PSI_NB
R/W
1
0
*VID_MANUAL
_MODE
R/W
0
Description
Select the different bank to access other register at the same index.
Reserved
If parallel VID interface is detected. Program this bit to determine AMD/Intel
model.
0: Intel VRM11
1: AMD PVID
This bit is used for AMD SVID only.
0: force PSI of VDD1 “0”.
1: PSI of VDD1 is determined by the reading from CPU.
This bit is used for AMD SVID only.
0: force PSI of VDD0 “0”.
1: PSI of VDD0 is determined by the reading from CPU.
This bit is used for AMD SVID only.
0: force PSI of VDDNB “0”.
1: PSI of VDDNB is determined by the reading from CPU.
0: VID is in bypass mode or on-the-fly mode determined by the offset value.
1: VID is in manual mode.
This bit will be “0” before PWROK.
*Those register is reset by SLOTOCC# falling edge (CPU change) or Watchdog timer timeout (if enabled).
8.10 SPI Registers (CR08)
SPI Control Register ⎯ Index F0h (powered by VAT)
Bit
Name
R/W Default
Description
7-6
Reserved
-
-
Reserved.
5
SPTIE
R/W
0
SPI interrupt enable. Set to 1, SPIE interrupt enabled, set to 0 spie interrupt
disabled.
4
Reserved
-
-
Reserved.
3
CPOL
R/W
0
Clock polarity this bit selects inverted or non-inverted SPI clock. Set to 1,
active low clock selected; SCK idles high. Set to 0, active high clock
selected; SCK idles low.
2
CPHA
R/W
0
Clock phase. This bit is used to shift the SCK serial clock. Set to 1, the first
SCK edge is issued at the beginning of the transfer operation. Set to 0, the
first SCK edge is issued one-half cycle into the transfer operation.
1
Reserved
-
0
Reserved
0
LSBFE
R/W
0
This bit control data shift from lsb or msb. Set to 1, data is transferred from
lsb to msb. Set to 0, data is transferred from msb to lsb.
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Reserved ⎯ Index F1h
Bit
Name
7-0 Reserved
R/W Default
-
-
Description
Reserved
SPI Baud Rate Divisor Register ⎯ Index F2h
Bit
Name
7-3
Reserved
2-0
BAUD_VAL
Description
R/W Default
-
R/W
0
Reserved
1
This register decides to SCK frequency. Baud rate divisor equation is
33MHz/2*(BAUD_VAL).
00: 33MHz.
01: 16.7MHz.
SPI Status Register ⎯ Index F3h
Bit
Name
R/W Default
Description
7
SPIE
R/W
0
SPI interrupt status. When SPI is transferred or received data from device
finish, this bit will be set. Write 1 to clear this bit.
6
Reserved
-
-
Reserved
5
SPE
R
-
This bit reflects the SPI_EN register (which will be 1 when SPI is enabled.)
4
Reserved
-
-
Reserved
3
SPTEF
R
0
SPI operation status. When SPI is transferred or received data from device,
this bit will be set 1, Clear by SPI operation finish.
2-0
Reserved
-
-
Reserved
SPI High Byte Data Register ⎯ Index F4h
Bit
Name
7-0
H_DATA
R/W Default
R
0
Description
When SPI is received 16 bits data from device. This register saves high byte
data.
SPI command data Register ⎯ Index F5h
Bit
Name
7-0
CMD_DATA
R/W Default
R/W
0
Description
This register provides command value for flash command.
SPI chip select Register ⎯ Index F6h
Bit
Name
R/W Default
Description
7-4
Reserved
-
-
Reserved
3
CS3
R/W
0
Chip select 3. To select device 3
2
CS2
R/W
0
Chip select 2. To select device 2
1
CS1
R/W
0
Chip select 1. To select device 1
0
CS0
R/W
0
Chip select 0. To select device 0
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SPI memory mapping Register ⎯ Index F7h (powered by VBAT)
Bit
Name
R/W Default
Description
7-5
Reserved
-
0
Reserved
4-0
Reserved
-
-
Reserved
SPI operate Register ⎯ Index F8h
Bit
Name
R/W Default
Description
7
TYPE
R/W
0
This bit decide flash continuous programming mode. Set to 1, if
programming continuous mode is same as the SST flash. Set to 0 if
programming continuous mode is same as the ATMEL flash
6
IO_SPI
R/W
0
This bit control SPI function transfer 8 bit command to device. Clear 0 by
operation finish.
5
RDSR
R/W
0
This bit control SPI function read status from to device. Clear 0 by operation
finish.
4
WRSR
R/W
0
This bit control SPI function write status to device. Clear 0 by operation
finish.
3
SECTOR_ERASE
R/W
0
This bit control SPI function sector erase device. Clear 0 by operation finish.
2
READ_ID
R/W
0
This bit control SPI function read id from device. Clear 0 by operation finish.
1
PROG
R/W
0
This bit control SPI function program data to device or set to 1 when memory
cycle for LPC interface program flash. Clear 0 by operation finish.
0
READ
R/W
0
This bit control SPI function read data from device or set to 1 when memory
cycle for LPC interface read flash. Clear 0 by operation finish.
SPI Low Byte Data Register ⎯ Index FAh
Bit
Name
7-0
L_DATA
R/W Default
R
0
Description
When SPI is received 16 bits or 8 bits data from device. This register saves
low byte data.
SPI address high byte Register ⎯ Index FBh
Bit
Name
7-0
Addr_H_byte
R/W Default
R/W
0
Description
This register provides high byte address for sector erase, program, read
operation.
SPI address medium byte Register ⎯ Index FCh
Bit
Name
7-0
Addr_M_byte
R/W Default
R/W
0
Description
This register provides medium byte address for sector erase, program, read
operation.
SPI address low byte Register ⎯ Index FDh
Bit
Name
7-0
Addr_L_byte
R/W Default
R/W
0
Description
This register provides low byte address for sector erase, program, read
operation.
SPI program byte Register ⎯ Index FEh
Bit
Name
7-0
PORG_BYTE
R/W Default
R/W
0
Description
This register provides number to program flash for continuous mode.
SPI write data Register ⎯ Index FFh
Bit
Name
7-0
WR_dat
R/W Default
R/W
0
Description
This register provides data to write flash for program, write status function.
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8.11 PME and ACPI Registers (CR0A)
Device Enable Register ⎯ Index 30h
Bit
Name
R/W Default
Description
7-1
Reserved
-
-
Reserved
0
PME_EN
R/W
0
0: disable PME.
1: enable PME.
PME Event Enable Register ⎯ Index F0h
Bit
Name
7
Reserved
-
-
Reserved
6
MO_PME_EN
R/W
0
Mouse PME event enable.
0: disable mouse PME event.
1: enable mouse PME event.
0
Keyboard PME event enable.
0: disable keyboard PME event.
1: enable keyboard PME event.
5
KB_PME_EN
R/W Default
R/W
Description
4
HM_PME_EN
R/W
0
Hardware monitor PME event enable.
0: disable hardware monitor PME event.
1: enable hardware monitor PME event.
3
PRT_PME_EN
R/W
0
Parallel port PME event enable.
0: disable parallel port PME event.
1: enable parallel port PME event.
2
UR2_PME_EN
R/W
0
UART 2 PME event enable.
0: disable UART 2 PME event.
1: enable UART 2 PME event.
1
UR1_PME_EN
R/W
0
UART 1 PME event enable.
0: disable UART 1 PME event.
1: enable UART 1 PME event.
0
FDC_PME_EN
R/W
0
FDC PME event enable.
0: disable FDC PME event.
1: enable FDC PME event.
PME Event Status Register ⎯ Index F1h
Bit
Name
7
Reserved
6
5
4
MO_PME_ST
KB_PME_ST
HM_PME_ST
R/W Default
-
R/W
R/W
R/W
Description
-
Reserved
-
Mouse PME event status.
0: Mouse has no PME event.
1: Mouse has a PME event to assert. Write 1 to clear to be ready for next
PME event.
-
Keyboard PME event status.
0: Keyboard has no PME event.
1: Keyboard has a PME event to assert. Write 1 to clear to be ready for next
PME event.
-
Hardware monitor PME event status.
0: Hardware monitor has no PME event.
1: Hardware monitor has a PME event to assert. Write 1 to clear to be ready
for
next PME event.
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3
2
1
0
PRT_PME_ST
UR2_PME_ST
UR1_PME_ST
FDC_PME_ST
R/W
R/W
R/W
R/W
-
Parallel port PME event status.
0: Parallel port has no PME event.
1: Parallel port has a PME event to assert. Write 1 to clear to be ready for
next PME event.
-
UART 2 PME event status.
0: UART 2 has no PME event.
1: UART 2 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
-
UART 1 PME event status.
0: UART 1 has no PME event.
1: UART 1 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
-
FDC PME event status.
0: FDC has no PME event.
1: FDC has a PME event to assert. Write 1 to clear to be ready for next PME
event.
ACPI Control Register 1 ⎯ Index F4h
Bit
Name
R/W Default
Description
7
Reserved
R/W
0
Reserved
6
Reserved
R/W
0
Dummy for future use.
5
DUAL_GATE_S5_O
N
R/W
1
0: DUAL_GATE_N tri-state in S5 state.
1: DUAL_GATE_N output low in S5 state.
4
EN_KBWAKEUP
R/W
0
Set one to enable keyboard wakeup event asserted via PWSOUT#.
3
EN_MOWAKEUP
R/W
0
Set one to enable mouse wakeup event asserted via PWSOUT#.
2-1
PWRCTRL
R/W
11
The ACPI Control the PSON_N to always on or always off or keep last state
00 : keep last state
10 : Always on
01 : Always on without PSOUT#
11: Always off
0
VSB_PWR_LOSS
R/W
0
When VSB 3V comes, it will set to 1, and write 1 to clear it
ACPI Control Register 2 ⎯ Index F5h
Bit
Name
7
Reserved
6-5
PWROK_DELAY
R/W Default
R/W
R/W
Description
0
Dummy for future use.
0
The additional PWROK delay.
00: no delay
01: 100ms.
10: 200ms
11: 400ms.
The PWROK delay timing from VDD3VOK by followed setting
4-3
11
00 : 100ms
01 : 200ms
10 : 300ms
11 : 400ms
VDD_DELAY
R/W
2
VINDB_EN
R/W
1
Enable the PCIRSTIN_N and ATXPWGD de-bounce.
1
PCIRST_DB_EN
R/W
0
Enable the LRESET_N de-bounce.
0
Reserved
R/W
0
Dummy register.
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ACPI Control Register ⎯ Index F6h
Bit
Name
R/W Default
Description
7
S3_SEL
R/W
0
Select the KBC S3 state.
0: Enter S3 state when internal VDD3VOK signal de-asserted.
1: Enter S3 state when S3# is low or the TS3 register is set to 1.
6
SPI_RST_EN
R/W
0
0: Disable SPI time out reset signal
1: Enable SPI time out reset signal output form PWROK and PCIRST#.
5
WDT_RST_EN
R/W
0
0: Disable WDT time out reset signal
1: Enable WDT time out reset signal output form PWROK.
4
PSON_DEL_EN
R/W
0
0: PSON# is the inverted of S3# signal.
1: PSON# will sink low only if the time after the last turn-off elapse at least 4
seconds.
3
VREF_S3_RST_EN
R/W
0
1: The VREF output value will be reset to default (64h) when enter S3/S5
state.
2
PCIRST3_GATE
R/W
1
Write “0” to this bit will force PCIRST3# to sink low.
1
PCIRST2_GATE
R/W
1
Write “0” to this bit will force PCIRST2# to sink low.
0
PCIRST1_GATE
R/W
1
Write “0” to this bit will force PCIRST1# to sink low.
0: The VREF output value programmed by user will keep in S3/S5 state.
8.12 VREF Control Registers (CR0B)
VREF3 Output Value ⎯ Index F0h
Bit
Name
7-0
VREF3_H
R/W Default
R/W
Description
8’h64 The bit8-1 of VREF3 output value.
VREF2 Output Value ⎯ Index F1h
Bit
Name
7-0 VREF2_H
R/W Default
R/W
Description
8’h64 The bit8-1 of VREF2 output value.
VREF1 Output Value ⎯ Index F2h
Bit
Name
7-0
VREF1_H
R/W Default
R/W
Description
8’h64 The bit8-1 of VREF1 output value.
Voltage LSB ⎯ Index F3h
Bit
Name
R/W Default
Description
7-3
Reserved
R/W
-
Reserved.
2
VREF1_L
R/W
0
The bit0 of VREF1 output value.
1
VREF2_L
R/W
0
The bit0 of VREF2 output value.
0
VREF3_L
R/W
0
The bit0 of VREF3 output value.
WDT Reset Enable ⎯ Index FFh
Bit
Name
R/W Default
Description
7-1
Reserved.
-
-
Reserved.
0
WD_RST_EN
R/W
0
0: disable the WDT reset function.
1: VREF1~3 will be reset to default if WDT timeout occurs.
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9. Electrical Characteristics
Absolute Maximum Ratings
PARAMETER
Power Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
RATING
-0.5 to 5.5
-0.5 to VDD+0.5
0 to 70
-55 to 150
UNIT
V
V
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely
affect the life and reliability of the device
DC Characteristics
(Ta = 0° C to 70° C, VDD = 3.3V ± 10%, VSS = 0V) (Note)
Parameter
Conditions
60 oC < TD < 100 oC, VCC = 3.0V to 3.6V
Temperature Error, Remote Diode
-40 oC <TD < 60oC 100 oC <TD < 127oC
Supply Voltage range
Average operating supply current
Standby supply current
VBAT Current
Resolution
Power on reset threshold
High Level
Diode source current
Low Level
MIN
3.0
TYP
±1
±1
3.3
10
5
1
1
2.2
95
10
MAX
±3
±3
3.6
Unit
o
C
2.4
V
mA
uA
uA
o
C
V
uA
uA
PARAMETER
SYM. MIN. TYP.
MAX.
UNIT
CONDITIONS
I/OD12st,5v-TTL level bi-directional pin with schmitt trigger, Open-drain output with12 mA sink
capability, 5V tolerance.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Output Low Current
IOL
+12
mA
VOL = 0.4V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0V
I/OD12t-TTL level bi-directional pin, Open-drain output with12 mA sink capability.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Output Low Current
IOL
-12
mA
VOL = 0.4 V
I/OOD12t-TTL level bi-directional pin, Output pin with 12mA source-sink capability, and can
programming to open-drain function.
Input Low Threshold Voltage
Vt0.8
V
VDD = 3.3 V
Input High Threshold Voltage
Vt+
2.0
V
VDD = 3.3 V
Output Low Current
IOL
-12
-9
mA
VOL = 0.4 V
Output High Current
IOH
+9
+12
mA
VOH = 2.4V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0V
I/O12t- TTL level bi-directional pin, Output pin with 12mA source-sink capability.
Input Low Threshold Voltage
Vt0.6
V
VDD = 3.3 V
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F71889
Input High Threshold Voltage
Output High Current
Input High Leakage
Input Low Leakage
Vt+
0.9
V
VDD = 3.3 V
IOH
+9
+12
mA
VOH = 2.4V
ILIH
+1
μA
VIN = 1.2V
ILIL
-1
μA
VIN = 0V
INst - TTL level input pin with schmitt trigger
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0 V
INt,5v - TTL level input pin with 5V tolerance.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0 V
INst,5v - TTL level input pin with schmitt trigger, 5V tolerance.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0 V
OD12-Open-drain output with12 mA sink capability.
Output Low Current
IOL
-12
mA
VOL = 0.4V
OD12,5v-Open-drain output with12 mA sink capability, 5V tolerance.
Output Low Current
IOL
-12
mA
VOL = 0.4V
OD24-Open-drain output with 24 mA sink capability.
Output Low Current
IOL
-24
mA
VOL = 0.4V
OD16,u10,5v-Open-drain output with 16 mA sink capability, pull-up 10k ohms, 5V tolerance.
Output Low Current
IOL
-16
mA
VOL = 0.4V
O8,u47,5v- Output pin with 8 mA source-sink capability, pull-up 47k ohms, 5V tolerance.
Output High Current
IOH
+6
+8
mA
VOH = 2.4V
O12- Output pin with 12 mA source-sink capability.
Output High Current
IOH
+9
+12
mA
VOH = 2.4V
O30- Output pin with 30 mA source-sink capability.
Output High Current
IOH
+26
+30
mA
VOH = 2.4V
I/OD14t-TTL level bi-directional pin, Open-drain output with14 mA sink capability.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Output Low Current
IOL
-14
mA
VOL = 0.4 V
I/Os1, D8,st, lv - Low level bi-directional pin (VIH Æ 0.9V, VIL Æ 0.6V.) with schmitt trigger. Output with
8mA drive and 1mA sink capability.
Input Low Voltage
VIL
0.6
V
Input High Voltage
VIH
0.9
V
Output High Current
IOH
+8
mA
VOH = 1.0V
Input Low Leakage
ILIL
-1
μA
VIN = 0 V
I/OD8,st, lv - Low level bi-directional pin (VIH Æ 0.9V, VIL Æ 0.6V.) with schmitt trigger. Output with 8mA
drive
Input Low Voltage
VIL
0.6
V
Input High Voltage
VIH
0.9
V
Output High Current
IOH
+8
mA
VOH = 1.0V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0 V
I/OD12,st,lv - Low level bi-directional pin with schmitt trigger. Open-drain output with 12mA sink
capability.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
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Output Low Current
Input High Leakage
Input Low Leakage
IOL
ILIH
ILIL
-12
+1
-1
mA
μA
μA
VOH = 0.4V
VIN = VDD
VIN = 0 V
I/OOD12,st,lv - Low level bi-directional pin with schmitt trigger, can select to OD or OUT by register,
with 12 mA source-sink capability.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Output Low Current
IOL
-12
mA
VOH = 0.4V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0 V
I/OD12st,lv-TTL level bi-directional pin with schmitt trigger, Open-drain output with12 mA sink
capability, low voltage.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Output Low Current
IOL
+12
mA
VOL = 0.4V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0V
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10.Ordering Information
Part Number
Package Type
Production Flow
F71889F
128-PQFP Green Package
Commercial, 0°C to +70°C
Fintek
F71889F
XXXXLAF
XXXXXX.X
Version Identification:
An example for LAF version:
The version shows on RED area. Ex: LAF
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April, 2010
V0.28P
F71889
11.Package Dimensions
128 PQFP (14*20)
Feature Integration Technology Inc.
Headquarters
Taipei Office
3F-7, No 36, Tai Yuan St.,
Bldg. K4, 7F, No.700, Chung Cheng Rd.,
Chupei City, Hsinchu, Taiwan 302, R.O.C.
Chungho City, Taipei, Taiwan 235, R.O.C.
TEL : 886-3-5600168
TEL : 866-2-8227-8027
FAX : 886-3-5600166
FAX : 866-2-8227-8037
www: http://www.fintek.com.tw
Please note that all datasheet and specifications are subject to change without notice. All
the trade marks of products and companies mentioned in this datasheet belong to their
respective owner
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April, 2010
V0.28P
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12.Application Circuit
(GND close to IC)
VREF3
VREF2
VREF1
DD3+
D2+
D1+
VREF
VIN6
VIN5
VIN4
VIN3
VIN2
VCORE
VSB3V
SLCT/VIDIN0
PE/VIDIN1
BUSY /VIDIN2
R1
R3
R2
R7
R4
R5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
BUSY/VIDIN2/GPIO62
PE/VIDIN1/GPIO61
SLCT/VIDIN0/GPIO60
AVSB
VCORE(VIN1)
VIN2
VIN3
VIN4
VIN5
VIN6
VREF
D1+(CPU)
D2+
D3+(System)
AGND(D-)
VREF1
VREF2
VREF3
VREF_EN
COPEN#
VBAT
RSMRST#
PWOK
PS_ON#
S3#
PWSOUT#
PWSIN#
PME#
ATXPG_IN
S5#
DUALGATE
VCCGATE
GND
MCLK
MDATA
KCLK
KDATA
VSB3V
ACK#/VIDIN3/GPIO63
SLIN#/CoreTP/VIDIO_TRAP
INIT#/VIDIN4/GPIO64
ERR#/VIDIN5/GPIO65
AFD#/H#/VIDIN6/GPIO66
STB#/L#/VIDIN7/GPIO67
PD0/SEGA/VIDOUT0/GPIO70
PD1/SEGB/VIDOUT1/GPIO71
PD2/SEGC/VIDOUT2/GPIO72
PD3/SEGD/VIDOUT3/GPIO73
PD4/SEGE/VIDOUT4/GPIO74
PD5/SEGF/VIDOUT5/GPIO75
PD6/SEGG/VIDOUT6/GPIO76
PD7/VIDOUT7/GPIO77
GND
DCD1#
RI1#
CTS1#
DTR1#/FAN60_100
RTS1#/80PORT_TRAP
DSR1#
SOUT1/Conf ig4E_2E
SIN1
DCD2#/GPIO30
RI2#/GPIO31
CTS2#/GPIO32
F71889F
PCIRST3#
PCIRST2#
PCIRST1#
OVT#
GPIO06/BEEP/ALERT#
GPIO05/LED_VCC
GPIO04/LED_VSB
SLOTOCC#/GPIO03
BUSOUT2/GPIO02
BUSOUT1/GPIO01
BUSOUT0/GPIO00
BUSIN2/GPIO27
BUSIN1/GPIO26
BUSIN0/GPIO25
GND
GPIO24/FWH_DIS
GPIO23/SPI_MOSI
GPIO22/SPI_MISO
GPIO21/SPI_CS0#
GPIO20/SPI_CLK
PECI/IBX_SDA/TSI_DAT/GPIO16
SST/IBX_SCL/TSI_CLK/GPIO15
PECI_AVL/IRRX/GPIO14
PECI_REQ#/IRTX/GPIO13
GPIO12/WDTRST#
GA20
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
VCC3V
WPT#
INDEX#
TRK0#
RDATA#
DSKCHG#
1K
1K
1K
1K
1K
MCLK
MDAT
KCLK
KDAT
VSB3V
VCC
DTR2#/GPIO33/FWH_TRAP
RTS2#/GPIO34/PWM_DC
DSR2#/GPIO35
SOUT2/GPIO36/SPI_TRAP
SIN2/GPIO37
DENSEL#/GPIO40
MOA#/GPIO41
DRVA#/GPIO42
WDATA#/GPIO43
DIR#/GPIO44
STEP#/GPIO45
HDSEL#/GPIO46
WGATE#/GPIO47
RDATA#/GPIO50
TRK0#/GPIO51
INDEX#/GPIO52
WPT#/GPIO53
DSKCHG#/GPIO54
GND
FANIN1
FANCTL1
FANIN2
FANCTL2
FANIN3/GPIO10/IRRX1
FANCTL3/GPIO11/IRTX1
LRESET#
LDRQ#
SERIRQ
LFRAM#
LAD0
LAD1
LAD2
LAD3
VCC
PCICLK
CLKIN
KBRST#
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DTR1# 121
RTS1# 122
123
SOUT1 124
125
126
127
128
VCC5V
J1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
R150 R151 R152 R153 R154
4.7K 4.7K 4.7K 4.7K 4.7K
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
DENSEL#
RDATA#
TRK0#
INDEX#
MOA#
INDEX#
DRVA#
WPT#
DIR#
STEP#
WDATA#
WGATE#
TRK0#
WPT#
RDATA#
HDSEL#
DSKCHG#
DSKCHG#
If you do not use the floppy,
please pull-up these pin to VCC3V.
HEADER 17X2
FLOPPY
PCIRST3#
PCIRST2#
PCIRST1#
OVT#
BEEP
LED_VCC
LED_VSB
SLOTOCC#
BUSOUT2
BUSOUT1
BUSOUT0
BUSIN2
BUSIN1
BUSIN0
OVT#
WDT#
SOUT1
RTS1#
DTR1#
LDRQ#
SOUT2
RTS2#
DTR2#
VSB3V VSB3V
R9
4.7K
R10
4.7K
RSMRST#
PWOK
FWH_DIS
MOSI
MISO
SPI_CS0#
SCK
PECI
SST
PECI_AVL
PECI_REQ#
WDT#
GA20
R11
560
R12
560
R13
560
R14
560
R15
560
R16
560
R17
560
RSMRST# AND PWOK PULL UP
VCC3V
POWER TRIP R
R104
4.7K
R11
R12
R13
R14
R15
R16
R17
WDT#
WDT# PULL-UP
OFF:
OFF:
OFF:
OFF:
OFF:
OFF:
OFF:
SPI AS BACKUP BIOS
PWM
SPI DISABLE
PIN 51~56 ARE BUS INTERFACE
FAN 60%
80 PORT ENABLE
CONFIG 4E
ON: SPI AS A PRIMARY BIOS
ON: DAC
ON: SPI ENABLE
ON: PIN 51~56 ARE GPIO PIN
ON: FAN 100%
ON: 80 PORT DISABLE
ON :CONFIG 2E
VREF3
VCC3V VCC3V VSB3V
VSB3V
VBAT
1
1
1
1
0.1U
C3
0.1U
C4
0.1U
R18
2M
0.1U
SLOTOCC#
SLOTOCC#_CPU
SLOT_OCC#
(PLACE THE CAPCITOR CLOSE TO IC)
Title
Size
B
Date:
101
VBAT
C5
2
0.1U
C2
2
0.1U
C1
2
0.1U
C59
2
0.1U
C60
1
VREF2
C61
1
VREF1
2
LAD3
LAD2
LAD1
LAD0
LFRAME#
SERIRQ
LDRQ#
PCIRST#
KBRST#
CLK_24/48M
PCICLK
VCC3V
LAD3
LAD2
LAD1
LAD0
LFRAME#
SERIRQ
LDRQ#
PCIRST#
FANCTL3
FANIN3
FANCTL2
FANIN2
FANCTL1
FANIN1
2
DENSEL#
MOA#
DRVA#
WDATA#
DIR#
STEP#
HDSEL#
WGATE#
RDATA#
TRK0#
INDEX#
WPT#
DSKCHG#
CLK_24/48M
PCICLK
1
SOUT2
2
DTR2#
RTS2#
2
VCC3V
DTR2#
RTS2#
DSR2#
SOUT2
SIN2
DENSEL#
MOA#
DRVA#
WDATA#
DIR#
STEP#
HDSEL#
WGATE#
RDATA#
TRK0#
INDEX#
WPT#
DSKCHG#
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
DCD1#
RI1#
CTS1#
DTR1#
RTS1#
DSR1#
SOUT1
SIN1
DCD2#
RI2#
CTS2#
0
VCORE
U1
ACK#/VIDIN3
SLIN#
INIT#/VIDIN4
ERR#/VIDIN5
AFD#/VIDIN6
STB#/VIDIN7
PD0/VIDOUT0
PD1/VIDOUT1
PD2/VIDOUT2
PD3/VIDOUT3
PD4/VIDOUT4
PD5/VIDOUT5
PD6/VIDOUT6
PD7/VIDOUT7
VREF_EN
COPEN#
VBAT
RSMRST#
PWOK
PSON#
S3#
PWSOUT#
PWSIN#
PME#
ATXPG_IN
S5#
DUALGATE
VCCGATE
Feature Integration Technology Inc.
Document Number
F71889/FDC
Monday , August 24, 2009
Rev
<Rev Code>
Sheet
1
of
6
April, 2010
V.28P
F71889
VCC5V/3V
VCC3V
U2
20
VCC5V
RI1#
CTS1#
DSR1#
RTS1#
DTR1#
SIN1
SOUT1
DCD1#
19
18
17
16
15
14
13
12
11
VCC
+12V
RY1
RY2
RY3
DA1
DA2
RY4
DA3
RY5
RA1
RA2
RA3
DY 1
DY 2
RA4
DY 3
RA9
GND
-12V
1
2
3
4
5
6
7
8
9
10
+12V
GND
RIN1
DTRN1
CTSN1
SOUTN1
RTSN1
SINN1
DSRN1
DCDN1
RIN1
CTSN1
DSRN1
RTSN1
DTRN1
SINN1
SOUTN1
DCDN1
P1
5
9
4
8
3
7
2
6
1
JP1
R140 R141 R142 R143 R144
4.7K 4.7K 4.7K 4.7K 4.7K
-12V
PECI_AVL
DCD1#
RI1#
CTS1#
DSR1#
SIN1
UART DB9
1
2
3
4
5
PECI_REQ#
HEADER 5
C23
IR INTERFACE
0.1U
If you do not use the UART port 1,
please pull-up these pin to VCC3V.
UART
1 PORT INTERFACE
VSB5V
VSB3V
If you do not use the KBC,
please pull-up these pin to VSB5V.
J3
1
2
3
R160
8.2K
F1
Q17
NPN
R162
R20
4.7K
RIN1
4.7K
R21
4.7K
FUSE
1
2
3
6
5
4
R22
4.7K
R23
4.7K
L1
1N4148
MDAT
C58
6
5
4
FB
L3
MCLK
M-DIN_6-R JS2
1
2
3
FUSE
L2
KDAT
FB
R161
2.2K
1000P
F2
M-DIN_6-R JS1
CON3
VCC5V
D10
CHIPSET_RI1#
L4
KCLK
FB
FB
C24
C25
C26
C27
C28
C29
100P
100P
0.1U
100P
100P
0.1U
Wake up on ring for serial port circuit.
PS2 MOUSE INTERFACE
PS2 KEYBOARD INTERFACE
VCC3V
20
VCC5V
RI2#
CTS2#
DSR2#
RTS2#
DTR2#
SIN2
SOUT2
DCD2#
19
18
17
16
15
14
13
12
11
U3
VCC
+12V
RY1
RY2
RY3
DA1
DA2
RY4
DA3
RY5
RA1
RA2
RA3
DY 1
DY 2
RA4
DY 3
RA9
GND
-12V
UART
1
2
3
4
5
6
7
8
9
10
2
+12V
RIN2
CTSN2
DSRN2
RTSN2
DTRN2
SINN2
SOUTN2
DCDN2
GND
RIN2
DTRN2
CTSN2
SOUTN2
RTSN2
SINN2
DSRN2
DCDN2
-12V
PORT INTERFACE
5
9
4
8
3
7
2
6
1
P2
UART DB9
R145 R146 R147 R148 R149
4.7K 4.7K 4.7K 4.7K 4.7K
DCD2#
RI2#
CTS2#
DSR2#
SIN2
If you do not use the UART port 2,
please pull-up these pin to VCC3V.
Title
Feature Intergration Technology Inc
Size
Document Number
CustomUART_PS2_IR
Date:
102
Wednesday , August 13, 2008
Rev
0.1
Sheet
April, 2010
V.28P
2
of
6
F71889
+12V
+12V
VCC5V
R101
4.7K
R25
4.7K
3
4 HEADER
100
4
3
2
1
C30
+
R26
27K
FANIN1
U4A
D3
1N4148
R27
4.7K
LM358
JP3
R30 10K
C31
0.1U
C32
47u
R31 27K
3
2
1
C33
0.1u
FANIN1
R33
10K
CON3
R32
3.6K
PWM FAN1 SPEED CONTROL
NDS0605/SOT
Q1
1
-
R29
10K
JP2
47U
(FOUR PIN FAN CONTROL)
2
FANCTL1
+
4
R28
FANCTL1
8
D2
1N4148
10K
R24
DC FAN CONTROL WITH OP 1
+12V
+12V
4.7K
R35
4.7K
2
R102
4.7K
R39
D
Q2
C34 PNP JP4
Q4
+
3
MOSFET N
2
2N7002 47U
1
330
G
S
FANCTL2
1N4148
3
R36
4.7K
D4
R37
4.7K
5
6
FANCTL2
R38
27K
FANIN2
+
R41
10K
NDS0605/SOT
Q3
D5
1N4148
7
R40
4.7K
LM358
JP5
R43 10K
C35
0.1U
HEADER 3
U4B
4
VCC3V
8
1
R34
C36
47u
R42 27K
3
2
1
C37
0.1u
CON3
R44
3.6K
FANIN2
R45
10K
PWM FAN2 SPEED CONTROL
DC FAN CONTROL WITH OP 2
+12V
R103
4.7K
4.7K
3
1
R46
8
+12V
VCC3V
D
330
G
S
FANCTL3
R54
1N4148
3
R47
4.7K
2
FANCTL3
4.7K
2
Q6
C38 PNP JP6
Q7
+
3
MOSFET N
2
2N7002 47U
1
HEADER 3
D7
R49
4.7K
R52
FANIN3
R55
10K
R56
3.6K
C40
0.1U
D6
1N4148
1
R50
4.7K
LM358
JP7
R53 10K
27K
NDS0605/SOT
Q5
U5A
4
R48
+
C39
47u
R51 27K
3
2
1
C41
0.1u
FANIN3
R57
10K
CON3
DC FAN CONTROL WITH OP 3
PWM FAN3 SPEED CONTROL
Title
Feature Integration Technology Inc.
FAN CONTROL FOR PWM OR DC
Size
B
Date:
103
Document Number
FAN Control
Wednesday , August 13, 2008
Rev
0.1
Sheet
3
of
6
April, 2010
V.28P
R59
1K
R60
10K
R61
D+
C42
3300P
D-
R58
2M
D2+
D2+
C43
3300P
C44
1000P
for
SYSTEM
D-
10K
200K
VIN3
C49
100p
R63
for
SYSTEM
VSB5V
VSB3V
DIODE SENSING CIRCUIT
10K
R65
VIN4
C50
100p
10K
1K
10K
R69
VREF
RT1
10K 1%
R71
VREF
RT2
10K 1%
VSB5V
(for system)
VSB3V
The best voltage input level is about 1V.
RT3
10K 1%
THERMISTOR
D3+
C46
R75
0
R76
0
(for system)
Q11
NPN
LED_VSB
THERMISTOR SENSING CIRCUIT
LED
FRONT PANEL RESET
Temperature Sensing
VSB5V
1uF
D9
LED
CHIPSET_PWROK
Q12
MOSFET N
FWH_DIS
SUS_LED
10K 1%
T
R72
VREF
R74
330
R73
4.7K
THERMISTOR SENSING CIRCUIT
VOLTAGE SENSING.
D8
LED
(for system)
10K 1%
THERMISTOR
D2+
P_LED
Q10
NPN
LED_VCC
10K 1%
THERMISTOR
D1+
VIN6
C52
100p
VCC1.5V
R66
330
R68
4.7K
VIN5
C51
100p
VLDT
R70
3300P
D-
VDIMM
R67
Q9
PNP
3906
T
R64
C45
20K
CASE OPEN CIRCUIT
D3+
D3+
T
+12V
SW1
1
2
COPEN#
Q8
PNP
3906
DIODE SENSING CIRCUIT
R62
F71889
VBAT
from CPU
D-
VIN2
C48
100p
VDDA
D1+
D1+
VCORE
C47
100p
VCORE
+12V
VCC5V
R77
100K
R125
4.7K
BIOS RESET CIRCUIT
C55
100u ~ 1000u
R126
4.7K
Q14
MOSFET N
Q13
2N1069
VCCGATE
5V_DUAL
C53
100u ~ 1000u
VSB5V
R127
4.7K
Q15
VSB5V
MOSFET P
DUALGATE
VCC3V
VCC3V
R81
4.7K
VCC3V
R78
4.7K
OVT#
OVT# PULL-UP
U6
SPI_CS0#
MISO
W#
1
2
3
4
S#
Q
W#
VSS
VCC
HOLD#
C
D
8
7
6
5
R79
4.7K
VCC3V
C54
100u ~ 1000u
R80
4.7K
POWER CONTROL
HOLD#
SPI FLASH MEMORY
SCK
MOSI
Title
Size
B
Date:
104
Feature Integration Technology Inc.
Document Number
Hardware Monitor
Wednesday , August 05, 2009
Rev
<Rev Code>
Sheet
4
April, 2010
V.28P
of
6
F71889
VCC5V
R107
20K
PWM Controller
SLIN#
CPU
R110
47K
SLIN#
VTT1.2V
POWER ON TRAP
PULL-HIGH 20K PIN 100-116
AS PVID CONTROLLER
POWER ON TRAP
PULL-DOWN 47K PIN 100-103 AND PIN 105-116 AS GPIO PIN
ACK#/VIDIN3
PD4/VIDOUT4
INIT#/VIDIN4
ERR#/VIDIN5
PD6/VIDOUT6
AFD#/VIDIN6
PD7/VIDOUT7
STB#/VIDIN7
RN1
RN2
RN3
D1
1
VCC5V
RN4
2.7K-8P4R 2.7K-8P4R 2.7K-8P4R 2.7K-8P4R
1
3
5
7
PD5/VIDOUT5
2
1N5819
FOR LEKAGE TO POWER
2
4
6
8
BUSY /VIDIN2
PD3/VIDOUT3
1
3
5
7
PE/VIDIN1
PD2/VIDOUT2
2
4
6
8
SLCT/VIDIN0
PD1/VIDOUT1
1
3
5
7
PD0/VIDOUT0
2
4
6
8
R128 R129 R130 R131 R132 R133 R134 R135
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
1
3
5
7
R89
R88
R91
R90
R93
R92
R95
R94
2
4
6
8
VCC3V
R19
2.7K
RN5
1
3
5
7
STB#/VIDIN7
AFD#/VIDIN6
INIT#/VIDIN4
SLIN#
2
4
6
8
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
33-8P4R
FOR INTEL CPU
RN6
1
3
5
7
PD0/VIDOUT0
PD1/VIDOUT1
PD2/VIDOUT2
PD3/VIDOUT3
2
4
6
8
33-8P4R
RN7
1
3
5
7
PD4/VIDOUT4
PD5/VIDOUT5
PD6/VIDOUT6
PD7/VIDOUT7
2
4
6
8
33-8P4R
VCC5V
ERR#/VIDIN5
ACK#/VIDIN3
BUSY/VIDIN2
PE/VIDIN1
SLCT/VIDIN0
R108
20K
ERR#
ACK#
BUSY
PE
SLCT
CPU_CORE_TY PE
PWM Controller
CPU
VCC3V
J2
DB25
(FEMALE)
SLIN#
C6
POWER ON TRAP
PULL-HIGH 20K PIN 100-116
AS PVID CONTROLLER
180pC14
180p
C7
C8
180p
180p
C15
180p
C9
C10
180p
180p
C16
C17
C18
180p
180p
180p
C11
C12
180p
180p
C19
180p
C13
C20
180p
C21
C22 180p
180p
180p
VDDIO
R111 R112 R113 R114 R115 R116
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
PARALLEL PORT INTERFACE
R117 R118 R119 R120 R121 R122
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
VCC3V
PD0/VIDOUT0
PD1/VIDOUT1
SLCT/VIDIN0
PD2/VIDOUT2
PE/VIDIN1
PD3/VIDOUT3
BUSY/VIDIN2
PD4/VIDOUT4
ACK#/VIDIN3
PD5/VIDOUT5
INIT#/VIDIN4
ERR#/VIDIN5
R155 R156 R157 R158 R159
4.7K 4.7K 4.7K 4.7K 4.7K
SLCT
PE
BUSY
ACK#
ERR#
If you do not use the prarllel port ,
please pull-up these pin to VCC3V.
FOR AMD CPU
Title
Size
C
Date:
105
Feature Integration Technology Inc.
Document Number
VID/PRINTER PORT
Wednesday , August 13, 2008
Rev
<Rev Code>
Sheet
5
of
6
April, 2010
V.28P
F71889
VDDIO
R96
300
R97
300
U8
DCD2#
PECI
SST
PECI_CLIENT
CTS2#
RI2#
DSR2#
SIC
PECI
R138 100
1
2
3
4
5
SEGG
NC
SEGA
SEGF
L#
10
9
8
7
6
R139 100
H#
SOUT2
RTS2#
SIN2
DTR2#
Dual Digit Display
R98
100K
(avoid pre-bios floating)
SID
H#
SEGB
SEGC
SEGE
SEGD
VCC3V
R82
D
AMDSI
VCC3V
DSR2#
80 PORT 1 (output by COM2 interface)
PECI_AVL
PECI_REQ#
SST
CHIPSET_BMBUSY #
SST_HOST
U7
PD6/VIDOUT6
R99
100K
(avoid pre-bios floating)
Q16
MOSFET N
G
S
R100
4.7K
4.7K
H#
PECI
PD0/VIDOUT0
PD5/VIDOUT5
STB#/VIDIN7
SST
R136 100
1
2
3
4
5
SEGG
NC
SEGA
SEGF
L#
H#
SEGB
SEGC
SEGE
SEGD
10
9
8
7
6
R137 100
AFD#/VIDIN6
PD1/VIDOUT1
PD2/VIDOUT2
PD4/VIDOUT4
PD3/VIDOUT3
Dual Digit Display
80 PORT 2 (output by parallel port interface)
VCC3V
R109
300
R123
300
PECI
SST
SMLINK[1]
Title
INTEL IBEX
Client
Size
B
Date:
106
Feature Integration Technology Inc.
Document Number
AMDSI/SST/PECI/80PORT
Rev
<Rev Code>
Monday , August 24, 2009
Sheet
April, 2010
V.28P
6
of
6
F71889
CPU
VCC3V
R6
R8
NORTH BRIDGE
IDE
PCIRST3#
4.7K
4.7K
VSB3V
PCIRST3#
PCIRST2#
ATA133
U9
SOUTH BRIDGE
SATA
PCIRST2#
5
7
RSTGND
RESET
PSW+
PSW-
6
8
PWR_BTN
R105
R84
4.7K
C57
CAP NP
FRONT PANEL
LRESET#
PWSIN#
F71889
ATXPG_IN
PSON#
PCLK_1,2,3(33MHz)
PCI
VSB3V
S3#
PWSOUT#
RSMRST#
PCIRST1#
R85
R86
R87
4.7K
4.7K
1K
VCC3V
VSB5V
R106
4.7K -12V
VCC5V
VCC3V
ATX1
11
12
13
14
15
16
17
18
19
20
3V3
-12V
GND
PS-ON
GND
GND
GND
-5V
5V
5V
3V3
3V3
GND
5V
GND
5V
GND
PW-OK
5VSB
12V
ATX CONNECT
1
2
3
4
5
6
7
8
9
10
VSB5V
VCC5V
R83
4.7K
+12V
VSB5V
C56
22uF
Title
Feature Integration Technology Inc.
Size
B
Date:
107
Document Number
ACPI SAMPLE
Wednesday , August 13, 2008
Rev
<Rev Code>
Sheet
1
of
April, 2010
V.28P
7