Fairchild FAN2564UC12X 300ma low vin ldo for digital application Datasheet

FAN2564
300mA Low VIN LDO for Digital Applications
Features
Description














The FAN2564 operates from a minimum input of 1.65V
and provides outputs as low as 1.2V. Output current is
guaranteed to 300mA, making this regulator ideal for
digital loads.
Input Voltage 1.65V to 3.6V
Guaranteed 300mA Output
High Initial Output Voltage Accuracy: ±1%
Fixed Output Voltage options from 1.2V to 2.8V
Very Low Dropout: 100mV at 300mA
45µA Quiescent Current at No Load
Low Output Noise of 100µVRMS
Inrush Current Controlled to Less Than 500mA
PSRR of 60dB at 1kHz
The unique low input voltage capability and very low
dropout make this device an ideal post regulator to a
synchronous buck regulator. In this configuration, accurate low voltage regulation is provided without the inefficiencies typically related to linear regulators.
The enable pin can be used to initiate shutdown mode,
where the operating current falls to an extremely low
10nA, typically.
The FAN2564 is designed to be stable with spacesaving ceramic capacitors as small as 0402 case size.
100µs Startup Time
Stable with Ceramic Capacitors
Thermal and Short-Circuit Protection
4-bump WLCSP, 0.5mm Pitch
The FAN2564 is available in 4-bump 0.5mm pitch waferlevel chip-scale package (WLCSP) and a 6-lead 2 x
2mm ultra-thin molded leadless package (UMLP).
6-pin 2 x 2mm UMLP
Applications




Post Regulator
Cell Phones and Smart Phones
WLAN, 3G, and 4G Data Cards
PMP and MP3 Players
Typical Application Circuit
Figure 1.
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
Typical Application Circuit
www.fairchildsemi.com
FAN2564 — 300mA Low VIN LDO for Digital Applications
April 2011
Part Number
Output Voltage(1)
FAN2564UC12X
1.2
FAN2564UC13X
1.3
FAN2564UC15X
1.5
FAN2564UC18X
1.8
FAN2564UC25X
2.5
FAN2564UMP12X
1.2
FAN2564UMP13X
1.3
FAN2564UMP15X
1.5
FAN2564UMP18X
1.8
Temperature Range
Package
Packing Method
–40 to 85°C
WLCSP-4 0.5mm Pitch
Tape and Reel
–40 to 85°C
6 Lead UMLP 2 x 2mm
Tape and Reel
Notes:
1. Other voltage options available upon request. Contact a Fairchild representative.
Block Diagram
Figure 2.
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
Block Diagram
www.fairchildsemi.com
2
FAN2564 — 300mA Low VIN LDO for Digital Applications
Ordering Information
GN
A1
A2
EN
EN
A2
A1
GND
VOU
B1
B2
VIN
VIN
B2
B1
VOU
Figure 3.
WLCSP Bumps Facing Down
EN
1
NC
2
VIN
3
Figure 5.
Figure 4.
(AGND)
6
GND
5
NC
WLCSP, Bumps Facing Up
4 VOUT
UMLP, Leads Facing Down
Pin Definitions
Pin #
Name
Description
WLCSP
UMLP
A1
6
GND
Ground. Power and IC ground. All signals are referenced to this pin.
B1
4
VOUT
VOUT. Connect to output voltage.
B2
3
VIN
Input Voltage. Connect to input power source.
A2
1
EN
Enable. The device is in shutdown mode when voltage to this pin is <0.4V and
enabled when >0.95V.
5
NC
No connect.
2
NC
No connect.
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
www.fairchildsemi.com
3
FAN2564 — 300mA Low VIN LDO for Digital Applications
Pin Configuration
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
Input Voltage with Respect to GND
-0.3
4.5
V
Voltage on Any Other Pin with Respect to GND
-0.3
VIN
V
TJ
Junction Temperature
-40
+150
°C
TSTG
Storage Temperature
-65
+150
°C
+260
°C
VIN
TL
ESD
Lead Temperature (Soldering 10 Seconds)
Electrostatic Discharge
Protection Level
Human Body Model per JESD22-A114
4
Charged Device Model per JESD22-C101
2
Machine Model per JESD22-A115
kV
200
V
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
VCC
Supply Voltage Range
IOUT
Output Current
CIN
Input Capacitor
COUT
Min.
Typ.
Max.
1.8
3.6
V
0
300
mA
1.0
Output Capacitor
Unit
1.0
µF
4.7
10.0
µF
TA
Operating Ambient Temperature
-40
+85
°C
TJ
Operating Junction Temperature
-40
+125
°C
Thermal Properties
Symbol
ΘJA
Parameter
Min.
Junction-to-Ambient Thermal Resistance(2)
Typ.
Max.
Units
WLSCP
200
°C/W
UMLP
49
°C/W
Note:
2. Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured
with four-layer 2s2p boards in accordance to JESD51- JEDEC standard. Special attention must be paid not to
exceed junction temperature TJ(max) at a given ambient temperate TA.
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
www.fairchildsemi.com
4
FAN2564 — 300mA Low VIN LDO for Digital Applications
Absolute Maximum Ratings
VIN(3)=VOUT + 0.5V or 1.8V (whichever is higher). TA=-40°C to +85°C, test circuit is Figure 1, typical values are at
TA=25°C, ILOAD=1 mA, VEN=VIN, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ. Max. Units
1.65
3.60
V
Power Supplies
VIN
Input Voltage Range
IGND
Ground Current
ISD
Shutdown Supply Current
V(EN)
I(EN)
ILOAD=0mA
45
75
A
ILOAD=300mA
140
200
A
VIN=3.6V, EN=GND
0.01
1.00
A
Enable High-level Input Voltage
0.95
Enable Low-level Input Voltage
Enable Input Leakage Current
0.4
EN=GND
V
0
EN=VIN=3.6V
2.5
4.0
A
Regulation
IOUT
Minimum Output Current
0
mA
IOUT
Maximum Output Current
300
mA
VDO
(4)
Dropout Voltage
ILOAD=300mA
1.8V, 2.5V
1.2V, 1.3V, 1.5V
∆VOUT
Output Voltage Accuracy
1.2V, 1.3V, 1.5V,
1.8V, 2.5V
∆VOUTline
100
Over Full VIN,
IOUT, at Room
Temperature
Over Full VIN,
IOUT, Temperature Range
VIN=VOUT(NOM) + 0.5V to 3.6V,
IOUT=1mA
Line Regulation
∆VOUTload Load Regulation
IOUT=1mA to 300mA
160
-1.0
1.0
-1.5
1.5
mV
%
-2.5
2.5
0.03
0.50
%/V
10
60
µV/mA
500
900
mA
900
mA
ISCP
Short-circuit Current Limit
ISU
Start-up Peak Current
EN Transition, LOW to HIGH
500
tON
Turn-on Time(5)
EN Transition, LOW to HIGH
100
µs
Startup Overshoot(5)
IOUT=1mA
0
%
Rising Temperature
+160
°C
Hysteresis
+30
°C
TSD
PSRR
en
Thermal Shutdown
(5)
Power Supply Rejection Ratio
f=1kHz
60
dB
Output Noise Voltage(5)
10Hz to 100kHz
100
µVRMS
600mV, tRISE=tFALL=30µs
±6
mV
1mA-300mA-1mA, tRISE=tFALL=1µs
±50
mV
Timing Characteristics
Peak
∆VOUTline
Line Transient Response(5)
Peak
Load Transient Response(5)
∆VOUTload
Note:
3. VIN voltage tolerance +/- 5%.
4. Dropout voltage is the minimum input to output differential voltage needed to maintain VOUT to within 5% of nominal value. This parameter is only specified for output voltages greater than or equal to 1.8V.
5. This electrical specification is guaranteed by design.
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
www.fairchildsemi.com
5
FAN2564 — 300mA Low VIN LDO for Digital Applications
Electrical Characteristics
Unless otherwise noted, VIN=VOUT(Nominal)+0.5V or 1.8V (whichever is greater), VOUT=1.2V,CIN=1µF, COUT=4.7µF,
and TA=25C.
Figure 6.
Output Voltage Change
vs. Temperature
Figure 8.
Dropout Voltage
Figure 7.
Output Voltage vs. Minimum Input
Voltage
Figure 9.
Ground Current vs. Load Current
Figure 10. Ground Current vs. VIN, ILOAD=1mA
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
www.fairchildsemi.com
6
FAN2564 — 300mA Low VIN LDO for Digital Applications
Typical Performance Characteristics
Unless otherwise noted, VIN=VOUT(Nominal)+0.5V or 1.8V (whichever is greater), VOUT=1.2V,CIN=1µF, COUT=4.7µF,
and TA=25C.
Figure 11. Load Transient, VOUT= 1.2V
Figure 12. Load Transient, VOUT= 2.8V
Figure 13. Line Transient, ILOAD= 1mA
Figure 14. Line Transient, ILOAD= 300mA
Figure 15. Enable Characteristics
Figure 16. Short Circuit Current
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
www.fairchildsemi.com
7
FAN2564 — 300mA Low VIN LDO for Digital Applications
Typical Performance Characteristics
Unless otherwise noted, VIN=VOUT(Nominal)+0.5V or 1.8V (whichever is greater), VOUT=1.2V,CIN=1µF, COUT=4.7µF,
and TA=25C.
Figure 17. Inrush Current
Figure 18. Inrush Current
Figure 19. Power Supply Rejection Ratio
Figure 20. Power Supply Rejection Ratio
Figure 21. Noise Density
Figure 22. Noise Density
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
www.fairchildsemi.com
8
FAN2564 — 300mA Low VIN LDO for Digital Applications
Typical Performance Characteristics
Enable and Soft Start
Thermal Considerations
A 1.4 M pull-down resistor ensures the EN pin to be in
LOW state when it is floating. The chip is in shut-down
mode when EN pin is LOW.
For best performance, the die temperature and the power dissipated should be kept at moderate values. The
maximum power dissipated can be evaluated based on
the following relationship:
To enable the chip, the EN pin needs to be raised higher
than 0.95V. The output pin starts to charge up to the final
voltage. On-chip soft-start circuitry limits the peak inrush
current through VIN pin to less than the specified typical
value of 500mA, regardless of COUT value and load conditions.
 TJ(max)  TA 
PD(max)  

 JA


(1)
where TJ(max) is the maximum allowable junction temperature of the die and TA is the ambient operating temperature. θJA is dependent on the surrounding PCB layout
and can be improved by providing a heat sink of surrounding copper ground.
The startup time increases as VOUT, COUT, and load increases, but meets the specified 100µs under the worst
load and VOUT conditions.
The addition of backside copper with through-holes, stiffeners, and other enhancements can also aid in reducing
θJA. The heat contributed by the dissipation of other devices located nearby must be included in design considerations.
Short-Circuit and Thermal Protection
The output current is short-circuit protected. When a
short-circuit fault occurs, the output current is automatically limited and VOUT drops, depending on the actual
short-circuit resistance.
Capacitors Selection
Short-circuit fault or output overload may cause the die
temperature to increase and exceed maximum ratings
due to power dissipation. In such cases, depending upon
the ambient temperature; VIN, load current, and the junction-to-air thermal resistance (θJA) of the die; the device
may enter thermal shutdown.
The FAN2564 is stable with a wide range of capacitor
values and sizes.
For loop stability, a 1µF input capacitor or bigger is recommended. Tolerance, temperature, and voltage coefficients of the capacitor must be considered to ensure
effective capacitance stays around 1µF or above. There
is no special requirement on its ESR value.
When the die temperature exceeds the shutdown limit
temperature, the onboard thermal protection disables the
output until the temperature drops below its hysteresis
value, at which point the output is re-enabled and a new
soft-start sequence occurs as described above.
An output capacitor with an effective capacitance between 1µF and 10µF is required for loop stability. The
ESR value should be within 5 to 100m. 2.2µF or 4.7µF
ceramic capacitors are recommended to ensure stability
over the full temperature, input, and output voltage range
of operation, such as those listed in Table 1.
Table 1. Recommended Capacitors
Capacitance
Size
Vendor
Part Number
1F
0603
MURATA
GRM188R71C105KA120
2.2F
0603
MURATA
GRM188R61A225KF340
2.2F
0402
MURATA
GRM155R60J225ME15
4.7F
0603
MURATA
GRM188C80G475KE19
4.7F
0402
MURATA
GRM155R60G475M
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
www.fairchildsemi.com
9
FAN2564 — 300mA Low VIN LDO for Digital Applications
Application Information
CIN and COUT should be placed close to the device for
optimal transient response and device behavior. A dedicated ground plane is recommended for proper GND
connection.
Figure 25. Bottom Layer
Figure 23. Assembly Diagram
Figure 24. Top Layer
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
www.fairchildsemi.com
10
FAN2564 — 300mA Low VIN LDO for Digital Applications
Layout Considerations
FAN2564 — 300mA Low VIN LDO for Digital Applications
Physical Dimensions
0.03 C
E
2X
F
A
PIN A1 AREA
B
0.50
D
0.50
(Ø0.250)
Cu Pad
(Ø0.350)
Solder Mask
0.03 C
2X
TOP VIEW
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
0.06 C
0.332±0.018
0.250±0.025
0.625
0.539
0.05 C
C
D
SEATING PLANE
SIDE VIEWS
0.005
0.50
C A B
Ø0.315±0.025
4X
B
A
0.50
A. NO JEDEC REGISTRATION APPLIES.
(Y)±0.018
F
1 2
(X)±0.018
NOTES:
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. DATUM C IS DEFINED BY THE SPHERICAL
CROWNS OF THE BALLS.
E. PACKAGE NOMINAL HEIGHT IS 582 MICRONS
±43 MICRONS (539-625 MICRONS).
BOTTOM VIEW
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
G. DRAWING FILENAME: MKT-UC004ABrev2.
Figure 26. 4-Bump, Wafer-Level Chip-Scale Package (WLCSP), 0.5mm Pitch
Product Specific Dimensions
Product
D
E
X
Y
FAN2564UCX
1.41 +/-0.030
0.93 +/-0.030
0.215
0.455
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
www.fairchildsemi.com
11
FAN2564 — 300mA Low VIN LDO for Digital Applications
Physical Dimensions
0.10 C
2.0
2X
A
B
1.60
1.50
2.0
6
4
0.50
0.10 C
2X
PIN1
IDENT
1.10
1.40
TOP VIEW
1
0.55 MAX
3
0.65
0.10 C
0.08 C
2.40
0.30
(0.15)
RECOMMENDED LAND PATTERN
0.05
0.00
C
SEATING
PLANE
SIDE VIEW
NOTES:
PIN1
IDENT
1
1.50
MAX
A. OUTLINE BASED ON JEDEC REGISTRATION
MO-229, VARIATION VCCC.
3
B. DIMENSIONS ARE IN MILLIMETERS.
6x
1.10
MAX
0.35
0.25
6
4
0.65
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. DRAWING FILENAME: MKT-UMLP06Crev1
0.35
6x
0.25
1.30
0.10 C A B
0.05 C
BOTTOM VIEW
Figure 27. 6-Pin, Ultrathin Molded Leadless Package (UMLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
www.fairchildsemi.com
12
FAN2564 — 300mA Low VIN LDO for Digital Applications
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
www.fairchildsemi.com
13