FD7T Series Multi-Output CMOS Clock Oscillator May 2008 • Pletronics’ FD7T Series is a quartz crystal controlled precision square wave generator with multiple independent CMOS outputs • Output frequencies from 12 KHz to 230 MHZ • Selectable low jitter or spread spectrum outputs. • Device characteristics may be either factory or field programmable • 1.8V, 2.5 or 3.3V LVCMOS outputs • 5 x 7 mm LCC Ceramic Package • Low power • This is a low cost, mass produced oscillator. • Tape and Reel or cut tape packaging is available. • The package is designed for high density surface mount designs Model Number PLLs Outputs FD77xxT 4 7 FD75xxT 3 5 FD74xxT 2 4 FD73xxT 1 3 Pletronics Inc. certifies this device is in accordance with the RoHS 6/6 (2002/95/EC) and WEEE (2002/96/EC) directives. Pletronics Inc. guarantees the device does not contain the following: Cadmium, Hexavalent Chromium, Lead, Mercury, PBB’s, PBDE’s Weight of the Device: 0.17 grams Moisture Sensitivity Level: 1 As defined in J-STD-020C Second Level Interconnect code: e4 Absolute Maximum Ratings: Parameter Unit VDD -0.5V to +2.5V VDDOUT -0.5V to +4.6V Vi Input Voltage -0.5V to VDD+ 0.5V Vo Output Voltage -0.5V to VDDOUT + 0.5V Io Continuous Output Current _ + 50 mA Tj Maximum Junction Temperature 125oC Thermal Resistance, Junction to Case 50oC/Watt Product information is current as of publication date. The product conforms to specifications per the terms of the Pletronics standard warranty. Production processsing does not necessarily include testing of all parameters. Copyright © 2007, 2008, Pletronics Inc. FD7T Series Multi-Output CMOS Clock Oscillator May 2008 BLOCK DIAGRAMS OF THE FD7T SERIES FD73xxT Vdd 1.8V (1) Vddout Reference oscillator optional Voltage controlled (5) Vcontrol (2) S0 Programming control (14) S1/SDA (13) MUX #1 PLL Multiplier #1 optional Spread Spectrum optional Bypass Mode Divider #1 /1 to /1023 Divider #2 /1 to /127 Y1 MUX #2 Y2 MUX #3 Y3 Divider #3 /1 to /127 eePROM S2/SCL (12) (11) Out1 (10) Out2 (9) Out3 SDA/SCL Registers Ground (3) Sx Control FD74xxT Vdd 1.8V (1) Vddout (5) Vcontrol (2) S0 (14) S1/SDA (13) Reference oscillator optional Voltage controlled PLL Multiplier #1 optional Spread Spectrum optional Bypass Mode eePROM SDA/SCL Registers Divider #2 /1 to /127 Divider #1 /1 to /1023 Y1 MUX #2 Y2 MUX #3 Y3 MUX #4 Y5 Divider #3 /1 to /127 Programming control S2/SCL (12) Ground (3) MUX #1 PLL Multiplier #2 optional Spread Spectrum optional Bypass Mode (11) Out1 (10) Out2 (9) Out3 (4) Out4 Divider #4 /1 to /127 Divider #5 /1 to /127 Sx Control www.pletronics.com 425-776-1880 2 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 FD75xxT Vdd 1.8V (1) MUX #1 Vddout (5) Vcontrol (2) Reference oscillator optional Voltage controlled PLL Multiplier #1 optional Spread Spectrum optional Bypass Mode Divider #2 /1 to /127 Divider #1 /1 to /1023 Y1 MUX #2 Y2 MUX #3 Y3 MUX #4 Y5 MUX #5 Y7 Divider #3 /1 to /127 S0 (14) S1/SDA (13) Programming control eePROM PLL Multiplier #2 optional Spread Spectrum optional Bypass Mode SDA/SCL Registers Sx Control Ground (3) PLL Multiplier #3 optional Spread Spectrum optional Bypass Mode Out1 (10) Out2 (9) Out3 (4) Out4 (8) Out5 (11) Out1 (10) Out2 (9) Out3 (4) Out4 (8) Out5 (6) Out6 (7) Out7 Divider #4 /1 to /127 Divider #5 /1 to /127 S2/SCL (12) (11) Divider #6 /1 to /127 Divider #7 /1 to /127 FD77xxT Vdd 1.8V (1) Vddout MUX #1 Divider #1 /1 to /1023 Y1 (5) PLL Multiplier #1 optional Spread Spectrum optional Bypass Mode Divider #2 /1 to /127 MUX #2 Y2 MUX #3 Y3 MUX #4 Y5 MUX #5 Y7 MUX #6 Y8 MUX #7 Y9 Divider #3 /1 to /127 Vcontrol (2) Reference oscillator optional Voltage controlled PLL Multiplier #2 optional Spread Spectrum optional Bypass Mode Divider #4 /1 to /127 Divider #5 /1 to /127 S0 (14) S1/SDA (13) Programming control PLL Multiplier #3 optional Spread Spectrum optional Bypass Mode Divider #7 /1 to /127 eePROM S2/SCL (12) SDA/SCL Registers Sx Control PLL Multiplier #4 optional Spread Spectrum optional Bypass Mode Divider #8 /1 to /127 Divider #9 /1 to /127 Ground (3) www.pletronics.com Divider #6 /1 to /127 425-776-1880 3 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Description: The FD7T series Multi-Output CMOS Clock Oscillator is a modular PLL-based low cost, high-performance, programmable oscillator. The FD7T generates up to seven output frequencies, OUT1 through OUT7. Frequencies are mutually independent and may be programmed to any frequency from 100KHz to 230MHZ and one output can be as low as 12KHz. There are versions including 1 to 4 PLLs, the number of PLLs impacts the cost. The FD7T base frequency, as noted in the device part number, is established during manufacture and is permanently fixed. For convenience, the divider for output OUT1 and the remaining seven output frequencies, and their characteristics may be pre-programmed at the factory, or field programmed. The FD7T has a separate output supply pin, VDDOUT, for either 1.8, 2.5 or 3.3V output logic levels. The device supply, VDD which provides power to all the internal circuits, is nominally 1.8V. The FD7xxxTL version has increased output drive for then 1.8V output levels. This version can be used at 1.8V VDDOUT only. The deep M/N PLL divider ratio allows the generation of zero-ppm clocks for applications such as WLAN, BlueTooth, Ethernet, GPS, USB, IEEE1394, etc. from the base frequency. Each of the independent PLLs supports Spread Spectrum Clocking (SSC). SSC may be programmed to be either center-spread or down-spread. This is an important technique to reduce electro-magnetic interference (EMI). The device supports non-volatile eePROM programming for easy customization of the device. As shipped, the device is pre-programmed. Standard combinations are denoted by three characters in the device part number. However, the FD7T may be reprogrammed to a different configuration. Reprogramming may be either prior to assembly, or in-circuit via a 2-wire SDA/SCL I2C bus. Three programmable control inputs, S0, S1 and S2, may be used to control various aspects of FD7T operation including selection of alternative frequency set(s), selection of SSC functionality, output tri-state and power-down. Reference Oscillator The Reference Oscillator is an AT cut quartz crystal based oscillator. This oscillator is very similar to the Pletronics SM77xxH product oscillator. This signal is the lowest jitter and can be an output on Out1, Out2 or Out3 and can be divided down by the Divider #1. The user may specify any frequency between 12MHz and 32MHz for this reference. All output frequencies are derived from (referenced to) this Reference Oscillator. Reference Oscillator - VCXO The reference oscillator frequency can be modulated by the Vcontrol input, if the VCXO option is selected. As this Reference Signal is the reference for all other parts of this circuit, all PLLs will be modulated also. The VCXO input has a limited voltage range, the VCXO is associated with the internal 1.8V core. A resistor in series with the Vcontrol input will permit interfacing to 3.3V analog circuits, the voltage range that changes the frequency will still be limited but the larger voltages swings will not cause problems. www.pletronics.com 425-776-1880 4 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 PLL Multipliers There are up to 4 each independent PLL Multipliers and these can multiply the Reference Oscillator frequency from 1 (bypass mode) to any value that is <=230MHz (the lowest frequency is the Reference Oscillator frequency). Each of the PLL Multipliers can have two setup options, 0 or 1, depending on which option is chosen and set by the Sx control signals and the user’s definitions are stored in eePROM. Spread Spectrum Each PLL has its individual Spread Spectrum (SS) function that can be enabled. This permits the modulation of the output frequency by a user-set amount. The modulation can be centered on the output frequency or down side only. Which of the 1 of 8 SS settings is being used is set by the Sx input and the user definition. The value is a percentage of the output frequency that will be modulated. SS Option Down Side Modulation Centered Modulation 0 No SS No SS 1 -0.25% + _ 0.25% 2 -0.50% + _ 0.50% 3 -0.75% + _ 0.75% 4 -1.00% + _ 1.00% 5 -1.25% + _ 1.25% 6 -1.50% + _ 1.50% 7 -2.00% + _ 2.00% Divider Section The dividers operate on the output of the PLLs. There are two dividers on each PLL that divide by 1 through 127, the value is user defined. There is only 1 setting allowed per divider. These are not set by the Sx input state. The dividers add very little jitter to the output signals. Multiplexers MUX #1 selects the input to the Divider #1, this can be the reference oscillator signal or the output from PLL Multiplier #1. MUX #2 through MUX #7 connect various divider outputs to the output buffers. The device can make only one of the setting of connections shown in the block diagram (only one pattern stored in eePROM). www.pletronics.com 425-776-1880 5 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Output Buffers Each output buffer can have 3 modes of operation: 1) Tri State 2) Active Low 3) The signal output of the Multiplexer The output buffers for Out2 and Out3 and the output buffers Out6 and Out7 function as pairs. When selecting on the function both outputs in the pair function the same. There can be two options stored for the Output Buffers, State 0 and State 1. The eight Sx input settings can have assigned one of the two Output Buffer states for each of Output Buffer sets. This permits wired ‘OR’ of tri-state outputs, this permits setting total enable and disable functions of all outputs. Control Inputs The three inputs, S0, S1/SDA and S2/SCL can be configured in two ways. 1) Used as 3 user inputs to permit up to 8 states, Sx input setting. 2) S0 used as an input to permit up to 2 states, S0 input setting. The SDA and SCL become clock and data inputs to write to the FD7T internal setting memory. The interface follows the I2C protocol. If the SDA and SCL are not set then the internal eePROM sets the operation. The S0, S1 and S2 input signals control and variations states allowed: Inputs PLL #1 PLL #2 PLL #3 PLL #4 Output S2 S1 S0 SS PLL SS PLL SS PLL SS PLL 1 2 3 4 5 6 7 0 0 0 0/7 0/1 0/7 0/1 0/7 0/1 0/7 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 0 1 0/7 0/1 0/7 0/1 0/7 0/1 0/7 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 1 0 0/7 0/1 0/7 0/1 0/7 0/1 0/7 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 1 1 0/7 0/1 0/7 0/1 0/7 0/1 0/7 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 0 0 0/7 0/1 0/7 0/1 0/7 0/1 0/7 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 0 1 0/7 0/1 0/7 0/1 0/7 0/1 0/7 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 1 0 0/7 0/1 0/7 0/1 0/7 0/1 0/7 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 1 1 0/7 0/1 0/7 0/1 0/7 0/1 0/7 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 The MUX inputs are fixed independent of the Sx setting. The Divider Values are fixed independent of the Sx setting Specifying The FD7T Device For A Specific Application Pletronics provides an EXCEL spreadsheet based program that assists in defining the FD77T functions. The program only permits setting of parameters that will properly function. After defining the desired functions, this spreadsheet is sent to Pletronics and the Configuration Part Number will then be assigned. Pletronics uses the values in the spreadsheet to program the devices for shipment. www.pletronics.com 425-776-1880 6 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 PART NUMBER: FD7 7 45 T L E -25.0M -YYY -XX Packaging code or blank T250 = 250 per Tape and Reel T500 = 500 per Tape and Reel T1K = 1000 per Tape and Reel Configuration Number This is a 3 character alpha-numeric code issued by Pletronics that defines the FD77T function (the output pin functions, the available frequencies and the pin number assignments). Each configuration is given a unique value. Base Frequency (Crystal oscillator frequency) in MHZ Optional Enhanced Operating temperature Range Blank = Temp. range -20oC to +70oC E = Temp. range -40oC to +85oC Blank = VDDOUT 3.3V, 2.5V and 1.8V device L = VDDOUT 1.8V only high output drive level device Series Model Frequency Stability for fixed frequency oscillator 45 = + _ 50 ppm 15 = + _ 15 ppm 44 = + _ 25 ppm 10 = + _ 10 ppm 20 = + _ 20 ppm Frequency Pull Ability for VCXO option enabled 99 = + _ 100 ppm Absolute Pull Range (APR) 75 = _ + 25 ppm Absolute Pull Range (APR) 50 = _ + 50 ppm Absolute Pull Range (APR) 7 = 7 outputs 5 = 5 outputs 4 = 4 outputs 3 = 3 outputs 4 PLL version 3 PLL version 2 PLL version 1 PLL version Series Model Part Marking: PLE FD7x ZZZ YMD Marking Legend: PLE = Pletronics ZZZ = configuration All other marking is internal factory codes X YMD = = Model type Date of Manufacture (year-month-day) Codes for Date Code YMD Code 8 9 0 1 2 Code A B C D E F G H J K L M Year 2008 2009 2010 2011 2012 Month JAN FEB MAR APR MAY JUN JUL AUG SEP OCT NOV DEC Code Day Code Day 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 A 10 B 11 C 12 D 13 E 14 F 15 H 17 J 18 K 19 L 20 M 21 N 22 P 23 R 24 T 25 U 26 V 27 W 28 X 29 Y 30 Z 31 www.pletronics.com 425-776-1880 7 G 16 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Electrical Specification over the specified temperature range Item Min Max Unit 12 32 MHZ Frequency Range OUT1 0.0117 230 MHZ Frequency Range OUT2 - 7 0.0945 230 MHZ “45" -50 +50 ppm “44" -25 +25 “20" -20 +20 Device Supply Voltage VDD 1.7 1.9 V Output Supply Voltage VDDOUT 1.7 3.6 V Output Supply Voltage “L” VDDOUT 1.7 1.9 V Low Level Input voltage -- 30 % of VDD High Level Input voltage 70 -- % of VDD Input Voltage Range, S0 If 1K ohm in series with S0 pad 0 -1 1.9 4.0 V VTH is 0.5 * VDD Input Voltage Range, S1, S2 0 3.6 V VTH is 0.5 * VDD Input current for: S0 with 1K ohm in series 0 3 mA VIN = 4V; VDD = 1.8V 0 5 µA VIN = VDD; VDD = 1.9V -4 0 µA VIN = 0.0VD; VDD = 1.9V Output Current, VDDOUT = 3.3V -12 +12 mA Output Current, VDDOUT = 2.5V -10 +10 mA Output Current, VDDOUT = 1.8V -5 +5 mA Output Current “L”, VDDOUT = 1.8V -8 +8 mA Output Load, LVCMOS -- 10 pf Higher loads can be used 2.9 -- V IOH = -0.1 mA 2.4 -- V IOH = -8.0 mA 2.2 -- V IOH = -12.0 mA -- 0.1 V IOH = +0.1 mA -- 0.5 V IOH = +8.0 mA -- 0.8 V IOH = +12.0 mA Rise & Fall Time -- 0.6 nS VDDOUT = 3.3v, 20 - 80%, 10pF Load Output Symmetry 45 55 % at 50% point of VDDOUT Base Frequency Frequency Accuracy Condition Base Frequency / (1 to 1023) -or- PLL1 For all supply voltages, load changes, aging for 1 year, shock, vibration and temperatures Recommended Operating Conditions S0, S1, S2 LVCMOS Output Parameters for VDDOUT = 3.3v Output High, VDDOUT = 3.3V Output Low, VDDOUT = 3.3V www.pletronics.com 425-776-1880 8 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Item Peak-to-Peak Jitter (1)(2) (1)(2) Cycle-to-Cycle Jitter Output Skew Min Max Unit Condition -- 100 pS 1 PLL Switching -- 180 pS 4 PLLs Switching -- 90 pS 1 PLL Switching -- 170 pS 4 PLLs Switching -- 60 pS OUT1 to OUT2 -- 160 pS OUT3 to OUT7 2.2 -- V IOH = -0.1 mA 1.7 -- V IOH = -6.0 mA 1.6 -- V IOH = -10.0 mA -- 0.1 V IOH = +0.1 mA -- 0.5 V IOH = +6.0 mA -- 0.7 V IOH = +10.0 mA -- 0.6 nS VDDOUT = 2.5v, 20 - 80%, 10pF Load 45 55 % at 50% point of VDDOUT -- 100 pS 1 PLL Switching -- 180 pS 4 PLLs Switching -- 90 pS 1 PLL Switching -- 170 pS 4 PLLs Switching -- 60 pS OUT1 to OUT2 -- 160 pS OUT3 to OUT7 1.6 -- V IOH = -0.1 mA 1.4 -- V IOH = -3.0 mA 1.1 -- V IOH = -6.0 mA -- 0.1 V IOH = +0.1 mA -- 0.3 V IOH = +3.0 mA -- 0.6 V IOH = +6.0 mA -- 0.9 nS VDDOUT = 1.8v, 20 - 80%, 10pF Load 45 55 % at 50% point of VDDOUT -- 140 pS 1 PLL Switching -- 190 pS 4 PLLs Switching -- 120 pS 1 PLL Switching -- 170 pS 4 PLLs Switching LVCMOS Output Parameters for VDDOUT = 2.5v Output High, VDDOUT = 2.5V Output Low, VDDOUT = 2.5V Rise & Fall Time Output Symmetry (1)(2) Peak-to-Peak Jitter (1)(2) Cycle-to-Cycle Jitter Output Skew LVCMOS Output Parameters for VDDOUT = 1.8v Output High, VDDOUT = 1.8V Output Low, VDDOUT = 1.8V Rise & Fall Time Output Symmetry (1)(2) Peak-to-Peak Jitter (1)(2) Cycle-to-Cycle Jitter www.pletronics.com 425-776-1880 9 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Item Output Skew Min Max Unit -- 60 pS OUT1 to OUT2 -- 160 pS OUT3 to OUT7 LVCMOS Output Parameters for VDDOUT = 1.8v Output High, VDDOUT = 1.8V Condition “L” Version 1.6 -- V IOH = -0.1 mA 1.4 -- V IOH = -4.0 mA 1.1 -- V IOH = -8.0 mA -- 0.1 V IOH = +0.1 mA -- 0.3 V IOH = +4.0 mA -- 0.6 V IOH = +8.0 mA 0.7 nS VDDOUT = 1.8v, 20 - 80%, 10pF Load 45 55 % at 50% point of VDDOUT -- 140 pS 1 PLL Switching -- 190 pS 4 PLLs Switching -- 120 pS 1 PLL Switching -- 170 pS 4 PLLs Switching -- 60 pS OUT1 to OUT2 -- 160 pS OUT3 to OUT7 Vcontrol Input Range Usable 0.5 VDD - 0.5V V The slope is positive Vcontrol Input Range Allowed - Direct connect to Vcontrol - Limit current to + _ 3mA 0.0 -1.0 VDD 4.0 V The slope is positive Recommend >=1K ohm to Vcontrol -10 +10 % Output Low, VDDOUT = 1.8V Rise & Fall Time Output Symmetry (1)(2) Peak-to-Peak Jitter (1)(2) Cycle-to-Cycle Jitter Output Skew VCXO Function Pull Ability specified in the P.N. Linearity (1) 10,000 cycles (2) Jitter depends on the device configuration. Data is taken under the following conditions: 1-PLL; 27MHz Crystal, Out2 and Out3 are 27MHz (measured at Out2). 4-PLL; 27MHz Crystal, Out2 and Out3 are 27MHz (measured at Out2). Out4 is 16.384MHz, Out5 is 74.25MHz, Out6 and Out7 are 48MHz. Frequency Tolerance: For the FD7x15T and the FD7x10T devices, Pletronics recommends that the tight tolerance be required on the PLL outputs only. In this case the reference frequency output would only achieve ±25ppm tolerance. This will reduce the cost of the device. www.pletronics.com 425-776-1880 10 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 FD7xxxT IDDOUT Current for Various Number of Outputs On No Load VDDOUT=2.5V VDDOUT=3.3V VDD=1.8V VDDOUT=1.8V 20 30 14 18 12 7 Outputs On 6 Outputs On 5 Outputs On 4 Outputs On 3 Outputs On 2 Outputs On 1 Output On All outputs Off 16 20 15 10 Idd out (mA) 14 Idd out (mA) Idd out (mA) 25 12 10 8 10 6 4 6 4 5 8 2 2 0 0 0 10 30 50 70 90 110 130 150 170 190 210 230 10 30 Fout (MHz) 50 70 Fout (MHz) Fout (MHz) FD7xxxTL VDD = VDDOUT=1.8V No Load FD7 Series IDD versus PLLs Used VDD=1.8V 10 90 9 7 6 5 4 3 2 Idd Current (mA) 80 7 Outputs On 6 Outputs On 5 Outputs On 4 Outputs On 3 Outputs On 2 Outputs On 1 Output On All outputs Off 8 Idd out (mA) 10 30 50 70 90 110 130 150 170 190 210 230 90 110 130 150 170 190 210 230 70 4 PLLs On 3 PLLs On 2 PLLs On 1 PLL On All PLLs Off 60 50 40 30 20 10 1 0 0 10 30 50 70 90 110 130 150 170 190 210 230 Fout (MHz) 10 30 50 70 90 110 130 150 170 190 210 230 PLL Frequency (MHz) Phase noise of the reference signal, Out1. 25MHz Reference Frequency RMS jitter is 1.4pS from 10Hz to 2MHz Example of the PLL synthesizing a frequency. 25MHz Reference Frequency Multiply by 8 to 200MHz Divide the 200MHz PLL output by 8 Phase noise plot of the resulting 25MHz on Out 2 www.pletronics.com 425-776-1880 11 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Load Circuit and Test Waveform Symmetry Vhigh 90% * Vcc 50% * Vcc 10% * Vcc Vlow Ground Trise Tfall Reliability: Environmental Compliance Parameter Condition Mechanical Shock MIL-STD-883 Method 2002, Condition B Vibration MIL-STD-883 Method 2007, Condition A Solderability MIL-STD-883 Method 2003 Thermal Shock MIL-STD-883 Method 1011, Condition A ESD Rating Model Minimum Voltage Conditions Human Body Model 1500 MIL-STD-883 Method 3115 Charged Device Model 1000 JESD 22-C101 www.pletronics.com 425-776-1880 12 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Mechanical: Inches 14 13 12 2 11 3 10 4 8 5 1 1 6 A 0.276 + _ 0.006 7.00 + _ 0.15 B 0.197 + _ 0.006 5.00 + _ 0.15 C 8 7 Contacts: Gold 11.8 µinches 0.3 µm minimum over Nickel 50 to 350 µinches 1.27 to 8.89 µm 1 Typical dimensions Not to Scale mm 0.067 max 1.70 max 1 D 0.050 1.27 E1 0.050 1.27 F1 0.004 0.10 G1 0.039 1.00 H1 0.025 0.63 I1 0.020 0.50 J1 0.004r 0.10r K1 0.008r 0.20r Package Labeling Label is 1" x 2.6" (25.4mm x 66.7mm) Font is Courier New Bar code is 39-Full ASCII www.pletronics.com 425-776-1880 Label is 1" x 2.6" (25.4mm x 66.7mm) Font is Arial 13 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Pad Functions FD73xxT: Pad Function Note Output Function O t h e r S S C S S D 1 Vsupply1 1.8V, powers internal circuitry of the oscillator. Bypass capacitor required near the package pin. 2 Vcontrol Frequency control input when the VCXO function is enabled 3 Ground (GND) 4 n.c. No connection or connect to ground (do not connect to a signal lead) 5 Vsupply2 1.8V, 2.5V or 3.3V supply for the output buffers. Sets CMOS output level. Bypass capacitor required near the package pin. 6 n.c. No connection or connect to ground (do not connect to a signal lead) 7 n.c. No connection or connect to ground (do not connect to a signal lead) 8 n.c. No connection or connect to ground (do not connect to a signal lead) 9 Out3 (Y3) Crystal reference frequency divider 1 and divided by 1 through 1023 X X X PLL1 frequency divider 2 and divided by 1 through 127 X X X PLL1 frequency divider 3 and divided by 1 through 127 X X X Crystal reference frequency divider 1 and divided by 1 through 1023 X PLL1 frequency divider 2 and divided by 1 through 127 X X X Crystal reference frequency divider 1 and divided by 1 through 1023 X PLL1 frequency divider 1 and divided by 1 through 1023 X X X 10 11 Out2 (Y2) Out1 (Y1) 12 S2 / SCL Serial Data Clock S2 13 S1 / SDA Serial Data S1 14 S0 Input to select 1 of 8 preprogrammed functions of the outputs S0 Other Logic “0" or tri-stated (off) SSC The output can have a spread spectrum centered about the output frequency. SSD The output can have a spread spectrum from the output frequency downward. All unused inputs should be pulled high. www.pletronics.com 425-776-1880 14 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Pad Functions FD74xxT: Pad Function Note Output Function O t h e r 1 Vsupply1 1.8V, powers internal circuitry of the oscillator. Bypass capacitor required near the package pin. 2 Vcontrol Frequency control input when the VCXO function is enabled 3 Ground (GND) 4 Out4 (Y5) S S C S S D X X PLL1 frequency divider 2 and divided by 1 through 127 PLL2 frequency divider 4 and divided by 1 through 127 X PLL2 frequency divider 5 and divided by 1 through 127 5 Vsupply2 1.8V, 2.5V or 3.3V supply for the output buffers. Sets CMOS output level. Bypass capacitor required near the package pin. 6 n.c. No connection or connect to ground (do not connect to a signal lead) 7 n.c. No connection or connect to ground (do not connect to a signal lead) 8 n.c. No connection or connect to ground (do not connect to a signal lead) 9 Out3 (Y3) Crystal reference frequency divider 1 and divided by 1 through 1023 X X X PLL1 frequency divider 2 and divided by 1 through 127 X X X PLL1 frequency divider 3 and divided by 1 through 127 X X X Crystal reference frequency divider 1 and divided by 1 through 1023 X PLL1 frequency divider 2 and divided by 1 through 127 X X X Crystal reference frequency divider 1 and divided by 1 through 1023 X PLL1 frequency divider 1 and divided by 1 through 1023 X X X 10 11 Out2 (Y2) Out1 (Y1) 12 S2 / SCL Serial Data Clock S2 13 S1 / SDA Serial Data S1 14 S0 Input to select 1 of 8 preprogrammed functions of the outputs S0 Other Logic “0" or tri-stated (off) SSC The output can have a spread spectrum centered about the output frequency. SSD The output can have a spread spectrum from the output frequency downward. All unused inputs should be pulled high. www.pletronics.com 425-776-1880 15 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Pad Functions FD75xxT: Pad Function Note Output Function O t h e r 1 Vsupply1 1.8V, powers internal circuitry of the oscillator. Bypass capacitor required near the package pin. 2 Vcontrol Frequency control input when the VCXO function is enabled 3 Ground (GND) 4 Out4 (Y5) S S C S S D X X PLL1 frequency divider 2 and divided by 1 through 127 PLL2 frequency divider 4 and divided by 1 through 127 X PLL2 frequency divider 5 and divided by 1 through 127 5 Vsupply2 1.8V, 2.5V or 3.3V supply for the output buffers. Sets CMOS output level. Bypass capacitor required near the package pin. 6 n.c. No connection or connect to ground (do not connect to a signal lead) 7 n.c. No connection or connect to ground (do not connect to a signal lead) 8 Out5 (Y7) PLL2 frequency divider 4 and divided by 1 through 127 X X X PLL3 frequency divider 6 and divided by 1 through 127 X X X PLL3 frequency divider 7 and divided by 1 through 127 X X X Crystal reference frequency divider 1 and divided by 1 through 1023 X X X PLL1 frequency divider 2 and divided by 1 through 127 X X X PLL1 frequency divider 3 and divided by 1 through 127 X X X Crystal reference frequency divider 1 and divided by 1 through 1023 X PLL1 frequency divider 2 and divided by 1 through 127 X X X Crystal reference frequency divider 1 and divided by 1 through 1023 X PLL1 frequency divider 1 and divided by 1 through 1023 X X X 9 10 11 Out3 (Y3) Out2 (Y2) Out1 (Y1) 12 S2 / SCL Serial Data Clock S2 13 S1 / SDA Serial Data S1 14 S0 Input to select 1 of 8 preprogrammed functions of the outputs S0 Other Logic “0" or tri-stated (off) SSC The output can have a spread spectrum centered about the output frequency. SSD The output can have a spread spectrum from the output frequency downward. All unused inputs should be pulled high. www.pletronics.com 425-776-1880 16 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Pad Functions FD77xxT: Pad Function Note Output Function O t h e r 1 Vsupply1 1.8V, powers internal circuitry of the oscillator. Bypass capacitor required near the package pin. 2 Vcontrol Frequency control input when the VCXO function is enabled 3 Ground (GND) 4 Out4 (Y5) S S C S S D X X PLL1 frequency divider 2 and divided by 1 through 127 PLL2 frequency divider 4 and divided by 1 through 127 X PLL2 frequency divider 5 and divided by 1 through 127 5 Vsupply2 1.8V, 2.5V or 3.3V supply for the output buffers. Sets CMOS output level. Bypass capacitor required near the package pin. 6 Out6 (Y8) PLL3 frequency divider 6 and divided by 1 through 127 X X X PLL4 frequency divider 8 and divided by 1 through 127 X X X PLL3 frequency divider 6 and divided by 1 through 127 X X X PLL4 frequency divider 8 and divided by 1 through 127 X X X PLL4 frequency divider 9 and divided by 1 through 127 X X X PLL2 frequency divider 4 and divided by 1 through 127 X X X PLL3 frequency divider 6 and divided by 1 through 127 X X X PLL3 frequency divider 7 and divided by 1 through 127 X X X Crystal reference frequency divider 1 and divided by 1 through 1023 X X X PLL1 frequency divider 2 and divided by 1 through 127 X X X PLL1 frequency divider 3 and divided by 1 through 127 X X X Crystal reference frequency divider 1 and divided by 1 through 1023 X PLL1 frequency divider 2 and divided by 1 through 127 X X X Crystal reference frequency divider 1 and divided by 1 through 1023 X PLL1 frequency divider 1 and divided by 1 through 1023 X X X 7 8 9 10 11 Out7 (Y9) Out5 (Y7) Out3 (Y3) Out2 (Y2) Out1 (Y1) 12 S2 / SCL Serial Data Clock S2 13 S1 / SDA Serial Data S1 14 S0 Input to select 1 of 8 preprogrammed functions of the outputs S0 Other Logic “0" or tri-stated (off) SSC The output can have a spread spectrum centered about the output frequency. SSD The output can have a spread spectrum from the output frequency downward. All unused inputs should be pulled high. www.pletronics.com 425-776-1880 17 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Temperature (°C) Reflow Cycle (typical for lead free-processing) 260°C Maximum 10 Seconds Maximum 250 215°C±10°C 200 175°C±10°C 150 100 Approximately 50 Seconds 120 to 160 Seconds Allowed rate of temperature change Maximum 4°C per second The part may be reflowed 2 times without degradation. Tape and Reel: available for quantities of 250 to 1000 per reel, cut tape for < 250 Constant Dimensions Table 1 Tape Size D0 8mm D1 Min E1 P0 1.0 12mm 1.5 16mm +0.1 -0.0 24mm P2 S1 Min T Max 0.6 0.6 T1 Max 2.0 +0.05 _ 1.75 1.5 4.0 _ +0.1 _0.1 + 1.5 0.1 2.0 _ +0.1 1.5 Variable Dimensions Table 2 Tape Size B1 Max E2 Min F P1 T2 Max W Max Ao, Bo & Ko 16 mm 12.1 14.25 7.5 _ +0.1 8.0 + _0.1 8.0 16.3 Note 1 Note 1: Embossed cavity to conform to EIA-481-B Not to scale REEL DIMENSIONS A inches 7.0 10.0 13.0 mm 177.8 254.0 330.2 B inches 2.50 4.00 3.75 mm 63.5 101.6 95.3 Tape Width C mm D mm 16.4 +2.0 -0.0 16.0 13.0 +0.5 / -0.2 16.4 +2.0 -0.0 16.4 +2.0 -0.0 Reel dimensions may vary from the above www.pletronics.com 425-776-1880 18 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 IMPORTANT NOTICE Pletronics Incorporated (PLE) reserves the right to make corrections, improvements, modifications and other changes to this product at any time. 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