FDD3680 100V N-Channel PowerTrench MOSFET General Description Features This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. • 25 A, 100 V. RDS(ON) = 46 mΩ @ V GS = 10 V RDS(ON) = 51 mΩ @ V GS = 6 V • Low gate charge (38 nC typical) These MOSFETs feature faster switching and lower gate charge than other MOSFETs with comparable RDS(ON) specifications. • Fast switching speed • High performance trench technology for extremely low RDS(ON) The result is a MOSFET that is easy and safer to drive (even at very high frequencies), and DC/DC power supply designs with higher overall efficiency. • High power and current handling capability. D D G G S TO-252 S Absolute Maximum Ratings Symbol Parameter V DSS Drain-Source Voltage V GSS Gate-Source Voltage ID Drain Current – Continuous Drain Current – Pulsed PD T A=25oC unless otherwise noted (Note 1) Units 100 V ±20 25 V A 100 Maximum Power Dissipation TJ , TSTG Ratings (Note 1) 68 (Note 1a) 3.8 (Note 1b) 1.6 W –55 to +175 °C (Note 1) 2.2 °C/W (Note 1b) 96 °C/W Operating and Storage Junction Temperature Range Thermal Characteristics RθJ C Thermal Resistance, Junction-to-Case RθJA Thermal Resistance, Junction-to-Ambient Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity FDD3680 FDD3680 13’’ 16mm 2500 units 2001 Fairchild Semiconductor Corporation FDD3680 Rev B1(W) FDD3680 February 2001 Symbol Parameter Test Conditions Drain-Source Avalanche Ratings WDSS IAR TA = 25°C unless otherwise noted Single Pulse Drain-Source Avalanche Energy Maximum Drain-Source Avalanche Current Min Typ Max Units (Note 1) V DD = 50 V, ID = 6.1 A 245 mJ 6.1 A Off Characteristics ∆BV DSS ∆TJ IDSS Drain–Source Breakdown V GS = 0 V, ID = 250 µA Voltage Breakdown Voltage Temperature ID = 250 µA, Referenced to 25°C Coefficient Zero Gate Voltage Drain Current V DS = 80 V, V GS = 0 V IGSSF Gate–Body Leakage, Forward V GS = 20 V, V DS = 0 V 100 µA nA IGSSR Gate–Body Leakage, Reverse V GS = –20 V V DS = 0 V –100 nA ID = 250 µA BV DSS On Characteristics 100 V –101 mV/°C 10 (Note 2) V GS(th) Gate Threshold Voltage V DS = V GS , ∆V GS(th) ∆TJ RDS(on) Gate Threshold Voltage Temperature Coefficient Static Drain–Source On–Resistance ID = 250 µA, Referenced to 25°C ID(on) gFS On–State Drain Current V GS = 10 V, V GS = 10 V, V GS = 6 V, V GS = 10 V, ID = 6.1 A ID = 6.1 A, TJ = 125°C ID = 5.8 A V DS = 5 V Forward Transconductance V DS = 5 V, ID = 6.1 A V DS = 50 V, f = 1.0 MHz V GS = 0 V, 2 2.4 4 –6.5 32 61 34 V mV/°C 46 92 51 25 mΩ 25 A S 1735 pF 176 pF 53 pF Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Switching Characteristics td(on) Turn–On Delay Time tr Turn–On Rise Time td(off) (Note 2) V DD = 50 V, V GS = 10 V, 14 25 ns 8.5 17 ns Turn–Off Delay Time 63 94 ns tf Turn–Off Fall Time 21 34 ns Qg Total Gate Charge 38 53 nC Qgs Gate–Source Charge Qgd Gate–Drain Charge V DS = 50 V, V GS = 10 V ID = 1 A, RGEN = 10 Ω ID = 6.1 A, 8.1 nC 9.2 nC Drain–Source Diode Characteristics and Maximum Ratings IS V SD Maximum Continuous Drain–Source Diode Forward Current Drain–Source Diode Forward V GS = 0 V, IS = 2.9 A (Note 2) Voltage 0.73 2.9 A 1.3 V Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while Rθ CA is determined by the user's board design. a) RθJA= 40oC/ W when mounted on a 1in2 pad of 2oz copper. b) RθJA= 96 oC/W on a minimum mounting pad. Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% FDD3680 Rev B1(W) FDD3680 Electrical Characteristics FDD3680 Typical Characteristics 1.8 40 5V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE ID , DRAIN-SOURCE CURRENT (A) VGS = 10V 4.5V 30 4V 20 10 3.5V 1.6 VGS =4.0V 1.4 4.5V 5.0V 1.2 6.0 V10V 1 0.8 0 0 2 4 0 6 10 20 Figure 1. On-Region Characteristics. 50 60 0.12 ID = 6.1A VGS = 10V 2.2 RDS(ON), ON-RESISTANCE (OHM) RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 40 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 2.6 1.8 1.4 1 0.6 0.2 ID = 3.0A 0.08 o TA = 125 C 0.04 o TA = 25 C 0 -50 -25 0 25 50 75 100 125 150 175 2 4 o 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) T J, JUNCTION TEMPERATURE ( C) Figure 3. On-Resistance Variation with Temperature. Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 100 40 VGS = 0V IS, REVERSE DRAIN CURRENT (A) VDS =5V ID , DRAIN CURRENT (A) 30 ID, DRAIN CURRENT (A) VD S, DRAIN-SOURCE VOLTAGE (V) 30 o 125 C 20 o TA = -55 C o 25 C 10 10 o TA = 125 C 1 o 25 C o -55 C 0.1 0.01 0.001 0 0 1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 1.4 VSD, BODY DIODE FORWARD VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDD3680 Rev B1(W) FDD3680 Typical Characteristics 3000 ID = 6.1A f = 1MHz VGS = 0 V VD S = 15V 30V 8 2500 50V CAPACITANCE (pF) VGS, GATE-SOURCE VOLTAGE (V) 10 6 4 2 2000 CISS 1500 1000 500 0 COSS 0 0 5 10 15 20 25 30 35 40 0 20 Q g, GATE CHARGE (nC) 60 80 100 Figure 8. Capacitance Characteristics. 40 100 RDS(ON) LIMIT P(pk), PEAK TRANSIENT POWER (W) 1000 100µs 1ms 10ms 100ms 10 1s 1 10s VGS = 10V SINGLE PULSE o RθJ A = 96 C/W 0.1 DC o TA = 25 C 0.01 0.1 1 10 100 SINGLE PULSE RθJ A = 96°C/W TA = 25°C 30 20 10 0 0.1 1000 1 VDS , DRAIN-SOURCE VOLTAGE (V) 10 100 1000 t1 , TIME (sec) Figure 9. Maximum Safe Operating Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 40 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics. ID, DRAIN CURRENT (A) CRSS Figure 10. Single Pulse Maximum Power Dissipation. 1 D = 0.5 R θJA(t) = r(t) + R θJA RθJA = 96°C/W 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 t1 0.01 t2 T J - T A = P * RθJA(t) Duty Cycle, D = t1 / t2 SINGLE PULSE 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 t1, TIME (sec) Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design. FDD3680 Rev B1(W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DOME™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST FASTr™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ PowerTrench QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER SMART START™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. 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