Fairchild FIN12ACMLX Low-voltage 12-bit bi-directional serializer/deserializer with multiple frequency ranges Datasheet

FIN12AC
Low-Voltage 12-Bit Bi-Directional
Serializer/Deserializer with Multiple Frequency Ranges
Features
Description
■ Low power consumption
The FIN12AC is a 12-bit serializer / deserializer capable
of running a parallel frequency range between 5MHz
and 40MHz, selected by the S1 and S2 control signals.
The bi-directional data flow is controlled through use of a
direction (DIRI) control pin. The devices can be configured to operate in a unidirectional mode only by hardwiring the DIRI pin. An internal Phase-Locked Loop (PLL)
generates the required bit clock frequency for transfer
across the serial link. Options exist for dual or single PLL
operation, dependent upon system operational parameters. The device has been designed for low power operation and utilizes Fairchild proprietary low-power control
Current Transistor Logic (CTL™) interface. The device
also supports an ultra low power power-down mode for
conserving power in battery-operated applications.
■ Fairchild proprietary low-power CTL™ interface
■ LVCMOS parallel I/O interface:
■
■
■
■
■
■
■
■
■
■
– 2mA source / sink current
– Over-voltage tolerant control signals
Parallel I/O power supply (VDDP) range between
1.65V and 3.6V
Analog power supply range of 2.5V to 3.3V
Multi-mode operation allows for a single device to
operate as Serializer or Deserializer
Internal PLL with no external components
Standby power-down mode support
Small footprint packaging:
– 32-terminal MLP and 42-ball BGA
Built-in differential termination
Supports external CKREF frequencies; 5MHz to 40MHz
Serialized data rate up to 560Mb/s
Voltage translation from 1.65V to 3.6V
Applications
■ Microcontroller or pixel interfaces
■ Image sensors
■ Small displays: LCD, cell phone, digital camera,
portable gaming, printer, PDA, video camera,
automotive
Ordering Information
Part Number
Operating
Temperature Range
FIN12ACGFX
-30 to +70°C
42-Ball Ultra Small Scale Ball Grid Array
(USS-BGA), JEDEC MO-195, 3.5mm Wide
Tape and Reel
FIN12ACMLX
-30 to +70°C
32-Terminal Molded Leadless Package
(MLP), Quad, JEDEC MO-220, 5mm Square
Tape and Reel
Package
Packing
Method
Pb-free package per JEDEC J-STD-020B.
µSerDes™ is a trademark of Fairchild Semiconductor Corporation.
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
April 2008
PLL
CKREF
STROBE
CKS0+
CKS0-
I
cksint
Register
DP[21:22]
+
-
0
Serializer
Control
DSO+/DSI-
+
-
Serializer
DP[1:20]
DSO-/DSI+
DP[23:24]
Register
Register
oe
+
-
Deserializer
Deserializer
Control
cksint
CKSI+
CKSI100
Termination
WORD CK
Generator
CKP
+
-
100 Gated
Termination
Control Logic
S1
S2
DIRO
Freq
Control
Direction
Control
DIRI
oe
Power Down
Control
Figure 1. Block Diagram
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
2
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
Functional Block Diagram
Pin Name
I/O Type
Number of
Terminals
DP[1:12]
I/O
12
LVCMOS parallel I/O, Direction controlled by DIRI pin
Description of Signals
CKREF
IN
1
LVCMOS clock input and PLL reference
STROBE
IN
1
LVCMOS strobe signal for latching data into the serializer
CKP
OUT
1
LVCMOS word clock output. This signal is the regenerated STROBE
signal
2
CTL differential serial I/O data signals(1)
DSO: Refers to output signal pair
DSI: Refers to input signal pair
DSO(I)+: Positive signal of DSO(I) pair
DSO(I)-: Negative signal of DSO(I) pair
2
CTL differential deserializer input bit clock
CKSI: Refers to signal pair
CKSI+: Positive signal of CKSI pair
CKSI-: Negative signal of CKSI pair
CTL differential deserializer output bit clock
CKSO: Refers to signal pair
CKSO+: Positive signal of CKSO pair
CKSO-: Negative signal of CKSO pair
DSO+ / DSIDSO- / DSI+
CKSI+ / CKSI-
DIFF-I/O
DIFF-IN
CKSO+ / CKSO-
DIFF-OUT
2
S1
IN
1
S2
IN
1
PLLx_SEL
IN
1
Used to define PLL multiplication mode.
PLLX_SEL = 0 multiplication factor 7-1/3x
PLLX_SEL = 1 multiplication factor 7x
DIRI
IN
1
LVCMOS control input. Used to control direction of data flow:
DIRI = “1” Serializer
DIRI = “0” Deserializer
DIRO
OUT
1
LVCMOS output, inversion of DIRI
VDDP
Supply
1
Power supply for parallel I/O and translation circuitry
VDDS
Supply
1
Power supply for core and serial I/O
VDDA
Supply
1
Power supply for analog PLL circuitry
GND
Supply
0
Use bottom ground plane for ground signals
Used to define frequency range for the RefClock, CKREF.
Note:
1 The DSO/DSI serial port pins have been arranged such that if one device is rotated 180° with respect to the other
device, the serial connections properly aligns without the need for any traces or cable signals to cross. Other layout
orientations may require that traces or cables cross.
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
3
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
Terminal Descriptions
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
Pin Assignments
25 DIRO
26 CKREF
27 STROBE
28 N/C
29 N/C
30 DP[1]
Pin Assignments for BGA
1
21 DSO-/DSI+
5
20 CKSI-
D
6
19 CKSI+
E
7
18 DIRI
8
17 VDDS
2
3
4
5
6
A
B
C
F
16
G
DP[10]
DP[11]
DP[12]
N/C
PLLx_SEL
S2
S1
VDDA
15
4
14
22 DSO+/DSI-
13
23 CKSO-
3
12
2
11
24 CKSO+
10
1
9
DP[4]
DP[5]
DP[6]
VDDP
CKP
DP[7]
DP[8]
DP[9]
31 DP[2]
32 DP[3]
Terminal Assignments for MLP
(Top View)
(Top View)
Figure 2. Terminal and Pin Assignments
BGA Pin Assignments
1
2
3
4
5
6
A
DP4
DP2
N/C
N/C
N/C
CKREF
B
DP6
DP5
DP1
N/C
STROBE
DIRO
C
CKP
N/C
DP3
N/C
CKSO+
CKSO-
D
N/C
DP7
VDDP
GND
DSO-/DSI+
DSO+/DSI-
E
DP8
DP9
GND
VDDS
CKSI+
CKSI-
F
DP10
DP11
N/C
VDDA
N/C
DIRI
G
DP12
N/C
N/C
PLLx_SEL
S2
S1
N/C = No Connect
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
4
The FIN12AC can be used as a 12-bit serializer or a 12bit deserializer. Terminals S1 and S2 must be set to
accommodate the clock reference input frequency range
of the serializer. Table 1 shows the terminal programming of these options based on the S1 and S2 control
terminals. When DIRI is asserted LOW, the device is
configured as a deserializer. When the DIRI terminal is
asserted HIGH, the device is configured as a serializer.
Changing the state on the DIRI signal reverses the direction of the I/O signals and generates the opposite state
signal on DIRO. For unidirectional operation, the DIRI
terminal should be hardwired to the HIGH or LOW state
and the DIRO terminal should be left floating. For bidirectional operation, the DIRI of the master device is
driven by the system and the DIRO signal of the master
is used to drive the DIRI of the slave device.
Turn-Around Functionality
PLL Multiplier
Mode 0 is used for powering down and resetting the
device. When both of the mode signals are driven to a
LOW state, the PLL and references are disabled, differential input buffers are shut off, differential output buffers
are placed into a HIGH-impedance state, LVCMOS outputs are placed into a HIGH-impedance state, LVCMOS
inputs are driven to a valid level internally, and all internal
circuitry are reset. The loss of CKREF state is also
enabled to ensure that the PLL only powers up if there is
a valid CKREF signal.
The device passes and inverts the DIRI signal through
the device asynchronously to the DIRO signal. Care
must be taken by the system designer to ensure that no
contention occurs between the deserializer outputs and
the other devices on this port. Optimally the peripheral
device driving the serializer should be put into a HIGHimpedance state prior to the DIRI signal being asserted.
When a device with dedicated data outputs turns from a
deserializer to a serializer, the dedicated outputs remain
at the last logical value asserted. This value only
changes if the device is once again turned into a deserializer and the values are overwritten.
Power-Down Mode
The multiply select pin PLLx_SEL determines whether
the PLL multiplication factor is 7 times the CKREF frequency or 7-1/3 times the CKREF frequency. Overclocking the PLL increases the range of spread spectrum on
the CKREF input clock that can be tolerated.
Both of the PLL multiplier modes can work with a nonspread spectrum clock. When operating with the standard 7x multiplier and operating in a CKREF = STROBE
mode, the serialized word is 14 data bits long. Each
deserializer output period has the same period of the
STROBE signal.
In a typical application mode, signals of the device do not
change other than between the desired frequency range
and the power-down mode. This allows for system-level
power-down functionality to be implemented via a single
wire for a SerDes pair. The S1 and S2 selection signals
that have their operating mode driven to a “logic 0”
should be hardwired to GND. The S1 and S2 signals that
have their operating mode driven to a “logic 1” should be
connected to a system-level power-down signal.
In the overclocking mode, the average deserializer
period is the same as the STROBE signal. The individual
periods vary between 14 and 16 data bits long. The pattern repeats every three cycles with two 14-bit cycles,
followed by a third 16-bit cycle. The last two bits in the
16-bit cycle are zero. The deserializer output clock
period has the same variation as the serializer outputs.
Table 1. Control Logic Circuitry
Mode
Number
PLLx_SEL
S2
S1
DIRI
0
X
0
0
X
Power-Down Mode
1
0
1
1
12-Bit Serializer, Standard Clocking, 20MHz to 40MHz CKREF
0
0
1
1
12-Bit Serializer, Over-Clocked PLL, 19MHz to 38.2MHz CKREF
X
0
1
0
12-Bit Deserializer
1
1
0
1
12-Bit Serializer, Standard Clocking, 5MHz to 14MHz CKREF
0
1
0
1
12-Bit Serializer, Over-Clocked PLL, 4.7MHz to 13.3MHz CKREF
X
1
0
0
12-Bit Deserializer
1
1
1
1
12-Bit Serializer, Standard Clocking, 8MHz to 28MHz CKREF
0
1
1
1
12-Bit Serializer, Over-Clocked PLL, 9.5MHz to 26.7MHz CKREF
X
1
1
0
12-Bit Deserializer
1
2
3
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
Description
www.fairchildsemi.com
5
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
Control Logic Circuitry
Serializer Operation: DIRI = 1, No CKREF
The serializer configurations are described in the following sections. The basic serialization circuitry works similarly in these modes, but the actual data and clock
streams differ, dependent on whether CKREF is the
same as the STROBE signal. When it is stated that
CKREF = STROBE, the CKREF and STROBE signals
have an identical frequency of operation, but may or may
not be phase aligned. When it is stated that CKREF does
not equal STROBE, each signal is distinct and CKREF
must be running at a frequency high enough to avoid any
loss of data condition. CKREF must never be a lower frequency than STROBE.
A third method of serialization uses a free-running bit
clock on the CKSI signal. This is enabled by grounding
the CKREF signal and driving the DIRI signal HIGH.
At power-up, the device is configured to accept a serialization clock from CKSI. If a CKREF is received, this
device enables the CKREF serialization mode. The
device remains in this mode even if CKREF is stopped.
To re-enable this mode, the device must be powered
down and powered back up with “logic 0” on CKREF.
Deserializer Operation Mode
The operation of the deserializer is dependent on the
data received on the DSI data signal pair and the CKSI
clock signal pair. The following sections describe the
operation of the deserializer under distinct serializer
source conditions. References to the CKREF and
STROBE signals refer to the signals associated with the
serializer device generating the serial data and clock signals that are inputs to the deserializer.
Serializer Operation: Modes, 1, 2, 3 DIRI = 1,
CKREF = STROBE
The PLL must receive a stable CKREF signal to achieve
lock prior to valid data being sent. During PLL stabilization phase, STROBE should not be connected to the
CKREF signal.
Once the PLL is stable and locked, the device can begin
to capture and serialize data. Data is captured on the
rising edge of the STROBE signal and serialized. When
operating in serializer mode, the internal deserializer circuitry is disabled, including the DS input buffer. The
CKSI serial inputs remain active to allow the pass
through of the CKSI signal to the CKP output.
When operating in derserializer mode, the internal serializer circuitry is disabled, including the parallel data input
buffers. If there is a CKREF signal provided, the CKSO
serial clock continues to transmit bit clocks. When S1
and S2 are asserted low, all CMOS outputs are driven
low at the output of the deserializer.
Deserializer Operation DIRI = 0 (Serializer
Source: CKREF = STROBE
Serializer Operation: DIRI=1, CKREF Does Not
= STROBE
When the DIRI signal is asserted LOW, the device is
configured as a deserializer. Data is captured on the
serial port and deserializer through use of the bit clock
sent with the data.
If this mode is not needed, the CKSI inputs can either be
driven to valid levels or left to float. For lowest power
operation, let the CKSI inputs float.If the same signal is
not used for CKREF and STROBE, the CKREF signal
must be run at a higher frequency than the STROBE rate
to serialize the data correctly. The actual serial transfer
rate remains at 14 times the CKREF frequency. A data
value of zero is sent when no valid data is present in the
serial bit stream. The operation of the serializer otherwise remains the same.
Deserializer Operation: PwrDwn = 1, DIRI = 0
(Serializer Source: CKREF Does Not = STROBE)
The logical operation of the deserializer remains the
same if the CKREF is equal in frequency to the STROBE
or at a higher frequency than the STROBE. The actual
serial data stream presented to the deserializer differs
because it has nonvalid data bits sent between words.
The duty cycle of CKP varies based on the ratio of the
frequency of the CKREF signal to the STROBE signal.
The frequency of the CKP signal is equal to the STROBE
frequency. The CKP HIGH time is equal to STROBE
period - half of the CKREF period.
The exact frequency that the reference clock needs is
dependent upon the stability of the CKREF and
STROBE signal. If the source of the CKREF signal
implements spread spectrum technology, the minimum
frequency of this spread spectrum clock should be used
in calculating the ratio of STROBE frequency to the
CKREF frequency. Similarly if the STROBE signal has
significant cycle-to-cycle variation, the maximum cycleto-cycle time needs to be factored into the selection of
the CKREF frequency.
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
6
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
Serializer Operation Mode
The LVCMOS input buffers have a nominal threshold
value equal to half VDDP . The input buffers are only
operational when the device is operating as a serializer.
When the device is operating as a deserializer, the inputs
are gated off to conserve power.
From
Deserializer
The LVCMOS 3-STATE output buffers are rated for a
source / sink current of 2mA at 1.8V. The outputs are
active when the DIRI signal is asserted LOW. When the
DIRI signal is asserted HIGH, the bi-directional LVCMOS
I/Os are in HIGH-Z state. Under purely capacitive load
conditions, the output swings between GND and VDDP.
DP[n]
To
Serializer
From
Control
Figure 3.
LVCMOS I/O
Application Mode Diagrams
Modes 1, 2, 3: Unidirectional Data Transfer
PLL
BIT CK
Gen.
STROBE_M
DP[1:12]_M
Register
Serializer
Control
+
–
+
–
CKSO
Work CK
Gen
CKSI
DS
Serializer
+
–
+
–
Master Device Operating as a Serializer
DIR = “1”
CKP_S
Deserializer
Control
Deserializer
Register
CKREF_M
DP[1:12]_S
Slave Device Operating as a Deserializer
DIR = “0”
Figure 4. Simplified Block Diagram for Unidirectional Serializer and Deserializer
Figure 4. shows basic operation when a pair of µSerDes is configured in an unidirectional operation mode.
Master Operation:
Slave Operation:
1. During power-up, the device is configured as a
serializer based on the value of the DIRI signal.
1. The device is configured as a deserializer at powerup based on the value of the DIRI signal.
2. The device accepts CKREF_M word clock and generates a bit clock, which is sent to the slave device
through the CKSO port.
2. The device accepts the bit clock on CKSI.
3. The device receives parallel data on the rising edge
of STROBE_M.
4. The device writes parallel data onto the DP_S port
and generates the CKP_S only when a valid data
word occurs.
3. The device deserializes the DS data stream using the
CKSI input clock.
4. The device generates and transmits serialized data
on the DS signals, which is source synchronous with
CKSO.
5. The device generates an embedded word clock for
each strobe signal.
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
7
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
LVCMOS Data I/O
Baseband
Processor
2.775
VDDP VDDA
PIXEL_CLK
VDD2
VDDS
VDDS VDDA
FIN12AC
FIN12AC
CKP
VSYNC
PIXEL_CLK
LCD
Display
Module
STROBE
CKREF
CKSI+
CKSIDATA[7:0]
DSO-/DSI+ DP[8:1]
HSYNC
DSO+/DSI- DP[9]
DP[10] VSYNC
CKSOCKSO+ DP[12:11]
CKSO+
CKSODP[8:1] DSO+/DSIDP[9] DSO-/DSI+
DP[10]
CKSIDP[12:11]
CKSI+
HSYNC
VDDP
CKREF
STROBE
CKP
DATA[7:0]
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
VDD1
VDD1
DIRO
DIRO
DIRI
S2
DIRI
S2
S1
S1
PWRDWN
Note:
VDD1 does not have to equal VDD2.
Figure 5. Unidirectional 8-bit RGB Interface (10MHz to 40MHz Operation)
VDD1
Baseband
Processor
Camera
Interface
VDDP VDDA
2.775
VDD2
VDDS
VDDS VDDA
FIN12AC
MASTER_CLK
PIXEL_CLK
YUV[7:0]
HSYNC
VSYNC
VDDP
FIN12AC
CKP
CKREF
STROBE
CKP
CKREF
CKSI+
STROBE
CKSIDSO-/DSI+ DP[8:1]
DSO+/DSI- DP[9]
DP[10]
CKSOCKSO+ DP[12:11]
CKSO+
CKSODP[8:1] DSO+/DSIDP[9] DSO-/DSI+
DP[10]
CKSIDP[12:11]
CKSI+
MASTER_CLK
CMOS
Image
Sensor
PIXEL_CLK
DATA[7:0]
HSYNC
VSYNC
VDD2
DIRO
DIRI
S2
DIRO
S2
S1
DIRI
S1
PWRDWN
MODE0
MODE1
Note:
VDD1 does not have to equal VDD2.
Figure 6. Unidirectional 8-bit YUV Sensor with Master Clock on Base (10MHz to 40MHz Operation)
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
8
For the serializer:
For some applications, it is desirable to pass a word
clock across a differential signal pair in the opposite
direction of serialization. The FIN12AC supports this
mode of operation.
1. Connect CKSO of the deserializer to CKSI of the
serializer.
2. CKSI passes the signal to CKP.
When PLL-bypass mode is used, the bit clock toggles on
the CKP signal.
For the deserializer:
1. DIRI = LOW
2. CKREF = LOW
3. Word clock should be connected to the STROBE.
This passes the STROBE signal out the CKSO port.
Table 2. Control I/O
Mode Number
DIRI
DIRO
CKSO
CKP
0
x
Z
Z
Z
1, 2, 3
0
1
CKSO = STROBE
1, 2, 3
1
0
Serializer
Output Bit Clock
Mode of Operation
Power Down Mode: S2 = 0, S1 = 0
Deserializer
Deserializer: Any active mode
Output STROBE
CKSI
Serializer: Any active mode
Flex Circuit Design Guidelines
The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex cable.
The following best practices should be used when developing the flex cabling or Flex PCB:
■ Keep all four differential wires the same length.
■ Allow no noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential wires.
■ Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom.
■ Do not place test points on differential serial wires.
■ Use differential serial wires a minimum of 2cm away from the antenna.
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
9
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
STROBE Pass-Through Mode
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
Symbol
VDD
IOS
TSTG
Parameter
Min.
Max.
Unit
Supply Voltage
-0.5
+4.6
V
All Input/Output Voltage
-0.5
+4.6
V
+150
°C
CTL Output Short-Circuit Duration
Continuous
Storage Temperature Range
-65
TJ
Maximum Junction Temperature
+150
°C
TL
Lead Temperature (Soldering, 4 seconds)
+260
°C
ESD
Human Body Model, JESD22-A114,Serial I/O Pins
8.0
Human Body Model, JESD22-A114, All Pins
2.5
Charged Device Model, JESD22-C101
1.5
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Min.
Max.
Unit
VDDA, VDDS Supply Voltage
2.5
3.3
V
Supply Voltage
1.65
3.6
V
Operating Temperature
-30
+70
°C
100
mVPP
VDDP
TA
VDDA-PP
Parameter
Supply Noise Voltage
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
10
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
Absolute Maximum Ratings
Over-supply voltage and operating temperature ranges, unless otherwise specified. Typical values are given for VDD =
2.775V and TA = 25°C. Positive current values refer to the current flowing into the device and negative values refer to
current flowing out of pins. Voltages are referenced to GROUND unless otherwise specified (except ΔVOD and VOD).
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
LVCMOS I/O
VIH
Input High Voltage
0.65 x VDDP
VDDP
VIL
Input Low Voltage
GND
0.35 x VDDP
V
VDDP = 3.3 ±0.30
VOH
Output High Voltage
IOH = –2.0mA VDDP = 2.5 ±0.20
V
0.75 x VDDP
VDDP = 1.8 ±0.15
VDDP = 3.3 ±0.30
VOL
Output Low Voltage
IOL = 2.0mA
VDDP = 2.5 ±0.20
0.25 x VDDP
V
5.0
µA
VDDP = 1.8 ±0.15
IIN
Input Current
VIN = 0V to 3.6V
–5.0
Differential I/O
IODH
Output HIGH Source
Current
VOS = 1.0V, Figure 7
–1.75
mA
IODL
Output LOW Sink
Current
VOS = 1.0V, Figure 7
0.950
mA
IOZ
Disabled Output
Leakage Current
CKSO, DSO = 0V to VDDS
S2 = S1 = 0V
±1.0
±5.0
µA
IIZ
Disabled Input
Leakage Current
CKSI, DSI = 0V to VDDS
S2 = S1 = 0V
±1.0
±5.0
µA
VICM
Input Common Mode
Range
VDDS = 2.775 ±5%
VGO
Input Voltage Ground
Offset Relative to
Driver(2)
Figure 8
RTRM
CKSI Internal Receiver
Termination Resistor
VID = 50mV, VIC = 925mV, DIRI = 0
| CKSI+ – CKSI– | = VID
80.0
100
120
Ω
RTRM
CKSI Internal Receiver
Termination Resistor
VID = 50mV, VIC = 925mV, DIRI = 0
| DSI+ – DSI– | = VID
80.0
100
120
Ω
VGO + 0.80
V
0
V
Note:
2 VGO is the difference in device ground levels between the CTL driver and the CTL receiver.
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
11
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
DC Electrical Characteristics
The worst-case test pattern produces a maximum toggling of internal digital circuits, CTL I/O and LVCMOS I/O with the
PLL operating at the reference frequency unless otherwise specified. Maximum power is measured at the maximum
VDD values. Minimum values are measured at the minimum VDD values. Typical values are measured at VDD = 2.5V.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Unit
IDDA1
All DP and Control Inputs at 0V or
VDDA Serializer Static Supply Current VDD NOCKREF, S2 = 0, S1 = 1,
DIR = 1
437
µA
IDDA2
VDDA Deserializer Static Supply
Current
All DP and Control Inputs at 0V or
VDD NOCKREF, S2 = 0, S1 = 1,
DIR = 0
528
µA
IDDS1
All DP and Control Inputs at 0V or
VDDS Serializer Static Supply Current VDD NOCKREF, S2 = 0, S1 = 1,
DIR = 1
4.4
mA
IDDS2
VDDS Deserializer Static Supply
Current
All DP and Control Inputs at 0V or
VDD NOCKREF, S2 = 0, S1 = 1,
DIR = 0
5.5
mA
IDD_PD
VDD Power-Down Supply Current
IDD_PD = IDDA + IDDS + IDDP
S1 = S2 = 0
All Inputs at GND or VDD
1.0
µA
S2 = H 5MHz
S1 = L 14MHz
14:1 Dynamic Serializer
IDD_SER1 Power Supply Current
IDD_SER1 = IDDA + IDDS + IDDP
14:1 Dynamic Deserializer
IDD_DES1 Power Supply Current
IDD_DES1 = IDDA + IDDS + IDDP
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
CKREF = STROBE
S2 = H
DIRI = H
S1 = H
Figure 10
S2 = L
S1 = H
8.5
15.0
10MHz
9.5
28MHz
17.0
20MHz
11.0
40MHz
17.0
S2 = H 5MHz
S1 = L 14MHz
6.5
CKREF = STROBE
S2 = H
DIRI = L
S1 = H
Figure 10
S2 = L
S1 = H
mA
7.5
10MHz
7.0
28MHz
10.0
20MHz
8.5
40MHz
11.5
mA
www.fairchildsemi.com
12
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
Power Supply Currents
Characteristics at recommended over-supply voltage and operating temperature ranges, unless otherwise specified.
Typical values are given for VDD = 2.775V and TA = 25°C. Positive current values refer to the current flowing into
device and negative values refer to current flowing out of pins. Voltages are referenced to GROUND unless otherwise
specified (except ΔVOD and VOD).
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
CKREF = STROBE
S2=1 S1=0
Figure 13
71.0
200
S2=1 S1=1
35.0
100
S2=0 S1=1
25.0
50.0
S2=1 S1=0
1.1 x
fSTROBE
40
Unit
Serializer Input Operating Conditions
tTCP
ƒREF
CKREF Clock Period
(5MHz – 40MHz)
CKREF Frequency Relative to
STROBE Frequency
CKREF does not =
STROBE
S2=1 S1=0
14
S2=0 S1=1
28
ns
MHz
tCPWH
CKREF Clock High Time
0.2
0.5
T
tCPWL
CKREF Clock Low Time
0.2
0.5
T
tCLKT
LVCMOS Input Transition Time
Figure 13
tSPWH
STROBE Pulse Width HIGH/LOW
Figure 13
fMAX
Maximum Serial Data Rate
tSTC
DP(n) Setup to STROBE
tHTC
DP(n) Hold to STROBE
CKREF x 14
(T x 4)/14
90.0
ns
(T x 12)/14
ns
540
S2=0 S1=1
280
S2=1 S1=0
70
196
S2=1 S1=1
140
392
DIRI = 1
Figure 3 (f = 5MHz)
Mb/s
2.5
ns
2.0
ns
Serializer AC Electrical Characteristics
tTCCD
Transmitter Clock Input to Clock
Output Delay
DIRI = 1, a=(1/f)/14
CKREF = STROBE,
tSPOS
CKSO Position Relative to DS(3)
Figure 17
23a+1.5
21a+6.5
ns
-200
200
ps
Figure 15
200
µs
Figure 18
30.0
µs
Figure 19
20.0
ns
PLL AC Electrical Characteristics
tTPLLS0
Serializer Phase-Lock Loop
Stabilization Time
tTPLLD0 PLL Disable Time Loss of Clock
tTPLLD1 PLL Power-Down
Time(4)
Deserializer AC Electrical Characteristics
tRCOP
Deserializer Clock Output
(CKP OUT) Period
tRCOL
CKP OUT Low Time
tRCOH
CKP OUT High Time(6)
Figure 14
17.8
200
ns
Figure 14 (Rising Edge Strobe)
Serializer source STROBE =
CKREF
where a = (1/f)/14
7a–3
7a+3
ns
7a–3
7a+3
ns
7a–3
7a+3
ns
3.5
7.0
ns
3.5
7.0
ns
tPDV
Data Valid to CKP LOW(6)
Figure 14 (Rising Edge Strobe)
where a = (1/f)/14
tROLH
Output Rise Time (20% to 80%)
tROHL
Output Fall Time (80% to 20%)
CL = 5pF
Figure 11
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
13
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
AC Electrical Characteristics
Control Logic Timing Controls
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
tPHL_DIR,
tPLH_DIR
Propagation Delay
DIRI-to-DIRO
DIRI LOW-to-HIGH or HIGH-to-LOW
17
ns
tPLZ, tPHZ
Propagation Delay
DIRI-to-DP
DIRI LOW-to-HIGH
25
ns
tPZL, tPZH
Propagation Delay
DIRI-to-DP
DIRI HIGH-to-LOW
25
ns
tPLZ, tPHZ
Deserializer Disable Time
S0 or S1 to DP
DIRI = 0, S1(2) = 0 and S2(1) = LOW-to-HIGH
Figure 21
25
ns
tPZL, tPZH
Deserializer Enable Time
S0 or S1 to DP(7)
DIRI = 0, S1(2) = 0 and S2(1) = LOW-to-HIGH
Figure 21
2
µs
tPLZ, tPHZ
Serializer Disable Time
S0 or S1 to CKSO, DS
DIRI = 1, S1(2) = 0 and S2(1) = HIGH-to-LOW
Figure 20
25
ns
tPZL, tPZH
Serializer Enable Time
S0 or S1 to CKSO, DS
DIRI = 1, S1(2) and S2(1) = LOW-to-HIGH
Figure 20
65
ns
Note:
7 Serializer enable time includes the amount of time required for internal voltage and current references to stabilize.
This time is significantly less than the PLL lock time and does not limit overall system startup time.
Capacitance
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
CIN
Capacitance of Input Only Signals, CKREF, DIRI = 1, S1 = 0, S2=0,
STROBE, S1, S2, DIRI
VDD = 2.5V
2
pF
CIO
Capacitance of Parallel Port Pins DP[1:12]
DIRI = 1, S1 = 0, S2=0,
VDD = 2.5V
2
pF
Capacitance of Differential I/O Signals
DIRI = 1, S2=0, S1 = 0,
VDD = 2.5V
2
pF
CIO-DIFF
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
14
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
Notes:
3 Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO).
Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid.
4 The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the
state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies
dependent upon the operating mode of the device.
5 Signals are transmitted from the serializer source synchronously. Note that, in some cases, data is transmitted when
the clock remains at a HIGH state. Skew should only be measured when data and clock are transitioning at the same
time. Total measured input skew would be a combination of output skew from the serializer, load variations, and ISI
and jitter effects.
6 Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP
occurs approximately 8 bit times after a data transition or 6 bit times after the falling edge of CKSO. Variation of the
data with respect to the CKP signal is due to internal propagation delay differences of the data and CKP path and
propagation delay differences on the various data pins. Note that if the CKREF is not equal to STROBE for the
serializer, the CKP signal does not maintain a 50% duty cycle.The low time of CKP remains 13 bit times.
DS+
DUT
RL/2
VOD
Input
RL/2
DUT
+
+
–
–
VOS
DS-
100Ω Termination
+
– VGO
Figure 8. CTL Input Common
Mode Test Circuit
Figure 7. Differential CTL
Output DC Test Circuit
T
DP[1:24]
666h
999h
666h
CKREF
CKS0Note:
The “worst-case” test pattern produces a maximum toggling of internal digital curcuits, CTL I/O and LVCMOS I/O with PLL operating at the reference frequency,
unless otherwise specified. Maximum power is measured at the maximum VDD values. Minimum values are measured at the minimum VDD values.
Typical values are measured at VDD = 2.5V.
Figure 9. “Worst Case” Serializer Test Pattern
tTLH
80%
80%
VDIFF 20%
20%
DPn
VDIFF = (DS+) – (DS-)
DS+
5 pF
80%
DPn 20%
20%
+
–
tROHL
tROLH
tTHL
80%
5pF
1000Ω
100Ω
DSFigure 11. LVCMOS Output Load
and Transition Times
Figure 10. CTL Output Load
and Transition Times
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
15
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
AC Loading and Waveforms
tCLKT
Setup Time
tCLKT
tSTC
90%
90%
STROBE
DP[1:12]
Data
10%
tHTC
Hold Time
tTCP
STROBE
CKREF 50%
DP[1:12]
10%
VIH
VIL
Data
tCPWH
50%
tCPWL
Setup: MODE0 = “0” or “1”, MODE1 = “1”, SER/DES = “1”
Figure 13. LVCMOS Clock Parameters
Figure 12. Serial Setup and Hold Time
Data Time
tPDV
CKP
tTPLLS0
Data
DP[1:12]
VDD/VDDA
tRCOP
CKREF
50%
S1 or S2
75%
50%
25%
tRCOH
tRCOL
CKREF
CKS0
Note: CKREF Signa is free running.
Setup: DIRI = “0”, CKSI and DS are valid signals.
Figure 15. Serializer PLL Lock Time
Figure 14. Deserializer Data Valid Window Time and
Clock Output Parameters
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
16
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
AC Loading and Waveforms (Continued)
CKSOCKSI-
DSO+
VDIFF=0
CKSI+
VDIFF = 0
CKSO+
tH_DS
tS_DS
VID / 2
VDIFF = 0
DSO-
DSI+
VDIFF=0
DSI-
VID/2
tSPOS
Figure 16. Differential Input
Setup and Hold Times
Figure 17. Differential Output Signal Skew
tTPPLD0
CKREF
tTPPLD1
S1 or S2
CKS0
CKS0
Note: CKREF Signal can be stopped either High or LOW.
Figure 18. PLL Loss of Clock Disable Time
Figure 19. PLL Power-Down Time
tPLZ(HZ)
tPZL(ZH)
tPLZ(HZ)
S1 or S2
S1 or S2
DS+,CKS0+
DS–,CKS0-
tPZL(ZH)
DP
HIGHZ
Note: CKREF must be active and PLL must be stable.
Note: If S1(2) transitioning, then S2(1) must = 0 for test to be valid.
Figure 21. Deserializer Enable
and Disable Times
Figure 20. Serializer Enable and Disable Time
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
17
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
AC Loading and Waveforms (Continued)
MLP Embossed Tape Dimension
Dimensions are in millimeters.
D
P0
T
P2
E
F
K0
Wc
W
B0
Tc
A0
P1
D1
User Direction of Feed
Package
A0
±0.1
B0
±0.1
D
±0.05
D1
Min.
E
±0.1
F
±0.1
K0
±0.1
P1
Typ.
P0
Typ.
P2
±0/05
T
Typ.
TC
±0.005
W
±0.3
WC
Typ.
5x5
5.35
5.35
1.55
1.50
1.75
5.50
1.40
8.00
4.00
2.00
0.30
0.07
12.00 9.30
6x6
6.30
6.30
1.55
1.50
1.75
5.50
1.40
8.00
4.00
2.00
0.30
0.07
12.00 9.30
Notes:
Ao, Bo, and Ko dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement
requirements (see sketches A, B, and C).
Shipping Reel Dimensions
Dimensions are in millimeters.
1.0mm
maximum
10° maximum
Typical component
cavity center line
Typical component
center line
B0
10° maximum component rotation
1.0mm
maximum
Sketch A (Side or Front Sectional View)
Sketch C (Top View)
A0
Sketch B (Top View)
Component Rotation
Component lateral movement
Component Rotation
W2 max Measured at Hub
W1 Measured at Hub
B Min
Dia C
Dia A
max
Dia D
min
Dia N
DETAIL AA
See detail AA
W3
Tape
Width
Dia A
Max.
Dim B
Min.
Dia C
+0.5/–0.2
Dia D
Min.
Dim N
Min.
Dim W1
+2.0/–0
Dim W2
Max.
Dim W3
(LSL–USL)
8
330.0
1.5
13.0
20.2
178.0
8.4
14.4
7.9 ~ 10.4
12
330.0
1.5
13.0
20.2
178.0
12.4
18.4
11.9 ~ 15.4
16
330.0
1.5
13.0
20.2
178.0
16.4
22.4
15.9 ~ 19.4
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
18
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
Tape and Reel Specification
2X
3.50
0.10 C
2X
(0.35)
(0.5)
0.10 C
(0.6)
2.5
(0.75)
TERMINAL
A1 CORNER
INDEX AREA
4.50
3.0
0.5
0.5
Ø0.3±0.05
BOTTOM VIEW
X42
0.15
0.05
C A B
C
0.89±0.082
(QA CONTROL VALUE)
0.45±0.05
1.00 MAX
0.21±0.04
0.10 C
C
0.2+0.1
-0.0
0.08 C
0.23±0.05
SEATING PLANE
LAND PATTERN
RECOMMENDATION
Figure 22. 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide
Note: Click here for tape and reel specifications, available at:
http://www.fairchildsemi.com/products/analog/packaging/bga42.html.
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the
most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
19
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
Physical Dimensions
Figure 23. 32-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO-220, 5mm Square
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the
most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
20
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
Physical Dimensions (Continued)
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
21
www.fairchildsemi.com
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2