AEC Q100 Grade 1 Compliant FM25CL64B – Automotive Temp. 64Kb Serial 3V F-RAM Memory Features 64K bit Ferroelectric Nonvolatile RAM Organized as 8,192 x 8 bits High Endurance 10 Trillion (1013) Read/Writes NoDelay™ Writes Advanced High-Reliability Ferroelectric Process Fast Serial Peripheral Interface - SPI Up to 16 MHz Frequency Direct Hardware Replacement for EEPROM SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Description Sophisticated Write Protection Scheme Hardware Protection Software Protection Low Power Consumption Low Voltage Operation 3.0-3.6V 6 A Standby Current (+85 C) Industry Standard Configuration Automotive Temperature -40 C to +125 C o Qualified to AEC Q100 Specification “Green”/RoHS 8-pin SOIC Pin Configuration The FM25CL64B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The FM25CL64B performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte has been transferred to the device. The next bus cycle may commence without the need for data polling. The FM25CL64B is capable of supporting 1013 read/write cycles, or 10 million times more write cycles than EEPROM. These capabilities make the FM25CL64B ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding automotive controls where the long write time of EEPROM can cause data loss. CS SO WP 1 8 2 7 3 6 VSS 4 5 Pin Name /CS /WP /HOLD SCK SI SO VDD VSS VDD HOLD SCK SI Function Chip Select Write Protect Hold Serial Clock Serial Data Input Serial Data Output Supply Voltage Ground Ordering Information The FM25CL64B provides substantial benefits to users of serial EEPROM as a hardware drop-in replacement. The FM25CL64B uses the high-speed SPI bus, which enhances the high-speed write capability of FRAM technology. Device specifications are guaranteed over the automotive temperature range of -40°C to +125°C. FM25CL64B-GA FM25CL64B-GATR “Green”/RoHS 8-pin SOIC, Automotive Grade 1 “Green”/RoHS 8-pin SOIC, Automotive Grade 1, Tape & Reel This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Cypress Semiconductor Corporation • Document Number: 001-86149 Rev. *A 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 07, 2013 FM25CL64B - Automotive Temp. WP Instruction Decode Clock Generator Control Logic Write Protect CS HOLD SCK 1,024 x 64 FRAM Array Instruction Register ` Address Register Counter SI 13 8 Data I/O Register SO 3 Nonvolatile Status Register Figure 1. Block Diagram Pin Descriptions Pin Name /CS I/O Input SCK Input /HOLD Input /WP Input SI Input SO Output VDD VSS Supply Supply Description Chip Select: This active low input activates the device. When high, the device enters low-power standby mode, ignores other inputs, and all outputs are tri-stated. When low, the device internally activates the SCK signal. A falling edge on /CS must occur prior to every op-code. Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. Since the device is static, the clock frequency may be any value between 0 and 16 MHz and may be interrupted at any time. Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation for another task. When /HOLD is low, the current operation is suspended. The device ignores any transition on SCK or /CS. All transitions on /HOLD must occur while SCK is low. Write Protect: This active low pin prevents write operations to the Status Register. This is critical since other write protection features are controlled through the Status Register. A complete explanation of write protection is provided below. *Note that the function of /WP is different from the FM25040 where it prevents all writes to the part. Serial Input: All data is input to the device on this pin. The pin is sampled on the rising edge of SCK and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications. * SI may be connected to SO for a single pin data interface. Serial Output: This is the data output pin. It is driven during a read and remains tristated at all other times including when /HOLD is low. Data transitions are driven on the falling edge of the serial clock. * SO may be connected to SI for a single pin data interface. Power Supply (3.0V to 3.6V) Ground Document Number: 001-86149 Rev. *A Page 2 of 15 FM25CL64B - Automotive Temp. Overview The FM25CL64B is a serial FRAM memory. The memory array is logically organized as 8,192 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM25CL64B and a serial EEPROM with the same pinout is the FRAM‟s superior write performance. Memory Architecture When accessing the FM25CL64B, the user addresses 8,192 locations of 8 data bits each. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code, and a two-byte address. The upper 3 bits of the address range are „don‟t care‟ values. The complete address of 13-bits specifies each byte address uniquely. Most functions of the FM25CL64B either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25CL64B due to its fast write cycle and high endurance as compared with EEPROM. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM25CL64B contains no power management circuits other than a simple internal power-on reset. It is the user‟s responsibility to ensure that VDD is within datasheet tolerances to prevent incorrect operation. up to 16 MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25CL64B operates in SPI Mode 0 and 3. The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. It is possible to connect the two data pins together. Figure 2 illustrates a typical system configuration using the FM25CL64B with a microcontroller that offers an SPI port. Figure 3 shows a similar configuration for a microcontroller that has no hardware support for the SPI bus. Protocol Overview The SPI interface is a synchronous serial interface using clock and data pins. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25CL64B will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25CL64B supports modes 0 and 3. Figure 4 shows the required signal relationships for modes 0 and 3. For both modes, data is clocked into the FM25CL64B on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After /CS is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Note that the WREN and WRDI op-codes are commands with no subsequent data transfer. Important: The /CS pin must go inactive after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select. Serial Peripheral Interface – SPI Bus The FM25CL64B employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds Document Number: 001-86149 Rev. *A Page 3 of 15 FM25CL64B - Automotive Temp. SCK MOSI MISO SO SPI Microcontroller SI SCK SO SI SCK FM25CL64B FM25CL64B CS CS HOLD HOLD SS1 SS2 HOLD1 HOLD2 MOSI: Master Out, Slave In MISO: Master In, Slave Out SS: Slave Select Figure 2. System Configuration with SPI port SO Microcontroller SI SCK FM25CL64B CS HOLD Figure 3. System Configuration without SPI port SPI Mode 0: CPOL=0, CPHA=0 7 6 5 4 3 2 1 0 SPI Mode 3: CPOL=1, CPHA=1 7 6 5 4 3 2 1 0 Figure 4. SPI Modes 0 & 3 Document Number: 001-86149 Rev. *A Page 4 of 15 FM25CL64B - Automotive Temp. Data Transfer All data transfers to and from the FM25CL64B occur in 8-bit groups. They are synchronized to the clock signal (SCK), and they transfer most significant bit (MSB) first. Serial inputs are registered on the rising edge of SCK. Outputs are driven from the falling edge of SCK. Command Structure There are six commands called op-codes that can be issued by the bus master to the FM25CL64B. They are listed in the table below. These op-codes control the functions performed by the memory. They can be divided into three categories. First, there are commands that have no subsequent operations. They perform a single function such as to enable a write operation. Second are commands followed by one byte, either in or out. They operate on the Status Register. The third group includes commands for memory transactions followed by address and one or more bytes of data. Table 1. Op-code Commands Name Description Set Write Enable Latch WREN Write Disable WRDI Read Status Register RDSR Write Status Register WRSR Read Memory Data READ WRITE Write Memory Data Op-code 0000 0000 0000 0000 0000 0000 0110b 0100b 0101b 0001b 0011b 0010b WREN - Set Write Enable Latch The FM25CL64B will power up with writes disabled. The WREN command must be issued prior to any write operation. Sending the WREN op-code will allow the user to issue subsequent op-codes for write operations. These include writing the Status Register and writing the memory. Sending the WREN op-code causes the internal Write Enable Latch to be set. A flag bit in the Status Register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. Attempting to write the WEL bit in the Status Register has no effect. Completing any write operation will automatically clear the write-enable latch and prevent further writes without another WREN command. Figure 5 below illustrates the WREN command bus configuration. WRDI - Write Disable The WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that writes are disabled by reading the WEL bit in the Status Register and verifying that WEL=0. Figure 6 illustrates the WRDI command bus configuration. Figure 5. WREN Bus Configuration Figure 6. WRDI Bus Configuration Document Number: 001-86149 Rev. *A Page 5 of 15 FM25CL64B - Automotive Temp. RDSR - Read Status Register The RDSR command allows the bus master to verify the contents of the Status register. Reading Status provides information about the current state of the write protection features. Following the RDSR opcode, the FM25CL64B will return one byte with the contents of the Status register. The Status register is described in detail in a later section. WRSR – Write Status Register The WRSR command allows the user to select certain write protection features by writing a byte to the Status register. Prior to issuing a WRSR command, the /WP pin must be high or inactive. Note that on the FM25CL64B, /WP only prevents writing to the Status register, not the memory array. Prior to sending the WRSR command, the user must send a WREN command to enable writes. Note that executing a WRSR command is a write operation and therefore clears the Write Enable Latch. Figure 7. RDSR Bus Configuration Figure 8. WRSR Bus Configuration (WREN not shown) Status Register & Write Protection The write protection features of the FM25CL64B are multi-tiered. First, a WREN op-code must be issued prior to any write operation. Assuming that writes are enabled using WREN, writes to memory are controlled by the Status register. As described above, writes to the Status Register are performed using the WRSR command and subject to the /WP pin. The Status register is organized as follows. Table 2. Status Register Bit Name 7 WPEN 6 0 5 0 4 0 3 BP1 2 BP0 1 WEL 0 0 Bits 0 and 4-6 are fixed at 0 and cannot be modified. Note that bit 0 (“Ready” in EEPROMs) is unnecessary as the FRAM writes in real-time and is never busy. The WPEN, BP1 and BP0 control write protection features. They are nonvolatile (shaded Document Number: 001-86149 Rev. *A yellow). The WEL flag indicates the state of the Write Enable Latch. Attempting to directly write the WEL bit in the Status Register has no effect on its state. This bit is internally set and cleared via the WREN and WRDI commands, respectively. BP1 and BP0 are memory block write protection bits. They specify portions of memory that are write protected as shown in the following table. Table 3. BP1 0 0 1 1 Block Memory Write Protection BP0 Protected Address Range 0 None 1 1800h to 1FFFh (upper ¼) 0 1000h to 1FFFh (upper ½) 1 0000h to 1FFFh (all) Page 6 of 15 FM25CL64B - Automotive Temp. The BP1 and BP0 bits and the Write Enable Latch are the only mechanisms that protect the memory from writes. The remaining write protection features protect inadvertent changes to the block protect bits. The WPEN bit controls the effect of the hardware /WP pin. When WPEN is low, the /WP pin is ignored. When WPEN is high, the /WP pin controls write access to the Status Register. Thus the Status register is write protected if WPEN=1 and /WP=0. Table 4. Write Protection WEL WPEN /WP 0 X X 1 0 X 1 1 0 1 1 1 Protected Blocks Protected Protected Protected Protected Memory Operation The SPI interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the FRAM technology. Unlike SPI-bus EEPROMs, the FM25CL64B can perform sequential writes at bus speed. No page register is needed and any number of sequential writes may be performed. Write Operation All writes to the memory array begin with a WREN op-code. The next op-code is the WRITE instruction. This op-code is followed by a two-byte address value. The upper 3-bits of the address are ignored. In total, the 13-bits specify the address of the first data byte of the write operation. Subsequent bytes are data and they are written sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 1FFFh is reached, the counter will roll over to 0000h. Data is written MSB first. A write operation is shown in Figure 9. Unlike EEPROMs, any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (after the Document Number: 001-86149 Rev. *A This scheme provides a write protection mechanism, which can prevent software from writing the memory under any circumstances. This occurs if the BP1 and BP0 are set to 1, the WPEN bit is set to 1, and /WP is set to 0. This occurs because the block protect bits prevent writing memory and the /WP signal in hardware prevents altering the block protect bits (if WPEN is high). Therefore in this condition, hardware must be involved in allowing a write operation. The following table summarizes the write protection conditions. Unprotected Blocks Protected Unprotected Unprotected Unprotected Status Register Protected Unprotected Protected Unprotected 8th clock). The rising edge of /CS terminates a WRITE op-code operation. Read Operation After the falling edge of /CS, the bus master can issue a READ op-code. Following this instruction is a twobyte address value. The upper 3-bits of the address are ignored. In total, the 13-bits specify the address of the first byte of the read operation. After the op-code and address are complete, the SI line is ignored. The bus master issues 8 clocks, with one bit read out for each. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 1FFFh is reached, the counter will roll over to 0000h. Data is read MSB first. The rising edge of /CS terminates a READ op-code operation. A read operation is shown in Figure 10. Hold The /HOLD pin can be used to interrupt a serial operation without aborting it. If the bus master pulls the /HOLD pin low while SCK is low, the current operation will pause. Taking the /HOLD pin high while SCK is low will resume an operation. The transitions of /HOLD must occur while SCK is low, but the SCK pin can toggle during a hold state. Page 7 of 15 FM25CL64B - Automotive Temp. CS 0 1 2 3 4 5 6 7 0 1 2 X X X 3 4 5 3 4 5 6 7 0 1 2 3 4 5 6 7 4 3 2 1 0 7 6 Data 5 4 3 2 1 0 SCK op-code SI 0 0 0 0 0 0 1 0 13-bit Address 12 11 10 MSB LSB MSB LSB SO Figure 9. Memory Write (WREN not shown) CS 0 1 2 3 4 5 6 7 0 1 2 X X X 3 4 5 3 4 5 6 7 4 3 2 1 0 0 1 2 3 4 5 Data 4 3 5 6 7 SCK op-code SI 0 0 0 0 0 0 1 1 13-bit Address 12 11 10 MSB LSB MSB SO 7 LSB 6 2 1 0 Figure 10. Memory Read Endurance The FM25CL64B devices are capable of being accessed at least 1013 times, reads or writes. An FRAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. The F-RAM architecture is based on an array of rows and columns. Rows are defined by A12-A3 and column addresses by A2-A0. See Block Diagram (pg 2) which shows the array as 1K rows of 64-bits each. The entire row is internally accessed once whether a single byte or all eight bytes are read or written. Each byte in the row is counted only once in an endurance calculation. The table below shows endurance calculations for 64-byte repeating loop, which includes an op-code, a starting address, and a sequential 64-byte data stream. This causes each byte to experience one endurance cycle through the loop. F-RAM read and write endurance is virtually unlimited even at 10MHz clock rate. Table 5. Time to Reach Endurance Limit for Repeating 64-byte Loop SCK Freq Endurance Endurance Years to Reach (MHz) Cycles/sec. Cycles/year Limit 10 18,660 5.88 x 1011 17.0 5 9,330 2.94 x 1011 34.0 1 1,870 5.88 x 1010 170.1 Document Number: 001-86149 Rev. *A Page 8 of 15 FM25CL64B - Automotive Temp. Electrical Specifications Absolute Maximum Ratings Symbol Description VDD Power Supply Voltage with respect to VSS VIN Voltage on any pin with respect to VSS TSTG TLEAD VESD Storage Temperature Lead Temperature (Soldering, 10 seconds) Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) Package Moisture Sensitivity Level Ratings -1.0V to +5.0V -1.0V to +5.0V and VIN < VDD+1.0V -55 C to + 125 C 260 C 4kV 1.25kV 300V MSL-1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40 C to +125 C, VDD = 3.0V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units VDD Power Supply Voltage 3.0 3.3 3.6 V IDD VDD Supply Current @ SCK = 1.0 MHz 0.3 mA @ SCK = 16.0 MHz 3 mA ISB Standby Current 6 @ +85 C A 20 @ +125 C A ILI Input Leakage Current 1 A ILO Output Leakage Current 1 A VIH Input High Voltage 0.75 VDD VDD + 0.3 V VIL Input Low Voltage -0.3 0.25 VDD V VOH Output High Voltage VDD – 0.5 V @ IOH = -2 mA VOL Output Low Voltage 0.4 V @ IOL = 2 mA VHYS Input Hysteresis 0.05 VDD V Notes 1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. SCK = SI = /CS=VDD. All inputs VSS or VDD. 3. VSS VIN VDD and VSS VOUT VDD. 4. Characterized but not 100% tested in production. Applies only to /CS and SCK pins. Document Number: 001-86149 Rev. *A Notes 1 2 3 3 4 Page 9 of 15 FM25CL64B - Automotive Temp. AC Parameters Symbol fCK tCH tCL tCSU tCSH tOD tODV tOH tD tR tF tSU tH tHS tHH tHZ tLZ Notes 1. 2. 3. (TA = -40 C to +125 C, VDD = 3.0V to 3.6V unless otherwise specified) Parameter Min Max SCK Clock Frequency 0 16 Clock High Time 25 Clock Low Time 25 Chip Select Setup 10 Chip Select Hold 10 Output Disable Time 20 Output Data Valid Time 25 Output Hold Time 0 Deselect Time 60 Data In Rise Time 50 Data In Fall Time 50 Data Setup Time 5 Data Hold Time 5 /HOLD Setup Time 10 /HOLD Hold Time 10 /HOLD Low to Hi-Z 20 /HOLD High to Data Active 20 Notes Units pF pF Notes 1 1 1 1 2 2,3 2,3 2 2 tCH + tCL = 1/fCK. Characterized but not 100% tested in production. Rise and fall times measured between 10% and 90% of waveform. Capacitance (TA = 25 C, f=1.0 MHz, VDD = 3.3V) Symbol Parameter CO Output Capacitance (SO) CI Input Capacitance Notes 1. Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min - Max 8 6 This parameter is periodically sampled and not 100% tested. AC Test Conditions Input Pulse Levels Input rise and fall times 10% and 90% of VDD 5 ns Input and output timing levels Output Load Capacitance 0.5 VDD 30 pF Power Cycle Timing VDD VDD min tVF tVR tPU tPD CS Power Cycle Timing (TA = -40 C to +125 C, VDD = 3.0V to 3.6V unless otherwise specified) Symbol Parameter Min Max Units tPU VDD(min) to First Access Start 1 ms tPD Last Access Complete to VDD(min) 0 s tVR VDD Rise Time 30 s/V tVF VDD Fall Time 20 s/V Notes 1. Slope measured at any point on VDD waveform. Document Number: 001-86149 Rev. *A Notes 1 1 Page 10 of 15 FM25CL64B - Automotive Temp. Serial Data Bus Timing tD tF tCSU tSU tR 1/fCK tCL tCH tCSH tH tODV tOH tOD /Hold Timing Data Retention (VDD = 3.0V to 3.6V unless otherwise specified) Automotive Grade SS Retention AEC-Q100 Grade 3 AEC-Q100 Grade 2 AEC-Q100 Grade 1 Unlimited Unlimited Unlimited Experiment Results OS Retention 10.9 yrs @ 85OC 5.5 years @ 105OC 11,200 hours @ 125OC 10 Years 5 Years 11k Hours Note : Data retention qualification tests are accelerated tests and are performed such that all three conditions have been applied : (1) 10 years at a temperature of +85 C, (2) 5 years at +105 C, and (3) 11,000 hours at +125 C. Document Number: 001-86149 Rev. *A Page 11 of 15 FM25CL64B - Automotive Temp. Opposite State Data Retention Graphs for Grade 1, 2 and 3 Automotive: These specifications can be used for different multi-temperature thermal profiles. Example of an AEC – Q100 Grade 1 Automotive F-RAM application. Temperature ( T ) Time Factor Profile Life Time (t) L( P ) T1 = 125oC T2 = 105oC T3 = 85oC T4 = 55oC Document Number: 001-86149 Rev. *A 10% 15% 25% 50% > 10.46 years Page 12 of 15 FM25CL64B - Automotive Temp. Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012 variation AA) Recommended PCB Footprint 7.70 3.90 ±0.10 3.70 6.00 ±0.20 2.00 Pin 1 0.65 1.27 4.90 ±0.10 1.27 0.33 0.51 0.25 0.50 1.35 1.75 0.10 0.25 0.19 0.25 45 0.10 mm 0 -8 0.40 1.27 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. SOIC Package Marking Scheme XXXXXXX-PT RRLLLLLZ RICYYWW Legend: XXXXXXX = part number, P = package type, T = temp (A = automotive grade, blank = ind.) RR = rev code, LLLLL = lot code, Z = Package code RIC = Ramtron Int‟l Corp, YY = year, WW = work week = Pb-free Example: FM25CL64B, “Green”/RoHS SOIC, Automotive Temperature Rev. BA, Lot 64179, SOIC Year 2013, Work Week 07 Pb-free 25CL64B-GA BA64179S RIC1307 Document Number: 001-86149 Rev. *A Page 13 of 15 FM25CL64B - Automotive Temp. Revision History Revision 1.0 1.1 3.0 3.1 3.2 Date 2/18/2011 5/3/2011 9/12/2011 3/31/2012 10/31/2012 Summary Initial release. Added ESD ratings. Changed to Production status. Improved tPU and tVF specs. Changed Retention specifications Document History Document Title: FM25CL64B 64Kb Serial 3V F-RAM Memory (Automotive Temp) Document Number: 001-86149 Revision ECN Orig. of Change Submission Date ** 3912930 GVCH 02/25/2013 New Spec *A 3985108 GVCH 05/07/2013 Updated SOIC package marking scheme Document Number: 001-86149 Rev. *A Description of Change Page 14 of 15 FM25CL64B - Automotive Temp. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions Automotive cypress.com/go/automotive Clocks & Buffers cypress.com/go/clocks Interface cypress.com/go/interface Lighting & Power Control cypress.com/go/powerpsoc cypress.com/go/plc Cypress Developer Community Memory cypress.com/go/memory Community | Forums | Blogs | Video | Training PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch Technical Support USB Controllers cypress.com/go/usb cypress.com/go/support psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 RAMTRON is a registered trademark and NoDelay™ is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. © Cypress Semiconductor Corporation, 2011-2013. The information contained herein is subject to change without notice. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-86149 Rev. *A Page 15 of 15