Pre-Production
FM25V05
512Kb Serial 3V F-RAM Memory
Features
512K bit Ferroelectric Nonvolatile RAM
• Organized as 65,536 x 8 bits
• High Endurance 100 Trillion (1014) Read/Writes
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Very Fast Serial Peripheral Interface - SPI
• Up to 40 MHz Frequency
• Direct Hardware Replacement for Serial Flash
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Device ID and Serial Number
• Device ID reads out Manufacturer ID & Part ID
• Unique Serial Number (FM25VN05)
Low Voltage, Low Power
• Low Voltage Operation 2.0V – 3.6V
• 90 µA Standby Current (typ.)
• 5 µA Sleep Mode Current (typ.)
Industry Standard Configurations
• Industrial Temperature -40°C to +85°C
• 8-pin “Green”/RoHS SOIC Package
Write Protection Scheme
• Hardware Protection
• Software Protection
Description
The FM25V05 is a 512-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by Serial
Flash and other nonvolatile memories.
Unlike Serial Flash, the FM25V05 performs write
operations at bus speed. No write delays are incurred.
Data is written to the memory array immediately
after it has been transferred to the device. The next
bus cycle may commence without the need for data
polling. The product offers very high write
endurance, orders of magnitude more endurance than
Serial Flash. Also, F-RAM exhibits lower power
consumption than Serial Flash.
These capabilities make the FM25V05 ideal for
nonvolatile memory applications requiring frequent
or rapid writes or low power operation. Examples
range from data collection, where the number of
write cycles may be critical, to demanding industrial
controls where the long write time of Serial Flash can
cause data loss.
The FM25V05 provides substantial benefits to users
of Serial Flash as a hardware drop-in replacement.
The devices use the high-speed SPI bus, which
enhances the high-speed write capability of F-RAM
This is a product in the pre-production phase of development. Device
characterization is complete and Ramtron does not expect to change the
specifications. Ramtron will issue a Product Change Notice if any
specification changes are made.
Rev. 2.0
May 2010
technology. The FM25VN05 is offered with a unique
serial number that is read-only and can be used to
identify a board or system. Both devices incorporate
a read-only Device ID that allows the host to
determine the manufacturer, product density, and
product revision. The devices are guaranteed over an
industrial temperature range of -40°C to +85°C.
Pin Configuration
S
1
8
VDD
Q
2
7
HOLD
W
3
6
C
VSS
4
5
D
Pin Name
/S
/W
/HOLD
C
D
Q
VDD
VSS
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage
Ground
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 16
FM25V05 - 512Kb SPI FRAM
W
S
Instruction Decode
Clock Generator
Control Logic
Write Protect
HOLD
C
8192 x 64
FRAM Array
Instruction Register
Address Register
Counter
16
8
D
Data I/O Register
Q
3
Nonvolatile Status
Register
Figure 1. Block Diagram
Pin Descriptions
Pin Name
/S
I/O
Input
C
Input
/HOLD
Input
/W
Input
D
Input
Q
Output
VDD
VSS
Supply
Supply
Rev. 2.0
May 2010
Description
Chip Select: This active-low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the C signal. A falling edge on /S must occur prior
to every op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 40 MHz and may be interrupted at
any time.
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on C or /S. All transitions on /HOLD must occur while C is low.
This pin has a weak internal pull-up (see RIN spec, pg 11). However, if it is not used,
the /HOLD pin should be tied to VDD.
Write Protect: This active-low pin prevents write operations to the Status Register
only. A complete explanation of write protection is provided on pages 6 and 7. If not
used, the /W pin should be tied to VDD.
Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of C and is ignored at other times. It should always be driven to a valid
logic level to meet IDD specifications.
* D may be connected to Q for a single pin data interface.
Serial Output: This is the data output pin. It is driven during a read and remains tristated at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* Q may be connected to D for a single pin data interface.
Power Supply
Ground
Page 2 of 16
FM25V05 - 512Kb SPI FRAM
Overview
The FM25V05 is a serial F-RAM memory. The
memory array is logically organized as 65,536 x 8
and is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the F-RAM is similar to Serial Flash. The major
differences between the FM25V05 and a Serial Flash
with the same pinout are the F-RAM’s superior write
performance, very high endurance, and lower power
consumption.
Memory Architecture
When accessing the FM25V05, the user addresses
64K locations of 8 data bits each. These data bits are
shifted serially. The addresses are accessed using the
SPI protocol, which includes a chip select (to permit
multiple devices on the bus), an op-code, and a twobyte address. The complete address of 16-bits
specifies each byte address uniquely.
Most functions of the FM25V05 either are controlled
by the SPI interface or are handled automatically by
on-board circuitry. The access time for memory
operation is essentially zero, beyond the time needed
for the serial protocol. That is, the memory is read or
written at the speed of the SPI bus. Unlike Serial
Flash, it is not necessary to poll the device for a ready
condition since writes occur at bus speed. So, by the
time a new bus transaction can be shifted into the
device, a write operation will be complete. This is
explained in more detail in the interface section.
Users expect several obvious system benefits from
the FM25V05 due to its fast write cycle and high
endurance as compared to Serial Flash. In addition
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than Serial Flash
since it is completed quickly. By contrast, Serial
Flash requiring milliseconds to write is vulnerable to
noise during much of the cycle.
Serial Peripheral Interface – SPI Bus
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data pins. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25V05 will begin monitoring
the clock and data lines. The relationship between the
falling edge of /S, the clock and data is dictated by
the SPI mode. The device will make a determination
of the SPI mode on the falling edge of each chip
select. While there are four such modes, the
FM25V05 supports only modes 0 and 3. Figure 2
shows the required signal relationships for modes 0
and 3. For both modes, data is clocked into the
FM25V05 on the rising edge of C and data is
expected on the first rising edge after /S goes active.
If the clock starts from a high state, it will fall prior to
the first data transfer in order to create the first rising
edge.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the device. After
/S is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred.
Certain op-codes are commands with no subsequent
data transfer. The /S must go inactive after an
operation is complete and before a new op-code can
be issued. There is one valid op-code only per active
chip select.
SPI Mode 0: CPOL=0, CPHA=0
SPI Mode 3: CPOL=1, CPHA=1
The FM25V05 employs a Serial Peripheral Interface
(SPI) bus. It is specified to operate at speeds up to
40MHz. This high-speed serial bus provides high
performance serial communication to a host
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25V05 operates in SPI Mode 0 and 3.
Figure 2. SPI Modes 0 & 3
Rev. 2.0
May 2010
Page 3 of 16
FM25V05 - 512Kb SPI FRAM
System Hookup
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. A typical system
configuration uses one or more FM25V05 devices
with a microcontroller that has a dedicated SPI port,
as Figure 3 illustrates. Note that the clock, data-in,
and data-out pins are common among all devices.
The Chip Select and Hold pins must be driven
separately for each FM25V05 device.
For a microcontroller that has no dedicated SPI bus, a
general purpose port may be used. To reduce
hardware resources on the controller, it is possible to
connect the two data pins together and tie off the
Hold pin. Figure 4 shows a configuration that uses
only three pins.
Figure 3. 1Mbit (128KB) System Configuration with SPI port
Figure 4. System Configuration without SPI port
Rev. 2.0
May 2010
Page 4 of 16
FM25V05 - 512Kb SPI FRAM
Power Up to First Access
The FM25V05 is not accessible for a period of time
(tPU) after power up. Users must comply with the
timing parameter tPU, which is the minimum time
from VDD (min) to the first /S low.
Data Transfer
All data transfers to and from the FM25V05 occur in
8-bit groups. They are synchronized to the clock
signal (C), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of C. Outputs are driven from the falling edge of
clock C.
Command Structure
There are ten commands called op-codes that can be
issued by the bus master to the FM25V05. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function, such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the Status
Register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
Table 1. Op-code Commands
Name
Description
Set Write Enable Latch
WREN
Write Disable
WRDI
Read Status Register
RDSR
Write Status Register
WRSR
Read Memory Data
READ
FSTRD Fast Read Memory Data
WRITE Write Memory Data
Enter Sleep Mode
SLEEP
Read Device ID
RDID
Read S/N
SNR
clear the write-enable latch and prevent further
writes without another WREN command. Figure 5
below illustrates the WREN command bus
configuration.
S
0
1
2
3
4
5
6
7
0
0
0
0
0
1
1
0
C
D
Hi-Z
Q
Figure 5. WREN Bus Configuration
WRDI – Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the Status Register and verifying that WEL=0.
Figure 6 illustrates the WRDI command bus
configuration.
S
Op-code
0000
0000
0000
0000
0000
0000
0000
1011
1001
1100
0110b
0100b
0101b
0001b
0011b
1011b
0010b
1001b
1111b
0011b
WREN – Set Write Enable Latch
The FM25V05 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for write
operations. These include writing the Status Register
(WRSR) and writing the memory (WRITE).
0
1
2
3
4
5
6
7
0
0
0
0
0
1
0
0
C
D
Q
Hi-Z
Figure 6. WRDI Bus Configuration
RDSR – Read Status Register
The RDSR command allows the bus master to
verify the contents of the Status Register. Reading
Status provides information about the current state
of the write protection features. Following the
RDSR op-code, the FM25V05 will return one byte
with the contents of the Status Register. The Status
Register is described in detail in the section below.
Sending the WREN op-code causes the internal Write
Enable Latch to be set. A flag bit in the Status
Register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the Status
Register has no effect on the state of this bit.
Completing any write operation will automatically
Rev. 2.0
May 2010
Page 5 of 16
FM25V05 - 512Kb SPI FRAM
WRSR – Write Status Register
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status Register. Prior to issuing a WRSR
command, the /W pin must be high or inactive. Prior
to sending the WRSR command, the user must send
a WREN command to enable writes. Note that
executing a WRSR command is a write operation
and therefore clears the Write Enable Latch. The bus
configuration of RDSR and WRSR are shown
below.
S
C
D
Q
Figure 7. RDSR Bus Configuration
S
C
D
Q
Figure 8. WRSR Bus Configuration
Status Register & Write Protection
The write protection features of the FM25V05 are
multi-tiered. Taking the /W pin to a logic low state is
the hardware write-protect function. Status Register
write operations are blocked when /W is low. To
write the memory with /W high, a WREN op-code
must first be issued. Assuming that writes are enabled
using WREN and by /W, writes to memory are
controlled by the Status Register. As described
above, writes to the Status Register are performed
using the WRSR command and subject to the /W pin.
The Status Register is organized as follows.
Table 2. Status Register
Bit
Name
7
6
5
4
3
2
1
0
WPEN
1
0
0
BP1
BP0
WEL
0
Bits 0, 4, 5 are fixed at 0 and bit 6 is fixed at 1, and
none of these bits can be modified. Note that bit 0
(“Ready” in Serial Flash) is unnecessary as the FRAM writes in real-time and is never busy, so it
reads out as a ‘0’. There is an exception to this when
the device is waking up from Sleep Mode, which is
described on the following page. The BP1 and BP0
control software write protection features. They are
nonvolatile (shaded yellow). The WEL flag indicates
the state of the Write Enable Latch. Attempting to
directly write the WEL bit in the Status Register has
Rev. 2.0
May 2010
no effect on its state. This bit is internally set and
cleared via the WREN and WRDI commands,
respectively.
BP1 and BP0 are memory block write protection bits.
They specify portions of memory that are writeprotected as shown in the following table.
Table 3. Block Memory Write Protection
BP1
BP0 Protected Address Range
0
0
None
0
1
C000h to FFFFh (upper ¼)
1
0
8000h to FFFFh (upper ½)
1
1
0000h to FFFFh (all)
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes. The remaining write protection features
protect inadvertent changes to the block protect bits.
The WPEN bit controls the effect of the hardware /W
pin. When WPEN is low, the /W pin is ignored.
When WPEN is high, the /W pin controls write
access to the Status Register. Thus the Status Register
is write protected if WPEN=1 and /W=0.
This scheme provides a write protection mechanism,
which can prevent software from writing the memory
Page 6 of 16
FM25V05 - 512Kb SPI FRAM
under any circumstances. This occurs if the BP1 and
BP0 bits are set to 1, the WPEN bit is set to 1, and
the /W pin is low. This occurs because the block
protect bits prevent writing memory and the /W
signal in hardware prevents altering the block protect
Table 4. Write Protection
WEL
WPEN
0
X
1
0
1
1
1
1
/W
X
X
0
1
Protected Blocks
Protected
Protected
Protected
Protected
Memory Operation
The SPI interface, which is capable of a relatively
high clock frequency, highlights the fast write
capability of the F-RAM technology. Unlike Serial
Flash, the FM25V05 can perform sequential writes at
bus speed. No page buffer is needed and any number
of sequential writes may be performed.
Write Operation
All writes to the memory array begin with a WREN
op-code. The next op-code is the WRITE instruction.
This op-code is followed by a two-byte address
value, which specifies the 16-bit address of the first
data byte of the write operation. Subsequent bytes are
data and they are written sequentially. Addresses are
incremented internally as long as the bus master
continues to issue clocks. If the last address of FFFFh
is reached, the counter will roll over to 0000h. Data is
written MSB first. A write operation is shown in
Figure 9.
Unlike Serial Flash, any number of bytes can be
written sequentially and each byte is written to
memory immediately after it is clocked in (after the
8th clock). The rising edge of /S terminates a WRITE
op-code operation. Asserting /W active in the middle
of a write operation will have no effect until the next
falling edge of /S.
Read Operation
After the falling edge of /S, the bus master can issue
a READ op-code. Following this instruction is a twobyte address value (A15-A0), specifying the address
of the first data byte of the read operation. After the
op-code and address are complete, the D pin is
ignored. The bus master issues 8 clocks, with one bit
Rev. 2.0
May 2010
bits (if WPEN is high). Therefore in this condition,
hardware must be involved in allowing a write
operation. The following table summarizes the write
protection conditions.
Unprotected Blocks
Protected
Unprotected
Unprotected
Unprotected
Status Register
Protected
Unprotected
Protected
Unprotected
read out for each. Addresses are incremented
internally as long as the bus master continues to issue
clocks. If the last address of FFFFh is reached, the
counter will roll over to 0000h. Data is read MSB
first. The rising edge of /S terminates a READ opcode operation and tri-states the Q pin. A read
operation is shown in Figure 10.
Fast Read Operation
The FM25V05 supports the FAST READ op-code
(0Bh) that is found on Serial Flash devices. It is
implemented for code compatibility with Serial Flash
devices. Following this instruction is a two-byte
address (A15-A0), specifying the address of the first
data byte of the read operation. A dummy byte
follows the address. It inserts one byte of read
latency. The D pin is ignored after the op-code, 2byte address, and dummy byte are complete. The bus
master issues 8 clocks, with one bit read out for each.
The Fast Read operation is otherwise the same as an
ordinary READ. If the last address of FFFFh is
reached, the counter will roll over to 0000h. Data is
read MSB first. The rising edge of /S terminates a
FAST READ op-code operation and tri-states the Q
pin. A Fast Read operation is shown in Figure 11.
Hold
The FM25V05 and FM25VN05 devices have a
/HOLD pin that can be used to interrupt a serial
operation without aborting it. If the bus master pulls
the /HOLD pin low while C is low, the current
operation will pause. Taking the /HOLD pin high
while C is low will resume an operation. The
transitions of /HOLD must occur while C is low, but
the C and /S pins can toggle during a hold state.
Page 7 of 16
FM25V05 - 512Kb SPI FRAM
S
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
4
5
6
7
0
1
2
3
4
5
6
7
9
8
3
2
1
0
7
6
Data
5 4
3
2
1
0
C
op-code
D
0
0
0
0
0
16-bit Address
0
1
0
15 14 13 12
11 10
MSB
LSB MSB
LSB
Q
Figure 9. Memory Write with 2-Byte Address
S
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
4
9
8
3
5
6
7
1
0
0
1
2
7
6
5
0
1
2
6
5
3
4
5
6
7
4
3
2
1
0
3
4
5
6
7
3
2
1
C
16-bit Address
op-code
D
0
0
0
0
0
0
1
1
15 14 13 12 11 10
2
LSB
MSB
Q
Data
MSB
LSB
Figure 10. Memory Read with 2-Byte Address
S
0
1
2
3
4
5
6
7
0
1
2
3
5
6
7
1
0
4
5
6
7
C
0
0
0
0
1
0
1
1
15 14 13 12
MSB
Q
Dummy byte
16-bit Address
op-code
D
2
LSB
X
X
X
X
Data
MSB
7
4
LSB
0
Figure 11. Fast Read with 2-Byte Address and Dummy Byte
Rev. 2.0
May 2010
Page 8 of 16
FM25V05 - 512Kb SPI FRAM
Sleep Mode
A low power mode called Sleep Mode is
implemented on both FM25V05 and FM25VN05
devices. The device will enter this low power state
when the SLEEP op-code B9h is clocked-in and a
rising edge of /S is applied. Once in sleep mode, the
C and D pins are ignored and Q will be high-Z, but
the device continues to monitor the /S pin. On the
next falling edge of /S, the device will return to
normal operation within tREC (400 µs max.). The Q
pin remains in a hi-Z state during the wakeup period.
The device will not necessarily respond to an opcode
within the wakeup period. To start the wakeup
procedure, the controller may send a “dummy” read,
for example, and wait the remaining tREC time.
Enter Sleep
Mode
S
C
D
Q
Figure 12. Sleep Mode Entry
Device ID
The FM25V05 and FM25VN05 devices can be interrogated for its manufacturer, product identification, and die
revision. The RDID op-code 9Fh allows the user to read the manufacturer ID and product ID, both of which are
read-only bytes. The JEDEC-assigned manufacturer ID places the Ramtron identifier in bank 7, therefore there are
six bytes of the continuation code 7Fh followed by the single byte C2h. There are two bytes of product ID, which
includes a Family code, a Density code, a Sub code, and Product Revision code.
Table 6. Manufacturer and Product ID
Manufacturer ID
Device ID (1st Byte)
Device ID (2nd Byte)
7
0
0
0
0
0
0
1
6
1
1
1
1
1
1
1
5
1
1
1
1
1
1
0
Bit
4 3
1 1
1 1
1 1
1 1
1 1
1 1
0 0
2
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
Hex
7F
7F
7F
7F
7F
7F
C2
Continuation code
Continuation code
Continuation code
Continuation code
Continuation code
Continuation code
JEDEC assigned Ramtron C2h in bank 7
Family
Density
0 0 1 0 0 0 1 1
Sub
Rev.
Rsvd
0 0 0 0 0 0 0 0
Hex
23h
Density: 01h=128K, 02h=256K, 03h=512K, 04=1M
00h
00h=FM25V05, 01h=FM25VN05
S
.......
C
D
Q
9Fh
7Fh
…
7Fh
1
C2h
23h
00h
6
Six bytes of continuation code 7Fh
Figure 13. Read Device ID
Rev. 2.0
May 2010
Page 9 of 16
FM25V05 - 512Kb SPI FRAM
The 8-bit CRC value can be used to compare to the
value calculated by the controller. If the two values
match, then the communication between slave and
master was performed without errors. The function
(shown below) is used to calculate the CRC value.
To perform the calculation, 7 bytes of data are filled
into a memory buffer in the same order as they are
read from the part – i.e. byte7, byte6, byte5, byte4,
byte3, byte2, byte1 of the serial number. The
calculation is performed on the 7 bytes, and the result
should match the final byte out from the part which is
byte0, the 8-bit CRC value.
Unique Serial Number (FM25VN05 only)
The FM25VN05 device incorporates a read-only 8byte serial number. It can be used to uniquely
identify a pc board or system. The serial number
includes a 40-bit unique number, an 8-bit CRC, and a
16-bit number that can be defined upon request by
the customer. If a customer-specific number is not
requested, the 16-bit Customer Identifier is 0x0000.
The serial number is read by issuing the SNR opcode (C3h).
CUSTOMER IDENTIFIER *
40-bit UNIQUE NUMBER
SN(63:56)
SN(55:48)
SN(47:40)
SN(39:32)
SN(31:24)
* Contact factory for requesting a customer identifier number.
SN(23:16)
8-bit CRC
SN(15:8)
SN(7:0)
Figure 14. 8-Byte Serial Number (read-only)
Function to Calculate CRC
BYTE calcCRC8( BYTE* pData, int nBytes )
{
static BYTE crctable[256] = {
0x00, 0x07, 0x0E, 0x09, 0x1C, 0x1B,
0x38, 0x3F, 0x36, 0x31, 0x24, 0x23,
0x70, 0x77, 0x7E, 0x79, 0x6C, 0x6B,
0x48, 0x4F, 0x46, 0x41, 0x54, 0x53,
0xE0, 0xE7, 0xEE, 0xE9, 0xFC, 0xFB,
0xD8, 0xDF, 0xD6, 0xD1, 0xC4, 0xC3,
0x90, 0x97, 0x9E, 0x99, 0x8C, 0x8B,
0xA8, 0xAF, 0xA6, 0xA1, 0xB4, 0xB3,
0xC7, 0xC0, 0xC9, 0xCE, 0xDB, 0xDC,
0xFF, 0xF8, 0xF1, 0xF6, 0xE3, 0xE4,
0xB7, 0xB0, 0xB9, 0xBE, 0xAB, 0xAC,
0x8F, 0x88, 0x81, 0x86, 0x93, 0x94,
0x27, 0x20, 0x29, 0x2E, 0x3B, 0x3C,
0x1F, 0x18, 0x11, 0x16, 0x03, 0x04,
0x57, 0x50, 0x59, 0x5E, 0x4B, 0x4C,
0x6F, 0x68, 0x61, 0x66, 0x73, 0x74,
0x89, 0x8E, 0x87, 0x80, 0x95, 0x92,
0xB1, 0xB6, 0xBF, 0xB8, 0xAD, 0xAA,
0xF9, 0xFE, 0xF7, 0xF0, 0xE5, 0xE2,
0xC1, 0xC6, 0xCF, 0xC8, 0xDD, 0xDA,
0x69, 0x6E, 0x67, 0x60, 0x75, 0x72,
0x51, 0x56, 0x5F, 0x58, 0x4D, 0x4A,
0x19, 0x1E, 0x17, 0x10, 0x05, 0x02,
0x21, 0x26, 0x2F, 0x28, 0x3D, 0x3A,
0x4E, 0x49, 0x40, 0x47, 0x52, 0x55,
0x76, 0x71, 0x78, 0x7F, 0x6A, 0x6D,
0x3E, 0x39, 0x30, 0x37, 0x22, 0x25,
0x06, 0x01, 0x08, 0x0F, 0x1A, 0x1D,
0xAE, 0xA9, 0xA0, 0xA7, 0xB2, 0xB5,
0x96, 0x91, 0x98, 0x9F, 0x8A, 0x8D,
0xDE, 0xD9, 0xD0, 0xD7, 0xC2, 0xC5,
0xE6, 0xE1, 0xE8, 0xEF, 0xFA, 0xFD,
};
0x12,
0x2A,
0x62,
0x5A,
0xF2,
0xCA,
0x82,
0xBA,
0xD5,
0xED,
0xA5,
0x9D,
0x35,
0x0D,
0x45,
0x7D,
0x9B,
0xA3,
0xEB,
0xD3,
0x7B,
0x43,
0x0B,
0x33,
0x5C,
0x64,
0x2C,
0x14,
0xBC,
0x84,
0xCC,
0xF4,
0x15,
0x2D,
0x65,
0x5D,
0xF5,
0xCD,
0x85,
0xBD,
0xD2,
0xEA,
0xA2,
0x9A,
0x32,
0x0A,
0x42,
0x7A,
0x9C,
0xA4,
0xEC,
0xD4,
0x7C,
0x44,
0x0C,
0x34,
0x5B,
0x63,
0x2B,
0x13,
0xBB,
0x83,
0xCB,
0xF3
BYTE crc = 0;
while( nBytes-- ) crc = crctable[crc ^ *pData++];
return crc;
}
Rev. 2.0
May 2010
Page 10 of 16
FM25V05 - 512Kb SPI FRAM
S
.......
C
D
Q
C3h
Byte 7
Byte 6
...
Byte 1
Byte 0
Figure 15. Read Serial Number
Endurance
The FM25V05 and FM25VN05 devices are capable
of being accessed at least 1014 times, reads or writes.
An F-RAM memory operates with a read and restore
mechanism. Therefore, an endurance cycle is applied
on a row basis for each access (read or write) to the
memory array. The F-RAM architecture is based on
an array of rows and columns. Rows are defined by
A15-A3 and column addresses by A2-A0. See Block
Diagram (pg 2) which shows the array as 8K rows of
64-bits each. The entire row is internally accessed
once whether a single byte or all eight bytes are read
or written. Each byte in the row is counted only once
in an endurance calculation. The table below shows
endurance calculations for 64-byte repeating loop,
which includes an op-code, a starting address, and a
sequential 64-byte data stream. This causes each byte
to experience one endurance cycle through the loop.
F-RAM read and write endurance is virtually
unlimited even at 40MHz clock rate.
Table 7. Time to Reach 100 Trillion Cycles for Repeating 64-byte Loop
Endurance
Endurance
Years to Reach
SCK Freq
(MHz)
Cycles/sec.
Cycles/year
1014 Cycles
40
74,620
2.35 x 1012
42.6
85.1
20
37,310
1.18 x 1012
10
18,660
5.88 x 1011
170.2
5
9,330
2.94 x 1011
340.3
Rev. 2.0
May 2010
Page 11 of 16
FM25V05 - 512Kb SPI FRAM
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
VDD
Power Supply Voltage with respect to VSS
VIN
Voltage on any pin with respect to VSS
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
- Human Body Model (AEC-Q100-002 Rev. E)
- Charged Device Model (AEC-Q100-011 Rev. B)
- Machine Model (AEC-Q100-003 Rev. E)
Package Moisture Sensitivity Level
Ratings
-1.0V to +4.5V
-1.0V to +4.5V
and VIN < VDD+1.0V
-55°C to + 125°C
260° C
4kV
1.25kV
200V
MSL-1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40°C to + 85°C, VDD = 2.0V to 3.6V unless otherwise specified)
Symbol Parameter
Min
Typ
Max
Units
Notes
VDD
Power Supply Voltage
2.0
3.3
3.6
V
1
IDD
Power Supply Operating Current
mA
0.3
@ C = 1 MHz
mA
3.0
1.5
@ C = 40 MHz
ISB
Standby Current
90
150
µA
2
IZZ
Sleep Mode Current
5
8
µA
3
ILI
Input Leakage Current
µA
4
±1
ILO
Output Leakage Current
µA
4
±1
VIH
Input High Voltage
0.7 VDD
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.3 VDD
V
VOH1
Output High Voltage (IOH = -1 mA, VDD=2.7V)
2.4
V
VOH2
Output High Voltage (IOH = -100 µA)
VDD-0.2
V
VOL1
Output Low Voltage (IOL = 2 mA, VDD=2.7V)
0.4
V
VOL2
Output Low Voltage (IOL = 150 µA)
0.2
V
RIN
Input Resistance (/HOLD pin)
5
For VIN = VIH (min)
40
KΩ
For VIN = VIL (max)
1
MΩ
Notes
1. C toggling between VDD-0.2V and VSS, other inputs VSS or VDD-0.2V.
2. /S=VDD. All inputs VSS or VDD.
3. In Sleep mode and /S=VDD. All inputs VSS or VDD.
4. VSS ≤ VIN ≤ VDD and VSS ≤ VOUT ≤ VDD.
5. The input pull-up circuit is stronger (> 40KΩ) when the input voltage is above VIH and weak (> 1MΩ) when the input
voltage is below VIL.
Data Retention (TA = -40°C to + 85°C)
Parameter
Data Retention
Rev. 2.0
May 2010
Min
10
Max
-
Units
Years
Notes
Page 12 of 16
FM25V05 - 512Kb SPI FRAM
AC Parameters (TA = -40°C to + 85°C, CL = 30pF, unless otherwise specified)
VDD 2.0 to 2.7V
VDD 2.7 to 3.6V
Symbol
Parameter
Min
Max
Min
Max
fCK
C Clock Frequency
0
25
0
40
tCH
Clock High Time
20
11
tCL
Clock Low Time
20
11
tCSU
Chip Select Setup
12
10
tCSH
Chip Select Hold
12
10
tOD
Output Disable Time
20
12
tODV
Output Data Valid Time
18
9
tOH
Output Hold Time
0
0
tD
Deselect Time
60
40
tR
Data In Rise Time
50
50
tF
Data In Fall Time
50
50
tSU
Data Setup Time
8
5
tH
Data Hold Time
8
5
tHS
/HOLD Setup Time
12
10
tHH
/HOLD Hold Time
12
10
tHZ
/HOLD Low to Hi-Z
25
20
tLZ
/HOLD High to Data Active
25
20
Notes
1.
2.
3.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
2
2,3
2,3
2
2
tCH + tCL = 1/fCK.
This parameter is characterized but not 100% tested.
Rise and fall times measured between 10% and 90% of waveform.
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V)
Symbol Parameter
CO
Output Capacitance (Q)
CI
Input Capacitance
Notes
1. This parameter is characterized and not 100% tested.
AC Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing levels
Output Load Capacitance
Min
-
Max
8
6
Units
pF
pF
Notes
1
1
10% and 90% of VDD
3 ns
0.5 VDD
30 pF
Serial Data Bus Timing
Rev. 2.0
May 2010
Page 13 of 16
FM25V05 - 512Kb SPI FRAM
/HOLD Timing
tHS
S
tHH
C
tHH
tHS
HOLD
Q
tHZ
tLZ
Power Cycle Timing
VDD
VDD min.
tVR
tVF
tPU
tPD
S
Power Cycle & Sleep Timing (TA = -40° C to + 85° C, VDD = 2.0V to 3.6V, unless otherwise specified)
Symbol Parameter
Min
Max
Units
Notes
tVR
VDD Rise Time
50
µs/V
1,2
tVF
VDD Fall Time
100
µs/V
1,2
tPU
Power Up (VDD min) to First Access (/S low)
250
µs
tPD
Last Access (/S high) to Power Down (VDD min)
0
µs
tREC
Recovery Time from Sleep Mode
400
µs
Notes
1. This parameter is characterized and not 100% tested.
2. Slope measured at any point on VDD waveform.
Rev. 2.0
May 2010
Page 14 of 16
FM25V05 - 512Kb SPI FRAM
Mechanical Drawing
8-pin SOIC (JEDEC MS-012 variation AA)
Recommended PCB Footprint
7.70
3.90 ±0.10
3.70
6.00 ±0.20
2.00
Pin 1
0.65
1.27
4.90 ±0.10
1.27
0.33
0.51
0.25
0.50
1.35
1.75
0.10
0.25
0.10 mm
0.19
0.25
45 °
0°- 8°
0.40
1.27
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimensions in millimeters.
SOIC Package Marking Scheme
XXXXXX-P
RLLLLLLL
RICYYWW
Legend:
XXXXX= part number, P=package type
R=rev code, LLLLLLL= lot code
RIC=Ramtron Int’l Corp, YY=year, WW=work week
Examples: FM25V05, “Green”/RoHS SOIC package,
Rev. A, Lot 9646447, Year 2010, Work Week 11
Without S/N feature
FM25V05-G
A9646447
RIC1011
Rev. 2.0
May 2010
With S/N feature
FM25VN05-G
A9646447
RIC1011
Page 15 of 16
FM25V05 - 512Kb SPI FRAM
Revision History
Revision
1.0
1.1
Date
8/29/2008
10/6/2009
2.0
5/25/2010
Summary
Initial release.
Updated ESD ratings. Added tape and reel ordering information. Updated
lead temperature rating in Abs Max table. Expanded CRC check description.
Changed to Pre-Production status. Changed part marking scheme.
Ordering Information
Part Number
FM25V05-G
FM25VN05-G
FM25V05-GTR
Device ID
Device ID, S/N
Device ID
Operating
Voltage
2.0-3.6V
2.0-3.6V
2.0-3.6V
FM25VN05-GTR
Device ID, S/N
2.0-3.6V
Rev. 2.0
May 2010
Features
Package
8-pin “Green”/RoHS SOIC
8-pin “Green”/RoHS SOIC
8-pin “Green”/RoHS SOIC
in Tape & Reel
8-pin “Green”/RoHS SOIC
in Tape & Reel
Page 16 of 16