Fairchild FM27C256VE150 262,144-bit (32k x 8) high performance cmos eprom Datasheet

FM27C256
262,144-Bit (32K x 8) High Performance CMOS EPROM
General Description
The FM27C256 is one member of a high density EPROM Family
which range in densities up to 4 Mb.
The FM27C256 is a 256K Electrically Programmable Read Only
Memory. It is manufactured in Fairchild’s latest CMOS split gate
EPROM technology which enables it to operate at speeds as fast
as 90 ns access time over the full operating range.
Features
■ High performance CMOS
— 90 ns access time
The FM27C256 provides microprocessor-based systems extensive storage capacity for large portions of operating system and
application software. Its 90 ns access time provides high speed
operation with high-performance CPUs. The FM27C256 offers a
single chip solution for the code storage requirements of 100%
firmware-based equipment. Frequently-used software routines
are quickly executed from EPROM storage, greatly enhancing
system utility.
■ JEDEC standard pin configuration
— 28-pin PDIP package
— 32-pin chip carrier
— 28-pin CERDIP package
■ Drop-in replacement for 27C256 or 27256
■ Manufacturer’s identification code
The FM27C256 is configured in the standard EPROM pinout
which provides an easy upgrade path for systems which are
currently using standard EPROMs.
Block Diagram
Data Outputs O0 - O7
VCC
GND
VPP
OE
Output Enable
and Chip Enable Logic
Output
Buffers
CE/PGM
..
Y Decoder
Y Gating
.......
A0 - A14
Address
Inputs
X Decoder
DS800034-1
© 1998 Fairchild Semiconductor Corporation
FM27C256
1
www.fairchildsemi.com
FM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
January 2000
27C040
27C010 27C512
XX/VPP XX/VPP
A16
A16
A15
A15
A12
A12
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
A0
O0
O0
O1
O1
O2
O2
GND
GND
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
DlP
FM27C256
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
27C512
27C010
27C040
VCC
VCC
XX/PGM
A18
VCC
VCC
XX
A17
A14
A14
A14
A14
A13
A13
A13
A13
A8
A8
A8
A8
A9
A9
A9
A9
A11
A11
A11
A11
OE/VPP
OE
OE
OE
A10
A10
A10
A10
CE/PGM CE/PGM
CE
CE/PGM
O7
O7
O7
O7
O6
O6
O6
O6
O5
O5
O5
O5
O4
O4
O4
O4
O3
O3
O3
O3
Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the FM27C256 pins.
Commercial Temp. Range (0°C to +70°C)
VCC = 5V ±10%
DS800034-2
Pin Names
Symbol
Description
Parameter/Order Number
Access Time (ns)
A0–A14
Addresses
FM27C256 Q, N, V 90
90
CE/PGM
Chip Enable/Program
FM27C256 Q, N, V 120
120
OE
FM27C256 Q, N, V 150
150
O0–O7
FM27C256 QE, NE, VE 120
120
FM27C256 QE, NE, VE 150
150
Don’t Care (during Read)
PLCC
A7
A12
VPP
XX
VCC
A14
A13
Access Time (ns)
Outputs
XX
Extended Temp. Range (-40°C to +85°C)
VCC = 5V ±10%
Parameter/Order Number
Output Enable
4
Note: Surface mount PLCC package available for commercial and extended
temperature ranges only.
A6
A5
A4
A3
A2
A1
A0
XX
O0
Package Types: FM27C256 Q, N, V XXX
Q = Quartz-Windowed Ceramic DIP
N = Plastic OTP DIP
V = Surface-Mount PLCC
• All Packages conform to the JEDEC standard.
2
1 32 31 30
29
28
27
26
25
24
23
22
21
5
6
7
8
9
10
11
12
13
A8
A9
A11
XX
OE
A10
CE/PGM
O7
O6
14 15 16 17 18 19 20
O1
O2
GND
XX
O3
O4
O5
• All versions are guaranteed to function for slower speeds.
3
DS800034-3
Top
2
FM27C256
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FM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Connection Diagrams
ESD Protection
Storage Temperature
All Output Voltages with
Respect to Ground
-65°C to +150°C
All Input Voltages except A9 with
Respect to Ground
-0.7V to +14V
VCC Supply Voltage with
Respect to Ground
VCC + 1.0V to GND -0.6V
Operating Range
-0.6V to +7V
VPP and A9 with Respect
to Ground
> 2000V
-0.6V to +7V
Range
Temperature
VCC
Comm’l
0°C to +70°C
+5V ±10%
Industrial
-40°C to +85°C
+5V ±10%
Read Operation
DC Electrical Characteristics Over Operating Range with VPP = VCC
Symbol
Parameter
Test Conditions
Min
Max
Units
VIL
Input Low Level
-0.5
0.8
V
VIH
Input High Level
2.0
VCC +1
V
VOL
Output Low Voltage
IOL = 2.1 mA
0.4
V
VOH
Output High Voltage
IOH = -2.5 mA
ISB1
(Note 11)
VCC Standby Current
(CMOS)
CE = VCC ±0.3V
ISB2
VCC Standby Current (TTL)
ICC1
3.5
V
100
µA
CE = VIH
1
mA
VCC Active Current
TTL Inputs
CE = OE = VIL,f=5 MHz
Inputs = VIH or VIL, I/O = 0 mA
35
mA
IPP
VPP Supply Current
VPP = VCC
10
µA
VPP
VPP Read Voltage
VCC - 0.7
VCC
V
ILI
Input Load Current
VIN = 5.5V or GND
-1
1
µA
ILO
Output Leakage Current
VOUT = 5.5V or GND
-10
10
µA
AC Electrical Characteristics Over Operating Range with VPP = VCC
Symbol
Parameter
90
100
120
150
200
Units
Min Max Min Max Min Max Min Max Min Max
tACC
Address to Output Delay
90
100
120
150
200
tCE
CE to Output Delay
90
100
120
150
200
tOE
OE to Output Delay
35
50
50
50
50
tDF
(Note 2)
Output Disable to
Output Float
30
30
35
45
45
tOH
(Note 2)
Output Hold from
Addresses,
CE or OE, Whichever
Occurred First
0
0
0
0
ns
0
Capacitance (Note 2) TA = +25˚C, f = 1 MHz
Symbol
Parameter
CIN
Input Capacitance
VIN = 0V
6
12
pF
Output Capacitance
VOUT = 0V
9
12
pF
COUT
Conditions Typ Max Units
3
FM27C256
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FM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Absolute Maximum Ratings (Note 1)
Output Load
1 TTL Gate and CL = 100 pF (Note 8)
≤ 5 ns
Input Rise and Fall Times
Input Pulse Levels
0.45 to 2.4V
Timing Measurement Reference Level (Note 10)
Inputs
0.8V and 2.0V
Outputs
0.8V and 2.0V
AC Waveforms (Note 6) (Note 7) (Note 9)
ADDRESSES
2.0V
ADDRESSES VALID
0.8V
CE
2.0V
0.8V
tCE
OE
tCE
(Notes 4, 5)
2.0V
0.8V
tOE
(Note 3)
tDF
(Notes 4, 5)
OUTPUT
2.0V
Hi-Z
Hi-Z
VALID OUTPUT
0.8V
t
tOH
ACC
(Note 3)
DS800034-4
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC.
Note 4: The tDF and tCF compare level is determined as follows:
High to TRI-STATE®, the measured VOH1 (DC) - 0.10V;
Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.
Note 5: TRI-STATE may be attained using OE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device
between VCC and GND.
Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.
Note 8: TTL Gate: IOL = 1.6 mA, IOH = -400 µA.
CL = 100 pF includes fixture capacitance.
Note 9: VPP may be connected to VCC except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Note 11: CMOS inputs: VIL = GND ±0.3V, VIH = VCC ±0.3V.
4
FM27C256
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FM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
AC Test Conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tAS
Address Setup Time
1
µs
tOES
OE Setup Time
1
µs
tVPS
VPP Setup Time
1
µs
tVCS
VCC Setup Time
1
µs
tDS
Data Setup Time
1
µs
tAH
Address Hold Time
0
µs
tDH
Data Hold Time
1
µs
tDF
Output Enable to Output
Float Delay
tPW
Program Pulse Width
tOE
Data Valid from OE
CE = VIL
100
ns
IPP
VPP Supply Current
during Programming Pulse
CE = VIL
30
mA
ICC
VCC Supply Current
50
mA
TA
Temperature Ambient
20
25
30
°C
VCC
Power Supply Voltage
6.25
6.5
6.75
V
VPP
Programming Supply Voltage
12.5
12.75
13.0
tFR
Input Rise, Fall Time
CE = VIL
0
45
50
60
ns
105
µs
5
V
ns
VIL
Input Low Voltage
VIH
Input High Voltage
2.4
tIN
Input Timing Reference Voltage
0.8
2.0
V
Output Timing Reference Voltage
0.8
2.0
V
tOUT
0.0
0.45
4.0
V
V
Programming Waveforms (Note 14)
PROGRAM
VERIFY
PROGRAM
ADDRESSES
2.0V
ADDRESS N
0.8V
tAS
DATA
2.0V
tAH
DATA IN STABLE
ADD N
0.8V
tDS
VCC
DATA OUT VALID
ADD N
tDH
tDF
5.25V
tVCS
VPP
12.75V
tVPS
CE
2.0V
0.8V
tOES
tOE
tPW
OE
2.0V
0.8V
DS800034-5
Note 12: Fairchild’s standard product warranty applies to devices programmed to specifications described herein.
Note 13: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC.
Note 14: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients
which may damage the device.
Note 15: During power up the PGM pin must be brought high (≥ VIH) either coincident with or before power is applied to VPP.
5
FM27C256
www.fairchildsemi.com
FM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Programming Characteristics (Note 12) (Note 13) (Note 14) (Note 15)
FM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Turbo Programming Algorithm Flow Chart
VCC = 6.5V VPP = 12.75V
n=0
ADDRESS = FIRST LOCATION
PROGRAM ONE 50µs PULSE
INCREMENT n
NO
DEVICE
FAILED
YES
n = 10?
FAIL
VERIFY
BYTE
PASS
LAST
ADDRESS
?
NO
INCREMENT
ADDRESS
n=0
YES
ADDRESS = FIRST LOCATION
VERIFY
BYTE
FAIL
PASS
INCREMENT
ADDRESS
NO
PROGRAM ONE
50 µs
PULSE
LAST
ADDRESS
?
YES
CHECK ALL BYTES
1ST: VCC = VPP = 6.0V
2ND: VCC = VPP = 4.3V
Note:
The standard National Semiconductor algorithm may also be used but it will have longer programming time.
DS800034-6
FIGURE 1.
6
FM27C256
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The EPROM is in the programming mode when the VPP power
supply is at 12.75V and OE is at VIH. It is required that at least a
0.1 µF capacitor be placed across VPP, VCC to ground to suppress
spurious voltage transients which may damage the device. The
data to be programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and data inputs
are TTL.
DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table 1. It
should be noted that all inputs for the six modes are at TTL levels.
The power supplies required are VCC and VPP. The VPP power
supply must be at 12.75V during the three programming modes,
and must be at 5V in the other three modes. The VCC power supply
must be at 6.5V during the three programming modes, and at 5V
in the other three modes.
When the address and data are stable, an active low, TTL program
pulse is applied to the CE/PGM input. A program pulse must be
applied at each address location to be programmed. The EPROM
is programmed with the Turbo Programming Algorithm shown in
Figure 1. Each Address is programmed with a series of 50 µs
pulses until it verifies good, up to a maximum of 10 pulses. Most
memory cells will program with a single 50 µs pulse. (The standard
National Semiconductor Algorithm may also be used but it will
have longer programming time.)
Read Mode
The EPROM has two control functions, both of which must be
logically active in order to obtain data at the outputs. Chip Enable
(CE/PGM) is the power control and should be used for device
selection. Output Enable (OE) is the output control and should be
used to gate data to the output pins, independent of device
selection. Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE). Data is
available at the outputs tOE after the falling edge of OE, assuming
that CE/PGM has been low and addresses have been stable for
at least tACC –tOE.
The EPROM must not be programmed with a DC signal applied to
the CE/PGM input.
Programming multiple EPROM in parallel with the same data can
be easily accomplished due to the simplicity of the programming
requirments. Like inputs of the parallel EPROM may be connected
together when they are programmed with the same data. A low
level TTL pulse applied to the CE/PGM input programs the
paralleled EPROM.
Standby Mode
The EPROM has a standby mode which reduces the active power
dissipation by over 99%, from 385 mW to 0.55 mW. The EPROM
is placed in the standby mode by applying a CMOS high signal to
the CE/PGM input. When in standby mode, the outputs are in a
high impedance state, independent of the OE input.
Program Inhibit
Programming multiple EPROMs in parallel with different data is
also easily accomplished. Except for CE/PGM, all like inputs
(including OE) of the parallel EPROMs may be common. A TTL
low level program pulse applied to an EPROM’s CE/PGM input
with VPP at 12.75V will program that EPROM. A TTL high level CE/
PGM input inhibits the other EPROMs from being programmed.
Output Disable
The EPROM is placed in output disable by applying a TTL high
signal to the OE input. When in output disable all circuitry is
enabled, except the outputs are in a high impedance state (TRISTATE).
Program Verify
A verify should be performed on the programmed bits to determine
whether they were correctly programmed. The verify may be
performed with VPP at 12.75V. VPP must be at VCC, except during
programming and program verify.
Output OR-Typing
Because the EPROM is usually used in larger memory arrays,
Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control
function allows for:
AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window to
prevent unintentional erasure. Covering the window will also
prevent temporary functional failure due to the generation of photo
currents.
1. the lowest possible memory power dissipation, and
2. complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended
that CE/PGM be decoded and used as the primary device selecting function, while OE be made a common connection to all
devices in the array and connected to the READ line from the
system control bus. This assures that all deselected memory
devices are in their low power standby modes and that the output
pins are active only when data is desired from a particular memory
device.
MANUFACTURER’S IDENTIFICATION CODE
The EPROM has a manufacturer’s identification code to aid in
programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then
automatically calls up the specific programming algorithm for the
part. This automatic programming control is only possible with
programmers which have the capability of reading the code.
Programming
The Manufacturer’s Identification code, shown in Table 2, specifically identifies the manufacturer and device type. The code for
FM27C256 is “8F04”, where “8F” designates that it is made by
Fairchild Semiconductor, and “04” designates a 256K part.
CAUTION: Exceeding 14V on pin 1 (VPP) will damage the EPROM.
Initially, and after each erasure, all bits of the EPROM are in the
“1’s” state. Data is introduced by selectively programming “0’s”
into the desired bit locations. Although only “0’s” will be programmed, both “1’s” and “0’s” can be presented in the data word.
The only way to change a “0” to a “1” is by ultraviolet light erasure.
The code is accessed by applying 12V ±0.5V to address pin A9.
Addresses A1–A8, A10–A16, and all control pins are held at VIL.
Address pin A0 is held at VIL for the manufacturer’s code, and held
at VIH for the device code. The code is read on the eight data pins,
O0 –O7. Proper code access is only guaranteed at 25°C to ±5°C.
7
FM27C256
www.fairchildsemi.com
FM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Functional Description
be checked to make certain full erasure is occurring. Incomplete
erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem.
ERASURE CHARACTERISTICS
The erasure characteristics of the device are such that erasure
begins to occur when exposed to light with wavelengths shorter
than approximately 4000 Angstroms (Å). It should be noted that
sunlight and certain types of fluorescent lamps have wavelengths
in the 3000Å–4000Å range.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require careful
decoupling of the devices. The supply current, ICC, has three
segments that are of interest to the system designer: the standby
current level, the active current level, and the transient current
peaks that are produced by voltage transitions on input pins. The
magnitude of these transient current peaks is dependent of the
output capacitance loading of the device. The associated VCC
transient voltage peaks can be suppressed by properly selected
decoupling capacitors. It is recommended that at least a 0.1 µF
ceramic capacitor be used on every device between VCC and
GND. This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor
should be used between VCC and GND for each eight devices. The
bulk capacitor should be located near where the power supply is
connected to the array. The purpose of the bulk capacitor is to
overcome the voltage drop caused by the inductive effects of the
PC board traces.
The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of
2537Å. The integrated dose (i.e., UV intensity x exposure time) for
erasure should be a minimum of 15W-sec/cm2.
The EPROM should be placed within 1 inch of the lamp tubes
during erasure. Some lamps have a filter on their tubes which
should be removed before erasure
An erasure system should be calibrated periodically. The distance
from lamp to device should be maintained at one inch. The erasure
time increases as the square of the distance from the lamp (if
distance is doubled the erasure time increases by factor of 4).
Lamps lose intensity as they age. When a lamp is changed, the
distance has changed, or the lamp has aged, the system should
Mode Selection
The modes of operation of FM27C256 listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels
except for VPP and A9 for device signature.
TABLE 1. Modes Selection
Pins
CE/PGM
OE
VPP
VCC
Outputs
VIL
VIL
VCC
5.0V
DOUT
X
(Note 16)
VIH
VCC
5.0V
High-Z
Standby
VIH
X
VCC
5.0V
High-Z
Programming
VIL
VIH
12.75V
6.25V
DIN
Program Verify
VIH
VIL
12.75V
6.25V
DOUT
Program Inhibit
VIH
VIH
12.75V
6.25V
High-Z
Mode
Read
Output Disable
Note 16: X can be VIL or VIH.
TABLE 2. Manufacturer’s Identification Code
Pins
A0
(10)
A9
(24)
O7
(19)
O6
(18)
O5
(17)
O4
(16)
O3
(15)
O2
(13)
O1
(12)
O0
(11)
Hex
Data
Manufacturer Code
VIL
12V
1
0
0
0
1
1
1
1
8F
Device Code
VIH
12V
0
0
0
0
0
1
0
0
04
8
FM27C256
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FM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Functional Description (Continued)
FM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
1.450
[36.83]
MAX
28
15
R 0.025
[0.64]
0.520 ± 0.006
0.600
[13.21 ±0.15]
[15.24]
MAX
Glass
1
14
0.280 ±0.010
[7.11 ±0.25]
UV WINDOW
R 0.030-0.055
[0.76 - 1.40]
TYP
0.005 MIN
TYP
0.050-0.060
TYP
Glass
Sealant
0.590-0.620
[14.99 - 15.75]
0.175
MAX
0.225 MAX TYP
0.125 MIN
TYP
86°-94°
TYP
0.060-0.1000.090-0.110
TYP
TYP
0.015-0.021
TYP
0.015 -0.060
TYP
0.150 MIN
TYP
95° ±5° 0.010 ±0.002
TYP
TYP
[0.25 ±0.05]
+0.025
-0.060
+0.64
17.40
-1.52
0.685
UV Window Cavity Dual-In-Line CerDIP Package (Q)
Order Number FM27C256QXXX
Package Number J28AQ
28 27 26 25 24 23 22 21 20 19 18 17 16 15
0.030
Max
(0.762)
0.600 - 0.620
(15.24 - 15.75)
0.062 RAD
(1.575)
0.510 ±0.005
(12.95 ±0.127)
95° ±5°
0.580
(14.73)
0.008-0.015
(0.229-0.381)
Pin #1
IDENT
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1.393 - 1.420
(35.38 - 36.07)
+0.025
0.625 -0.015
(15.88 +0.635
(
-0.381
0.050
(1.270)
Typ
0.053 - 0.069
(1.346 - 1.753)
0.125-0.165
(3.175-4.191)
0.108 ±0.010
(2.540 ±0.254)
0.050 ±0.015
(1.270 ±0.381)
88° 94°
Typ
0.20 Min
(0.508)
0.125-0.145
(3.175-3.583)
0.018 ±0.003
(0.457 ±0.076)
28-Lead Plastic One-Time-Programmable Dual-In-Line Package
Order Number FM27C256NXXX
Package Number N28B
9
FM27C256
www.fairchildsemi.com
FM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.485-0.495
[12.32-12.57]
0.106-0.112
[2.69-2.84]
0.007[0.18] S B D-E S
0.449-0.453
[11.40-11.51]
-H-
Base
Plane
0.023-0.029
[0.58-0.74]
0.015
[0.38] Min Typ
-A0.045
[1.143]
60
°
0.007[0.18] S B D-E S
0.002[0.05] S B
0.000-0.010
[0.00-0.25]
Polished Optional
1
0.490-0530
[12.45-13.46]
0.400
-D4
( [10.16] )
30
0.541-0.545
[13.74-13-84]
29
5
0.549-0.553
[13.94-14.05]
0.015[0.38] S
C
D-E, F-G S
-G-
-B0.585-0.595
[14.86-15.11]
0.013-0.021
TYP
[0.33-0.53]
-FSee detail A
-J13
14
20
-E-
0.002[0.05] S A
0.007[0.18] S
0.007[0.18] S
A F-G S
A F-G S
0.118-0.129
[3.00-3.28]
0.010[0.25] L
0.007[0.18] M
21
B A D-E, F-G S
B
0.042-0.048
45°X [1.07-1.22]
0.123-0.140
[3.12-3.56]
0.050
;;
0.025
[0.64]
Min
B
0.007[0.18] S
0.019-0.025
[0.48-0.64]
H D-E, F-G S
D-E, F-G S
-C0.004[0.10]
0.020
[0.51]
0.005 Max
[0.13]
0.0100
[0.254]
0.045
[1.14]
0.025
[0.64] Min
Detail A
Typical
Rotated 90°
0.021-0.027
[0.53-0.69]
R
0.030-0.040
[0.76-1.02]
0.065-0.071
[1.65-1.80]
0.053-0.059
[1.65-1.80]
0.031-0.037
[0.79-0.94]
0.006-0.012
[0.15-0.30]
0.026-0.032
Typ
[0.66-0.81]
C
0.078-0.095
[1.98-2.41]
0.027-0.033
[0.69-0.84]
Section B-B
Typical
32-Lead Plastic Leaded Chip Carrier (PLCC)
Order Number FM27C256VXXX
Package Number VA32A
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10
FM27C256
www.fairchildsemi.com