ETC FMMT660A

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FM24C256.pdf
20-Aug-99 00:00
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FM93C06.pdf
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FM93C46.pdf
22-Dec-99 00:04
110K
FM93C46A.pdf
20-Jan-00 00:00
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FM93C56.pdf
22-Dec-99 00:04
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FM93C56A.pdf
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FM93C66.pdf
22-Dec-99 00:04
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FM93C66A.pdf
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FM93C86A.pdf
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FM93CS06.pdf
09-Feb-00 00:00
164K
FM93CS46.pdf
09-Feb-00 00:00
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FM93CS56.pdf
09-Feb-00 00:00
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FM93CS66.pdf
09-Feb-00 00:00
162K
FMB100.pdf
22-Dec-99 00:04
44K
FMB1020.pdf
22-Dec-99 00:04
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FMB200.pdf
22-Dec-99 00:04
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FMB2222A.pdf
22-Dec-99 00:04
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FMB2227A.pdf
22-Dec-99 00:04
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FMB2907A.pdf
22-Dec-99 00:04
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FMB3904.pdf
22-Dec-99 00:04
77K
FMB3906.pdf
11-Feb-00 00:00
81K
FMB3946.pdf
22-Dec-99 00:04
30K
FMBA06.pdf
22-Dec-99 00:04
53K
Description
FMBA0656.pdf
22-Dec-99 00:04
28K
FMBA14.pdf
22-Dec-99 00:04
48K
FMBA56.pdf
22-Dec-99 00:04
42K
FMKA140.pdf
22-Dec-99 00:04
32K
FMMT449.pdf
22-Dec-99 00:04
194K
FMMT549.pdf
22-Dec-99 00:04
25K
FMMT560.pdf
03-Dec-99 15:42
26K
FMMT560A.pdf
03-Dec-99 15:42
26K
FMMT660.pdf
03-Dec-99 15:42
26K
FMMT660A.pdf
03-Dec-99 15:42
26K
FMS2701.pdf
22-Dec-99 00:04
110K
August 1999
FM24C256
256 KBit 2-Wire Bus Interface
Serial EEPROM with Write Protect
General Description
Features
The FM24C256/C256L/C256LZ devices are 256 Kbits CMOS
nonvolatile electrically erasable memory. These devices offer the
designer different low voltage and low power options. They
conform to all requirements in the Extended I2C™ 2-wire protocol.
Furthermore, they are designed to minimize device pin count and
simplify PC board layout requirements.
■ Extended Operating Voltages
— C256: 4.5V - 5.5V
— C256L: 2.7V - 5.5V
— C256LZ: 2.7V - 5.5V
■ Low Power CMOS
— 1mA active current typical
— C256/C256L: 10µA standby current typical
— C256LZ: less than 1µA standby current
The entire memory array can be disabled (Write Protection) by
connecting the WP pin to VCC.
■ 2-wire I2C serial interface
Functional address lines allow up to eight devices on the same
bus, for up to a total of 2 Mbit address space.
■ 64 byte page write mode
■ Max write cycle time of 6ms byte/page
The I2C communication protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
■ 40 years data retention
■ Endurance: 100,000 data changes
■ Hardware write protect for entire array
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power consumption.
■ Schmitt trigger inputs for noise suppression
■ Electrostatic discharge protection > 4000V
■ 8-pin DIP and 8-pin SO (150 mil) packages
Block Diagram
WRITE
LOCKOUT
VCC
WP
START CYCLE
H.V. GENERATION
TIMING &CONTROL
START
STOP
LOGIC
SDA
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
SCL
XDEC
LOAD
A2
A1
A0
E2PROM
ARRAY
INC
WORD
ADDRESS
COUNTER
R/W
YDEC
CK
DATA REGISTER
DIN
DOUT
DS800023-1
© 1999 Fairchild Semiconductor Corporation
FM24C256 rev. A.2
1
www.fairchildsemi.com
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
PRELIMINARY
Dual-In-Line Package (N)
and 8-Pin SO Package (M8)
A0
1
A1
2 FM24C256 7
FM24C256L
3 FM24C256LZ 6
WP
4
SDA
A2
VSS
8
5
VCC
SCL
DS800023-2
Top View
See Package Number N08E and M08A
Pin Names
A0, A1, A2
Device Address Input
VSS
Ground
SDA
Data I/O
SCL
Clock Input
WP
Write Protect
VCC
Power Supply
Ordering Information
FM
24
C
XX
F
LZ
E
XX
Letter
Description
N
M8
8-pin DIP
8-pin SO8
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
SCL Clock Frequency
Blank
F
100KHz
400KHz
256
256K with write protect
Package
Density
Interface
2
FM24C256 rev. A.2
C
CMOS
24
IIC - 2 Wire
FM
Fairchild Non-Volatile
Memory
www.fairchildsemi.com
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
Connection Diagram
Ambient Storage Temperature
Operating Conditions
–65°C to +150°C
All Input or Output Voltages
with Respect to Ground
6.5V to –0.3V
Lead Temperature
(Soldering, 10 seconds)
+300°C
ESD Rating
Ambient Operating Temperature
FM24C256
FM24C256E
FM24C256V
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Positive Power Supply
FM24C256
FM24C256L
FM24C256LZ
4000V min.
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
Standard VCC (4.5V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min
Limits
Typ
Max
Units
ICCA
Active Power Supply Current
fSCL = 100 kHz
fSCL = 400 kHz
0.5
1.0
mA
ISB
Standby Current
VIN = GND or VCC
10
50
µA
ILI
Input Leakage Current
VIN = GND to VCC
0.1
1
µA
ILO
Output Leakage Current
VOUT = GND to VCC
0.1
1
µA
VIL
Input Low Voltage
–0.3
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL
Output Low Voltage
0.4
V
IOL = 2.1 mA
Low VCC (2.7V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min
ICCA
ISB
(Note 1)
Limits
Typ
Max
Units
Active Power Supply Current
fSCL = 100 kHz
fSCL = 400 kHz
0.5
1.0
mA
Standby Current for L
VIN = GND or VCC = 4.5V - 5.5V
VIN = GND or VCC = 2.7V - 4.5V
VIN = GND or VCC = 4.5V - 5.5V
VIN = GND or VCC = 2.7V - 4.5V
10
1
10
0.1
50
10
50
1
µA
Standby Current for LZ
ILI
Input Leakage Current
VIN = GND to VCC
0.1
1
µA
ILO
Output Leakage Current
VOUT = GND to VCC
0.1
1
µA
VIL
Input Low Voltage
–0.3
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL
Output Low Voltage
0.4
V
IOL = 2.1 mA
Capacitance TA = +25°C, f = 1.0 MHz, VCC = 5V
Symbol
Test
Conditions
Max
Units
CI/O
Input/Output Capacitance (SDA)
VI/O = 0V
8
pF
CIN
Input Capacitance (A0, A1, A2, SCL)
VIN = 0V
6
pF
Note 1: Typical values are for TA = 25°C and nominal supply voltage (5V).
3
FM24C256 rev. A.2
www.fairchildsemi.com
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
Absolute Maximum Ratings
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10 ns
Input & Output Timing Levels
VCC x 0.5
Output Load
1 TTL Gate and CL = 100 pF
Read and Write Cycle Limits (Standard and Low VCC Range - 2.7V-5.5V)
Symbol
fSCL
TI
Parameter
100 kHz
Min
Max
400 kHz
Min
Max
Units
SCL Clock Frequency
100
400
kHz
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum VIN
Pulse width)
100
50
ns
1.2
µs
tAA
SCL Low to SDA Data Out Valid
0.3
tBUF
Time the Bus Must Be Free before
a New Transmission Can Start
4.7
1.3
µs
Start Condition Hold Time
4.0
0.6
µs
tLOW
Clock Low Period
4.7
1.5
µs
tHIGH
Clock High Period
4.0
0.6
µs
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
0.6
µs
tHD:DAT
Data in Hold Time
0
0
µs
tSU:DAT
Data in Setup Time
250
100
ns
tHD:STA
3.5
0.3
tR
SDA and SCL Rise Time
1
0.3
µs
tF
SDA and SCL Fall Time
300
300
ns
tSU:STO
tDH
tWR
(Note 2)
Stop Condition Setup Time
4.7
0.6
µs
Data Out Hold Time
100
100
ns
Write Cycle Time - FM24C256
- FM24C256L, FM24C256LZ
6
6
6
6
ms
Note 2: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
FM24C256 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address
4
FM24C256 rev. A.2
www.fairchildsemi.com
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
AC Conditions of Test
tR
tF
tHIGH
tLOW
tLOW
SCL
;;
tSU:STA
SDA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
IN
tBUF
tAA
tDH
SDA
OUT
Note 3: SCL = Serial Clock Data
SDA = Serial Data I/O
DS800023-3
BACKGROUND INFORMATION (I2C Bus)
SERIAL DATA (SDA)
As mentioned, the I2C bus allows synchronous bidirectional communication between Transmitter/Receiver using the SCL (clock)
and SDA (Data I/O) lines. All communication must be started with a
valid START condition, concluded with a STOP condition and
acknowledged by the Receiver with an ACKNOWLEDGE condition.
SDA is a bidirectional pin used to transfer data to and from the
device. It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs.
Device Address Inputs (A0, A1, A2)
Device address pins A0, A1, and A2 are connected to VCC or VSS
to configure the EEPROM address for multiple device configuration. A total of eight different devices can be attached to the same
SDA bus.
I2C
In addition, since the
bus is designed to support other devices
such as RAM, EPROM, etc., the device type identifier string, or
control byte, must follow the START condition. For EEPROMs, the
first 4-bit of the control byte is 1010 binary for READ and WRITE
operations. This is then followed by the device selection bits A2, A1
and A0, and acts as the three most significant bits of the word
address.The final bit in the control byte determines the type of
operation performed (READ/WRITE). A "1" signifies a READ while
a "0" signifies a WRITE. The control byte is then followed by two bytes
that define the word address, which is then followed by the data byte.
Write Protection (WP)
If WP is tied to VCC, program WRITE operations onto the entire
array of the memory will not be executed. READ operations are
always available.
If WP is tied to VSS, normal memory operation is enabled for
READ/WRITE over the entire 256K bit memory array.
The EEPROMs on the I2C bus may be configured in any manner
required, providing the total memory addressed does not exceed
512K bits (64K bytes). EEPROM memory addressing is controlled
by hardware configuring the A2, A1, and A0 pins (Device Address
pins) with pull-up or pull-down resistors. ALL UNUSED PINS
MUST BE GROUNDED (tied to VSS).
This feature allows the user to assign the entire array of the memory
as ROM, which can be protected against accidental programming
writes. When WRITE is disabled, slave address and word address
will be acknowledged but data will not be acknowledged.
Device Operation
Addressing an EEPROM memory location involves sending a
command string with the following information:
The FM24C256xxx supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the bus as a
transmitter and the receiving devices as the receiver. The device
controlling the transfer is the master and the device that is controlled is the slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations. Therefore, the FM24C256xxx is considered a slave in all applications.
[DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK ADDRESS]-[BYTE ADDRESS]
Pin Description
SERIAL CLOCK (SCL)
Definitions
CLOCK AND DATA CONVENTIONS
Word
8 bits (byte) of data
Page
64 sequential addresses (one byte each) that
may be programmed during a "Page Write"
programming cycle.
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH and are reserved for
indication of start and stop conditions. Refer to Figures 1 and 2.
START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
FM24C256xxx continuously monitors the SDA and SCL lines for
the start condition and will not respond to any command until this
condition has been met.
I2C
Master
Any
device CONTROLLING the transfer of
data (such as a microcontroller).
Slave
Device being controlled (EEPROMS are
always considered Slaves).
Transmitter
Device currently SENDING data on the bus
(may be either a Master or Slave).
Receiver
Device currently receiving data on the bus
(Master or Slave).
STOP CONDITION
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the FM24C256xxx to place the device in
the standby power mode.
The SCL input is used to clock all data into and out of the device.
5
FM24C256 rev. A.2
www.fairchildsemi.com
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
Bus Timing
both the device and a WRITE operation have been selected, the
FM24C256xxx will respond with an acknowledge after the receipt
of each subsequent eight bit word.
ACKNOWLEDGE
ACK (acknowledge) is a software convention used to indicate
successful data transfers. The transmitting device, either master or
slave, will release the bus after transmitting eight bits. During the ninth
clock cycle the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
In the READ mode the FM24C256xxx slave will transmit eight bits
of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.
The FM24C256xxx device will always respond with an acknowledge after recognition of a start condition and its slave address. If
Write Cycle Timing:
SCL
SDA
8th BIT
ACK
WORD n
tWR
START
CONDITION
STOP
CONDITION
DS800023-4
Data Validity (Figure 1)
SCL
DATA
CHANGE
DATA STABLE
SDA
DS800023-5
Definition of Start and Stop (Figure 2)
SCL
SDA
START CONDITION
STOP CONDITION
DS800023-6
Acknowledge Response from Receiver (Figure 3)
SCL FROM
MASTER
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
START
ACKNOWLEDGE
6
FM24C256 rev. A.2
DS800023-7
www.fairchildsemi.com
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
Write Cycle Timing
Following a start condition the master must output the address of
the slave it is accessing. The most significant four bits of the slave
address are those of the device type identifier. This is fixed as
1010 for all different FM24C256xxx devices.
The next three bits identify the device address. Address from 000
to 111 are acceptable thus allowing up to eight devices to be
connected to the I2C bus.
PAGE WRITE
The FM24C256xxx is capable of 64 byte page write operation. It
is initiated in the same manner as the byte write operation; but
instead of termination the write cycle after the first data word is
transfered, the master can transmit up to 63 more words. After the
receipt of each word, the device responds with an acknowledge.
The last bit of the slave address defines whether a write or read
condition is requested by the master. A "1" indicates that a READ
operation is to be executed and a "0" initiates the WRITE mode.
A simple review: After the FM24C256xxx recognizes the start
condition, the device interfaced to the I2C bus waits for a slave
address to be transmitted over the SDA line. If the transmitted
slave address matches an address of one of the devices, the
designated slave pulls the line LOW with an acknowledge signal
and awaits further transmissions.
After the receipt of each word, the internal address counter
increments to the next address and the next SDA data is accepted. If the master should transmit more than 64 words prior to
generating the stop condition, the address counter will "roll over"
and the previous written data will be overwritten. As with the byte
write operation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence.
Write Operations
BYTE WRITE
For a WRITE operation, two additional address fields are required
after the control byte acknowledge. These are the word addresses
and are comprised of fifteen bits to provide access to any one of
the 32K words. The first byte indicates the high-order byte of the
word address. Only the seven least signicant bits can be changed,
the most significant bit is pre-assigned the value "0". Following the
acknowledgement from the first word address, the next byte
indicates the low-order byte of the word address. Upon receipt of
the word address, the FM24C256xxx responds with another
acknowledge and waits for the next eight bits of data, again,
responding with an acknowledge. The master then terminates the
S
T
Bus Activity: A
Master R
T
SDA Line
Bus Activity
SLAVE
ADDRESS
Acknowledge Polling
Once the stop condition is isssued to indicate the end of the host's
write operation, the FM24C256xxx initiates the internal write
cycle. ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address for a write
operation. If the FM24C256xxx is still busy with the write operation, no ACK will be returned. If the device has completed the write
operation, an ACK will be returned and the host can then proceed
with the next read or write operation.
Byte Write (Figure 5)
WORD
ADDRESS (1)
1 0 1 0
WORD
ADDRESS (0)
S
T
O
P
DATA
0
A
C
K
A
C
K
A
C
K
A
C
K
DS800023-8
7
FM24C256 rev. A.2
www.fairchildsemi.com
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
transfer by generating a stop condition, at which time the
FM24C256xxx begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress, the device's
inputs are disabled and the device will not respond to any requests
from the master. Refer to Figure 5 for the address, acknowledge
and data transfer sequence.
DEVICE ADDRESSING
Programming of the memory array will not take place if the WP pin
is connected to VCC. The device will accept control and word
addresses; but if the memory accessed is write protected by the
WP pin, the FM24C256xxx will not generate an acknowledge after
the first byte of data has been received, and thus the program
cycle will not be started when the stop condition is asserted.
Read Operation
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave address
is set to "1". There are three basic read operations: current
address read, random read and sequential read.
SEQUENTIAL READ
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The FM24C256xxx continues to output data for each acknowledge received. The read operation is terminated by the
master not responding with an acknowledge or by generating a
stop condition.
CURRENT ADDRESS READ
Internally the FM24C256xxx contains an address counter that
maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to
address n, the next read operation would access data from
address n+1. Upon receipt of the slave address with R/W set to
"1," the FM24C256xxx issues an acknowledge and transmits the
eight bit word. The master will not acknowledge the transfer but
does generate a stop condition, and therefore discontinues transmission. Refer to Figure 7 for the sequence of address, acknowledge and data transfer.
The data output is sequential, with the data from address n,
followed by the data n+1. The address counter for read operations
increments all word address bits, allowing the entire memory
contents to be serially read during one operation. After the entire
memory has been read, the counter "rolls over" and the
FM24C256xxx continues to output data for each acknowledge
received. Refer to Figure 9 for the address, acknowledge, and
data transfer sequence.
RANDOM READ
Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
Page Write (Figure 6)
S
T
Bus Activity: A
Master R
T
SDA Line
Bus Activity
SLAVE
ADDRESS
WORD
ADDRESS (1)
1 0 1 0
WORD
ADDRESS (0)
DATA n
S
T
O
P
DATA n+31
0
A
C
K
A
C
K
A
C
K
A
C
K
DS800023-9
8
FM24C256 rev. A.2
www.fairchildsemi.com
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
with the R/W bit set to "1", the master must first perform a "dummy"
write operation. The master issues a start condition, a slave
address, and then the word address to be read. After the word
address acknowledge, the master immediately reissues the start
condition and the slave address with the R/W bit set to "1". This will
be followed by an acknowledge from the FM24C256xxx and then
by the eight bit word. The master will not acknowledge the transfer
but does generate the stop condition, and therefore the
FM24C256xxx discontinues transmission. Refer to Figure 8 for
the address, acknowledge, and data transfer sequence.
Write Protection
S
T
A
R SLAVE ADDRESS
T
S
T
O
P
DATA
1 0 1 0
A
C
K
NO
A
C
K
DS800023-10
Random Read (Figure 8)
S
T
A
Bus Activity: R
Master T
SDA Line
SLAVE
ADDRESS
WORD
ADDRESS (1)
1 0 1 0
S
T
A
R
T
WORD
ADDRESS (0)
0
1 0 1 0
A
C
K
Bus Activity
SLAVE
ADDRESS
A
C
K
A
C
K
DATA n
S
T
O
P
1 0
A
C
K
NO
A
C
K
DS800023-11
Sequential Read (Figure 9)
S
T
Bus Activity: A
Master R
T
SDA Line
Bus Activity
SLAVE
ADDRESS
DATA n
DATA n + 1
DATA n + x
S
T
O
P
1 0 1 0
A
C
K
A
C
K
A
C
K
A
C
K
NO
A
C
K
DS800023-12
9
FM24C256 rev. A.2
www.fairchildsemi.com
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
Current Address Read (Figure 7)
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
8° Max, Typ.
All leads
0.04
(0.102)
All lead tips
0.053 - 0.069
(1.346 - 1.753)
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020 Typ.
(0.356 - 0.508)
Molded Small Out-Line Package (M8)
Order Number FM24C256xxxM8 or FM24C256xxxEM8
Package Number M08A
10
FM24C256 rev. A.2
www.fairchildsemi.com
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
(6.35 ± 0.127)
+
Pin #1 IDENT
0.032 ± 0.005
(0.813 ± 0.127)
RAD
5
1
1
2
3
0.040 Typ.
(1.016)
0.300 - 0.320
(7.62 - 8.128)
7
Pin #1
IDENT
Option 1
0.280 MIN
(7.112)
8
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Order Number FM24C256xxxN or FM24C256xxxEN
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
Français
Tel:
+33 (0) 1-6930-3696
Italiano
Tel:
+39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
11
FM24C256 rev. A.2
www.fairchildsemi.com
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
Physical Dimensions inches (millimeters) unless otherwise noted
FM93C06
256-Bit Serial CMOS EEPROM
(MICROWIRE™ Bus Interface)
General Description
Features
The FM93C06 device is 256 bits of CMOS non-volatile electrically
erasable memory organized as 16x16 bit array. They are fabricated using Fairchild Semiconductor's floating-gate CMOS process for high reliability, high endurance and low power consumption. These memory devices are available in an 8-pin SOIC or 8pin TSSOP package for small space considerations.
■ Device status during programming mode
FM93C06 is compatible with MICROWIRE serial interface, which
offers simple interface to standard microcontrollers and microprocessors. There are 7 instructions which control this device: Read,
Write Enable, Erase, Erase All, Write, Write All, and Write Disable.
The ready/busy status is available on the DO pin to indicate the
completion of a programming cycle.
■ Reliable CMOS floating gate technology
■ Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
■ No erase required before write
■ 2.7V to 5.5V operation in all modes
■ MICROWIRE compatible serial l/O
■ Self-timed programming cycle
■ 40 years data retention
■ Endurance: 1,000,000 data changes
■ Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
■ Schmitt Trigger inputs and VCC lockout to prevent data
corruption
Block Diagram
VCC
CS
INSTRUCTION
DECODER
CONTROL LOGIC,
AND CLOCK
GENERATORS
SK
DI
INSTRUCTION
REGISTER
ADDRESS
REGISTER
VPP
DECODER
1 OF 16
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
EEPROM ARRAY
16
READ/WRITE AMPS
16
VSS
DATA IN/OUT REGISTER
16 BITS
DO
© 1999 Fairchild Semiconductor Corporation
FM93C06
DATA OUT BUFFER
1
DS800024-1
www.fairchildsemi.com
FM93C06 256-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
December 1999
Dual-In-Line Package (N),
8-Pin SO (M8) and 8-Pin TSSOP (MT8)
CS
1
8
VCC
SK
2
7
NC
DI
3
6
NC
DO
4
5
GND
DS800024-2
Top View
See Package Number
N08E, M08A and MTC08
Pin Names
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
VCC
Power Supply
Ordering Information
FM
93
C
XX
LZ
E
XX
Letter
Description
N
M8
MT8
8-Pin DIP
8-Pin SO8
8-Pin TSSOP
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
06
256 bit
C
CS
CMOS
Data protect and sequential
read
93
MICROWIRE
FM
Fairchild Non-Volatile
Memory
Package
Density
Interface
2
FM93C06
www.fairchildsemi.com
FM93C06 256-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Connection Diagrams
Operating Range
Ambient Storage Temperature
Ambient Operating Temperature
FM93C06
FM93C06E
FM93C06V
All Input or Output Voltage
with Respect to Ground
Lead Temperature (Soldering, 10 sec.)
ESD Rating
–65°C to +150°C
+6.5V to -0.3V
+300°C
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
4.5V to 5.5V
2000V
DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V
Symbol
Max.
Units
ICCA
Operating Current
Parameter
Part Number
CS = VIH, SK = 1MHz
Conditions
1
mA
ICCS
Standby Current
CS = VIL
50
µA
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
(Note 2)
±1
µA
VIL
VIH
Input Low Voltage
Input High Voltage
0.8
VCC +1
V
0.4
V
V
0.2
V
V
1
MHz
-0.1
2
VOL1
VOH1
Output Low Voltage
Output High Voltage
IOL = 2.1mA
IOH = -400 µA
2.4
VOL2
VOH2
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
VCC -0.2
fSK
SK Clock Frequency
(Note 3)
tSKH
SK High Time
tSKL
SK Low Time
tSKS
SK Setup Time
tCS
Minimum CS
Low Time
tCSS
CS Setup Time
50
ns
tDH
DO Hold Time
70
ns
tDIS
DI Setup Time
100
200
ns
tCSH
CS Hold Time
0
ns
tDIH
DI Hold Time
20
ns
tPD
Output Delay
500
ns
tSV
CS to Status Valid
500
ns
tDF
CS to DO in Hi-Z
tWP
Write Cycle Time
FM93C06
FM93C06E/V
0
250
300
ns
250
ns
SK must be at VIL for
tSKS before CS goes
high
50
ns
(Note 4)
250
ns
FM93C06
FM93C06E/V
CS = VIL
3
FM93C06
Min.
100
ns
10
ms
www.fairchildsemi.com
FM93C06 256-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Absolute Maximum Ratings (Note 1)
Operating Range
Ambient Storage Temperature
Ambient Operating Temperature
FM93C06L/LZ
FM93C06LE/LZE
FM93C06LV/LZV
–65°C to +150°C
All Input or Output Voltage
with Respect to Ground
+6.5V to -0.3V
Lead Temperature (Soldering, 10 sec.)
+300°C
ESD Rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
2000V
2.7V to 5.5V
DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified
Symbol
Parameter
Part Number
Conditions
Min.
Max.
Units
1
mA
10
1
µA
µA
±1
µA
0.15 VCC
VCC +1
V
0.1 VCC
V
V
250
KHz
ICCA
Operating Current
CS = VIH, SK = 250KHz
ICCS
Standby Current
L
LZ
CS = VIL
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
(Note 2)
VIL
VIH
Input Low Voltage
Input High Voltage
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
fSK
SK Clock Frequency
(Note 3)
tSKH
SK High Time
1
µs
tSKL
SK Low Time
1
µs
tSKS
SK Setup Time
SK must be at VIL for
tSKS before CS goes
high
0.2
µs
tCS
Minimum CS
Low Time
(Note 4)
1
µs
tCSS
CS Setup Time
0.2
µs
tDH
DO Hold Time
70
ns
tDIS
DI Setup Time
0.4
µs
tCSH
CS Hold Time
0
ns
tDIH
DI Hold Time
0.4
µs
tPD
Output Delay
2
µs
tSV
CS to Status Valid
1
µs
tDF
CS to DO in Hi-Z
tWP
Write Cycle Time
-0.1
0.8 VCC
0.9 VCC
0
CS = VIL
Capacitance TA = 25°C, f = 1 MHz (Note 5)
Symbol
Test
Max
Units
COUT
Output Capacitance
Typ
5
pF
CIN
Input Capacitance
5
pF
0.4
µs
15
ms
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2:
Typical leakage values are in the 20nA range.
Note 3: The shortest allowable SK clock period = 1/fSK (as shown under the fSK parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not
allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
Note 5:
This parameter is periodically sampled and not 100% tested.
AC Test Conditions
VCC Range
VIL/VIH
Input Levels
VIL/VIH
Timing Level
VOL/VOH
Timing Level
IOL/IOH
2.7V ≤ VCC ≤ 5.5V
.03V/1.8V
1.0V
0.8V/1.5V
±10µA
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(Extended Voltage Levels)
4.5V ≤ VCC ≤ 5.5V
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
FM93C06
www.fairchildsemi.com
FM93C06 256-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Absolute Maximum Ratings (Note 1)
Write (WRITE):
The FM93C06 device has 7 instructions as described below. Note
that the MSB of any instruction is a “1” and is viewed as a start bit
in the interface sequence. The next 8 bits carry the op code and
the 6-bit address for register selection.
The WRITE instruction is followed by the address and 16 bits of data
to be written into the specified address. After the last bit of data is
put in the data-in (DI) pin, CS must be brought low before the next
rising edge of the SK clock. This falling edge of the CS initiates the
self-timed programming cycle. The D0 pin indicates the READY/
BUSY status of the chip if CS is brought high after a minimum of tCS.
D0 = logical 1 indicates that the register at the address specified in
the instruction has been written with the data pattern specified in the
instruction and the part is ready for another instruction.
Read (READ):
The READ instruction outputs serial data on the D0 pin. After a
READ instruction is received, the instruction and address are
decoded, followed by data transfer from the selected memory
register into a 16-bit serial-out shift register. A dummy bit (logical
0) precedes the 16-bit data output string. Output data changes are
initiated by a low to high transition of the SK clock.
Erase All (ERAL):
The ERAL instruction will simultaneously program all registers in
the memory array and set each bit to the logical “1” state. The Erase
All cycle is identical to the ERASE cycle except for the different opcode. As in the ERASE mode, the DO pin indicates the READY/
BUSY status of the chip if CS is brought high after the t CS interval.
Write Enable (WEN):
When VCC is applied to the part, it 'powers-up' in the Write Disable
(WDS) state. Therefore, all programming modes must be preceded by a Write Enable (WEN) instruction. Once a Write Enable
instruction is executed, programming remains enabled until aWrite
Disable (WDS) instruction is executed or VCC is removed from the
part.
Write All (WRALL):
The WRALL instruction will simultaneously program all registers
with the data pattern specified in the instruction. As in the WRITE
mode, the DO pin indicates the READY/BUSY status of the chip
if CS is brought high after the tCS interval.
Erase (ERASE):
The ERASE instruction will program all bits in the specified
register to the logical “1” state. CS is brought low following the
loading of the last address bit. This falling edge of the CS pin
initiates the self-timed programming cycle.
Write Disable (WDS):
To protect against accidental data disturb, the WDS instruction
disables all programming modes and should follow all programming operations. Execution of a READ instruction is independent
of both the WEN and WDS instructions.
The DO pin indicates the READY/BUSY status of the chip if CS is
brought high after a minimum time of tCS. DO = logical “0” indicates
that the register, at the address specified in the instruction, has
been erased, and the part is ready for another instruction.
Note: The Fairchild CMOS EEPROMs do not require an "ERASE" or "ERASE ALL"
operation prior to the "WRITE" and "WRITE ALL" instructions. The "ERASE" and "ERASE
ALL" instructions are included to maintain compatibility with earlier technology EEPROMs.
Instruction Set for the FM93C06
Instruction
SB
Op. Code
Address
READ
1
10
00 A3 A2 A1 A0
WEN
1
00
11xxxx
ERASE
1
11
00 A3 A2 A1 A0
WRITE
1
01
00 A3 A2 A1 A0
Note:
ERAL
1
00
10xxxx
WRALL
1
00
01xxxx
WDS
1
00
00xxxx
Data
Reads data stored in memory, at specified address.
Write enable must precede all programming modes.
Erase selected register.
D15-D0
Writes selected register.
Erases all registers.
D15-D0
Writes all registers.
Disables all programming instructions.
Address bits A5 and A4 should be set to '0' for READ, ERASE and WRITE instructions.
x = Don't care
5
FM93C06
Comments
www.fairchildsemi.com
FM93C06 256-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Functional Description
Synchronous Data Timing
CS
SK
DI
VIH
VIL
tCSS
tSKH
tSKS
VIH
VIL
tDIS
VIH
tSKL
tDIH
VIL
tPD
VOH
DO (READ)
VOL
tSV
VOH
DO (PROGRAM)
VOL
tCSH
tDF
tDH
tDH
tDF
STATUS VALID
DS800024-4
READ
CS
tCS
SK
1
DI
1
0
0
0
...
A3
A0
DO
0
D15
...
D0
DS800024-5
WEN
WEN
CS
tCS
SK
DI
1
0
0
1
1
...
X
X
DS800024-6
WDS
WDS
CS
tCS
SK
DI
1
0
0
0
0
...
X
X
DS800024-7
6
FM93C06
www.fairchildsemi.com
FM93C06 256-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Timing Diagrams
WRITE
CS
tCS
SK
0
1
DI
1
0
0
A3
...
A0
D15
...
D0
DO
BUSY
READY
tWP
DS800024-8
WRALL
WRALL
CS
tCS
SK
1
DI
0
0
0
1
DON'T CARE (4 BITS)
D15
...
D0
DO
BUSY
READY
tWP
DS800024-9
ERASE
ERASE
tCS
CS
STANDBY
SK
DI
DO
1
1
1
0
0
A3
...
A0
HI-Z
BUSY
READY
HI-Z
tWP
DS800024-10
ERAL
ERAL
tCS
CS
STANDBY
SK
DI
1
DO
0
0
1
0
DON'T CARE BITS (4 BITS)
HI-Z
BUSY
READY
HI-Z
tWP
DS800024-11
7
FM93C06
www.fairchildsemi.com
FM93C06 256-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Timing Diagrams (Continued)
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.150 - 0.157
(3.810 - 3.988)
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.053 - 0.069
(1.346 - 1.753)
8° Max, Typ.
All leads
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.04
(0.102)
All lead tips
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.014 - 0.020 Typ.
(0.356 - 0.508)
0.050
(1.270)
Typ
Molded Small Out-Line Package (M8)
Package Number M08A
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0098
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
8
FM93C06
www.fairchildsemi.com
FM93C06 256-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
Min
(2.337)
7
6
0.250 - 0.005
(6.35 ± 0.127)
+
Pin #1 IDENT
0.032 ± 0.005
(0.813 ± 0.127)
RAD
5
8
Pin #1 IDENT
1
Option 1
1
0.280
DIA
(7.112)
2
3
0.040 Typ.
(1.016)
0.300 - 0.320
(7.62 - 8.128)
7
0.030
Max.
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
Français
Tel:
+33 (0) 1-6930-3696
Italiano
Tel:
+39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
9
FM93C06
www.fairchildsemi.com
FM93C06 256-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Physical Dimensions inches (millimeters) unless otherwise noted
FM93C46
1K-Bit Serial CMOS EEPROM
(MICROWIRE™ Bus Interface)
General Description
Features
The FM93C46 device is 1024 bits of CMOS non-volatile electrically erasable memory organized as 64x16 bit array. They are
fabricated using Fairchild Semiconductor's floating-gate CMOS
process for high reliability, high endurance and low power consumption. These memory devices are available in an 8-pin SOIC
or 8-pin TSSOP package for small space considerations.
■ Device status during programming mode
FM93C46 is compatible with MICROWIRE serial interface, which
offers simple interface to standard microcontrollers and microprocessors. There are 7 instructions which control this device: Read,
Write Enable, Erase, Erase All, Write, Write All, and Write Disable.
The ready/busy status is available on the DO pin to indicate the
completion of a programming cycle.
■ Reliable CMOS floating gate technology
■ Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
■ No erase required before write
■ 2.7V to 5.5V operation in all modes
■ MICROWIRE compatible serial l/O
■ Self-timed programming cycle
■ 40 years data retention
■ Endurance: 1,000,000 data changes
■ Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
■ Schmitt Trigger inputs and VCC lockout to prevent data
corruption
Block Diagram
VCC
CS
INSTRUCTION
DECODER
CONTROL LOGIC,
AND CLOCK
GENERATORS
SK
DI
INSTRUCTION
REGISTER
ADDRESS
REGISTER
VPP
DECODER
1 OF 64
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
EEPROM ARRAY
READ/WRITE AMPS
VSS
DATA IN/OUT REGISTER
16 BITS
DO
© 1999 Fairchild Semiconductor Corporation
FM93C46
DATA OUT BUFFER
1
DS800025-1
www.fairchildsemi.com
FM93C46 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
December 1999
Dual-In-Line Package (N),
8-Pin SO (M8) and 8-Pin TSSOP (MT8)
CS
1
8
VCC
SK
2
7
DI
3
DO
4
Rotated Die (93C46T)
NC
1
8
NC
NC
VCC
2
7
GND
6
NC
CS
3
6
DO
5
GND
SK
4
5
DI
DS800025-2
DS800025-12
Top View
See Package Number N08E, M08A and MTC08
Pin Names
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
VCC
Power Supply
Ordering Information
FM
93
C
XX
T
LZ
E
XX
Letter
Description
N
M8
MT8
8-Pin DIP
8-Pin SO8
8-Pin TSSOP
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
Blank
T
Normal Pin Out
Rotated Die Pin Out
Package
Density
Interface
2
FM93C46
46
1K
C
CS
CMOS
Data protect and sequential
read
93
MICROWIRE
FM
Fairchild Non-Volatile
Memory
www.fairchildsemi.com
FM93C46 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Connection Diagrams
Operating Range
Ambient Storage Temperature
Ambient Operating Temperature
FM93C46
FM93C46E
FM93C46V
All Input or Output Voltage
with Respect to Ground
Lead Temperature (Soldering, 10 sec.)
ESD Rating
–65°C to +150°C
+6.5V to -0.3V
+300°C
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
4.5V to 5.5V
2000V
Standard VCC (4.5V to 5.5V) DC and AC Electrical Characteristics
Symbol
Max.
Units
ICCA
Operating Current
Parameter
Part Number
CS = VIH, SK = 1MHz
Conditions
1
mA
ICCS
Standby Current
CS = VIL
50
µA
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
(Note 2)
±1
µA
VIL
VIH
Input Low Voltage
Input High Voltage
0.8
VCC +1
V
0.4
V
V
0.2
V
V
1
MHz
-0.1
2
VOL1
VOH1
Output Low Voltage
Output High Voltage
IOL = 2.1mA
IOH = -400 µA
2.4
VOL2
VOH2
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
VCC -0.2
fSK
SK Clock Frequency
(Note 3)
tSKH
SK High Time
tSKL
SK Low Time
tSKS
SK Setup Time
tCS
Minimum CS
Low Time
tCSS
CS Setup Time
50
ns
tDH
DO Hold Time
70
ns
tDIS
DI Setup Time
100
200
ns
tCSH
CS Hold Time
0
ns
tDIH
DI Hold Time
20
ns
tPD
Output Delay
500
ns
tSV
CS to Status Valid
500
ns
tDF
CS to DO in Hi-Z
tWP
Write Cycle Time
FM93C46
FM93C46E/V
0
250
300
ns
250
ns
SK must be at VIL for
tSKS before CS goes
high
50
ns
(Note 4)
250
ns
FM93C46
FM93C46E/V
CS = VIL
3
FM93C46
Min.
100
ns
10
ms
www.fairchildsemi.com
FM93C46 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Absolute Maximum Ratings (Note 1)
Operating Range
Ambient Storage Temperature
Ambient Operating Temperature
FM93C46L/LZ
FM93C46LE/LZE
FM93C46LV/LZV
–65°C to +150°C
All Input or Output Voltage
with Respect to Ground
+6.5V to -0.3V
Lead Temperature (Soldering, 10 sec.)
+300°C
ESD Rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
2000V
2.7V to 4.5V
DC and AC Electrical Characteristics VCC = 2.7V to 4.5V unless otherwise specified
Symbol
Parameter
Part Number
Conditions
Min.
Max.
Units
1
mA
10
1
µA
µA
±1
µA
0.15 VCC
VCC +1
V
0.1 VCC
V
V
250
KHz
ICCA
Operating Current
CS = VIH, SK = 250KHz
ICCS
Standby Current
L
LZ
CS = VIL
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
(Note 2)
VIL
VIH
Input Low Voltage
Input High Voltage
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
fSK
SK Clock Frequency
(Note 3)
tSKH
SK High Time
1
µs
tSKL
SK Low Time
1
µs
tSKS
SK Setup Time
SK must be at VIL for
tSKS before CS goes
high
0.2
µs
tCS
Minimum CS
Low Time
(Note 4)
1
µs
tCSS
CS Setup Time
0.2
µs
tDH
DO Hold Time
70
ns
tDIS
DI Setup Time
0.4
µs
tCSH
CS Hold Time
0
ns
tDIH
DI Hold Time
0.4
µs
tPD
Output Delay
2
µs
tSV
CS to Status Valid
1
µs
tDF
CS to DO in Hi-Z
tWP
Write Cycle Time
-0.1
0.8 VCC
Test
0
CS = VIL
Typ
Max
Units
COUT
Output Capacitance
5
pF
CIN
Input Capacitance
5
pF
0.4
µs
15
ms
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Capacitance TA = 25°C, f = 1 MHz (Note 5)
Symbol
0.9 VCC
Note 2:
Typical leakage values are in the 20nA range.
Note 3: The shortest allowable SK clock period = 1/fSK (as shown under the fSK parameter).
Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC
parameters stated in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed.
Therefore, it is not allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all
internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in the
opcode diagram on the following page.)
Note 5:
This parameter is periodically sampled and not 100% tested.
AC Test Conditions
VCC Range
VIL/VIH
Input Levels
VIL/VIH
Timing Level
VOL/VOH
Timing Level
IOL/IOH
2.7V ≤ VCC ≤ 5.5V
.03V/1.8V
1.0V
0.8V/1.5V
±10µA
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(Extended Voltage Levels)
4.5V ≤ VCC ≤ 5.5V
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
FM93C46
www.fairchildsemi.com
FM93C46 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Absolute Maximum Ratings (Note 1)
Write (WRITE):
The FM93C46 device has 7 instructions as described below. Note
that the MSB of any instruction is a “1” and is viewed as a start bit
in the interface sequence. The next 8 bits carry the op code and
the 6-bit address for register selection.
The WRITE instruction is followed by the address and 16 bits of data
to be written into the specified address. After the last bit of data is
put in the data-in (DI) pin, CS must be brought low before the next
rising edge of the SK clock. This falling edge of the CS initiates the
self-timed programming cycle. The D0 pin indicates the READY/
BUSY status of the chip if CS is brought high after a minimum of tCS.
D0 = logical 1 indicates that the register at the address specified in
the instruction has been written with the data pattern specified in the
instruction and the part is ready for another instruction.
Read (READ):
The READ instruction outputs serial data on the D0 pin. After a
READ instruction is received, the instruction and address are
decoded, followed by data transfer from the selected memory
register into a 16-bit serial-out shift register. A dummy bit (logical
0) precedes the 16-bit data output string. Output data changes are
initiated by a low to high transition of the SK clock.
Erase All (ERAL):
The ERAL instruction will simultaneously program all registers in
the memory array and set each bit to the logical “1” state. The Erase
All cycle is identical to the ERASE cycle except for the different opcode. As in the ERASE mode, the DO pin indicates the READY/
BUSY status of the chip if CS is brought high after the t CS interval.
Write Enable (WEN):
When VCC is applied to the part, it 'powers-up' in the Write Disable
(WDS) state. Therefore, all programming modes must be preceded by a Write Enable (WEN) instruction. Once a Write Enable
instruction is executed, programming remains enabled until aWrite
Disable (WDS) instruction is executed or VCC is removed from the
part.
Write All (WRALL):
The WRALL instruction will simultaneously program all registers
with the data pattern specified in the instruction. As in the WRITE
mode, the DO pin indicates the READY/BUSY status of the chip
if CS is brought high after the tCS interval.
Erase (ERASE):
The ERASE instruction will program all bits in the specified
register to the logical “1” state. CS is brought low following the
loading of the last address bit. This falling edge of the CS pin
initiates the self-timed programming cycle.
Write Disable (WDS):
To protect against accidental data disturb, the WDS instruction
disables all programming modes and should follow all programming operations. Execution of a READ instruction is independent
of both the WEN and WDS instructions.
The DO pin indicates the READY/BUSY status of the chip if CS is
brought high after a minimum time of tCS. DO = logical “0” indicates
that the register, at the address specified in the instruction, has
been erased, and the part is ready for another instruction.
Note: The Fairchild CMOS EEPROMs do not require an "ERASE" or "ERASE ALL"
operation prior to the "WRITE" and "WRITE ALL" instructions. The "ERASE" and "ERASE
ALL" instructions are included to maintain compatibility with earlier technology EEPROMs.
Instruction Set for the FM93C46
Instruction
SB
Op. Code
Address
READ
1
10
A5-A0
WEN
1
00
11xxxx
Write enable must precede all programming modes.
ERASE
1
11
A5-A0
Erase selected register.
WRITE
1
01
A5-A0
ERAL
1
00
10xxxx
WRALL
1
00
01xxxx
WDS
1
00
00xxxx
Data
Comments
Reads data stored in memory, at specified address.
D15-D0
Writes selected register.
Erases all registers.
D15-D0
Writes all registers.
Disables all programming instructions.
x = Don't care.
5
FM93C46
www.fairchildsemi.com
FM93C46 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Functional Description
CS
SK
DI
Synchronous Data Timing
VIH
VIL
tCSS
tSKH
tSKS
VIH
VIL
tDIS
VIH
tSKL
tDIH
VIL
tPD
VOH
DO (READ)
VOL
tSV
VOH
DO (PROGRAM)
VOL
tCSH
tDF
tDH
tDH
tDF
STATUS VALID
DS800025-4
READ
CS
tCS
SK
DI
1
1
0
...
A5
A0
DO
0
...
D15
D0
DS800025-5
WEN
WEN
CS
tCS
SK
DI
1
0
0
1
1
...
X
X
DS800025-6
WDS
WDS
CS
tCS
SK
DI
1
0
0
0
0
...
X
X
DS800025-7
6
FM93C46
www.fairchildsemi.com
FM93C46 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Timing Diagrams
WRITE
WRITE
CS
tCS
SK
1
DI
0
1
A5
A0
D15
...
D0
DO
BUSY
READY
tWP
DS800025-8
WRALL
WRALL
CS
tCS
SK
1
DI
0
0
0
1
DON'T CARE (4 BITS)
D15
...
D0
DO
BUSY
READY
tWP
DS800025-9
ERASE
ERASE
tCS
CS
STANDBY
SK
DI
DO
1
1
1
A5
A4
A3
...
A0
HI-Z
BUSY
READY
HI-Z
tWP
DS800025-10
ERAL
ERAL
tCS
CS
STANDBY
SK
DI
1
DO
0
0
1
0
DON'T CARE BITS (4 BITS)
HI-Z
BUSY
READY
HI-Z
tWP
DS800025-11
7
FM93C46
www.fairchildsemi.com
FM93C46 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Timing Diagrams (Continued)
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
8° Max, Typ.
All leads
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.04
(0.102)
All lead tips
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.014 - 0.020 Typ.
(0.356 - 0.508)
0.050
(1.270)
Typ
Molded Small Out-Line Package (M8)
Package Number M08A
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0098
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
8
FM93C46
www.fairchildsemi.com
FM93C46 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
(6.35 ± 0.127)
+
Pin #1 IDENT
0.032 ± 0.005
(0.813 ± 0.127)
RAD
5
1
1
0.300 - 0.320
(7.62 - 8.128)
7
Pin #1
IDENT
Option 1
0.280 MIN
(7.112)
8
2
3
0.040 Typ.
(1.016)
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
Français
Tel:
+33 (0) 1-6930-3696
Italiano
Tel:
+39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
9
FM93C46
www.fairchildsemi.com
FM93C46 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Physical Dimensions inches (millimeters) unless otherwise noted
FM93C46A
1K-Bit Serial CMOS EEPROM
(MICROWIRE™ Synchronous Bus)
General Description
Features
The FM93C46A is 1024 bits of CMOS nonvolatile EEPROM
(Electrically Erasable Programmable Read Only Memory) with
MICROWIRE serial interface. FM93C46A can be configured for
either 64 x 16 bit or 128 x 8 bit array using an organization (ORG)
input pin. This device is fabricated using Fairchild Semiconductor's
floating gate CMOS process for high reliability, high endurance
and low power consumption. This device is available in 8-pin DIP,
SO and TSSOP packages.
■ 2.7V to 5.5V operation in all modes
■ Typical active current 200µA
10 µA standby current typical
1 µA standby current typical (L)
0.1 µA standby current typical (LZ)
■ Self-timed programming cycle
■ Device status indication during programming mode
■ No erase required before write
The MICROWIRE serial interface offered by this EEPROM enables simple interface to a wide variety of microcontrollers and
microprocessors. There are 7 instructions that operate the
FM93C46A: Read, Erase/Write Enable, Erase, Write, Erase/
Write Disable, Write All and Erase All.
■ Reliable CMOS floating gate technology
■ MICROWIRE compatible serial I/O
■ 40 years data retention
■ Endurance: 1,000,000 data changes
■ Packages available: 8-pin TSSOP, 8-pin SO, 8-pin DIP
■ Schmitt Trigger inputs and VCC lockout to prevent data
corruption
Block Diagram
CS
VCC
Instruction
Decoder
Control Logic,
And Clock
Generators
SK
Instruction
Register
DI
ORG
Address
Register
VPP
High Voltage
Generator
And
Program
Timer
EEPROM Array
1024 Bits
(64x16) or (128x8)
Decoder
1 of 64
(or 128)
Read/Write Amps
Data In/Out Register
16 (or 8) Bits
GND
Data Out Buffer
DO
© 1999 Fairchild Semiconductor Corporation
FM93C46A Rev. A
DS800028-1
1
www.fairchildsemi.com
FM93C46A 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
January 2000
Dual-In-Line Package (N),
8-Pin SO Package (M8)
and 8-Pin TSSOP Package (MT8)
NC
1
8
ORG
VCC
2
FM93C46A 7
VSS
ORG
CS
3
6
DO
VSS
SK
4
5
DI
CS
1
SK
2 FM93C46A 7
NC
DI
3
6
DO
4
5
8
Rotated Die
(93C46AT)
VCC
DS800028-2
Top View
See Package Number N08E, M08A and MTC08
Pin Names
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
VSS
Ground
ORG
Memory Organizational Select
NC
No Connect
VCC
Positive Power Supply
Ordering Information
FM
93
C
XX
A
T
LZ
E
XX
Letter Description
Package
N
M8
MT8
8-Pin DIP
8-Pin SO8
8-Pin TSSOP
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
Blank
T
Normal Pin Out
Rotated Die Pin Out
A
x8 or x16 Configuration
Density
Interface
2
FM93C46A Rev. A
46
1K
C
CS
CMOS
Data protect and sequential
read
93
MICROWIRE
FM
Fairchild Non-Volatile
Memory
www.fairchildsemi.com
FM93C46A 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Connection Diagrams
Ambient Storage Temperature
Operating Range
-65°C to +150°C
All Input or Output Voltages:
with Respect to Ground
VCC +1 to -0.3V
Lead Temperature
(Soldering, 10 Seconds)
+300°C
EDS Rating
Ambient Operating Temperature
FM93C46A
FM93C46AE
FM93C46AV
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
2000V
4.5V to 5.5V
Standard VCC (4.5V to 5.5V) DC and AC Electrical Characteristics
Symbol
Parameter
Part Number
Conditions
Min
Max
Units
ICCA
Operating Current
CS = VIH ,SK=1 MHz
1
mA
ICCS
Standby Current
CS = 0V, ORG = VCC or NC
50
µA
IIL
Input Leakage
VIN = 0V to VCC (Note 2)
-1
1
µA
IILO
Input Leakage
ORG Pin
ORG tied to VCC
ORG tied to VSS (Note 3)
-1
-2.5
1
2.5
µA
IOL
Output Leakage
VIN = 0V to VCC
-1
1
µA
VIL
Input Low Voltage
-0.1
0.8
V
VIH
Input High Voltage
2
VCC +1
V
0.4
V
VOL1
Output Low Voltage
IOL = 2.1 mA
VOH1
Output High Voltage
IOH = -400 µA
VOL2
Output Low Voltage
IOL = 10 µA
VOH2
Output High Voltage
IOL = -10 µA
fSK
SK Clock Frequency
(Note 4)
tSKH
SK High Time
tSKL
SK Low Time
tSKS
SK Setup Time
tCS
Minimum CS
tCSS
FM93C46A
FM93C46AE/V
2.4
V
0.2
V
VCC - 0.2
0
V
1
MHz
250
300
ns
250
ns
50
ns
250
ns
CS Setup Time
50
ns
tDH
DO Hold Time
70
ns
tDIS
DI Setup Time
100
200
ns
tCSH
CS Hold Time
0
ns
tDIH
DI Hold Time
20
ns
tPD
Output Delay
500
ns
tSV
CS to Status Valid
500
ns
tDF
CS to DO in Hi-Z
100
ns
tWP
Write Cycle Time
10
ms
SK must be at VIL for
tSKS before CS goes
high
(Note 5)
FM93C46A
FM93C46AE/V
CS = VIL
3
FM93C46A Rev. A
www.fairchildsemi.com
FM93C46A 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Absolute Maximum Ratings (Note 1)
Operating Range
Ambient Storage Temperature
Ambient Operating Temperature
FM93C46AL/LZ
FM93C46ALE/LZE
FM93C46A LV/LZV
–65°C to +150°C
All Input or Output Voltage
with Respect to Ground
+6.5V to -0.3V
Lead Temperature (Soldering, 10 sec.)
+300°C
ESD Rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
2000V
2.7V to 5.5V
DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified
Symbol
Parameter
Part Number
Conditions
Min.
Max.
Units
1
mA
10
1
µA
µA
±1
1
2.5
µA
µA
±1
µA
0.15 VCC
VCC +1
V
0.1 VCC
V
V
250
KHz
ICCA
Operating Current
CS = VIH, SK = 250KHz
ICCS
Standby Current
L
LZ
CS = VIL
IIL
IILO
Input Leakage
Input Leakage
ORG Pin
VIN = 0V to VCC (Note 2)
ORG tied to VCC
ORG tied to VSS (Note 3)
IOL
Output Leakage
VIN = 0V to VCC
VIL
VIH
Input Low Voltage
Input High Voltage
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
fSK
SK Clock Frequency
(Note 4)
tSKH
SK High Time
1
µs
tSKL
SK Low Time
1
µs
tSKS
SK Setup Time
SK must be at VIL for
tSKS before CS goes high
0.2
µs
tCS
Minimum CS
Low Time
(Note 5)
1
µs
tCSS
CS Setup Time
0.2
µs
tDH
DO Hold Time
70
ns
µs
-1
-2.5
-0.1
0.8 VCC
0.9 VCC
0
tDIS
DI Setup Time
0.4
tCSH
CS Hold Time
0
ns
tDIH
DI Hold Time
0.4
µs
tPD
Output Delay
2
µs
tSV
CS to Status Valid
1
µs
tDF
CS to DO in Hi-Z
0.4
µs
tWP
Write Cycle Time
15
ms
CS = VIL
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Capacitance TA = 25°C, f = 1 MHz
Symbol
Test
Typ
Max
Units
COUT
Output Capacitance
5
pF
CIN
Input Capacitance
5
pF
Note 2:
Typical leakage values are in the 20 nA range.
Note 3:
The ORG pin may draw > 1 µA when in the x8 mode ude to an internal pull-up transistor.
Note 4: The shortest allowable SK clock period = 1/fSK (as shown under the fSK fSK parameter).
Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC
parameters stated in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed.
Therefore, it is not allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 5: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all
internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in
the opcode diagrams in the following pages.)
AC Test Conditions
VCC Range
VIL/VIH
Input Levels
VIL/VIH
Timing Level
VOL/VOH
Timing Level
IOL/IOH
2.7V ≤ VCC ≤ 5.5V
.03V/1.8V
1.0V
0.8V/1.5V
±10µA
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(Extended Voltage Levels)
4.5V ≤ VCC ≤ 5.5V
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
FM93C46A Rev. A
www.fairchildsemi.com
FM93C46A 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Absolute Maximum Ratings (Note 1)
Serial Clock (SK):
Chip Select (CS):
This pin is the clock input (rising edge active) for clocking in all
opcodes and data on the DI pin and clocking out all data on the DO
pin. However, this pin has no effect on the asynchronous programming cycle (see the CS pin section) as the BUSY/READY status
is a function of the CS pin only.
This pin enables and disables the MICROWIRE device and
performs 3 general functions:
1. When in the low state, the MICROWIRE device is disabled
and the output tri-stated (high impedance). If this pin is
brought high (rising edge active), all internal registers are
reset and the device is enabled, allowing MICROWIRE
communication via DI/DO pins. To restate, the CS pin must
be held high during all device communication and opcode
functions. If the CS pin is brought low, all functions will be
disabled and reset when CS is brought high again. The
exception to this is when a programming cycle is initiated
(see 2 and 3). Again, all activity on the CS, DI and DO pins
is ignored until CS is brought high.
Data-In (DI):
All serial communication into the device is performed using this
input pin (rising edge active). In order to avoid false Start Bits, or
related issues, it is advised to keep the DI pin in the low state
unless actually clocking in data bits (Start Bit, Opcode, Address or
incoming data bits to be programmed). Please note that the first
'1' clocked into the device (after CS is brought high) is seen as a
Start Bit and the beginning of a serial command string, so caution
must be observed when bringing CS high.
2. After entering all required opcode and address data, bringing
CS low initiates the (asynchronous) programming cycle.
Data-Out (DO):
All serial communication out of the device, Read Data ( during
normal reads) as well as READY/BUSY status indication ( during
programming ) are performed using this output pin. Note that,
during READ operations, the EEPROM device starts to drive the
DO output pin "active" after the last address bit (A0) is clocked in.
Hence in applications where 3-wire configuration is required (
where DI and DO pins are tied together ) caution must be observed
for correct operation. Please refer AN-758 for further information.
3. When programming is in progress, the Data-Out pin will
display the programming status as either BUSY (DO low) or
READY (DO high) when CS is brought high. (Again, the
output will be tri-stated when CS is low.) To restate, during
programming, the CS pin may be brought high and low any
number of times to view the programming status without
affect the programming operation. Once programming is
completed (Output in READY state), the output is 'cleared'
(returned to normal tri-state condition) by clocking in a Start
Bit. After the Start Bit is clocked in, the output will return to a
tri-stated condition. When clocked in, this Start Bit can be the
first bit in a command string, or CS can be brought low again
to reset all internal circuits.
Organization (ORG):
This pin controls the device architecture (8-bit data word vs. 16-bit
data word). If the ORG pin is brought to VCC, the device is
configured with a 16-bit data word and if the ORG pin is brought
to VSS (Ground), the device is configured with an 8-bit data word.
If the ORG pin is left floating, the device will default to a 16-bit data
word.
Instruction Set for the FM93C46A
ORG
5
FM93C46A Rev. A
Memory
Pin
Logic
Configuration
# of Address Bits
0
128 x 8
7 Bits
1
64 x 16
6 Bits
www.fairchildsemi.com
FM93C46A 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
MICROWIRE I/O Pin Description
Instruction
SB
OP-Code
2 Bits
Address
6 Bits
Data
16 Bits
Comments
READ
1
10
A5–A0
EWEN
1
00
11XXXX
Enables programming modes.
Read data stored in selected registers.
EWDS
1
00
00XXXX
Disables all programming modes.
ERASE
1
11
A5–A0
WRITE
1
01
A5–A0
ERAL
1
00
10XXXX
WRAL
1
00
01XXXX
Erases selected register.
D15–D0
Writes data pattern D15–D0 into selected register.
Erases all registers.
D15–D0
Writes data pattern D15–D0 into all registers.
X = Don't care.
128 by 8-Bit Organization (FM93C46A when ORG = GND)
Instruction
SB
OP-Code
2 Bits
Address
7 Bits
READ
1
10
A6–A0
EWEN
1
00
11XXXXX
Enables programming modes.
EWDS
1
00
00XXXXX
Disables all programming modes.
ERASE
1
11
A6–A0
WRITE
1
01
A6–A0
ERAL
1
00
10XXXXX
WRAL
1
00
01XXXXX
Data
8 Bits
Comments
Read data stored in selected registers.
Erases selected register.
D7–D0
Writes data pattern D7–D0 into selected register.
Erases all registers.
D7–D0
Writes data pattern D7–D0 into all registers.
X = Don't care.
Functional Description
Programming:
Read (READ):
1. Programming is initiated by clocking in the Start Bit, Opcode
bits, Address bits and the 8/16 data bits (refer to the ORG
pin section).
The READ instruction outputs serial data on the DO pin. After a
READ instruction is received, the instruction and address are
decoded, followed by data transfer from the selected memory
register into a serial-out shift register. A dummy bit (logical 0)
precedes the serial data output string. Output data changes are
initiated by a low to high transition of SK after the last address bit
(A0) is clocked in.
2. Programming is started by bringing the CS pin low. Once the
programming cycle is started, it cannot be stopped. (Bringing
VCC low will stop any programming, but will also result in
data corruption.)
3. The status of the programming cycle (BUSY or READY) is
observed by bringing the CS pin high and observing the
output state. If the output is LOW, the device is still programming (BUSY). If the output is HIGH, the programming cycle
has been completed and the device is ready for the next
operation. Note that the output will be tri-stated each time
CS is brought low and the READY/BUSY status will be
shown each time CS is brought high.
Erase/Write Enable (EWEN):
When VCC is applied to the part, it “powers up” in the Erase/Write
Disable (EWDS) state. Therefore, all programming modes must
be preceded by an Erase/Write Enable (EWEN) instruction. Once
an Erase/Write Enable instruction is executed, programming
remains enabled until an Erase/Write Disable (EWDS) instruction
is executed or VCC is removed from the part.
4. After programming, the READY state (output HIGH) can be
reset and the output tri-stated by clocking in a single Start
Bit. This Start Bit can be the first bit in a command string, or
CS can be brought low again to reset all internal circuits. In
any case, clocking in a '1' bit will tri-state the output.
6
FM93C46A Rev. A
www.fairchildsemi.com
FM93C46A 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
64 by 16-Bit Organization (FM93C46A when ORG = VCC or NC)
Write (WRITE):
Erase/Write Disable (EWDS):
The WRITE instruction is followed by 16 bits of data (or 8 bits of
data when using the FM93C46A in the x8 organization) to be
written into the specified address. Please refer to the Programming section for details.
To protect against accidental data overwrites, the Erase/Write
Disable (EWDS) instruction disables all programming modes and
should follow all programming operations. Execution of a READ
instruction is independent of both the EVEN and EWDS instructions.
Erase All (ERAL):
The ERAL instruction will simultaneously program all registers in
the memory array to the logical “1” state.
Erase (ERASE):
Write All (WRAL):
The ERASE instruction will program all bits in the specified
register to the logical “1” state. Please refer to the Programming
section for details.
The WRAL instruction will simultaneously program all registers
with the data pattern specified in the instruction.
Timing Diagrams for the FM93C46A
Synchronous Data Timing
CS
SK
DI
VIH
VIL
VIH
VIL
VIH
tCSS
tSKS
tDIS
tSKH
VOH
DO (PROGRAM)
VOL
tPD
tSV
tDH
tDH
tDF
tDF
STATUS VALID
DS800028-4
7
FM93C46A Rev. A
tCSH
tDIH
VIL
VOH
DO (READ)
VOL
tSKL
www.fairchildsemi.com
FM93C46A 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Functional Description (Continued)
ORG Pin
Organization
AN
DN
VCC or NC
64 x 16
A5
D15
VSS
128 x 8
A6
D7
READ
CS
tCS
SK
1
DI
1
...
AN
0
A0
DO
0
...
DN
D0
DS800028-5
EWEN
DO = HI-Z
tCS
CS
SK
1
DI
0
0
1
1
X
...
X
ORG = VCC, 4 X'S
ORG = VSS, 5 X'S
DS800028-6
EWDS
DO = HI-Z
tCS
CS
SK
1
DI
0
0
0
0
X
...
X
ORG = VCC, 4 X'S
ORG = VSS, 5 X'S
DS800028-7
ERASE
tCS
CS
Standby
SK
DI
DO
1
1
1
...
AN
A0
Busy
HI-Z
tWP
8
FM93C46A Rev. A
Ready
HI-Z
DS800028-8
www.fairchildsemi.com
FM93C46A 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Timing Diagrams for the FM93C46A (Continued)
Key for Timing Diagrams
Organization of Address and Data Fields for FM93C46A
WRITE
tCS
CS
SK
1
DI
1
0
AN . . .
A0
DN . . .
D0
Busy
DO
Ready
tWP
DS800028-9
ERAL
tCS
CS
STANDBY
SK
1
DI
0
0
1
0
...
X
X
ORG = VCC, 4 X's
ORG = VSS, 5 X's
DO
BUSY
READY
READY STATUS SIGNAL RESETS
TO HI-Z AFTER CLOCKING IN
ONE SK CYCLE WITH DI = 1
tWP
DS800028-10
WRAL
tCS
CS
STANDBY
SK
DI
1
0
0
0
1
X
...
X
DN . . . D0
ORG = VCC, 4 X's
ORG = VSS, 5 X's
DO
BUSY
tWP
READY
READY STATUS SIGNAL RESETS
TO HI-Z AFTER CLOCKING IN
ONE SK CYCLE WITH DI = 1
DS800028-11
9
FM93C46A Rev. A
www.fairchildsemi.com
FM93C46A 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Timing Diagrams for the FM93C46A (Continued)
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
8° Max, Typ.
All leads
0.04
(0.102)
All lead tips
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020 Typ.
(0.356 - 0.508)
Molded Small Outline Package (M8)
Package Number M08A
10
FM93C46A Rev. A
www.fairchildsemi.com
FM93C46A 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0098
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
11
FM93C46A Rev. A
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FM93C46A 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
(6.35 ± 0.127)
+
Pin #1 IDENT
0.032 ± 0.005
(0.813 ± 0.127)
RAD
5
1
1
2
3
0.040 Typ.
(1.016)
0.300 - 0.320
(7.62 - 8.128)
7
Pin #1
IDENT
Option 1
0.280 MIN
(7.112)
8
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
Français
Tel:
+33 (0) 1-6930-3696
Italiano
Tel:
+39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
12
FM93C46A Rev. A
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
www.fairchildsemi.com
FM93C46A 1K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Physical Dimensions inches (millimeters) unless otherwise noted
FM93C56
2K-Bit Serial CMOS EEPROM
(MICROWIRE™ Bus Interface)
General Description
Features
The FM93C56 device is 2048 bits of CMOS non-volatile electrically erasable memory organized as 128x16 bit array. They are
fabricated using Fairchild Semiconductor's floating-gate CMOS
process for high reliability, high endurance and low power consumption. These memory devices are available in an 8-pin SOIC
or 8-pin TSSOP package for small space considerations.
■ Device status during programming mode
FM93C56 is compatible with MICROWIRE serial interface, which
offers simple interface to standard microcontrollers and microprocessors. There are 7 instructions which control this device: Read,
Write Enable, Erase, Erase All, Write, Write All, and Write Disable.
The ready/busy status is available on the DO pin to indicate the
completion of a programming cycle.
■ Reliable CMOS floating gate technology
■ Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
■ No erase required before write
■ 2.7V to 5.5V operation in all modes
■ MICROWIRE compatible serial l/O
■ Self-timed programming cycle
■ 40 years data retention
■ Endurance: 1,000,000 data changes
■ Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
■ Schmitt Trigger inputs and VCC lockout to prevent data
corruption
Block Diagram
VCC
CS
INSTRUCTION
DECODER
CONTROL LOGIC,
AND CLOCK
GENERATORS
SK
DI
INSTRUCTION
REGISTER
ADDRESS
REGISTER
VPP
DECODER
1 OF 128
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
EEPROM ARRAY
16
READ/WRITE AMPS
16
VSS
DATA IN/OUT REGISTER
16 BITS
DO
© 1999 Fairchild Semiconductor Corporation
FM93C56
DATA OUT BUFFER
1
DS800026-1
www.fairchildsemi.com
FM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
December 1999
Dual-In-Line Package (N),
8-Pin SO (M8) and 8-Pin TSSOP (MT8)
CS
1
8
VCC
SK
2
7
DI
3
DO
4
Rotated Die (93C56T)
NC
1
8
NC
NC
VCC
2
7
GND
6
NC
CS
3
6
DO
5
GND
SK
4
5
DI
DS800026-2
DS800026-12
Top View
See Package Number
N08E, M08A and MTC08
Pin Names
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
VCC
Power Supply
Ordering Information
FM
93
C
XX
T
LZ
E
XX
Letter
Description
N
M8
MT8
8-Pin DIP
8-Pin SO8
8-Pin TSSOP
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
Blank
T
Normal Pin Out
Rotated Die Pin Out
Package
Density
Interface
2
FM93C56
56
2K
C
CS
CMOS
Data protect and sequential
read
93
MICROWIRE
FM
Fairchild Non-Volatile
Memory
www.fairchildsemi.com
FM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Connection Diagrams
Operating Range
Ambient Storage Temperature
Ambient Operating Temperature
FM93C56
FM93C56E
FM93C56V
All Input or Output Voltage
with Respect to Ground
Lead Temperature (Soldering, 10 sec.)
ESD Rating
–65°C to +150°C
+6.5V to -0.3V
+300°C
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
4.5V to 5.5V
2000V
DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V
Symbol
Max.
Units
ICCA
Operating Current
Parameter
Part Number
CS = VIH, SK = 1MHz
Conditions
1
mA
ICCS
Standby Current
CS = VIL
50
µA
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
(Note 2)
±1
µA
VIL
VIH
Input Low Voltage
Input High Voltage
0.8
VCC +1
V
0.4
V
V
0.2
V
V
1
MHz
-0.1
2
VOL1
VOH1
Output Low Voltage
Output High Voltage
IOL = 2.1mA
IOH = -400 µA
2.4
VOL2
VOH2
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
VCC -0.2
fSK
SK Clock Frequency
(Note 3)
tSKH
SK High Time
tSKL
SK Low Time
tSKS
SK Setup Time
tCS
Minimum CS
Low Time
tCSS
CS Setup Time
50
ns
tDH
DO Hold Time
70
ns
tDIS
DI Setup Time
100
200
ns
tCSH
CS Hold Time
0
ns
tDIH
DI Hold Time
20
ns
tPD
Output Delay
500
ns
tSV
CS to Status Valid
500
ns
tDF
CS to DO in Hi-Z
tWP
Write Cycle Time
FM93C56
FM93C56E/V
0
250
300
ns
250
ns
SK must be at VIL for
tSKS before CS goes
high
50
ns
(Note 4)
250
ns
FM93C56
FM93C56E/V
CS = VIL
3
FM93C56
Min.
100
ns
10
ms
www.fairchildsemi.com
FM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Absolute Maximum Ratings (Note 1)
Operating Range
Ambient Storage Temperature
Ambient Operating Temperature
FM93C56L/LZ
FM93C56LE/LZE
FM93C56LV/LZV
–65°C to +150°C
All Input or Output Voltage
with Respect to Ground
+6.5V to -0.3V
Lead Temperature (Soldering, 10 sec.)
+300°C
ESD Rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
2000V
2.7V to 5.5V
DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified
Symbol
Parameter
Part Number
Conditions
Min.
Max.
Units
1
mA
10
1
µA
µA
±1
µA
0.15 VCC
VCC +1
V
0.1 VCC
V
V
250
KHz
ICCA
Operating Current
CS = VIH, SK = 250KHz
ICCS
Standby Current
L
LZ
CS = VIL
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
(Note 2)
VIL
VIH
Input Low Voltage
Input High Voltage
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
fSK
SK Clock Frequency
(Note 3)
tSKH
SK High Time
1
tSKL
SK Low Time
1
µs
tSKS
SK Setup Time
SK must be at VIL for
tSKS before CS goes
high
0.2
µs
tCS
Minimum CS
Low Time
(Note 4)
1
µs
tCSS
CS Setup Time
0.2
µs
tDH
DO Hold Time
70
ns
tDIS
DI Setup Time
0.4
µs
tCSH
CS Hold Time
0
ns
tDIH
DI Hold Time
0.4
µs
tPD
Output Delay
2
µs
tSV
CS to Status Valid
1
µs
tDF
CS to DO in Hi-Z
tWP
Write Cycle Time
-0.1
0.8 VCC
Test
0
CS = VIL
Typ
Max
Units
COUT
Output Capacitance
5
pF
CIN
Input Capacitance
5
pF
µs
0.4
µs
15
ms
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Capacitance TA = 25°C, f = 1 MHz (Note 5)
Symbol
0.9 VCC
Note 2:
Typical leakage values are in the 20nA range.
Note 3: The shortest allowable SK clock period = 1/fSK (as shown under the fSK parameter).
Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC
parameters stated in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed.
Therefore, it is not allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all
internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in the
opcode diagram on the following page.)
Note 5:
This parameter is periodically sampled and not 100% tested.
AC Test Conditions
VCC Range
VIL/VIH
Input Levels
VIL/VIH
Timing Level
VOL/VOH
Timing Level
IOL/IOH
2.7V ≤ VCC ≤ 5.5V
.03V/1.8V
1.0V
0.8V/1.5V
±10µA
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(Extended Voltage Levels)
4.5V ≤ VCC ≤ 5.5V
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
FM93C56
www.fairchildsemi.com
FM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Absolute Maximum Ratings (Note 1)
Write (WRITE):
The FM93C56 device has 7 instructions as described below. Note
that the MSB of any instruction is a “1” and is viewed as a start bit
in the interface sequence. The next 10 bits carry the op code and
the 8-bit address for register selection.
The WRITE instruction is followed by the address and 16 bits of data
to be written into the specified address. After the last bit of data is
put in the data-in (DI) pin, CS must be brought low before the next
rising edge of the SK clock. This falling edge of the CS initiates the
self-timed programming cycle. The D0 pin indicates the READY/
BUSY status of the chip if CS is brought high after a minimum of tCS.
D0 = logical 1 indicates that the register at the address specified in
the instruction has been written with the data pattern specified in the
instruction and the part is ready for another instruction.
Read (READ):
The READ instruction outputs serial data on the D0 pin. After a
READ instruction is received, the instruction and address are
decoded, followed by data transfer from the selected memory
register into a 16-bit serial-out shift register. A dummy bit (logical
0) precedes the 16-bit data output string. Output data changes are
initiated by a low to high transition of the SK clock.
Erase All (ERAL):
The ERAL instruction will simultaneously program all registers in
the memory array and set each bit to the logical “1” state. The Erase
All cycle is identical to the ERASE cycle except for the different opcode. As in the ERASE mode, the DO pin indicates the READY/
BUSY status of the chip if CS is brought high after the t CS interval.
Write Enable (WEN):
When VCC is applied to the part, it 'powers-up' in the Write Disable
(WDS) state. Therefore, all programming modes must be preceded by a Write Enable (WEN) instruction. Once a Write Enable
instruction is executed, programming remains enabled until aWrite
Disable (WDS) instruction is executed or VCC is removed from the
part.
Write All (WRALL):
The WRALL instruction will simultaneously program all registers
with the data pattern specified in the instruction. As in the WRITE
mode, the DO pin indicates the READY/BUSY status of the chip
if CS is brought high after the tCS interval.
Erase (ERASE):
The ERASE instruction will program all bits in the specified
register to the logical “1” state. CS is brought low following the
loading of the last address bit. This falling edge of the CS pin
initiates the self-timed programming cycle.
Write Disable (WDS):
To protect against accidental data disturb, the WDS instruction
disables all programming modes and should follow all programming operations. Execution of a READ instruction is independent
of both the WEN and WDS instructions.
The DO pin indicates the READY/BUSY status of the chip if CS is
brought high after a minimum time of tCS. DO = logical “0” indicates
that the register, at the address specified in the instruction, has
been erased, and the part is ready for another instruction.
Note: The Fairchild CMOS EEPROMs do not require an "ERASE" or "ERASE ALL"
operation prior to the "WRITE" and "WRITE ALL" instructions. The "ERASE" and "ERASE
ALL" instructions are included to maintain compatibility with earlier technology EEPROMs.
Instruction Set for the FM93C56
Instruction
SB
Op. Code
Address
READ
1
10
A7-A0
WEN
1
00
11xxxxxx
ERASE
1
11
A7-A0
WRITE
1
01
A7-A0
ERAL
1
00
10xxxxxx
WRALL
1
00
01xxxxxx
WDS
1
00
00xxxxxx
Note:
A7 is "don't care" bit, but must be included in the address string.
Note:
x = Don't care.
Data
Comments
Reads data stored in memory, at specified address.
Write enable must precede all programming modes.
Erase selected register.
D15-D0
Erases all registers.
D15-D0
Writes all registers.
Disables all programming instructions.
5
FM93C56
Writes selected register.
www.fairchildsemi.com
FM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Functional Description
CS
SK
DI
Synchronous Data Timing
VIH
VIL
tCSS
tSKH
tSKS
VIH
VIL
tDIS
VIH
tSKL
tDIH
VIL
tPD
VOH
DO (READ)
VOL
tSV
VOH
DO (PROGRAM)
VOL
tCSH
tDF
tDH
tDH
tDF
STATUS VALID
DS800026-4
READ
CS
tCS
SK
DI
1
1
0
...
A7
A0
DO
0
...
D15
D0
DS800026-5
WEN
WEN
CS
tCS
SK
DI
1
0
0
1
1
...
X
X
DS800026-6
WDS
WDS
CS
tCS
SK
DI
1
0
0
0
0
...
X
X
DS800026-7
6
FM93C56
www.fairchildsemi.com
FM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Timing Diagrams
WRITE
WRITE
CS
tCS
SK
1
DI
0
1
A7
A0
D15
...
D0
DO
BUSY
READY
tWP
DS800026-8
WRALL
WRALL
CS
tCS
SK
1
DI
0
0
0
1
DON'T CARE (6 BITS)
D15
...
D0
DO
BUSY
READY
tWP
DS800026-9
ERASE
ERASE
tCS
CS
STANDBY
SK
DI
DO
1
1
1
A7
A6
A5
...
A0
HI-Z
BUSY
READY
HI-Z
tWP
DS800026-10
ERAL
ERAL
tCS
CS
STANDBY
SK
DI
1
DO
0
0
1
0
DON'T CARE BITS (6 BITS)
HI-Z
BUSY
READY
HI-Z
tWP
DS800026-11
7
FM93C56
www.fairchildsemi.com
FM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Timing Diagrams (Continued)
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.150 - 0.157
(3.810 - 3.988)
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.053 - 0.069
(1.346 - 1.753)
8° Max, Typ.
All leads
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.04
(0.102)
All lead tips
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.014 - 0.020 Typ.
(0.356 - 0.508)
0.050
(1.270)
Typ
Molded Small Out-Line Package (M8)
Package Number M08A
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0098
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
8
FM93C56
www.fairchildsemi.com
FM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
(6.35 ± 0.127)
+
Pin #1 IDENT
0.032 ± 0.005
(0.813 ± 0.127)
RAD
5
1
1
0.300 - 0.320
(7.62 - 8.128)
7
Pin #1
IDENT
Option 1
0.280 MIN
(7.112)
8
2
3
0.040 Typ.
(1.016)
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
Français
Tel:
+33 (0) 1-6930-3696
Italiano
Tel:
+39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
9
FM93C56
www.fairchildsemi.com
FM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Physical Dimensions inches (millimeters) unless otherwise noted
FM93C56A
2K-Bit Serial CMOS EEPROM
(MICROWIRE™ Synchronous Bus)
General Description
Features
The FM93C56A is 2048 bits of CMOS nonvolatile EEPROM (
Electrically Erasable Programmable Read Only Memory) with
MICROWIRE serial interface. FM93C56A can be configured for
either 128 x 16 bit or 256 x 8 bit array using an organization (ORG)
input pin. This device is fabricated using Fairchild Semiconductor's
floating gate CMOS process for high reliability, high endurance
and low power consumption. This device is available in 8-pin DIP,
SO and TSSOP packages.
■ 2.7V to 5.5V operation in all modes
■ Typical active current 200µA
10 µA standby current typical
1 µA standby current typical (L)
0.1 µA standby current typical (LZ)
■ Self-timed programming cycle
■ Device status indication during programming mode
■ No erase required before write
The MICROWIRE serial interface offered by this EEPROM enables simple interface to a wide variety of microcontrollers and
microprocessors. There are 7 instructions that operate the
FM93C56A: Read, Erase/Write Enable, Erase, Write, Erase/
Write Disable, Write All and Erase All.
■ Reliable CMOS floating gate technology
■ MICROWIRE compatible serial I/O
■ 40 years data retention
■ Endurance: 1,000,000 data changes
■ Packages available: 8-Pin TSSOP, 8-pin SO, 8-pin DIP
■ Schmitt Trigger inputs and VCC lockout to prevent data
corruption
Block DiagramCS
VCC
Instruction
Decoder
Control Logic,
And Clock
Generators
SK
Instruction
Register
DI
ORG
Address
Register
VPP
High Voltage
Generator
And
Program
Timer
EEPROM Array
2048 Bits
(128x16) or (256x8)
Decoder
1 of 128
(or 256)
Read/Write Amps
Data In/Out Register
16 (or 8) Bits
GND
Data Out Buffer
DO
DS800029-1
© 1999 Fairchild Semiconductor Corporation
FM93C56A Rev. A
1
www.fairchildsemi.com
FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
January 2000
Rotated Die
(93C56AT)
Dual-In-Line Package (N)
8-Pin SO Package (M8)
and 8-Pin TSSOP Package (MT8)
NC
1
8
ORG
VCC
2
7
VSS
ORG
CS
3
6
DO
VSS
SK
4
5
DI
CS
1
8
VCC
SK
2
7
NC
DI
3
6
DO
4
5
FM93C56A
FM93C56A
DS800029-2
Top View
See Package Number N08E, M08A and MTC08
Pin Names
Pin
Description
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
VSS
Ground
ORG
Memory Organization Select
NC
No Connect
VCC
Positive Power Supply
Ordering Information
FM
93
C
XX
A
T
LZ
E
XX
Letter Description
Package
N
M8
MT8
8-Pin DIP
8-Pin SO8
8-Pin TSSOP
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
Blank
T
Normal Pin Out
Rotated Die Pin Out
A
x8 or x16 Configuration
Density
Interface
2
FM93C56A Rev. A
56
2K
C
CS
CMOS
Data protect and sequential
read
93
MICROWIRE
FM
Fairchild Non-Volatile
Memory
www.fairchildsemi.com
FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Connection Diagram
Operating Conditions
Ambient Storage Temperature
Ambient Operating Temperature
FM93C56A
FM93C56AE
FM93C56AV
-65°C to +150°C
All Input or Output Voltages
with Respect to Ground
VCC +1 to -0.3V
Lead Temperature
(Soldering, 10 seconds)
+300°C
ESD Rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC) Range
4.5V to 5.5V
2000V
DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V
Symbol
Parameter
Part Number
Conditions
Min
Max
Units
ICCA
Operating Current
CS = VIH SK = 1 MHz
1
mA
ICCS
Standby Current
CS = 0V ORG = VCC or NC
50
µA
IIL
Input Leakage
VIN = 0V to VCC (Note 2)
-1
1
µA
IILO
Input Leakage
ORG Pin
ORG Tied to VCC
ORG Tied to VSS (Note 3)
-1
-2.5
1
2.5
µA
IOL
Output Leakage
VIN = 0V to VCC
-1
1
µA
VIL
Input Low Voltage
-0.1
0.8
V
2
VCC +1
V
0.4
V
VIH
Input High Voltage
VOL1
Output Low Voltage
IOL = 2.1 mA
VOH1
Output High Voltage
IOH = -400 µA
VOL2
Output Low Voltage
IOL = 10 µA
VOH2
Output High Voltage
IOL = -10 µA
fSK
SK Clock Frequency
(Note 4)
tSKH
SK High Time
tSKL
SK Low Time
tSKS
SK Setup Time
tCS
Minimum CS
Low Time
tCSS
FM93C56A
FM93C56AE
2.4
V
0.2
V
VCC -0.2
0
V
1
MHz
250
300
ns
250
ns
50
ns
250
ns
CS Set-Up Time
50
ns
tDH
D0 Hold Time
70
ns
tDIS
DI Set-Up Time
100
200
ns
tCSH
CS Hold Time
0
ns
tDIH
DI Hold Time
20
ns
tPD
Output Delay
500
ns
tSV
CS to Status Valid
500
ns
tDF
CS to DO in Hi-Z
100
ns
tWP
Write Cycle Time
10
ms
SK must be at VIL for
tSKS before CS goes
high
(Note 5)
FM93C56A
FM93C56AE/V
3
FM93C56A Rev. A
www.fairchildsemi.com
FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Absolute Maximum Ratings (Note 1)
Operating Range
Ambient Storage Temperature
Ambient Operating Temperature
FM93C56AL/LZ
FM93C56ALE/LZE
FM93C56A LV/LZV
–65°C to +150°C
All Input or Output Voltage
with Respect to Ground
+6.5V to -0.3V
Lead Temperature (Soldering, 10 sec.)
+300°C
ESD Rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
2000V
2.7V to 5.5V
DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified
Symbol
Parameter
Part Number
Conditions
Min.
Max.
Units
1
mA
10
1
µA
µA
±1
1
2.5
µA
µA
±1
µA
0.15 VCC
VCC +1
V
0.1 VCC
V
V
250
KHz
ICCA
Operating Current
CS = VIH, SK = 250KHz
ICCS
Standby Current
L
LZ
CS = VIL
IIL
IILO
Input Leakage
Input Leakage
ORG Pin
VIN = 0V to VCC (Note 2)
ORG tied to VCC
ORG tied to VSS (Note 3)
IOL
Output Leakage
VIN = 0V to VCC
VIL
VIH
Input Low Voltage
Input High Voltage
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
fSK
SK Clock Frequency
(Note 4)
tSKH
SK High Time
1
µs
tSKL
SK Low Time
1
µs
tSKS
SK Setup Time
SK must be at VIL for
tSKS before CS goes high
0.2
µs
tCS
Minimum CS
Low Time
(Note 5)
1
µs
tCSS
CS Setup Time
0.2
µs
tDH
DO Hold Time
70
ns
µs
-1
-2.5
-0.1
0.8 VCC
0.9 VCC
0
tDIS
DI Setup Time
0.4
tCSH
CS Hold Time
0
ns
tDIH
DI Hold Time
0.4
µs
tPD
Output Delay
2
µs
tSV
CS to Status Valid
1
µs
tDF
CS to DO in Hi-Z
0.4
µs
tWP
Write Cycle Time
15
ms
CS = VIL
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Capacitance TA = 25°C, f = 1 MHz
Symbol
Test
Typ
Max
Units
COUT
Output Capacitance
5
pF
CIN
Input Capacitance
5
pF
Note 2:
Typical leakage values are in the 20 nA range.
Note 3:
The ORG pin may draw > 1 µA when in the x8 mode ude to an internal pull-up transistor.
Note 4: The shortest allowable SK clock period = 1/fSK (as shown under the fSK fSK parameter).
Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC
parameters stated in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed.
Therefore, it is not allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 5: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all
internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in
the opcode diagrams in the following pages.)
AC Test Conditions
VCC Range
VIL/VIH
Input Levels
VIL/VIH
Timing Level
VOL/VOH
Timing Level
IOL/IOH
2.7V ≤ VCC ≤ 5.5V
.03V/1.8V
1.0V
0.8V/1.5V
±10µA
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(Extended Voltage Levels)
4.5V ≤ VCC ≤ 5.5V
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
FM93C56A Rev. A
www.fairchildsemi.com
FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Absolute Maximum Ratings (Note 1)
Serial Clock (SK):
Chip Select (CS):
This pin is the clock input (rising edge active) for clocking in all
opcodes and data on the DI pin and clocking out all data on the DO
pin. However, this pin has no effect on the asynchronous programming cycle (see the CS pin section) as the BUSY/READY status
is a function of the CS pin only.
This pin enables and disables the MICROWIRE device and
performs 3 general functions:
1. When in the low state, the MICROWIRE device is disabled
and the output tri-stated (high impedance). If this pin is
brought high (rising edge active), all internal registers are
reset and the device is enabled, allowing MICROWIRE
communication via DI/DO pins. To restate, the CS pin must
be held high during all device communication and opcode
functions. If the CS pin is brought low, all functions will be
disabled and reset when CS is brought high again. The
exception to this is when a programming cycle is initiated
(see 2 and 3). Again, all activity on the CS, DI and DO pins
is ignored until CS is brought high.
Data-In (DI):
All serial communication into the device is performed using this
input pin (rising edge active). In order to avoid false Start Bits, or
related issues, it is advised to keep the DI pin in the low state
unless actually clocking in data bits (Start Bit, Opcode, Address or
incoming data bits to be programmed). Please note that the first
'1' clocked into the device (after CS is brought high) is seen as a
Start Bit and the beginning of a serial command string, so caution
must be observed when bringing CS high.
2. After entering all required opcode and address data, bringing
CS low initiates the (asynchronous) programming cycle.
Data-Out (DO):
All serial communication out of the device, Read Data ( during
normal reads) as well as READY/BUSY status indication ( during
programming ) are performed using this output pin. Note that,
during READ operations, the EEPROM device starts to drive the
DO output pin "active" after the last address bit (A0) is clocked in.
Hence in applications where 3-wire configuration is required (
where DI and DO pins are tied together ) caution must be observed
for correct operation. Please refer AN-758 for further information.
3. When programming is in progress, the Data-Out pin will
display the programming status as either BUSY (DO low) or
READY (DO high) when CS is brought high. (Again, the
output will be tri-stated when CS is low.) To restate, during
programming, the CS pin may be brought high and low any
number of times to view the programming status without
affect the programming operation. Once programming is
completed (Output in READY state), the output is 'cleared'
(returned to normal tri-state condition) by clocking in a Start
Bit. After the Start Bit is clocked in, the output will return to a
tri-stated condition. When clocked in, this Start Bit can be the
first bit in a command string, or CS can be brought low again
to reset all internal circuits.
Organization (ORG):
This pin controls the device architecture (8-bit data word vs. 16-bit
data word). If the ORG pin is brought to VCC, the device is
configured wiht a 16-bit data word and if the ORG pin is brought
to VSS (Ground), the device is configured with an 8-bit data word.
If the ORG pin is left floating, the device will default to a 16-bit data
word.
Instruction Set for the FM93C56A
ORG
Note:
5
FM93C56A Rev. A
Memory
Pin
Logic
Configuration
# of Address Bits
0
256 x 8
9 Bits
1
128 x 16
8 Bits
The leading (MSB) bit is a "don't care," but must be included in the address string.
www.fairchildsemi.com
FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
MICROWIRE I/O Pin Description
Instruction
SB
OP-Code
2 Bits
Address
8 Bits
Data
16 Bits
Comments
READ
1
10
A7–A0
EWEN
1
00
11XXXXXX
Read data stored in selected registers.
Enables programming modes.
EWDS
1
00
00XXXXXX
Disables all programming modes.
ERASE
1
11
A7–A0
WRITE
1
01
A7–A0
ERAL
1
00
10XXXXXX
WRAL
1
00
01XXXXXX
Erase selected register.
D15–D0
Writes data pattern D15–D0 into selected register.
Erases all registers.
D15–D0
Writes data pattern D15–D0 into all registers.
Note: The A7 bit is a "don't care" bit, but must be entered in the Address string.
Note: X = Don't care.
256 by 8-Bit Organization (FM93C56A when ORG = GND)
Instruction
SB
OP-Code
2 Bits
Address
9 Bits
Data
8 Bits
Comments
READ
1
10
A8–A0
EWEN
1
00
11XXXXXXX
Enables programming modes.
EWDS
1
00
00XXXXXXX
Disables all programming modes.
ERASE
1
11
A8–A0
WRITE
1
01
A8–A0
ERAL
1
00
10XXXXXXX
WRAL
1
00
01XXXXXXX
Read data stored in selected registers.
Erase selected register.
D7–D0
Writes data pattern D7–D0 into selected registers.
Erases all registers.
D7–D0
Writes data pattern D7–D0 into all registers.
Note: The A8 bit is a "don't care" bit, but must be entered in the Address string.
Note: X = Don't care.
Functional Description
Read (READ)
Programming:
The READ instruction outputs serial data on the DO pin. After a
READ instruction is received, the instruction and address are
decoded, followed by data transfer from the selected memory
register into a serial-out shift register. A dummy bit (logical 0)
precedes the serial data output string. Output data changes are
initiated by a low to high transition of SK after the last address bit
(A0) is clocked in.
1. Programming is initiated by clocking in the Start Bit, Opcode
bits, Address bits and the 8/16 data bits (refer to the ORG
pin section).
2. Programming is started by bringing the CS pin low. Once the
programming cycle is started, it cannot be stopped. (Bringing
VCC low will stop any programming, but will also result in
data corruption.)
Erase/Write Enable (EWEN)
When VCC is applied to the part, it “powers up” in the Erase/Write
Disable (EWDS) state. Therefore, all programming modes must
be preceded by an Erase/Write Enable (EWEN) instruction. Once
an Erase/Write Enable instruction is executed, programming
remains enabled until an Erase/Write Disable (EWDS) instruction
is executed or VCC is removed from the part.
3. The status of the programming cycle (BUSY or READY) is
observed by bringing the CS pin high and observing the
output state. If the output is LOW, the device is still programming (BUSY). If the output is HIGH, the programming cycle
has been completed and the device is ready for the next
operation. Note that the output will be tri-stated each time
CS is brought low and the READY/BUSY status will be
shown each time CS is brought high.
4. After programming, the READY state (output HIGH) can be
reset and the output tri-stated by clocking in a single Start
Bit. This Start Bit can be the first bit in a command string, or
CS can be brought low again to reset all internal circuits. In
any case, clocking in a '1' bit will tri-state the output.
6
FM93C56A Rev. A
www.fairchildsemi.com
FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
128 by 16-Bit Organization (FM93C56A when ORG = VCC or NC)
Write (WRITE):
Erase/Write Disable (EWDS):
The WRITE instruction is followed by 16 bits of data (or 8 bits of
data when using the FM93C56A in the x8 organization) to be
written into the specified address. Please refer to the Programming section for details.
To protect against accidental data overwrites, the Erase/Write
Disable (EWDS) instruction disables all programming modes and
should follow all programming operations. Execution of a READ
instruction is independent of both the EWEN and EWDS instructions.
Erase All (ERAL):
The ERAL instruction will simultaneously program all registers in
the memory array to the logical “1” state.
Erase (ERASE):
Write All (WRAL):
The ERASE instruction will program all bits in the specified
register to the logical “1” state. Please refer to the Programming
section for details.
The WRAL instruction will simultaneously program all registers
with the data pattern specified in the instruction.
Timing Diagrams for the FM93C56A
Synchronous Data Timing
CS
SK
DI
VIH
VIL
VIH
VIL
VIH
tCSS
tSKS
tDIS
tSKH
VOH
DO (PROGRAM)
VOL
tPD
tSV
tCSH
tDIH
VIL
VOH
DO (READ)
VOL
tSKL
tDH
tDH
tDF
tDF
STATUS VALID
DS800029-4
7
FM93C56A Rev. A
www.fairchildsemi.com
FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Functional Description (Continued)
Key for Timing Diagrams
Organization of Address and Data Fields for FM93C56A
ORG Pin
Organization
AN
DN
VCC or NC
128 x 16
A7
D15
VSS
256 x 8
A8
D7
Note:
The MSB is "don't care."
READ
CS
tCS
SK
1
DI
1
...
AN
0
A0
DO
0
...
DN
D0
DS800029-5
EWEN
DO = HI-Z
tCS
CS
SK
1
DI
0
0
1
X
1
...
X
ORG = VCC, 4 X'S
ORG = VSS, 5 X'S
DS800029-6
EWDS
DO = HI-Z
tCS
CS
SK
1
DI
0
0
0
X
0
...
X
ORG = VCC, 4 X'S
ORG = VSS, 5 X'S
DS800029-7
ERASE
tCS
CS
Standby
SK
DI
DO
1
1
1
...
AN
A0
Busy
HI-Z
tWP
8
FM93C56A Rev. A
Ready
HI-Z
DS800029-8
www.fairchildsemi.com
FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Timing Diagrams for the FM93C56A (Continued)
WRITE
tCS
CS
SK
1
DI
1
0
AN . . .
DN . . .
A0
D0
Busy
DO
Ready
DS800029-9
tWP
ERAL
tCS
CS
STANDBY
SK
1
DI
0
0
1
0
X
...
X
ORG = VCC, 4 X's
ORG = VSS, 5 X's
DO
BUSY
READY
READY STATUS SIGNAL RESETS
TO HI-Z AFTER CLOCKING IN
ONE SK CYCLE WITH DI = 1
tWP
DS800029-10
WRAL
tCS
CS
STANDBY
SK
DI
1
0
0
0
1
X
...
X
D N . . . D0
ORG = VCC, 4 X's
ORG = VSS, 5 X's
DO
BUSY
tWP
READY
READY STATUS SIGNAL RESETS
TO HI-Z AFTER CLOCKING IN
ONE SK CYCLE WITH DI = 1
DS800029-11
9
FM93C56A Rev. A
www.fairchildsemi.com
FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Timing Diagrams for the FM93C56A (Continued)
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
8° Max, Typ.
All leads
0.04
(0.102)
All lead tips
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020 Typ.
(0.356 - 0.508)
Molded Small Outline Package (M8)
Package Number M08A
10
FM93C56A Rev. A
www.fairchildsemi.com
FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0098
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
11
FM93C56A Rev. A
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FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
(6.35 ± 0.127)
+
Pin #1 IDENT
0.032 ± 0.005
(0.813 ± 0.127)
RAD
5
1
1
2
3
0.040 Typ.
(1.016)
0.300 - 0.320
(7.62 - 8.128)
7
Pin #1
IDENT
Option 1
0.280 MIN
(7.112)
8
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
Français
Tel:
+33 (0) 1-6930-3696
Italiano
Tel:
+39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
12
FM93C56A Rev. A
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
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FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Physical Dimensions inches (millimeters) unless otherwise noted
FM93C66
4K-Bit Serial CMOS EEPROM
(MICROWIRE™ Bus Interface)
General Description
Features
The FM93C66 device is 4096 bits of CMOS non-volatile electrically erasable memory organized as 256x16 bit array. They are
fabricated using Fairchild Semiconductor's floating-gate CMOS
process for high reliability, high endurance and low power consumption. These memory devices are available in an 8-pin SOIC
or 8-pin TSSOP package for small space considerations.
■ Device status during programming mode
FM93C66 is compatible with MICROWIRE interface, which offers
simple interface to standard microcontrollers and microprocessors. There are 7 instructions which control this device: Read,
Write Enable, Erase, Erase All, Write, Write All, and Write Disable.
The ready/busy status is available on the DO pin to indicate the
completion of a programming cycle.
■ Reliable CMOS floating gate technology
■ Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
■ No erase required before write
■ 2.7V to 5.5V operation in all modes
■ MICROWIRE compatible serial l/O
■ Self-timed programming cycle
■ 40 years data retention
■ Endurance: 1,000,000 data changes
■ Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
■ Schmitt Trigger inputs and VCC lockout to prevent data
corruption
Block Diagram
VCC
CS
INSTRUCTION
DECODER
CONTROL LOGIC,
AND CLOCK
GENERATORS
SK
DI
INSTRUCTION
REGISTER
ADDRESS
REGISTER
VPP
DECODER
1 OF 256
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
EEPROM ARRAY
16
READ/WRITE AMPS
16
VSS
DATA IN/OUT REGISTER
16 BITS
DO
© 1999 Fairchild Semiconductor Corporation
FM93C66
DATA OUT BUFFER
1
DS800027-1
www.fairchildsemi.com
FM93C66 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
December 1999
Dual-In-Line Package (N),
8-Pin SO (M8) and 8-Pin TSSOP (MT8)
CS
1
8
VCC
SK
2
7
NC
DI
3
6
NC
DO
4
5
GND
DS800027-2
Top View
See Package Number
N08E, M08A and MTC08
Pin Names
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
VCC
Power Supply
Ordering Information
FM
93
C
XX
LZ
E
XX
Letter
Description
N
M8
MT8
8-Pin DIP
8-Pin SO8
8-Pin TSSOP
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
Package
Density
Interface
2
FM93C66
66
4K
C
CMOS
93
MICROWIRE
FM
Fairchild Non-Volatile
Memory
www.fairchildsemi.com
FM93C66 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Connection Diagrams
Operating Range
Ambient Storage Temperature
Ambient Operating Temperature
FM93C66
FM93C66E
FM93C66V
All Input or Output Voltage
with Respect to Ground
Lead Temperature (Soldering, 10 sec.)
ESD Rating
–65°C to +150°C
+6.5V to -0.3V
+300°C
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
4.5V to 5.5V
2000V
DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V
Symbol
Max.
Units
ICCA
Operating Current
Parameter
Part Number
CS = VIH, SK = 1MHz
Conditions
1
mA
ICCS
Standby Current
CS = VIL
50
µA
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
(Note 2)
±1
µA
VIL
VIH
Input Low Voltage
Input High Voltage
0.8
VCC +1
V
0.4
V
V
0.2
V
V
1
MHz
-0.1
2
VOL1
VOH1
Output Low Voltage
Output High Voltage
IOL = 2.1mA
IOH = -400 µA
2.4
VOL2
VOH2
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
VCC -0.2
fSK
SK Clock Frequency
(Note 3)
tSKH
SK High Time
tSKL
SK Low Time
tSKS
SK Setup Time
tCS
Minimum CS
Low Time
tCSS
CS Setup Time
50
ns
tDH
DO Hold Time
70
ns
tDIS
DI Setup Time
100
200
ns
tCSH
CS Hold Time
0
ns
tDIH
DI Hold Time
20
ns
tPD
Output Delay
500
ns
tSV
CS to Status Valid
500
ns
tDF
CS to DO in Hi-Z
tWP
Write Cycle Time
FM93C66
FM93C66E/V
0
250
300
ns
250
ns
SK must be at VIL for
tSKS before CS goes
high
50
ns
(Note 4)
250
ns
FM93C66
FM93C66E/V
CS = VIL
3
FM93C66
Min.
100
ns
10
ms
www.fairchildsemi.com
FM93C66 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Absolute Maximum Ratings (Note 1)
Operating Range
Ambient Storage Temperature
Ambient Operating Temperature
FM93C66L/LZ
FM93C66LE/LZE
FM93C66LV/LZV
–65°C to +150°C
All Input or Output Voltage
with Respect to Ground
+6.5V to -0.3V
Lead Temperature (Soldering, 10 sec.)
+300°C
ESD Rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
2000V
2.7V to 5.5V
DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified
Symbol
Parameter
Part Number
Conditions
Min.
Max.
Units
1
mA
10
1
µA
µA
±1
µA
0.15 VCC
VCC +1
V
0.1 VCC
V
V
250
KHz
ICCA
Operating Current
CS = VIH, SK = 250KHz
ICCS
Standby Current
L
LZ
CS = VIL
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
VIL
VIH
Input Low Voltage
Input High Voltage
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
fSK
SK Clock Frequency
(Note 3)
tSKH
SK High Time
1
tSKL
SK Low Time
1
µs
tSKS
SK Setup Time
SK must be at VIL for
tSKS before CS goes
high
0.2
µs
tCS
Minimum CS
Low Time
(Note 4)
1
µs
tCSS
CS Setup Time
0.2
µs
tDH
DO Hold Time
70
ns
tDIS
DI Setup Time
0.4
µs
tCSH
CS Hold Time
0
ns
tDIH
DI Hold Time
0.4
µs
tPD
Output Delay
2
µs
tSV
CS to Status Valid
1
µs
tDF
CS to DO in Hi-Z
tWP
Write Cycle Time
-0.1
0.8 VCC
0.9 VCC
0
CS = VIL
Test
Max
Units
COUT
Output Capacitance
Typ
5
pF
CIN
Input Capacitance
5
pF
0.4
µs
15
ms
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Capacitance TA = 25°C, f = 1 MHz (Note 5)
Symbol
µs
Note 2:
Typical leakage values are in the 20nA range.
Note 3: The shortest allowable SK clock period = 1/fSK (as shown under the fSK parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not
allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
Note 5:
This parameter is periodically sampled and not 100% tested.
AC Test Conditions
VCC Range
VIL/VIH
Input Levels
VIL/VIH
Timing Level
VOL/VOH
Timing Level
IOL/IOH
2.7V ≤ VCC ≤ 5.5V
.03V/1.8V
1.0V
0.8V/1.5V
±10µA
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(Extended Voltage Levels)
4.5V ≤ VCC ≤ 5.5V
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
FM93C66
www.fairchildsemi.com
FM93C66 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Absolute Maximum Ratings (Note 1)
Write (WRITE):
The FM93C66 device has 7 instructions as described below. Note
that the MSB of any instruction is a “1” and is viewed as a start bit
in the interface sequence. The next 10 bits carry the op code and
the 8-bit address for register selection.
The WRITE instruction is followed by the address and 16 bits of data
to be written into the specified address. After the last bit of data is
put in the data-in (DI) pin, CS must be brought low before the next
rising edge of the SK clock. This falling edge of the CS initiates the
self-timed programming cycle. The D0 pin indicates the READY/
BUSY status of the chip if CS is brought high after a minimum of tCS.
D0 = logical 1 indicates that the register at the address specified in
the instruction has been written with the data pattern specified in the
instruction and the part is ready for another instruction.
Read (READ):
The READ instruction outputs serial data on the D0 pin. After a
READ instruction is received, the instruction and address are
decoded, followed by data transfer from the selected memory
register into a 16-bit serial-out shift register. A dummy bit (logical
0) precedes the 16-bit data output string. Output data changes are
initiated by a low to high transition of the SK clock.
Erase All (ERAL):
The ERAL instruction will simultaneously program all registers in
the memory array and set each bit to the logical “1” state. The Erase
All cycle is identical to the ERASE cycle except for the different opcode. As in the ERASE mode, the DO pin indicates the READY/
BUSY status of the chip if CS is brought high after the t CS interval.
Write Enable (WEN):
When VCC is applied to the part, it 'powers-up' in the Write Disable
(WDS) state. Therefore, all programming modes must be preceded by a Write Enable (WEN) instruction. Once a Write Enable
instruction is executed, programming remains enabled until aWrite
Disable (WDS) instruction is executed or VCC is removed from the
part.
Write All (WRALL):
The WRALL instruction will simultaneously program all registers
with the data pattern specified in the instruction. As in the WRITE
mode, the DO pin indicates the READY/BUSY status of the chip
if CS is brought high after the tCS interval.
Erase (ERASE):
The ERASE instruction will program all bits in the specified
register to the logical “1” state. CS is brought low following the
loading of the last address bit. This falling edge of the CS pin
initiates the self-timed programming cycle.
Write Disable (WDS):
To protect against accidental data disturb, the WDS instruction
disables all programming modes and should follow all programming operations. Execution of a READ instruction is independent
of both the WEN and WDS instructions.
The DO pin indicates the READY/BUSY status of the chip if CS is
brought high after a minimum time of tCS. DO = logical “0” indicates
that the register, at the address specified in the instruction, has
been erased, and the part is ready for another instruction.
Note: The Fairchild CMOS EEPROMs do not require an "ERASE" or "ERASE ALL"
operation prior to the "WRITE" and "WRITE ALL" instructions. The "ERASE" and "ERASE
ALL" instructions are included to maintain compatibility with earlier technology EEPROMs.
Instruction Set for the FM93C66
Instruction
SB
Op. Code
Address
READ
1
10
A7-A0
WEN
1
00
11xxxxxx
ERASE
1
11
A7-A0
WRITE
1
01
A7-A0
ERAL
1
00
10xxxxxx
WRALL
1
00
01xxxxxx
WDS
1
00
00xxxxxx
Data
Comments
Reads data stored in memory, at specified address.
Write enable must precede all programming modes.
Erase selected register.
D15-D0
Writes selected register.
Erases all registers.
D15-D0
Writes all registers.
Disables all programming instructions.
X = Don't care.
5
FM93C66
www.fairchildsemi.com
FM93C66 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Functional Description
Synchronous Data Timing
CS
SK
DI
VIH
VIL
tCSS
tSKH
tSKS
VIH
VIL
tDIS
VIH
tSKL
tDIH
VIL
tPD
VOH
DO (READ)
VOL
tSV
VOH
DO (PROGRAM)
VOL
tCSH
tDF
tDH
tDH
tDF
STATUS VALID
DS800027-4
READ
CS
tCS
SK
DI
1
1
0
...
A7
A0
DO
0
...
D15
D0
DS800027-5
WEN
CS
tCS
SK
DI
1
0
0
1
1
...
X
X
DS800027-6
WDS
CS
tCS
SK
DI
1
0
0
0
0
...
X
X
DS800027-7
6
FM93C66
www.fairchildsemi.com
FM93C66 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Timing Diagrams
WRITE
CS
tCS
SK
1
DI
0
1
A7
A0
D15
...
D0
DO
BUSY
READY
tWP
DS800027-8
WRALL
CS
tCS
SK
1
DI
0
0
0
1
DON'T CARE (6 BITS)
D15
...
D0
DO
BUSY
READY
tWP
DS800027-9
ERASE
tCS
CS
STANDBY
SK
DI
DO
1
1
1
A7
A6
A5
...
A0
HI-Z
BUSY
READY
HI-Z
tWP
DS800027-10
ERAL
tCS
CS
STANDBY
SK
DI
1
DO
0
0
1
0
DON'T CARE BITS (6 BITS)
HI-Z
BUSY
READY
HI-Z
tWP
DS800027-11
7
FM93C66
www.fairchildsemi.com
FM93C66 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Timing Diagrams (Continued)
FM93C66 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.150 - 0.157
(3.810 - 3.988)
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.053 - 0.069
(1.346 - 1.753)
8° Max, Typ.
All leads
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.04
(0.102)
All lead tips
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.014 - 0.020 Typ.
(0.356 - 0.508)
0.050
(1.270)
Typ
Molded Small Out-Line Package (M8)
Package Number M08A
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0098
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
8
FM93C66
www.fairchildsemi.com
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
+
Pin #1 IDENT
8
0.032 ± 0.005
(6.35 ± 0.127)
Pin #1
IDENT
1
Option 1
1
0.280 MIN
(7.112)
0.300 - 0.320
(7.62 - 8.128)
7
(0.813 ± 0.127)
RAD
5
2
3
0.040 Typ.
(1.016)
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
0.039
(0.991)
(3.683 - 5.080)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
Français
Tel:
+33 (0) 1-6930-3696
Italiano
Tel:
+39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
9
FM93C66
www.fairchildsemi.com
FM93C66 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Physical Dimensions inches (millimeters) unless otherwise noted
FM93C66A
4K-Bit Serial CMOS EEPROM
(MICROWIRE™ Bus Interface)
General Description
Features
The FM93C66A is 4096 bits of CMOS nonvolatile EEPROM
(Electrically Erasable Programmable Read Only Memory) with
MICROWIRE serial interface. FM93C66A can be configured for
either 256 x 16 bit or 512 x 8 bit array using an organization (ORG)
input pin. This device is fabricated using Fairchild Semiconductor's
floating gate CMOS process for high reliability, high endurance
and low power consumption. This device is available in 8-pin DIP,
SO and TSSOP packages.
■ 2.7V to 5.5V operation in all modes
■ Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
■ Self-timed programming cycle
■ Device status indication during programming mode
■ No erase required before write
The MICROWIRE serial interface offered by this EEPROM enables simple interface to a wide variety of microcontrollers and
microprocessors. There are 7 instructions that operate the
FM93C66A: Read, Erase/Write Enable, Erase, Write, Erase/
Write Disable, Write All and Erase All.
■ Reliable CMOS floating gate technology
■ MICROWIRE compatible serial I/O
■ 40 years data retention
■ Endurance: 1,000,000 data changes
■ Packages available: 8-pin TSSOP, 8-pin SO, 8-pin DIP
■ Schmitt Trigger inputs and VCC lockout to prevent data
corruption
Block Diagram
CS
VCC
Instruction
Decoder
Control Logic,
And Clock
Generators
SK
Instruction
Register
DI
ORG
Address
Register
VPP
High Voltage
Generator
And
Program
Timer
EEPROM Array
2048 Bits
(256 x16) or (512 x8)
Decoder
1 of 256
(or 512)
Read/Write Amps
Data In/Out Register
16 (or 8) Bits
GND
Data Out Buffer
DO
DS800030-1
© 1999 Fairchild Semiconductor Corporation
FM93C66A Rev. A
1
www.fairchildsemi.com
FM93C66A 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
January 2000
Dual-In-Line Package (N)
8-Pin SO Package (M8)
and 8-Pin TSSOP Package (MT8)
CS
1
SK
2
8
VCC
7
NC
FM93C66A
DI
3
6
ORG
DO
4
5
VSS
DS800030-2
Top View
See Package Number
N08E, M08A and MTC08
Pin Names
Pin
Description
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
VSS
Ground
ORG
Memory Organization Select
NC
No Connect
VCC
Positive Power Supply
Ordering Information
FM
93
C
XX
A
LZ
E
XX
Letter Description
Package
N
M8
MT8
8-Pin DIP
8-Pin SO8
8-Pin TSSOP
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
A
x8 or x16 Configuration
Density
Interface
2
FM93C66A Rev. A
66
4K
C
CMOS
93
MICROWIRE
FM
Fairchild Non-Volatile
Memory
www.fairchildsemi.com
FM93C66A 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Connection Diagram
Ambient Storage Temperature
Operating Conditions
-65°C to +150°C
All Input or Output Voltages
with Respect to Ground
VCC +1 to -0.3V
Lead Temperature
(Soldering, 10 seconds)
+300°C
ESD Rating
Ambient Operating Temperature
FM93C66A
FM93C66AE
FM93C66AV
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC) Range
2000V
4.5V to 5.5V
DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V
Symbol
Parameter
Part Number
Conditions
Min
Max
Units
ICCA
Operating Current
CS = VIH,SK=1 MHz
1
mA
ICCS
Standby Current
CS = 0V ORG = VCC or NC
50
µA
-1
1
µA
-1
-2.5
1
2.5
µA
-1
1
µA
IIL
Input Leakage
VIN = 0V to VCC (Note 2)
IILO
Input Leakage
ORG Pin
ORG Tied to VCC
ORG Tied to VSS
(Note 3)
IOL
Output Leakage
VIN = 0V to VCC
VIL
Input Low Voltage
-0.1
0.8
V
VIH
Input High Voltage
2
VCC +1
V
VOL1
Output Low Voltage
IOL = 2.1 mA
0.4
V
VOH1
Output High Voltage
IOH = -400 µA
VOL2
Output Low Voltage
IOL = 10 µA
VOH2
Output High Voltage
IOL = -10 µA
fSK
SK Clock Frequency
(Note 4)
tSKH
SK High Time
tSKL
SK Low Time
tSKS
SK Setup Time
tCS
Minimum CS
Low Time
tCSS
FM93C66A
FM93C66AE
2.4
V
0.2
VCC - 0.2
0
V
V
1
MHz
250
300
ns
250
ns
SK must be at VIL for
tSKS before CS goes
high
50
ns
(Note 5)
250
ns
CS Set-Up Time
50
ns
tDH
DO Hold Time
70
ns
tDIS
DI Set-Up Time
100
200
ns
tCSH
CS Hold Time
0
ns
tDIH
DI Hold Time
20
ns
tPD
Output Delay
500
ns
tSV
CS to Status Valid
500
ns
tDF
CS to DO in Hi-Z
100
ns
tWP
Write Cycle Time
10
ms
FM93C66A
FM93C66AE/V
3
FM93C66A Rev. A
www.fairchildsemi.com
FM93C66A 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Absolute Maximum Ratings (Note 1)
Operating Range
Ambient Storage Temperature
Ambient Operating Temperature
FM93C66AL/LZ
FM93C66ALE/LZE
FM93C66ALV/LZV
–65°C to +150°C
All Input or Output Voltage
with Respect to Ground
+6.5V to -0.3V
Lead Temperature (Soldering, 10 sec.)
+300°C
ESD Rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
2000V
2.7V to 5.5V
DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified
Symbol
Parameter
Part Number
Conditions
Min.
Max.
Units
1
mA
10
1
µA
µA
±1
1
2.5
µA
µA
±1
µA
0.15 VCC
VCC +1
V
0.1 VCC
V
V
250
KHz
ICCA
Operating Current
CS = VIH, SK = 250KHz
ICCS
Standby Current
L
LZ
CS = VIL
IIL
IILO
Input Leakage
Input Leakage
ORG Pin
VIN = 0V to VCC (Note 2)
ORG tied to VCC
ORG tied to VSS (Note 3)
IOL
Output Leakage
VIN = 0V to VCC
VIL
VIH
Input Low Voltage
Input High Voltage
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
fSK
SK Clock Frequency
(Note 4)
tSKH
SK High Time
1
µs
tSKL
SK Low Time
1
µs
tSKS
SK Setup Time
SK must be at VIL for
tSKS before CS goes high
0.2
µs
tCS
Minimum CS
Low Time
(Note 5)
1
µs
tCSS
CS Setup Time
0.2
µs
tDH
DO Hold Time
70
ns
µs
-1
-2.5
-0.1
0.8 VCC
0.9 VCC
0
tDIS
DI Setup Time
0.4
tCSH
CS Hold Time
0
ns
tDIH
DI Hold Time
0.4
µs
tPD
Output Delay
2
µs
tSV
CS to Status Valid
1
µs
tDF
CS to DO in Hi-Z
0.4
µs
tWP
Write Cycle Time
15
ms
CS = VIL
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Capacitance TA = 25°C, f = 1 MHz
Symbol
Test
Typ
Max
Units
COUT
Output Capacitance
5
pF
CIN
Input Capacitance
5
pF
Note 2:
Typical leakage values are in the 20 nA range.
Note 3:
The ORG pin may draw > 1 µA when in the x8 mode ude to an internal pull-up transistor.
Note 4: The shortest allowable SK clock period = 1/fSK (as shown under the fSK fSK parameter).
Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC
parameters stated in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed.
Therefore, it is not allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 5: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all
internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in
the opcode diagrams in the following pages.)
AC Test Conditions
VCC Range
VIL/VIH
Input Levels
VIL/VIH
Timing Level
VOL/VOH
Timing Level
IOL/IOH
2.7V ≤ VCC ≤ 5.5V
.03V/1.8V
1.0V
0.8V/1.5V
±10µA
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(Extended Voltage Levels)
4.5V ≤ VCC ≤ 5.5V
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
FM93C66A Rev. A
www.fairchildsemi.com
FM93C66A 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Absolute Maximum Ratings (Note 1)
Serial Clock (SK):
Chip Select (CS):
This pin is the clock input (rising edge active) for clocking in all
opcodes and data on the DI pin and clocking out all data on the DO
pin. However, this pin has no effect on the asynchronous programming cycle (see the CS pin section) as the READY/BUSY status
is a function of the CS pin only.
This pin enables and disables the MICROWIRE device and
performs 3 general functions:
1. When in the low state, the MICROWIRE device is disabled
and the output tri-stated (high impedance). If this pin is
brought high (rising edge active), all internal registers are
reset and the device is enabled, allowing MICROWIRE
communication via DI/DO pins. To restate, the CS pin must
be held high during all device communication and opcode
functions. If the CS pin is brought low, all functions will be
disabled and reset when CS is brought high again. The
exception to this is when a programming cycle is initiated
(see 2 and 3). Again, all activity on the CS, DI and DO pins
is ignored until CS is brought high.
Data-In (DI):
All serial communication into the device is performed using this
input pin (rising edge active). In order to avoid false Start Bits, or
related issues, it is advised to keep the DI pin in the low state
unless actually clocking in data bits (Start Bit, Opcode, Address or
incoming data bits to be programmed). Please note that the first
'1' clocked into the device (after CS is brought high) is seen as a
Start Bit and the beginning of a serial command string, so caution
must be observed when bringing CS high.
2. After entering all required opcode and address data, bringing
CS low initiates the (asynchronous) programming cycle.
Data-Out (DO):
All serial communication out of the device, Read Data ( during
normal reads) as well as READY/BUSY status indication ( during
programming ) are performed using this output pin. Note that,
during READ operations, the EEPROM device starts to drive the
DO output pin "active" after the last address bit (A0) is clocked in.
Hence in applications where 3-wire configuration is required (
where DI and DO pins are tied together ) caution must be observed
for correct operation. Please refer AN-758 for further information.
3. When programming is in progress, the Data-Out pin will
display the programming status as either BUSY (DO low) or
READY (DO high) when CS is brought high. (Again, the
output will be tri-stated when CS is low.) To restate, during
programming, the CS pin may be brought high and low any
number of times to view the programming status without
affect the programming operation. Once programming is
completed (Output in READY state), the output is 'cleared'
(returned to normal tri-state condition) by clocking in a Start
Bit. After the Start Bit is clocked in, the output will return to a
tri-stated condition. When clocked in, this Start Bit can be the
first bit in a command string, or CS can be brought low again
to reset all internal circuits.
Organization (ORG):
This pin controls the device architecture (8-bit data word vs. 16-bit
data word). If the ORG pin is brought to VCC, the device is
configured with a 16-bit data word and if the ORG pin is brought
to VSS (Ground), the device is configured with an 8-bit data word.
If the ORG pin is left floating, the device will default to a 16-bit data
word.
Instruction Set for FM93C66A
ORG
5
FM93C66A Rev. A
Memory
Pin
Logic
Configuration
# of Address Bits
0
512 x 8
9 Bits
1
256 x 16
8 Bits
www.fairchildsemi.com
FM93C66A 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
MICROWIRE I/O Pin Description
Instruction
SB
OP-Code
2 Bits
Address
8 Bits
Data
16 Bits
Comments
READ
1
10
A7–A0
EWEN
1
00
11XXXXXX
Read data stored in selected registers.
Enables programming modes.
EWDS
1
00
00XXXXXX
Disables all programming modes.
ERASE
1
11
A7–A0
WRITE
1
01
A7–A0
ERAL
1
00
10XXXXXX
WRAL
1
00
01XXXXXX
Erase selected register.
D15–D0
Writes data pattern D15–D0 into selected register.
Erases all registers.
D15–D0
Writes data pattern D15–D0 into all registers.
X = Don't care.
512 by 8-Bit Organization (FM93C66A when ORG = GND)
Instruction
SB
OP-Code
2 Bits
Address
9 Bits
READ
1
10
A8–A0
EWEN
1
00
11XXXXXXX
Enables programming modes.
EWDS
1
00
00XXXXXXX
Disables all programming modes.
ERASE
1
11
A8–A0
WRITE
1
01
A8–A0
ERAL
1
00
10XXXXXXX
WRAL
1
00
01XXXXXXX
Data
8 Bits
Comments
Read data stored in selected registers.
Erase selected register.
D7–D0
Writes data pattern D7–D0 into selected register.
Erases all registers.
D7–D0
Writes data pattern D7–D0 into all registers.
X = Don't care.
Functional Description
Read (READ):
Programming:
The READ instruction outputs serial data on the DO pin. After a
READ instruction is received, the instruction and address are
decoded, followed by data transfer from the selected memory
register into a serial-out shift register. A dummy bit (logical 0)
precedes the serial data output string. Output data changes are
initiated by a low to high transition of SK after the last address bit
(A0) is clocked in.
1. Programming is initiated by clocking in the Start Bit, Opcode
bits, Address bits and the 8/16 data bits (refer to the ORG
pin section).
2. Programming is started by bringing the CS pin low. Once the
programming cycle is started, it cannot be stopped. (Bringing
VCC low will stop any programming, but will also result in
data corruption.)
Erase/Write Enable (EWEN):
When VCC is applied to the part, it “powers up” in the Erase/Write
Disable (EWDS) state. Therefore, all programming modes must
be preceded by an Erase/Write Enable (EWEN) instruction. Once
an Erase/Write Enable instruction is executed, programming
remains enabled until an Erase/Write Disable (EWDS) instruction
is executed or VCC is removed from the part.
3. The status of the programming cycle (BUSY or READY) is
observed by bringing the CS pin high and observing the
output state. If the output is LOW, the device is still programming (BUSY). If the output is HIGH, the programming cycle
has been completed and the device is ready for the next
operation. Note that the output will be tri-stated each time
CS is brought low and the READY/BUSY status will be
shown each time CS is brought high.
4. After programming, the READY state (output HIGH) can be
reset and the output tri-stated by clocking in a single Start
Bit. This Start Bit can be the first bit in a command string, or
CS can be brought low again to reset all internal circuits. In
any case, clocking in a '1' bit will tri-state the output.
6
FM93C66A Rev. A
www.fairchildsemi.com
FM93C66A 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
256 by 16-Bit Organization (FM93C66A when ORG = VCC or NC)
Write (WRITE):
Erase/Write Disable (EWDS):
The WRITE instruction is followed by 16 bits of data (or 8 bits of
data when using the FM93C66A in the x8 organization) to be
written into the specified address. Please refer to the Programming section for details.
To protect against accidental data overwrites, the Erase/Write
Disable (EWDS) instruction disables all programming modes and
should follow all programming operations. Execution of a READ
instruction is independent of both the EWEN and EWDS instructions.
Erase All (ERAL):
The ERAL instruction will simultaneously program all registers in
the memory array to the logical “1” state.
Erase (ERASE):
Write All (WRAL):
The ERASE instruction will program all bits in the specified
register to the logical “1” state. Please refer to the Programming
section for details.
The WRAL instruction will simultaneously program all registers
with the data pattern specified in the instruction.
Timing Diagrams for the FM93C66A
Synchronous Data Timing
CS
SK
DI
VIH
VIL
VIH
VIL
VIH
tCSS
tSKS
tDIS
tSKH
VOH
DO (PROGRAM)
VOL
tPD
tSV
tCSH
tDIH
VIL
VOH
DO (READ)
VOL
tSKL
tDH
tDH
tDF
tDF
STATUS VALID
DS800030-4
7
FM93C66A Rev. A
www.fairchildsemi.com
FM93C66A 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Functional Description (Continued)
ORG Pin
Organization
AN
DN
VCC or NC
256 x 16
A7
D15
VSS
512 x 8
A8
D7
READ
CS
tCS
SK
1
DI
1
0
...
AN
A0
DO
0
DN
...
D0
DS800030-5
EWEN
DO = HI-Z
tCS
CS
SK
DI
1
0
0
1
1
X
...
X
ORG = VCC, 4 X'S
ORG = VSS, 5 X'S
DS800030-6
EWDS
DO = HI-Z
tCS
CS
SK
DI
1
0
0
0
0
X
...
X
ORG = VCC, 4 X'S
ORG = VSS, 5 X'S
8
FM93C66A Rev. A
DS800030-7
www.fairchildsemi.com
FM93C66A 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Timing Diagrams for the FM93C66A (Continued)
Key for Timing Diagrams
Organization of Address and Data Fields for the FM93C66A
ERASE
tCS
CS
Standby
SK
DI
1
1
1
...
AN
A0
Busy
HI-Z
DO
Ready
HI-Z
DS800030-8
tWP
WRITE
tCS
CS
SK
1
DI
1
0
AN . . .
DN . . .
A0
D0
Busy
DO
Ready
DS800030-9
tWP
ERAL
tCS
CS
STANDBY
SK
1
DI
0
0
1
0
...
X
X
ORG = VCC, 4 X's
ORG = VSS, 5 X's
DO
BUSY
READY
READY STATUS SIGNAL RESETS
TO HI-Z AFTER CLOCKING IN
ONE SK CYCLE WITH DI = 1
tWP
DS800030-10
WRAL
tCS
CS
STANDBY
SK
DI
1
0
0
0
1
X
...
X
DN . . . D0
ORG = VCC, 4 X's
ORG = VSS, 5 X's
DO
BUSY
tWP
READY
READY STATUS SIGNAL RESETS
TO HI-Z AFTER CLOCKING IN
ONE SK CYCLE WITH DI = 1
DS800030-11
9
FM93C66A Rev. A
www.fairchildsemi.com
FM93C66A 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Timing Diagrams for the FM93C66A (Continued)
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
8° Max, Typ.
All leads
0.04
(0.102)
All lead tips
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020 Typ.
(0.356 - 0.508)
Molded Small Outline Package (M8)
Package Number M08A
10
FM93C66A Rev. A
www.fairchildsemi.com
FM93C66A 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0098
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
11
FM93C66A Rev. A
www.fairchildsemi.com
FM93C66A 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
+
Pin #1 IDENT
8
0.032 ± 0.005
(6.35 ± 0.127)
Pin #1
IDENT
1
Option 1
1
0.280 MIN
(7.112)
0.300 - 0.320
(7.62 - 8.128)
7
(0.813 ± 0.127)
RAD
5
2
3
0.040 Typ.
(1.016)
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
0.039
(0.991)
(3.683 - 5.080)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
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Tel:
+33 (0) 1-6930-3696
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Tel:
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8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
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Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
12
FM93C66A Rev. A
www.fairchildsemi.com
FM93C66A 4K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Physical Dimensions inches (millimeters) unless otherwise noted
FM93C86A
16K-Bit Serial EEPROM
(MICROWIRE™ Bus Interface)
General Description
Features
The FM93C86A is 16,384 bits of CMOS nonvolatile EEPROM
(Electrically Erasable Programmable Read Only Memory) with
MICROWIRE serial interface. FM93C86A can be configured for
either 1024 x 16 bit or 2048 x 8 bit array using an organization
(ORG) input pin. This device is fabricated using Fairchild
Semiconductor's floating gate CMOS process for high reliability,
high endurance and low power consumption. This device is
available in 8-pin DIP and SO packages.
■ 2.7V to 5.5V operation in all modes
■ Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
■ Device status indication during programming mode
■ No erase required before write
■ Reliable CMOS floating gate technology
The MICROWIRE serial interface offered by this EEPROM enables simple interface to a wide variety of microcontrollers and
microprocessors. There are 7 instructions that operate the
FM93C86A: Read, Erase/Write Enable, Erase, Write, Erase/
Write Disable, Write All and Erase All.
■ MICROWIRE™ compatible serial I/O
■ Self-timed programming cycle
■ 40 years data retention
■ Endurance: 1,000,000 data changes
■ Packages available: 8-pin SO, 8-pin DIP
■ Schmitt Trigger inputs and VCC lockout to prevent data
corruption
Block Diagram
CS
VCC
Instruction
Decoder
Control Logic,
And Clock
Generators
SK
Instruction
Register
DI
ORG
Address
Register
VPP
High Voltage
Generator
And
Program
Timer
EEPROM Array
16384 Bits
(1024x16) or (2048x8)
Decoder
1 of 1024
(or 2048)
Read/Write Amps
Data In/Out Register
16 (or 8) Bits
GND
Data Out Buffer
DO
© 1999 Fairchild Semiconductor Corporation
FM93C86A Rev. A
DS800031-12
1
www.fairchildsemi.com
FM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
January 2000
Dual-In-Line Package (N)
and 8-Pin SO Package (M8)
CS
1
SK
2
DI
DO
8
VCC
7
NC
3
6
ORG
4
5
VSS
NM93C86A
Top View
See Package Number
N08E and M08A
DS800031-14
Pin Names
Pin
Description
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
VSS
Ground
ORG
Memory Organization Select
NC
No Connect
VCC
Positive Power Supply
Ordering Information
FM
93
C
XX
A
LZ
E
XX
Letter Description
Package
N
M8
8-Pin DIP
8-Pin SO8
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
A
x8 or x16 Configuration
86
16K
Density
Interface
2
FM93C86A Rev. A
C
CMOS
93
MICROWIRE
FM
Fairchild Non-Volatile
Memory
www.fairchildsemi.com
FM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Connection Diagram
Operating Range
Ambient Storage Temperature
Ambient Operating Temperature
FM93C86A
FM93C86AE
FM93C86AV
-65°C to +150°C
All Input or Output Voltage
with Respect to Ground
VCC + 1 to -0.3V
Lead Temperature
(Soldering, 10 seconds)
+300°C
ESD Rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC) Range
4.5V to 5.5V
2000V
DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V
Symbol
Parameter
Part Number
Conditions
Min
Max
Units
ICCA
Operating Current
CS = VIH, SK=1 MHz
1
mA
ICCS
Standby Current
CS = 0V ORG = VCC or NC
50
µA
IIL
Input Leakage
VIN = 0V to VCC (Note 2)
-1
1
µA
IILO
Input Leakage ORG Pin
ORG tied to VCC
ORG tied to VSS
(Note 3)
-1
-2.5
1
2.5
µA
IOL
Output Leakage
-1
1
µA
VIL
Input Low Voltage
-0.1
0.8
V
VIH
Input High Voltage
2
VCC +1
V
VOL1
Output Low Voltage
IOL = 2.1 mA
0.4
V
VOH1
Output High Voltage
IOH = -400 µA
VIN = 0V to VCC
2.4
V
VOL2
Output Low Voltage
IOL = 10 µA
VOH2
Output High Voltage
IOL = -10 µA
fSK
SK Clock Frequency
(Note 4)
tSKH
SK High Time
tSKL
SK Low Time
tSKS
SK Setup Time
tCS
Minimum CS Low Time
tCSS
CS Set-up Time
50
ns
tDH
DO Hold Time
70
ns
tDIS
DI Set-up Time
100
200
ns
tCSH
CS Hold Time
0
ns
tDIH
DI Hold Time
20
ns
tPD
Output Delay
500
ns
tSV
CS to Status Valid
500
ns
tDF
CS to DO in Hi-Z
100
ns
tWP
Write Cycle Time
10
ms
FM93C86A
FM93C86AE/V
V
0
V
1
MHz
250
300
ns
250
ns
SK must be at VIL for
tSKS before CS goes
high
50
ns
(Note 5)
250
ns
FM93C86A
FM93C86AE/V
3
FM93C86A Rev. A
0.2
VCC - 0.2
www.fairchildsemi.com
FM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Absolute Maximum Ratings (Note 1)
Operating Range
Ambient Storage Temperature
Ambient Operating Temperature
FM93C86AL/LZ
FM93C86ALE/LZE
FM93C86ALV/LZV
–65°C to +150°C
All Input or Output Voltage
with Respect to Ground
+6.5V to -0.3V
Lead Temperature (Soldering, 10 sec.)
+300°C
ESD Rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
2000V
2.7V to 5.5V
DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified
Symbol
Parameter
Part Number
Conditions
Min.
Max.
Units
1
mA
10
1
µA
µA
±1
1
2.5
µA
µA
±1
µA
0.15 VCC
VCC +1
V
0.1 VCC
V
V
250
KHz
ICCA
Operating Current
CS = VIH, SK = 250KHz
ICCS
Standby Current
L
LZ
CS = VIL
IIL
IILO
Input Leakage
Input Leakage
ORG Pin
VIN = 0V to VCC (Note 2)
ORG tied to VCC
ORG tied to VSS (Note 3)
IOL
Output Leakage
VIN = 0V to VCC
VIL
VIH
Input Low Voltage
Input High Voltage
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
fSK
SK Clock Frequency
(Note 4)
tSKH
SK High Time
1
µs
tSKL
SK Low Time
1
µs
tSKS
SK Setup Time
SK must be at VIL for
tSKS before CS goes high
0.2
µs
tCS
Minimum CS
Low Time
(Note 5)
1
µs
tCSS
CS Setup Time
0.2
µs
tDH
DO Hold Time
70
ns
µs
-1
-2.5
-0.1
0.8 VCC
0.9 VCC
0
tDIS
DI Setup Time
0.4
tCSH
CS Hold Time
0
ns
tDIH
DI Hold Time
0.4
µs
tPD
Output Delay
2
µs
tSV
CS to Status Valid
1
µs
tDF
CS to DO in Hi-Z
0.4
µs
tWP
Write Cycle Time
15
ms
CS = VIL
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Capacitance TA = 25°C, f = 1 MHz
Symbol
Test
COUT
CIN
Typ
Max
Units
Output Capacitance
5
pF
Input Capacitance
5
pF
Note 2:
Typical leakage values are in the 20 nA range.
Note 3:
The ORG pin may draw > 1 µA when in the x8 mode ude to an internal pull-up transistor.
Note 4: The shortest allowable SK clock period = 1/fSK (as shown under the fSK fSK parameter).
Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC
parameters stated in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed.
Therefore, it is not allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 5: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all
internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in
the opcode diagrams in the following pages.)
AC Test Conditions
VCC Range
VIL/VIH
Input Levels
VIL/VIH
Timing Level
VOL/VOH
Timing Level
IOL/IOH
2.7V ≤ VCC ≤ 5.5V
.03V/1.8V
1.0V
0.8V/1.5V
±10µA
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(Extended Voltage Levels)
4.5V ≤ VCC ≤ 5.5V
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
FM93C86A Rev. A
www.fairchildsemi.com
FM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Absolute Maximum Ratings (Note 1)
Serial Clock (SK):
Chip Select (CS):
This pin is the clock input (rising edge active) for clocking in all
opcodes and data on the DI pin and clocking out all data on the DO
pin. However, this pin has no effect on the asynchronous programming cycle (see the CS pin section) as the BUSY/READY status
is a function of the CS pin only.
This pin enables and disables the MICROWIRE device and
performs 2 general functions:
1. When in the low state, the MICROWIRE device is disabled
and the output tri-stated (high impedance). If this pin is
brought high (rising edge active), all internal registers are
reset and the device is enabled, allowing MICROWIRE
communication via DI/DO pins. To restate, the CS pin must
be held high during all device communication and opcode
functions. If the CS pin is brought low, all functions will be
disabled and reset when CS is brought high again. The
exception to this is when a programming cycle is initiated.
Again, all activity on the CS, DI and DO pins is ignored until
CS is brought high.
Data-In (DI):
All serial communication into the device is performed using this
input pin (rising edge active). In order to avoid false Start Bits, or
related issues, it is advised to keep the DI pin in the low state
unless actually clocking in data bits (Start Bit, Opcode, Address or
incoming data bits to be programmed). Please note that the first
'1' clocked into the device (after CS is brought high) is seen as a
Start Bit and the beginning of a serial command string, so caution
must be observed when bringing CS high.
2. When programming is in progress, the Data-Out pin will
display the programming status as either BUSY (DO low) or
READY (DO high) when CS is brought high. (Again, the
output will be tri-stated when CS is low.) To restate, during
programming, the CS pin may be brought high and low any
number of times to view the programming status without
affect the programming operation. Once programming is
completed (Output in READY state), the output is 'cleared'
(returned to normal tri-state condition) by clocking in a Start
Bit. After the Start Bit is clocked in, the output will return to a
tri-stated condition. When clocked in, this Start Bit can be the
first bit in a command string, or CS can be brought low again
to reset all internal circuits.
Data-Out (DO):
All serial communication out of the device, Read Data ( during
normal reads) as well as READY/BUSY status indication ( during
programming ) are performed using this output pin. Note that,
during READ operations, the EEPROM device starts to drive the
DO output pin "active" after the last address bit (A0) is clocked in.
Hence in applications where 3-wire configuration is required (
where DI and DO pins are tied together ) caution must be observed
for correct operation. Please refer AN-758 for further information.
Organization (ORG):
This pin controls the device architecture (8-bit data word vs. 16-bit
data word). If the ORG pin is brought to VCC, the device is
configured with a 16-bit data word and if the ORG pin is brought
to VSS (Ground), the device is configured with an 8-bit data word.
If the ORG pin is left floating, the device will default to a 16-bit data
word.
Unlike the lower density members of the Microwire product
family (FM93C06, FM93C46, FM93C56, FM93C66)
programming is not initiated by bringing CS low but initiated
as soon as the last bit of information (address bit or data bit
depending on the instruction type) is clocked in. Refer the
section on Programming for further detail.
Instruction Set for the FM93C86A
ORG
5
FM93C86A Rev. A
Memory
Pin
Logic
Configuration
# of Address Bits
0
2048 x 8
11 Bits
1
1024 x 16
10 Bits
www.fairchildsemi.com
FM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
MICROWIRE I/O Pin Description
Instruction
SB
Op Code
2 Bits
Address
10 Bits
Data
16 Bits
Function
READ
1
10
A9–A0
Read data stored in selected registers.
EWEN
1
00
11XXXXXXXX
Enables programming modes.
EWDS
1
00
00XXXXXXXX
Disables all programming modes.
ERASE
1
11
A9–A0
WRITE
1
01
A9–A0
ERAL
1
00
10XXXXXXXX
WRAL
1
00
01XXXXXXXX
Erases selected register.
D15–D0
Writes data pattern D15–D0 into selected register.
Erases all registers.
D15–D0
Writes data pattern D15–D0 into all registers.
X = Don't care.
2048 by 8-Bit Organization (FM93C86A when ORG = GND)
Instruction
SB
Op Code
2 Bits
Address
11 Bits
Data
8 Bits
Function
READ
1
10
A10–A0
Read data stored in selected registers.
EWEN
1
00
11XXXXXXXXX
Enables programming modes.
EWDS
1
00
00XXXXXXXXX
Disables all programming modes.
ERASE
1
11
A10–A0
Erases selected register.
WRITE
1
01
A10–A0
ERAL
1
00
10XXXXXXXXX
WRAL
1
00
01XXXXXXXXX
D7–D0
Writes data pattern D7–D0 into selected register.
D7–D0
Writes data pattern D7–D0 into all registers.
Erases all registers.
X = Don't care.
Functional Description
BUSY status of the device. DO = logical “0” indicates that programming is still in progress and no other instruction can be executed.
DO = logical “1” indicates that the device is READY for another
instruction. If CS is forced “low” the DO pin will return to the high
impedance state. After the programming cycle has been completed and DO = logical “1”, the DO pin can be reset back to the
high impedance state by clocking a logical “1” into the DI pin. (This
is also performed with the start bit on all op codes, thus clocking
an instruction has the same effect.)
Programming
The programming cycle is automatically started after entering the
LAST bit of the programming instruction string (unlike other
Microwire family members which use the falling edge of CS to
initiate programming). This feature, counting the number of instruction bits, decreases the likelihood of inadvertent programming and allows the programming to be cancelled before sending
out the last bit in the string (by bringing CS low).
Programming Instruction
Last Bit in String
WRITE
D0
WRAL
D0
ERASE
A0
ERAL
A0
Read (READ)
The READ instruction outputs serial data on the DO pin. After a
READ instruction is received, the instruction and address are
decoded, followed by data transfer from the selected memory
register into a serial-out shift register. A dummy bit (logical 0)
precedes the serial data output string. Output data changes are
initiated by a low to high transition of SK clock after the last address
bit (A0) is clocked in.
Erase/Write Enable (EWEN)
Note that, in the ERASE/ERAL instructions, the A0 bit is the last
bit in the string and clocking in that bit will initiate programming. In
order to maintain compatibility, CS may be brought low after
clocking in the last bit, but it is not necessary.
When VCC is applied to the part, it “powers up” in the Erase/Write
Disable (EWDS) state. Therefore, all programming modes must
be preceded by an Erase/Write Enable (EWEN) instruction. Once
an Erase/Write Enable instruction is executed, programming
remains enabled until an Erase/Write Disable (EWDS) instruction
is executed or VCC is removed from the part.
In all programming modes the READY/BUSY status of the device
can be determined by polling the DO pin. After clocking in the last
bit of the instruction sequence and with the CS held “high”, the DO
pin will exit the high impedance state and indicate the READY/
6
FM93C86A Rev. A
www.fairchildsemi.com
FM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
1024 by 16-Bit Organization (FM93C86A when ORG = VCC or NC)
instruction will be aborted. The self-timed programming cycle is
initiated on the rising edge of the SK clock as the last data bit (D0)
is clocked in. At this point, CS, SK and DI become don’t care
states. No separate ERASE cycle is required before a WRITE
instruction.
Erase/Write Disable (EWDS)
To protect against accidental data overwrites, the Erase/Write
Disable (EWDS) instruction disables all programming modes and
should follow all programming operations. Execution of a READ
instruction is independent of both the EWEN and EWDS instructions.
As in the ERASE instruction, after starting a WRITE cycle, the DO
pin indicates the READY/BUSY status of the chip if CS is held
“high”. DO = logical “0” indicates that programming is still in
progress. DO = logical “1” indicates that the register, at the
address specified in the instruction, has been written and that the
part is ready for another instruction.
Erase (ERASE)
The ERASE instruction will program all bits in the specified
register to the logical “1” state. The self-timed programming cycle
is initiated on the rising edge of the SK clock as the last address
bit (A0) is clocked in. At this point CS, SK and DI become don’t care
states. After starting an Erase cycle the DO pin indicates the
READY/BUSY status of the chip if CS is held “high”. DO = logical
“0” indicates that programming is still in progress. DO = logical “1”
indicates that the register, at the address specified in the instruction, has been erased.
Erase All (ERAL)
The ERAL instruction will simultaneously program all registers in
the memory array to the logical “1” state.
Write All (WRAL)
The WRAL instruction will simultaneously program all registers
with the data pattern specified in the instruction.
Write (WRITE)
The WRITE instruction is followed by 16 bits of data (or 8 bits of
data when using the FM93C86A in the x8 organization) to be
written into the specified address. Note that if the CS is brought
“low” before clocking in all of the data bits, then the WRITE
Timing Diagrams for the FM93C86A
Synchronous Data Timing
CS
SK
DI
VIH
VIL
VIH
VIL
VIH
tCSS
tSKS
tDIS
tSKH
tSKL
tDIH
VIL
VOH
DO (READ)
VOL
VOH
DO (PROGRAM)
VOL
tPD
tSV
tDH
tDH
tDF
tDF
STATUS VALID
DS800031-3
7
FM93C86A Rev. A
tCSH
www.fairchildsemi.com
FM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Functional Description (Continued)
ORG
Organization
AN
DN
VCC or NC
1024 x 16
A9
D15
VSS
2048 x 8
A10
D7
READ
CS
tCS
SK
1
DI
1
0
...
AN
A0
DO
0
...
DN
D0
DS800031-4
EWEN
DO = HI-Z
tCS
CS
SK
0
1
DI
0
1
...
X
1
X
ORG = VCC, 4 X’S
ORG = VSS, 5 X’S
DS800031-5
EWDS
DO = HI
Z
DO
HI-Z
tCS
CS
SK
1
DI
0
0
0
0
X
...
X
ORG = VCC, 4 X’S
ORG = VSS, 5 X’S
DS800031-6
ERASE
ERASE
tCS
CS
Standby
SK
DI
DO
1
1
1
...
AN
A0
Busy
HI-Z
Ready
HI-Z
tWP
DS800031-7
8
FM93C86A Rev. A
www.fairchildsemi.com
FM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Timing Diagrams for the FM93C86A (Continued)
Key for Timing Diagrams
Organization of Address and Data Fields for the FM93C86A
WRITE
tCS
CS
SK
1
DI
1
0
AN . . .
A0
DN . . .
D0
Busy
DO
Ready
tWP
DS800031-8
ERAL
tCS
CS
STANDBY
SK
1
DI
0
0
1
0
X
...
X
ORG = VCC, 4 X's
ORG = VSS, 5 X's
DO
BUSY
READY
READY STATUS SIGNAL RESETS
TO HI-Z AFTER CLOCKING IN
ONE SK CYCLE WITH DI = 1
tWP
DS800031-9
WRAL
tCS
CS
STANDBY
SK
DI
1
0
0
0
1
X
...
X
DN . . . D 0
ORG = VCC, 4 X's
ORG = VSS, 5 X's
DO
BUSY
tWP
READY
READY STATUS SIGNAL RESETS
TO HI-Z AFTER CLOCKING IN
ONE SK CYCLE WITH DI = 1
DS800031-10
9
FM93C86A Rev. A
www.fairchildsemi.com
FM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Timing Diagrams for the FM93C86A (Continued)
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
8° Max, Typ.
All leads
0.04
(0.102)
All lead tips
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020 Typ.
(0.356 - 0.508)
Molded Small Outline Package (M8)
Package Number M08A
10
FM93C86A Rev. A
www.fairchildsemi.com
FM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
(6.35 ± 0.127)
+
Pin #1 IDENT
0.032 ± 0.005
(0.813 ± 0.127)
RAD
5
1
1
2
3
0.040 Typ.
(1.016)
0.300 - 0.320
(7.62 - 8.128)
7
Pin #1
IDENT
Option 1
0.280 MIN
(7.112)
8
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-in-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
Français
Tel:
+33 (0) 1-6930-3696
Italiano
Tel:
+39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
11
FM93C86A Rev. A
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
www.fairchildsemi.com
FM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Physical Dimensions inches (millimeters) unless otherwise noted
FM93CS06
(MICROWIRE™ Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
General Description
Features
FM93CS06 is a 256-bit CMOS non-volatile EEPROM organized
as 16 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compatible to many of standard Microcontrollers and Microprocessors.
FM93CS06 offers programmable write protection to the memory
array using a special register called Protect Register. Selected
memory locations can be protected against write by programming
this Protect Register with the address of the first memory location
to be protected (all locations greater than or equal to this first
address are then protected from further change). Additionally, this
address can be “permanently locked” into the device, making all
future attempts to change data impossible. In addition this device
features “sequential read”, by which, entire memory can be read
in one cycle instead of multiple single byte read cycles. There are
10 instructions implemented on the FM93CS06, 5 of which are for
memory operations and the remaining 5 are for Protect Register
operations. This device is fabricated using Fairchild Semiconductor floating-gate CMOS process for high reliability, high endurance
and low power consumption.
■ Wide VCC 2.7V - 5.5V
■ Programmable write protection
■ Sequential register read
■ Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
■ No Erase instruction required before Write instruction
■ Self timed write cycle
■ Device status during programming cycles
■ 40 year data retention
■ Endurance: 1,000,000 data changes
■ Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
“LZ” and “L” versions of FM93CS06 offer very low standby current
making them suitable for low power applications. This device is offered
in both SO and TSSOP packages for small space considerations.
Functional Diagram
VCC
CS
INSTRUCTION
DECODER
CONTROL LOGIC
AND CLOCK
GENERATORS
SK
DI
INSTRUCTION
REGISTER
ADDRESS
REGISTER
DECODER
COMPARATOR
AND
WRITE ENABLE
PROTECT
REGISTER
PRE
PE
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
EEPROM ARRAY
16
READ/WRITE AMPS
VSS
16
DATA IN/OUT REGISTER
16 BITS
DO
© 1999 Fairchild Semiconductor Corporation
FM93CS06 Rev. A
DATA OUT BUFFER
1
www.fairchildsemi.com
FM93CS06 (MICROWIRE Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
February 2000
FM93CS06 (MICROWIRE Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
Connection Diagram
Dual-In-Line Package (N)
8–Pin SO (M8) and 8–Pin TSSOP (MT8)
CS
1
8
VCC
SK
2
7
PRE
DI
3
6
PE
DO
4
5
GND
Top View
Package Number
N08E, M08A and MTC08
Pin Names
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
PE
Program Enable
PRE
Protect Register Enable
VCC
Power Supply
Ordering Information
FM
93
CS
XX
LZ
E
XXX
Letter
Description
N
M8
MT8
8-pin DIP
8-pin SO
8-pin TSSOP
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
06
256 bits
C
CS
CMOS
Data protect and sequential
read
93
MICROWIRE
Package
Density
Interface
Fairchild Memory Prefix
2
FM93CS06 Rev. A
www.fairchildsemi.com
Operating Conditions
Ambient Storage Temperature
Ambient Operating Temperature
FM93CS06
FM93CS06E
FM93CS06V
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
-65°C to +150°C
+6.5V to -0.3V
+300°C
ESD rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
4.5V to 5.5V
2000V
DC and AC Electrical Characteristics VCC = 4.5V to 5.5V unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
ICCA
Operating Current
CS = VIH, SK=1.0 MHz
1
mA
ICCS
Standby Current
CS = VIL
50
µA
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
(Note 2)
±-1
µA
VIL
VIH
Input Low Voltage
Input High Voltage
0.8
VCC +1
V
0.4
V
0.2
V
1
MHz
-0.1
2
VOL1
VOH1
Output Low Voltage
Output High Voltage
IOL = 2.1 mA
IOH = -400 µA
2.4
VOL2
VOH2
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
VCC - 0.2
fSK
SK Clock Frequency
(Note 3)
tSKH
SK High Time
0°C to +70°C
-40°C to +125°C
250
300
ns
ns
tSKL
SK Low Time
250
tSKS
SK Setup Time
50
ns
tCS
Minimum CS Low Time
250
ns
tCSS
CS Setup Time
100
ns
tPRES
PRE Setup Time
50
ns
tDH
DO Hold Time
70
ns
tPES
PE Setup Time
50
ns
tDIS
DI Setup Time
100
ns
tCSH
CS Hold Time
0
ns
tPEH
PE Hold Time
250
ns
tPREH
ns
(Note 4)
PRE Hold Time
50
tDIH
DI Hold Time
20
tPD
Output Delay
tSV
CS to Status Valid
tDF
CS to DO in Hi-Z
tWP
Write Cycle Time
CS = VIL
3
FM93CS06 Rev. A
ns
500
ns
500
ns
100
ns
10
ms
www.fairchildsemi.com
FM93CS06 (MICROWIRE Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
Absolute Maximum Ratings (Note 1)
Operating Conditions
Ambient Storage Temperature
Ambient Operating Temperature
FM93CS06L/LZ
FM93CS06LE/LZE
FM93CS06LV/LZV
-65°C to +150°C
All Input or Output Voltages
with Respect to Ground
+6.5V to -0.3V
Lead Temperature
(Soldering, 10 sec.)
+300°C
ESD rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
2.7V to 5.5V
2000V
DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified
Symbol
Parameter
Conditions
ICCA
Operating Current
CS = VIH, SK=1.0 MHz
ICCS
CS = VIL
IIL
IOL
VIL
VIH
VOL
VOH
fSK
tSKH
tSKL
tSKS
Standby Current
L
LZ (2.7V to 4.5V)
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
SK Low Time
SK Setup Time
tCS
Minimum CS Low Time
(Note 4)
Min
VIN = 0V to VCC
(Note 2)
-0.1
0.8VCC
IOL = 10µA
IOH = -10µA
(Note 3)
0.9VCC
0
1
1
0.2
Max
Units
1
mA
10
1
±1
µA
µA
µA
0.15VCC
VCC +1
0.1VCC
V
250
KHz
µs
µs
µs
V
1
µs
tCSS
tPRES
tDH
tPES
tDIS
CS Setup Time
PRE Setup Time
DO Hold Time
PE Setup Time
DI Setup Time
0.2
50
70
50
0.4
µs
ns
ns
ns
µs
tCSH
tPEH
tPREH
tDIH
tPD
CS Hold Time
PE Hold Time
PRE Hold Time
DI Hold Time
Output Delay
0
250
50
0.4
2
ns
ns
ns
µs
µs
1
µs
0.4
15
µs
ms
tSV
CS to Status Valid
tDF
tWP
CS to DO in Hi-Z
Write Cycle Time
CS = VIL
Capacitance TA = 25°C, f = 1 MHz (Note 5)
Symbol
Test
Typ
Max
Units
COUT
Output Capacitance
5
pF
CIN
Input Capacitance
5
pF
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2:
Typical leakage values are in the 20nA range.
Note 3: The shortest allowable SK clock period = 1/fSK (as shown under the fSK parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not
allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
Note 5:
AC Test Conditions
This parameter is periodically sampled and not 100% tested.
VCC Range
VIL/VIH
Input Levels
VIL/VIH
Timing Level
VOL/VOH
Timing Level
IOL/IOH
2.7V ≤ VCC ≤ 5.5V
0.3V/1.8V
1.0V
0.8V/1.5V
±10µA
4.5V ≤ VCC ≤ 5.5V
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(Extended Voltage Levels)
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
FM93CS06 Rev. A
www.fairchildsemi.com
FM93CS06 (MICROWIRE Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
Absolute Maximum Ratings (Note 1)
Program Enable (PE)
Chip Select (CS)
This is an active high input pin to the device and is used to enable
operations, that are write in nature, to the memory array and to the
Protect register. When this pin is held high, operations that are
“write” in nature are enabled. When this pin is held low, operations
that are “write” in nature are disabled. This pin operates in
conjunction with PRE pin. Refer Table1 for functional matrix of this
pin for various operations.
This is an active high input pin to FM93CS06 EEPROM (the device)
and is generated by a master that is controlling the device. A high
level on this pin selects the device and a low level deselects the
device. All serial communications with the device is enabled only
when this pin is held high. However this pin cannot be permanently
tied high, as a rising edge on this signal is required to reset the
internal state-machine to accept a new cycle and a falling edge to
initiate an internal programming after a write cycle. All activity on the
SK, DI and DO pins are ignored while CS is held low.
Microwire Interface
A typical communication on the Microwire bus is made through the
CS, SK, DI and DO signals. To facilitate various operations on the
Memory array and on the Protect Register, a set of 10 instructions
are implemented on FM93CS06. The format of each instruction is
listed in Table 1.
Serial Clock (SK)
This is an input pin to the device and is generated by the master that
is controlling the device. This is a clock signal that synchronizes the
communication between a master and the device. All input information (DI) to the device is latched on the rising edge of this clock input,
while output data (DO) from the device is driven from the rising edge
of this clock input. This pin is gated by CS signal.
Instruction
Each of the above 10 instructions is explained under individual
instruction descriptions.
Serial Input (DI)
Start Bit
This is an input pin to the device and is generated by the master
that is controlling the device. The master transfers Input information (Start bit, Opcode bits, Array addresses and Data) serially via
this pin into the device. This Input information is latched on the
rising edge of the SCK. This pin is gated by CS signal.
This is a 1-bit field and is the first bit that is clocked into the device
when a Microwire cycle starts. This bit has to be “1” for a valid cycle
to begin. Any number of preceding “0” can be clocked into the
device before clocking a “1”.
Serial Output (DO)
This is a 2-bit field and should immediately follow the start bit.
These two bits (along with PRE, PE signals and 2 MSB of address
field) select a particular instruction to be executed.
Opcode
This is an output pin from the device and is used to transfer Output
data via this pin to the controlling master. Output data is serially
shifted out on this pin from the rising edge of the SCK. This pin is
active only when the device is selected.
Address Field
This is a 6-bit field and should immediately follow the Opcode bits.
In FM93CS06, only the LSB 4 bits are used for address decoding
during READ, WRITE and PRWRITE instructions. During these
instructions (READ, WRITE and PRWRITE), the MSB 2 bits are
"don't care" (can be 0 or 1). During all other instructions (with the
exception of PRREAD), the MSB 2 bits are used to decode
instruction (along with Opcode bits, PRE and PE signals).
Protect Register Enable (PRE)
This is an active high input pin to the device and is used to
distinguish operations to memory array and operations to Protect
Register. When this pin is held low, operations to the memory
array are enabled. When this pin is held high, operations to the
Protect Register are enabled. This pin operates in conjunction
with PE pin. Refer Table1 for functional matrix of this pin for
various operations.
Data Field
This is a 16-bit field and should immediately follow the Address
bits. Only the WRITE and WRALL instructions require this field.
D15 (MSB) is clocked first and D0 (LSB) is clocked last (both
during writes as well as reads).
TABLE 1. Instruction set
Instruction
Start Bit
Opcode Field
PRE Pin
PE Pin
READ
1
10
X
Address Field
X
A3
A2
A1
A0
0
X
WEN
1
00
1
1
X
X
X
X
0
1
WRITE
1
01
X
X
A3
A2
A1
A0
D15-D0
0
1
WRALL
1
00
0
1
X
X
X
X
D15-D0
0
1
WDS
1
00
0
0
X
X
X
X
0
X
PRREAD
1
10
X
X
X
X
X
X
1
X
PREN
1
00
1
1
X
X
X
X
1
1
PRCLEAR
1
11
1
1
1
1
1
1
1
1
PRWRITE
1
01
X
X
A3
A2
A1
A0
1
1
PRDS
1
00
0
0
0
0
0
0
1
1
5
FM93CS06 Rev. A
Data Field
www.fairchildsemi.com
FM93CS06 (MICROWIRE Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
Pin Description
A typical Microwire cycle starts by first selecting the device
(bringing the CS signal high). Once the device is selected, a valid
Start bit (“1”) should be issued to properly recognize the cycle.
Following this, the 2-bit opcode of appropriate instruction should
be issued. After the opcode bits, the 6-bit address information
should be issued. For certain instructions, some (or all) of these
6 bits are don’t care values (can be “0” or “1”), but they should still
be issued. Following the address information, depending on the
instruction (WRITE and WRALL), 16-Bit data is issued. Otherwise, depending on the instruction (READ and PRREAD), the
device starts to drive the output data on the DO line. Other
instructions perform certain control functions and do not deal with
data bits. The Microwire cycle ends when the CS signal is brought
low. However during certain instructions, falling edge of the CS
signal initiates an internal cycle (Programming), and the device
remains busy till the completion of the internal cycle. Each of the
10 instructions is explained in detail in the following sections.
3) Write (WRITE)
WRITE instruction allows write operation to a specified location in
the memory with a specified data. This instruction is valid only
when the following are true:
■ Device is write-enabled (Refer WEN instruction)
■ Address of the write location is not write-protected
■ PE pin is held high during this cycle
■ PRE pin should be held low during this cycle
Input information (Start bit, Opcode, Address and Data) for this
WRITE instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Memory Instructions
Following five instructions, READ, WEN, WRITE, WRALL and
WDS are specific to operations intended for memory array. The
PRE pin should be held low during these instructions.
1) Read and Sequential Read (READ)
The status of the internal programming cycle can be polled at any
time by bringing the CS signal high again, after tCS interval. When
CS signal is high, the DO pin indicates the READY/BUSY status
of the chip. DO = logical 0 indicates that the programming is still
in progress. DO = logical 1 indicates that the programming is
finished and the device is ready for another instruction. It is not
required to provide the SK clock during this status polling. While
the device is busy, it is recommended that no new instruction be
issued. Refer Write cycle diagram.
READ instruction allows data to be read from a selected location
in the memory array. Input information (Start bit, Opcode and
Address) for this instruction should be issued as listed under
Table1. Upon receiving a valid input information, decoding of the
opcode and the address is made, followed by data transfer from
the selected memory location into a 16-bit serial-out shift register.
This 16-bit data is then shifted out on the DO pin. D15 bit (MSB)
is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit
(logical 0) precedes this 16-bit data output string. Output data
changes are initiated on the rising edge of the SK clock. After
reading the 16-bit data, the CS signal can be brought low to end
the Read cycle. The PRE pin should be held low during this cycle.
Refer Read cycle diagram.
It is also recommended to follow this instruction (after the device
becomes READY) with a Write Disable (WDS) instruction to
safeguard data against corruption due to spurious noise, inadvertent writes etc.
4) Write All (WRALL)
This device also offers “sequential memory read” operation to
allow reading of data from the additional memory locations instead
of just one location. It is started in the same manner as normal read
but the cycle is continued to read further data (instead of terminating after reading the first 16-bit data). After providing 16-bit data,
the device automatically increments the address pointer to the
next location and continues to provide the data from that location.
Any number of locations can be read out in this manner, however,
after reading out from the last location, the address pointer points
back to the first location. If the cycle is continued further, data will
be read from this first location onward. In this mode of read, the
dummy-bit is present only when the very first data is read (like
normal read cycle) and is not present on subsequent data reads.
The PRE pin should be held low during this cycle. Refer Sequential Read cycle diagram.
Write all (WRALL) instruction is similar to the Write instruction
except that WRALL instruction will simultaneously program all
memory locations with the data pattern specified in the instruction.
This instruction is valid only when the following are true:
■ Protect Register has been cleared (Refer PRCLEAR
instruction)
■ Device is write-enabled (Refer WEN instruction)
■ PE pin is held high during this cycle
■ PRE pin should be held low during this cycle
Input information (Start bit, Opcode, Address and Data) for this
WRALL instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer Write All
cycle diagram.
2) Write Enable (WEN)
When VCC is applied to the part, it “powers up” in the Write Disable
(WDS) state. Therefore, all programming operations (for both
memory array and Protect Register) must be preceded by a Write
Enable (WEN) instruction. Once a Write Enable instruction is
executed, programming remains enabled until a Write Disable
(WDS) instruction is executed or VCC is completely removed from
6
FM93CS06 Rev. A
www.fairchildsemi.com
FM93CS06 (MICROWIRE Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
the part. Input information (Start bit, Opcode and Address) for this
WEN instruction should be issued as listed under Table1. The
device becomes write-enabled at the end of this cycle when the
CS signal is brought low. The PRE pin should be held low during
this cycle. Execution of a READ instruction is independent of WEN
instruction. Refer Write Enable cycle diagram.
Functional Description
Write Disable (WDS) instruction disables all programming operations and is recommended to follow all programming operations.
Executing this instruction after a valid write instruction would
protect against accidental data disturb due to spurious noise,
glitches, inadvertent writes etc. Input information (Start bit, Opcode
and Address) for this WDS instruction should be issued as listed
under Table1. The device becomes write-disabled at the end of
this cycle when the CS signal is brought low. Execution of a READ
instruction is independent of WDS instruction. Refer Write Disable
cycle diagram.
■ PREN instruction was executed immediately prior to
PRCLEAR instruction
■ PE pin is held high during this cycle
■ PRE pin is held high during this cycle
Input information (Start bit, Opcode and Address) for this PRCLEAR
instruction should be issued as listed under Table1. After inputting
the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed clear cycle. It takes tWP time (Refer
appropriate DC and AC Electrical Characteristics table) for the
internal clear cycle to finish. During this time, the device remains
busy and is not ready for another instruction. Status of the internal
programming can be polled as described under WRITE instruction
description. While the device is busy, it is recommended that no
new instruction be issued. Refer Protect Register Clear cycle
diagram.
Protect Register Instructions
Following five instructions, PRREAD, PREN, PRCLEAR,
PRWRITE and PRDS are specific to operations intended for
Protect Register. The PRE pin should be held high during these
instructions.
1) Protect Register Read (PRREAD)
This instruction reads the content of the internal Protect Register.
Content of this register is 6-bit wide and is the starting address of
the “write-protected” section of the memory array. All memory
locations greater than or equal to this address are write-protected.
Input information (Start bit, Opcode and Address) for this PRREAD
instruction should be issued as listed under Table1. Upon receiving a valid input information, decoding of the opcode and the
address is made, followed by data transfer (address information)
from the Protect Register. This 6-bit data is then shifted out on the
DO pin with the MSB first and the LSB last. Like the READ
instruction a dummy-bit (logical 0) precedes this 6-bit data output
string. Output data changes are initiated on the rising edge of the
SK clock. After reading the 6-bit data, the CS signal can be
brought low to end the PRREAD cycle. The PRE pin should be
held high during this cycle. Refer Protect Register Read cycle
diagram.
4) Protect Register Write (PRWRITE)
This instruction is used to write the starting address of the memory
section to be write-protected into the Protect register. After the
execution of PRWRITE instruction, all memory locations greater
than or equal to this address are write-protected. PRWRITE
instruction is enabled (valid) only the following are true:
■ PRCLEAR instruction was executed first (to clear the Protect
Register)
■ PREN instruction was executed immediately prior to
PRWRITE instruction
■ PE pin is held high during this cycle
■ PRE pin is held high during this cycle
Input information (Start bit, Opcode and Address) for this PRWRITE
instruction should be issued as listed under Table1. After inputting
the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer Protect
Register Write cycle diagram.
Though the content of this register is 6-bit wide, only the last 4 bits
(LSB) are valid for FM93CS06 device.
2) Protect Register Enable (PREN)
This instruction is required to enable PRCLEAR, PRWRITE and
PRDS instructions and should be executed prior to executing
PRCLEAR, PRWRITE and PRDS instructions. However, this
PREN instruction is enabled (valid) only the following are true
■ Device is write-enabled (Refer WEN instruction)
■ PE pin is held high during this cycle
■ PRE pin is held high during this cycle
5) Protect Register Disable (PRDS)
Input information (Start bit, Opcode and Address) for this PREN
instruction should be issued as listed under Table1. The Protect
Register becomes enabled for PRCLEAR, PRWRITE and PRDS
instructions at the end of this cycle when the CS signal is brought
low. Note that this PREN instruction must immediately precede
a PRCLEAR, PRWRITE or PRDS instruction. In other words, no
other instruction should be executed between a PREN instruction
and a PRCLEAR, PRWRITE or PRDS instruction. Refer Protect
Register Enable cycle diagram.
Unlike all other instructions, this instruction is a one-time-only
instruction which when executed permanently write-protects
the Protect Register and renders it unalterable in the future. This
instruction is useful to safeguard vital data (typically read only
data) in the memory against any possible corruption. PRDS
instruction is enabled (valid) only the following are true:
■ PREN instruction was executed immediately prior to PRDS
instruction
3) Protect Register Clear (PRCLEAR)
■ PE pin is held high during this cycle
This instruction clears the content of the Protect register and
therefore enables write operations (WRITE or WRALL) to all
memory locations. Executing this instruction will program the
■ PRE pin is held high during this cycle
7
FM93CS06 Rev. A
www.fairchildsemi.com
FM93CS06 (MICROWIRE Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
content of the Protect Register with a pattern of all 1s. However,
in this case, WRITE operation to the last memory address
(0x001111) is still enabled. PRCLEAR instruction is enabled
(valid) only when the following are true:
5) Write Disable (WDS)
Clearing of Ready/Busy status
When programming is in progress, the Data-Out pin will display
the programming status as either BUSY (low) or READY (high)
when CS is brought high (DO output will be tri-stated when CS is
low). To restate, during programming, the CS pin may be brought
high and low any number of times to view the programming status
without affecting the programming operation. Once programming
is completed (Output in READY state), the output is ‘cleared’
(returned to normal tri-state condition) by clocking in a Start Bit.
After the Start Bit is clocked in, the output will return to a tri-stated
condition. When clocked in, this Start Bit can be the first bit in a
command string, or CS can be brought low again to reset all
internal circuits. Refer Clearing Ready Status diagram.
Related Document
Application Note: AN758 - Using Fairchild’s MICROWIRE™ EEPROM.
8
FM93CS06 Rev. A
www.fairchildsemi.com
FM93CS06 (MICROWIRE Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
Input information (Start bit, Opcode and Address) for this PRDS
instruction should be issued as listed under Table1. After inputting
the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. The Protect
Register is permanently write-protected at the end of this cycle.
Refer Protect Register Disable cycle diagram.
FM93CS06 (MICROWIRE Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams
;
;;
;;; ;; ;;
;;; ;; ;;
;;; ;;
;
;;;;;; ;;
;;;;;; ;;
;;;; ; ;;
;;; ;;;;;
;; ;;;;;;;;;
;;;;;;
; ;;;;;;;;
;
;;;;;;
; ;;;;;;;
;;;;;;;;
;
; ;;;;;;;
;;;;;;;;;
; ;
SYNCHRONOUS DATA TIMING
CS
SK
tSKS
tCSS
tSKH
tSKL
tPRES
PRE
tPES
PE
tDIS
tDIH
Valid
Input
DI
tPD
;
;
;
; ;
;
; ;
;
; ; ;
; ;;;
;
; ;;;
;
; ;;;
;
; ;;
;
;
; ;;;;;;;;;;;;;;;;;;;
; ;
;
;;;;;;;;;;;;;;;;;;;;;
;;;;;;;
; ;;;;;;;; ;
;;;;;; ;;;;;;;; ;
;
tCSH
tPREH
tPEH
Valid
Input
tDF
tPD
tDH
Valid
Output
DO (Data Read)
tSV
DO (Status Read)
Valid
Output
tDF
Valid Status
NORMAL READ CYCLE (READ)
;;;;
;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
1
0
A5
Opcode
Bits(2)
A4
A1
Address
Bits(6)
High - Z
DO
A0
;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
;;;
;;;
0
D15
D1
D0
Dummy
Bit
93CS06:
Address bits patter n -> x-x-A3-A2-A1-A0; (x -> Don't Care, can be 0 or 1); (A3-A0 -> User defined)
SEQUENTIAL READ CYCLE (PRE = 0; PE = X)
;;;;
;;;;
PRE
tCS
CS
SK
DI
1
Star t
Bit
DO
1
0
A5
Opcode
Bits(2)
High - Z
A0
Address
Bits(6)
;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;
;;;
;;;
0
Dummy
Bit
D15
D0
Data(n)
D15
D0
Data(n+1)
D15
D0
Data(n+2)
93CS06:
Address bits patter n -> x-x-A3-A2-A1-A0; (x -> Don't Care, can be 0 or 1); (A3-A0 -> User defined)
9
FM93CS06 Rev. A
www.fairchildsemi.com
FM93CS06 (MICROWIRE Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams (Continued)
WRITE ENABLE CYCLE (WEN)
PRE
PE
tCS
CS
SK
DI
1
0
Star t
Bit
0
A5
A4
Opcode
Bits(2)
A1
A0
Address
Bits(6)
High - Z
DO
93CS06:
A d d r e s s b i t s p a t t e r n - > 1 - 1 - x - x - x - x ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 )
WRITE DISABLE CYCLE (WDS)
PRE
PE
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
tCS
CS
SK
DI
1
0
Star t
Bit
0
A5
A4
Opcode
Bits(2)
A1
A0
Address
Bits(6)
High - Z
DO
93CS06:
Address bits patter n -> 0-0-x-x-x-x; (x -> Don't Care, can be 0 or 1)
WRITE CYCLE (WRITE)
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
0
1
Opcode
Bits(2)
A5
A4
A1
A0
D15 D14
Address
Bits(6)
Data
Bits(16)
D1
D0
tWP
High - Z
DO
Ready
Busy
93CS06:
A d d r e s s b i t s p a t t e r n - > x - x - A 3 - A 2 - A 1 - A 0 ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 ) ; ( A 3 - A 0 - > U s e r d e f i n e d )
Data bits pattern
-> User defined
10
FM93CS06 Rev. A
www.fairchildsemi.com
WRITE ALL CYCLE (WRALL)
PRE
PE
tCS
CS
SK
1
DI
Star t
Bit
0
0
A5
A4
Opcode
Bits(2)
A1
A0
D15 D14
Address
Bits(6)
D1
D0
tWP
Data
Bits(16)
High - Z
DO
Ready
Busy
93CS06:
Address bits patter n -> 0-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Data bits patter n
-> User defined
PROTECT REGISTER READ CYCLE (PRREAD)
;;;;
;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
1
0
A5
Opcode
Bits(2)
A4
A1
Address
Bits(6)
High - Z
DO
A0
;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
;;;
;;;
0
D5
D1
D0
Dummy
Bit
93CS06:
Address bits patter n -> x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Of the 6-bit output data(D5-D0), only D3 to D0 are valid and they correspond to A3 to A0 respectively.
PROTECT REGISTER ENABLE CYCLE (PREN)
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
0
0
Opcode
Bits(2)
A5
A4
A1
A0
Address
Bits(6)
High - Z
DO
93CS06:
Address bits patter n -> 1-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)
11
FM93CS06 Rev. A
www.fairchildsemi.com
FM93CS06 (MICROWIRE Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams (Continued)
FM93CS06 (MICROWIRE Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams (Continued)
PROTECT REGISTER CLEAR CYCLE (PRCLEAR)
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
PRE
PE
tCS
CS
SK
1
DI
1
Star t
Bit
1
Opcode
Bits(2)
DO
A5
A4
A1
A0
tWP
Address
Bits(6)
High - Z
Ready
Busy
93CS06:
Address bits patter n -> 1-1-1-1-1-1
PROTECT REGISTER WRITE CYCLE (PRWRITE)
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
0
Star t
Bit
1
Opcode
Bits(2)
DO
A5
A4
High - Z
A1
A0
tWP
Address
Bits(6)
Ready
Busy
93CS06:
Address bits patter n -> x-x-A3-A2-A1-A0; (x -> Don't Care, can be 0 or 1); (A3-A0 -> User defined)
PROTECT REGISTER DISABLE CYCLE (PRDS)
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
DO
0
0
Opcode
Bits(2)
A5
High - Z
A4
A1
Address
Bits(6)
A0
tWP
Ready
Busy
93CS06:
Address bits patter n -> 0-0-0-0-0-0
12
FM93CS06 Rev. A
www.fairchildsemi.com
FM93CS06 (MICROWIRE Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams (Continued)
CLEARING READY STATUS
PRE
PE
;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;
CS
SK
DI
Star t
Bit
DO
High - Z
Ready
High - Z
Busy
Note: This Star t bit can also be par t of a next instr uction. Hence the cycle
can be continued(instead of getting ter minated, as shown) as if a new
instr uction is being issued.
13
FM93CS06 Rev. A
www.fairchildsemi.com
FM93CS06 (MICROWIRE Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
8° Max, Typ.
All leads
0.04
(0.102)
All lead tips
0.053 - 0.069
(1.346 - 1.753)
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020 Typ.
(0.356 - 0.508)
Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8)
Package Number M08A
14
FM93CS06 Rev. A
www.fairchildsemi.com
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0098
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
15
FM93CS06 Rev. A
www.fairchildsemi.com
FM93CS06 (MICROWIRE Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
+
Pin #1 IDENT
8
0.032 ± 0.005
(6.35 ± 0.127)
Pin #1
IDENT
1
Option 1
1
0.280 MIN
(7.112)
0.300 - 0.320
(7.62 - 8.128)
7
(0.813 ± 0.127)
RAD
5
2
3
0.040 Typ.
(1.016)
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
0.039
(0.991)
(3.683 - 5.080)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
Français
Tel:
+33 (0) 1-6930-3696
Italiano
Tel:
+39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
16
FM93CS06 Rev. A
www.fairchildsemi.com
FM93CS06 (MICROWIRE Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
Physical Dimensions inches (millimeters) unless otherwise noted
FM93CS46
(MICROWIRE™ Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
General Description
Features
FM93CS46 is a 1024-bit CMOS non-volatile EEPROM organized
as 64 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compatible to many of standard Microcontrollers and Microprocessors.
FM93CS46 offers programmable write protection to the memory
array using a special register called Protect Register. Selected
memory locations can be protected against write by programming
this Protect Register with the address of the first memory location
to be protected (all locations greater than or equal to this first
address are then protected from further change). Additionally, this
address can be “permanently locked” into the device, making all
future attempts to change data impossible. In addition this device
features “sequential read”, by which, entire memory can be read
in one cycle instead of multiple single byte read cycles. There are
10 instructions implemented on the FM93CS46, 5 of which are for
memory operations and the remaining 5 are for Protect Register
operations. This device is fabricated using Fairchild Semiconductor floating-gate CMOS process for high reliability, high endurance
and low power consumption.
■ Wide VCC 2.7V - 5.5V
■ Programmable write protection
■ Sequential register read
■ Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
■ No Erase instruction required before Write instruction
■ Self timed write cycle
■ Device status during programming cycles
■ 40 year data retention
■ Endurance: 1,000,000 data changes
■ Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
“LZ” and “L” versions of FM93CS46 offer very low standby current
making them suitable for low power applications. This device is offered
in both SO and TSSOP packages for small space considerations.
Functional Diagram
VCC
CS
INSTRUCTION
DECODER
CONTROL LOGIC
AND CLOCK
GENERATORS
SK
DI
INSTRUCTION
REGISTER
ADDRESS
REGISTER
DECODER
COMPARATOR
AND
WRITE ENABLE
PROTECT
REGISTER
PRE
PE
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
EEPROM ARRAY
16
READ/WRITE AMPS
VSS
16
DATA IN/OUT REGISTER
16 BITS
DO
© 1999 Fairchild Semiconductor Corporation
FM93CS46 Rev. A
DATA OUT BUFFER
1
www.fairchildsemi.com
FM93CS46 (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
February 2000
Dual-In-Line Package (N)
8–Pin SO (M8) and 8–Pin TSSOP (MT8)
CS
1
SK
2
DI
3
DO
4
Normal
Pinout
8
VCC
PRE
1
7
PRE
VCC
2
6
PE
CS
3
5
GND
SK
4
Rotated
Pinout
8
PE
7
GND
6
DO
5
DI
Top View
Package Number
N08E, M08A and MTC08
Pin Names
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
PE
Program Enable
PRE
Protect Register Enable
VCC
Power Supply
Ordering Information
FM
93
CS
XX
T
LZ
E
XXX
Letter
Description
N
M8
MT8
8-pin DIP
8-pin SO
8-pin TSSOP
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
Blank
T
Normal Pin Out
Rotated Pin Out
46
1024 bits
C
CS
CMOS
Data protect and sequential
read
93
MICROWIRE
Package
Density
Interface
Fairchild Memory Prefix
2
FM93CS46 Rev. A
www.fairchildsemi.com
FM93CS46 (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
Connection Diagram
Operating Conditions
Ambient Storage Temperature
Ambient Operating Temperature
FM93CS46
FM93CS46E
FM93CS46V
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
-65°C to +150°C
+6.5V to -0.3V
+300°C
ESD rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
4.5V to 5.5V
2000V
DC and AC Electrical Characteristics VCC = 4.5V to 5.5V unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
ICCA
Operating Current
CS = VIH, SK=1.0 MHz
1
mA
ICCS
Standby Current
CS = VIL
50
µA
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
(Note 2)
±-1
µA
VIL
VIH
Input Low Voltage
Input High Voltage
0.8
VCC +1
V
0.4
V
0.2
V
1
MHz
-0.1
2
VOL1
VOH1
Output Low Voltage
Output High Voltage
IOL = 2.1 mA
IOH = -400 µA
2.4
VOL2
VOH2
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
VCC - 0.2
fSK
SK Clock Frequency
(Note 3)
tSKH
SK High Time
0°C to +70°C
-40°C to +125°C
250
300
ns
ns
tSKL
SK Low Time
250
tSKS
SK Setup Time
50
ns
tCS
Minimum CS Low Time
250
ns
tCSS
CS Setup Time
100
ns
tPRES
PRE Setup Time
50
ns
tDH
DO Hold Time
70
ns
tPES
PE Setup Time
50
ns
tDIS
DI Setup Time
100
ns
tCSH
CS Hold Time
0
ns
tPEH
PE Hold Time
250
ns
tPREH
ns
(Note 4)
PRE Hold Time
50
tDIH
DI Hold Time
20
tPD
Output Delay
tSV
CS to Status Valid
tDF
CS to DO in Hi-Z
tWP
Write Cycle Time
CS = VIL
3
FM93CS46 Rev. A
ns
500
ns
500
ns
100
ns
10
ms
www.fairchildsemi.com
FM93CS46 (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
Absolute Maximum Ratings (Note 1)
Operating Conditions
Ambient Storage Temperature
Ambient Operating Temperature
FM93CS46L/LZ
FM93CS46LE/LZE
FM93CS46LV/LZV
-65°C to +150°C
All Input or Output Voltages
with Respect to Ground
+6.5V to -0.3V
Lead Temperature
(Soldering, 10 sec.)
+300°C
ESD rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
2.7V to 5.5V
2000V
DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified
Symbol
Parameter
Conditions
ICCA
Operating Current
CS = VIH, SK=1.0 MHz
ICCS
CS = VIL
IIL
IOL
VIL
VIH
VOL
VOH
fSK
tSKH
tSKL
tSKS
Standby Current
L
LZ (2.7V to 4.5V)
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
SK Low Time
SK Setup Time
tCS
Minimum CS Low Time
(Note 4)
Min
VIN = 0V to VCC
(Note 2)
-0.1
0.8VCC
IOL = 10µA
IOH = -10µA
(Note 3)
0.9VCC
0
1
1
0.2
Max
Units
1
mA
10
1
±1
µA
µA
µA
0.15VCC
VCC +1
0.1VCC
V
250
KHz
µs
µs
µs
V
1
µs
tCSS
tPRES
tDH
tPES
tDIS
CS Setup Time
PRE Setup Time
DO Hold Time
PE Setup Time
DI Setup Time
0.2
50
70
50
0.4
µs
ns
ns
ns
µs
tCSH
tPEH
tPREH
tDIH
tPD
CS Hold Time
PE Hold Time
PRE Hold Time
DI Hold Time
Output Delay
0
250
50
0.4
2
ns
ns
ns
µs
µs
1
µs
0.4
15
µs
ms
tSV
CS to Status Valid
tDF
tWP
CS to DO in Hi-Z
Write Cycle Time
CS = VIL
Capacitance TA = 25°C, f = 1 MHz (Note 5)
Symbol
Test
Typ
Max
Units
COUT
Output Capacitance
5
pF
CIN
Input Capacitance
5
pF
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2:
Typical leakage values are in the 20nA range.
Note 3: The shortest allowable SK clock period = 1/fSK (as shown under the fSK parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not
allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
Note 5:
AC Test Conditions
This parameter is periodically sampled and not 100% tested.
VCC Range
VIL/VIH
Input Levels
VIL/VIH
Timing Level
VOL/VOH
Timing Level
IOL/IOH
2.7V ≤ VCC ≤ 5.5V
0.3V/1.8V
1.0V
0.8V/1.5V
±10µA
4.5V ≤ VCC ≤ 5.5V
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(Extended Voltage Levels)
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
FM93CS46 Rev. A
www.fairchildsemi.com
FM93CS46 (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
Absolute Maximum Ratings (Note 1)
Program Enable (PE)
Chip Select (CS)
This is an active high input pin to the device and is used to enable
operations, that are write in nature, to the memory array and to the
Protect register. When this pin is held high, operations that are
“write” in nature are enabled. When this pin is held low, operations
that are “write” in nature are disabled. This pin operates in
conjunction with PRE pin. Refer Table1 for functional matrix of this
pin for various operations.
This is an active high input pin to FM93CS46 EEPROM (the device)
and is generated by a master that is controlling the device. A high
level on this pin selects the device and a low level deselects the
device. All serial communications with the device is enabled only
when this pin is held high. However this pin cannot be permanently
tied high, as a rising edge on this signal is required to reset the
internal state-machine to accept a new cycle and a falling edge to
initiate an internal programming after a write cycle. All activity on the
SK, DI and DO pins are ignored while CS is held low.
Microwire Interface
A typical communication on the Microwire bus is made through the
CS, SK, DI and DO signals. To facilitate various operations on the
Memory array and on the Protect Register, a set of 10 instructions
are implemented on FM93CS46. The format of each instruction is
listed in Table 1.
Serial Clock (SK)
This is an input pin to the device and is generated by the master that
is controlling the device. This is a clock signal that synchronizes the
communication between a master and the device. All input information (DI) to the device is latched on the rising edge of this clock input,
while output data (DO) from the device is driven from the rising edge
of this clock input. This pin is gated by CS signal.
Instruction
Each of the above 10 instructions is explained under individual
instruction descriptions.
Serial Input (DI)
Start Bit
This is an input pin to the device and is generated by the master
that is controlling the device. The master transfers Input information (Start bit, Opcode bits, Array addresses and Data) serially via
this pin into the device. This Input information is latched on the
rising edge of the SCK. This pin is gated by CS signal.
This is a 1-bit field and is the first bit that is clocked into the device
when a Microwire cycle starts. This bit has to be “1” for a valid cycle
to begin. Any number of preceding “0” can be clocked into the
device before clocking a “1”.
Serial Output (DO)
This is a 2-bit field and should immediately follow the start bit.
These two bits (along with PRE, PE signals and 2 MSB of address
field) select a particular instruction to be executed.
Opcode
This is an output pin from the device and is used to transfer Output
data via this pin to the controlling master. Output data is serially
shifted out on this pin from the rising edge of the SCK. This pin is
active only when the device is selected.
Address Field
This is a 6-bit field and should immediately follow the Opcode bits.
In FM93CS46, all 6 bits are used for address decoding during
READ, WRITE and PRWRITE instructions. During all other instructions (with the exception of PRREAD), the MSB 2 bits are
used to decode instruction (along with Opcode bits, PRE and PE
signals).
Protect Register Enable (PRE)
This is an active high input pin to the device and is used to
distinguish operations to memory array and operations to Protect
Register. When this pin is held low, operations to the memory
array are enabled. When this pin is held high, operations to the
Protect Register are enabled. This pin operates in conjunction
with PE pin. Refer Table1 for functional matrix of this pin for
various operations.
Data Field
This is a 16-bit field and should immediately follow the Address
bits. Only the WRITE and WRALL instructions require this field.
D15 (MSB) is clocked first and D0 (LSB) is clocked last (both
during writes as well as reads).
TABLE 1. Instruction set
Instruction
Start Bit
Opcode Field
PRE Pin
PE Pin
READ
1
10
A5
A4
Address Field
A3
A2
A1
A0
0
X
WEN
1
00
1
1
X
X
X
X
0
1
WRITE
1
01
A5
A4
A3
A2
A1
A0
D15-D0
0
1
WRALL
1
00
0
1
X
X
X
X
D15-D0
0
1
WDS
1
00
0
0
X
X
X
X
0
X
PRREAD
1
10
X
X
X
X
X
X
1
X
PREN
1
00
1
1
X
X
X
X
1
1
PRCLEAR
1
11
1
1
1
1
1
1
1
1
PRWRITE
1
01
A5
A4
A3
A2
A1
A0
1
1
PRDS
1
00
0
0
0
0
0
0
1
1
5
FM93CS46 Rev. A
Data Field
www.fairchildsemi.com
FM93CS46 (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
Pin Description
A typical Microwire cycle starts by first selecting the device
(bringing the CS signal high). Once the device is selected, a valid
Start bit (“1”) should be issued to properly recognize the cycle.
Following this, the 2-bit opcode of appropriate instruction should
be issued. After the opcode bits, the 6-bit address information
should be issued. For certain instructions, some (or all) of these
6 bits are don’t care values (can be “0” or “1”), but they should still
be issued. Following the address information, depending on the
instruction (WRITE and WRALL), 16-Bit data is issued. Otherwise, depending on the instruction (READ and PRREAD), the
device starts to drive the output data on the DO line. Other
instructions perform certain control functions and do not deal with
data bits. The Microwire cycle ends when the CS signal is brought
low. However during certain instructions, falling edge of the CS
signal initiates an internal cycle (Programming), and the device
remains busy till the completion of the internal cycle. Each of the
10 instructions is explained in detail in the following sections.
3) Write (WRITE)
WRITE instruction allows write operation to a specified location in
the memory with a specified data. This instruction is valid only
when the following are true:
■ Device is write-enabled (Refer WEN instruction)
■ Address of the write location is not write-protected
■ PE pin is held high during this cycle
■ PRE pin should be held low during this cycle
Input information (Start bit, Opcode, Address and Data) for this
WRITE instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Memory Instructions
Following five instructions, READ, WEN, WRITE, WRALL and
WDS are specific to operations intended for memory array. The
PRE pin should be held low during these instructions.
1) Read and Sequential Read (READ)
The status of the internal programming cycle can be polled at any
time by bringing the CS signal high again, after tCS interval. When
CS signal is high, the DO pin indicates the READY/BUSY status
of the chip. DO = logical 0 indicates that the programming is still
in progress. DO = logical 1 indicates that the programming is
finished and the device is ready for another instruction. It is not
required to provide the SK clock during this status polling. While
the device is busy, it is recommended that no new instruction be
issued. Refer Write cycle diagram.
READ instruction allows data to be read from a selected location
in the memory array. Input information (Start bit, Opcode and
Address) for this instruction should be issued as listed under
Table1. Upon receiving a valid input information, decoding of the
opcode and the address is made, followed by data transfer from
the selected memory location into a 16-bit serial-out shift register.
This 16-bit data is then shifted out on the DO pin. D15 bit (MSB)
is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit
(logical 0) precedes this 16-bit data output string. Output data
changes are initiated on the rising edge of the SK clock. After
reading the 16-bit data, the CS signal can be brought low to end
the Read cycle. The PRE pin should be held low during this cycle.
Refer Read cycle diagram.
It is also recommended to follow this instruction (after the device
becomes READY) with a Write Disable (WDS) instruction to
safeguard data against corruption due to spurious noise, inadvertent writes etc.
4) Write All (WRALL)
This device also offers “sequential memory read” operation to
allow reading of data from the additional memory locations instead
of just one location. It is started in the same manner as normal read
but the cycle is continued to read further data (instead of terminating after reading the first 16-bit data). After providing 16-bit data,
the device automatically increments the address pointer to the
next location and continues to provide the data from that location.
Any number of locations can be read out in this manner, however,
after reading out from the last location, the address pointer points
back to the first location. If the cycle is continued further, data will
be read from this first location onward. In this mode of read, the
dummy-bit is present only when the very first data is read (like
normal read cycle) and is not present on subsequent data reads.
The PRE pin should be held low during this cycle. Refer Sequential Read cycle diagram.
Write all (WRALL) instruction is similar to the Write instruction
except that WRALL instruction will simultaneously program all
memory locations with the data pattern specified in the instruction.
This instruction is valid only when the following are true:
■ Protect Register has been cleared (Refer PRCLEAR
instruction)
■ Device is write-enabled (Refer WEN instruction)
■ PE pin is held high during this cycle
■ PRE pin should be held low during this cycle
Input information (Start bit, Opcode, Address and Data) for this
WRALL instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer Write All
cycle diagram.
2) Write Enable (WEN)
When VCC is applied to the part, it “powers up” in the Write Disable
(WDS) state. Therefore, all programming operations (for both
memory array and Protect Register) must be preceded by a Write
Enable (WEN) instruction. Once a Write Enable instruction is
executed, programming remains enabled until a Write Disable
(WDS) instruction is executed or VCC is completely removed from
6
FM93CS46 Rev. A
www.fairchildsemi.com
FM93CS46 (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
the part. Input information (Start bit, Opcode and Address) for this
WEN instruction should be issued as listed under Table1. The
device becomes write-enabled at the end of this cycle when the
CS signal is brought low. The PRE pin should be held low during
this cycle. Execution of a READ instruction is independent of WEN
instruction. Refer Write Enable cycle diagram.
Functional Description
in this case, WRITE operation to the last memory address
(0x111111) is still enabled. PRCLEAR instruction is enabled
(valid) only when the following are true:
Write Disable (WDS) instruction disables all programming operations and is recommended to follow all programming operations.
Executing this instruction after a valid write instruction would
protect against accidental data disturb due to spurious noise,
glitches, inadvertent writes etc. Input information (Start bit, Opcode
and Address) for this WDS instruction should be issued as listed
under Table1. The device becomes write-disabled at the end of
this cycle when the CS signal is brought low. Execution of a READ
instruction is independent of WDS instruction. Refer Write Disable
cycle diagram.
■ PREN instruction was executed immediately prior to
PRCLEAR instruction
■ PE pin is held high during this cycle
■ PRE pin is held high during this cycle
Input information (Start bit, Opcode and Address) for this PRCLEAR
instruction should be issued as listed under Table1. After inputting
the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed clear cycle. It takes tWP time (Refer
appropriate DC and AC Electrical Characteristics table) for the
internal clear cycle to finish. During this time, the device remains
busy and is not ready for another instruction. Status of the internal
programming can be polled as described under WRITE instruction
description. While the device is busy, it is recommended that no
new instruction be issued. Refer Protect Register Clear cycle
diagram.
Protect Register Instructions
Following five instructions, PRREAD, PREN, PRCLEAR,
PRWRITE and PRDS are specific to operations intended for
Protect Register. The PRE pin should be held high during these
instructions.
1) Protect Register Read (PRREAD)
This instruction reads the content of the internal Protect Register.
Content of this register is 6-bit wide and is the starting address of
the “write-protected” section of the memory array. All memory
locations greater than or equal to this address are write-protected.
Input information (Start bit, Opcode and Address) for this PRREAD
instruction should be issued as listed under Table1. Upon receiving a valid input information, decoding of the opcode and the
address is made, followed by data transfer (address information)
from the Protect Register. This 6-bit data is then shifted out on the
DO pin with the MSB first and the LSB last. Like the READ
instruction a dummy-bit (logical 0) precedes this 6-bit data output
string. Output data changes are initiated on the rising edge of the
SK clock. After reading the 6-bit data, the CS signal can be
brought low to end the PRREAD cycle. The PRE pin should be
held high during this cycle. Refer Protect Register Read cycle
diagram.
4) Protect Register Write (PRWRITE)
This instruction is used to write the starting address of the memory
section to be write-protected into the Protect register. After the
execution of PRWRITE instruction, all memory locations greater
than or equal to this address are write-protected. PRWRITE
instruction is enabled (valid) only the following are true:
■ PRCLEAR instruction was executed first (to clear the Protect
Register)
■ PREN instruction was executed immediately prior to
PRWRITE instruction
■ PE pin is held high during this cycle
■ PRE pin is held high during this cycle
Input information (Start bit, Opcode and Address) for this PRWRITE
instruction should be issued as listed under Table1. After inputting
the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer Protect
Register Write cycle diagram.
2) Protect Register Enable (PREN)
This instruction is required to enable PRCLEAR, PRWRITE and
PRDS instructions and should be executed prior to executing
PRCLEAR, PRWRITE and PRDS instructions. However, this
PREN instruction is enabled (valid) only the following are true
■ Device is write-enabled (Refer WEN instruction)
■ PE pin is held high during this cycle
■ PRE pin is held high during this cycle
Input information (Start bit, Opcode and Address) for this PREN
instruction should be issued as listed under Table1. The Protect
Register becomes enabled for PRCLEAR, PRWRITE and PRDS
instructions at the end of this cycle when the CS signal is brought
low. Note that this PREN instruction must immediately precede
a PRCLEAR, PRWRITE or PRDS instruction. In other words, no
other instruction should be executed between a PREN instruction
and a PRCLEAR, PRWRITE or PRDS instruction. Refer Protect
Register Enable cycle diagram.
5) Protect Register Disable (PRDS)
Unlike all other instructions, this instruction is a one-time-only
instruction which when executed permanently write-protects
the Protect Register and renders it unalterable in the future. This
instruction is useful to safeguard vital data (typically read only
data) in the memory against any possible corruption. PRDS
instruction is enabled (valid) only the following are true:
■ PREN instruction was executed immediately prior to PRDS
instruction
3) Protect Register Clear (PRCLEAR)
This instruction clears the content of the Protect register and
therefore enables write operations (WRITE or WRALL) to all
memory locations. Executing this instruction will program the
content of the Protect Register with a pattern of all 1s. However,
■ PE pin is held high during this cycle
■ PRE pin is held high during this cycle
7
FM93CS46 Rev. A
www.fairchildsemi.com
FM93CS46 (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
5) Write Disable (WDS)
Clearing of Ready/Busy status
When programming is in progress, the Data-Out pin will display
the programming status as either BUSY (low) or READY (high)
when CS is brought high (DO output will be tri-stated when CS is
low). To restate, during programming, the CS pin may be brought
high and low any number of times to view the programming status
without affecting the programming operation. Once programming
is completed (Output in READY state), the output is ‘cleared’
(returned to normal tri-state condition) by clocking in a Start Bit.
After the Start Bit is clocked in, the output will return to a tri-stated
condition. When clocked in, this Start Bit can be the first bit in a
command string, or CS can be brought low again to reset all
internal circuits. Refer Clearing Ready Status diagram.
Related Document
Application Note: AN758 - Using Fairchild’s MICROWIRE™ EEPROM.
8
FM93CS46 Rev. A
www.fairchildsemi.com
FM93CS46 (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
Input information (Start bit, Opcode and Address) for this PRDS
instruction should be issued as listed under Table1. After inputting
the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. The Protect
Register is permanently write-protected at the end of this cycle.
Refer Protect Register Disable cycle diagram.
FM93CS46 (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams
;
;;
;;; ;; ;;
;;; ;; ;;
;;; ;;
;
;;;;;; ;;
;;;;;; ;;
;;;; ; ;;
;;; ;;;;;
;; ;;;;;;;;;
;;;;;;
; ;;;;;;;;
;
;;;;;;
; ;;;;;;;
;;;;;;;;
;
; ;;;;;;;
;;;;;;;;;
; ;
SYNCHRONOUS DATA TIMING
CS
tSKS
SK
tCSS
tSKH
tSKL
tCSH
tPREH
tPRES
PRE
tPEH
tPES
PE
tDIS
tDIH
Valid
Input
DI
;
;
;
; ;
;
; ;
;
; ; ;
; ;;;
;
; ;;;
;
; ;;;
;
; ;;
;
;
; ;;;;;;;;;;;;;;;;;;;
; ;
;
;;;;;;;;;;;;;;;;;;;;;
;;;;;;;
; ;;;;;;;; ;
;;;;;; ;;;;;;;; ;
;
Valid
Input
tPD
tDF
tPD
tDH
Valid
Output
DO (Data Read)
tSV
DO (Status Read)
Valid
Output
tDF
Valid Status
NORMAL READ CYCLE (READ)
;;;;
;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
1
0
A5
A4
Opcode
Bits(2)
A1
A0
Address
Bits(6)
High - Z
DO
;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
;;;
;;;
0
D15
D1
D0
D u m my
Bit
93CS46:
Address bits pattern -> User defined
SEQUENTIAL READ CYCLE (PRE = 0; PE = X)
;;;;
;;;;
PRE
tCS
CS
SK
DI
1
Star t
Bit
DO
1
0
A5
Opcode
Bits(2)
A0
Address
Bits(6)
High - Z
;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;
;;;
;;;
0
Dummy
Bit
93CS46:
Address bits patter n -> User defined
D15
D0
Data(n)
9
FM93CS46 Rev. A
D15
D0
Data(n+1)
D15
D0
Data(n+2)
www.fairchildsemi.com
FM93CS46 (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams (Continued)
WRITE ENABLE CYCLE (WEN)
PRE
PE
tCS
CS
SK
DI
1
0
Star t
Bit
0
A5
A4
Opcode
Bits(2)
A1
A0
Address
Bits(6)
High - Z
DO
93CS46:
A d d r e s s b i t s p a t t e r n - > 1 - 1 - x - x - x - x ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 )
WRITE DISABLE CYCLE (WDS)
PRE
PE
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
tCS
CS
SK
DI
1
0
Star t
Bit
0
A5
A4
Opcode
Bits(2)
A1
A0
Address
Bits(6)
High - Z
DO
93CS46:
Address bits patter n -> 0-0-x-x-x-x; (x -> Don't Care, can be 0 or 1)
WRITE CYCLE (WRITE)
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
0
1
A5
Opcode
Bits(2)
A4
A1
A0
D15 D14
Address
Bits(6)
Data
Bits(16)
D1
D0
tWP
High - Z
DO
Ready
Busy
93CS46:
Address bits pattern -> User defined
Data bits pattern
-> User defined
10
FM93CS46 Rev. A
www.fairchildsemi.com
WRITE ALL CYCLE (WRALL)
PRE
PE
tCS
CS
SK
1
DI
0
Star t
Bit
0
A5
A4
Opcode
Bits(2)
A1
A0
D15 D14
Address
Bits(6)
D1
D0
tWP
Data
Bits(16)
High - Z
DO
Ready
Busy
93CS46:
Address bits patter n -> 0-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Data bits patter n
-> User defined
PROTECT REGISTER READ CYCLE (PRREAD)
;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
1
Star t
Bit
0
A5
A4
Opcode
Bits(2)
A1
A0
Address
Bits(6)
High - Z
DO
;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
;;;
;;;
D5
0
D1
D0
Dummy
Bit
93CS46:
Address bits patter n -> x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
PROTECT REGISTER ENABLE CYCLE (PREN)
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
0
0
Opcode
Bits(2)
A5
A4
A1
A0
Address
Bits(6)
High - Z
DO
93CS46:
Address bits patter n -> 1-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)
11
FM93CS46 Rev. A
www.fairchildsemi.com
FM93CS46 (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams (Continued)
FM93CS46 (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams (Continued)
PROTECT REGISTER CLEAR CYCLE (PRCLEAR)
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
1
1
Opcode
Bits(2)
DO
A5
A4
A1
A0
tWP
Address
Bits(6)
High - Z
Ready
Busy
93CS46:
Address bits patter n -> 1-1-1-1-1-1
PROTECT REGISTER WRITE CYCLE (PRWRITE)
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
0
1
Opcode
Bits(2)
DO
A5
A4
A1
A0
tWP
Address
Bits(6)
High - Z
Ready
Busy
93CS46:
Address bits patter n -> User defined
PROTECT REGISTER DISABLE CYCLE (PRDS)
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
DO
0
0
Opcode
Bits(2)
A5
High - Z
A4
A1
Address
Bits(6)
A0
tWP
Ready
Busy
93CS46:
Address bits patter n -> 0-0-0-0-0-0
12
FM93CS46 Rev. A
www.fairchildsemi.com
FM93CS46 (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams (Continued)
CLEARING READY STATUS
PRE
PE
;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;
CS
SK
DI
Star t
Bit
DO
High - Z
Ready
High - Z
Busy
Note: This Star t bit can also be par t of a next instr uction. Hence the cycle
can be continued(instead of getting ter minated, as shown) as if a new
instr uction is being issued.
13
FM93CS46 Rev. A
www.fairchildsemi.com
FM93CS46 (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
8° Max, Typ.
All leads
0.04
(0.102)
All lead tips
0.053 - 0.069
(1.346 - 1.753)
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020 Typ.
(0.356 - 0.508)
Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8)
Package Number M08A
14
FM93CS46 Rev. A
www.fairchildsemi.com
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0098
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
15
FM93CS46 Rev. A
www.fairchildsemi.com
FM93CS46 (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
+
Pin #1 IDENT
8
0.032 ± 0.005
(6.35 ± 0.127)
Pin #1
IDENT
1
Option 1
1
0.280 MIN
(7.112)
0.300 - 0.320
(7.62 - 8.128)
7
(0.813 ± 0.127)
RAD
5
2
3
0.040 Typ.
(1.016)
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
0.039
(0.991)
(3.683 - 5.080)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
Français
Tel:
+33 (0) 1-6930-3696
Italiano
Tel:
+39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
16
FM93CS46 Rev. A
www.fairchildsemi.com
FM93CS46 (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
Physical Dimensions inches (millimeters) unless otherwise noted
FM93CS56
(MICROWIRE™ Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
General Description
Features
FM93CS56 is a 2048-bit CMOS non-volatile EEPROM organized
as 128 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compatible to many of standard Microcontrollers and Microprocessors.
FM93CS56 offers programmable write protection to the memory
array using a special register called Protect Register. Selected
memory locations can be protected against write by programming
this Protect Register with the address of the first memory location
to be protected (all locations greater than or equal to this first
address are then protected from further change). Additionally, this
address can be “permanently locked” into the device, making all
future attempts to change data impossible. In addition this device
features “sequential read”, by which, entire memory can be read
in one cycle instead of multiple single byte read cycles. There are
10 instructions implemented on the FM93CS56, 5 of which are for
memory operations and the remaining 5 are for Protect Register
operations. This device is fabricated using Fairchild Semiconductor floating-gate CMOS process for high reliability, high endurance
and low power consumption.
■ Wide VCC 2.7V - 5.5V
■ Programmable write protection
■ Sequential register read
■ Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
■ No Erase instruction required before Write instruction
■ Self timed write cycle
■ Device status during programming cycles
■ 40 year data retention
■ Endurance: 1,000,000 data changes
■ Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
“LZ” and “L” versions of FM93CS56 offer very low standby current
making them suitable for low power applications. This device is offered
in both SO and TSSOP packages for small space considerations.
Functional Diagram
VCC
CS
INSTRUCTION
DECODER
CONTROL LOGIC
AND CLOCK
GENERATORS
SK
DI
INSTRUCTION
REGISTER
ADDRESS
REGISTER
DECODER
COMPARATOR
AND
WRITE ENABLE
PROTECT
REGISTER
PRE
PE
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
EEPROM ARRAY
16
READ/WRITE AMPS
VSS
16
DATA IN/OUT REGISTER
16 BITS
DO
© 1999 Fairchild Semiconductor Corporation
FM93CS56 Rev. A
DATA OUT BUFFER
1
www.fairchildsemi.com
FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
February 2000
FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
Connection Diagram
Dual-In-Line Package (N)
8–Pin SO (M8) and 8–Pin TSSOP (MT8)
CS
1
8
VCC
SK
2
7
PRE
DI
3
6
PE
DO
4
5
GND
Top View
Package Number
N08E, M08A and MTC08
Pin Names
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
PE
Ground
Program Enable
PRE
Protect Register Enable
VCC
Power Supply
Ordering Information
FM
93
CS
XX
LZ
E
XXX
Letter
Description
N
M8
MT8
8-pin DIP
8-pin SO
8-pin TSSOP
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
56
2048 bits
C
CS
CMOS
Data protect and sequential
read
93
MICROWIRE
Package
Density
Interface
Fairchild Memory Prefix
2
FM93CS56 Rev. A
www.fairchildsemi.com
Operating Conditions
Ambient Storage Temperature
Ambient Operating Temperature
FM93CS56
FM93CS56E
FM93CS56V
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
-65°C to +150°C
+6.5V to -0.3V
+300°C
ESD rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
4.5V to 5.5V
2000V
DC and AC Electrical Characteristics VCC = 4.5V to 5.5V unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
ICCA
Operating Current
CS = VIH, SK=1.0 MHz
1
mA
ICCS
Standby Current
CS = VIL
50
µA
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
(Note 2)
±-1
µA
VIL
VIH
Input Low Voltage
Input High Voltage
0.8
VCC +1
V
0.4
V
0.2
V
1
MHz
-0.1
2
VOL1
VOH1
Output Low Voltage
Output High Voltage
IOL = 2.1 mA
IOH = -400 µA
2.4
VOL2
VOH2
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
VCC - 0.2
fSK
SK Clock Frequency
(Note 3)
tSKH
SK High Time
0°C to +70°C
-40°C to +125°C
250
300
ns
ns
tSKL
SK Low Time
250
tSKS
SK Setup Time
50
ns
tCS
Minimum CS Low Time
250
ns
tCSS
CS Setup Time
100
ns
tPRES
PRE Setup Time
50
ns
tDH
DO Hold Time
70
ns
tPES
PE Setup Time
50
ns
tDIS
DI Setup Time
100
ns
tCSH
CS Hold Time
0
ns
tPEH
PE Hold Time
250
ns
tPREH
ns
(Note 4)
PRE Hold Time
50
tDIH
DI Hold Time
20
tPD
Output Delay
tSV
CS to Status Valid
tDF
CS to DO in Hi-Z
tWP
Write Cycle Time
CS = VIL
3
FM93CS56 Rev. A
ns
500
ns
500
ns
100
ns
10
ms
www.fairchildsemi.com
FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
Absolute Maximum Ratings (Note 1)
Operating Conditions
Ambient Storage Temperature
Ambient Operating Temperature
FM93CS56L/LZ
FM93CS56LE/LZE
FM93CS56LV/LZV
-65°C to +150°C
All Input or Output Voltages
with Respect to Ground
+6.5V to -0.3V
Lead Temperature
(Soldering, 10 sec.)
+300°C
ESD rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
2.7V to 5.5V
2000V
DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified
Symbol
Parameter
Conditions
ICCA
Operating Current
CS = VIH, SK=1.0 MHz
ICCS
CS = VIL
IIL
IOL
VIL
VIH
VOL
VOH
fSK
tSKH
tSKL
tSKS
Standby Current
L
LZ (2.7V to 4.5V)
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
SK Low Time
SK Setup Time
tCS
Minimum CS Low Time
(Note 4)
Min
VIN = 0V to VCC
(Note 2)
-0.1
0.8VCC
IOL = 10µA
IOH = -10µA
(Note 3)
0.9VCC
0
1
1
0.2
Max
Units
1
mA
10
1
±1
µA
µA
µA
0.15VCC
VCC +1
0.1VCC
V
250
KHz
µs
µs
µs
V
1
µs
tCSS
tPRES
tDH
tPES
tDIS
CS Setup Time
PRE Setup Time
DO Hold Time
PE Setup Time
DI Setup Time
0.2
50
70
50
0.4
µs
ns
ns
ns
µs
tCSH
tPEH
tPREH
tDIH
tPD
CS Hold Time
PE Hold Time
PRE Hold Time
DI Hold Time
Output Delay
0
250
50
0.4
2
ns
ns
ns
µs
µs
1
µs
0.4
15
µs
ms
tSV
CS to Status Valid
tDF
tWP
CS to DO in Hi-Z
Write Cycle Time
CS = VIL
Capacitance TA = 25°C, f = 1 MHz (Note 5)
Symbol
Test
Typ
Max
Units
COUT
Output Capacitance
5
pF
CIN
Input Capacitance
5
pF
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2:
Typical leakage values are in the 20nA range.
Note 3: The shortest allowable SK clock period = 1/fSK (as shown under the fSK parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not
allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
Note 5:
AC Test Conditions
This parameter is periodically sampled and not 100% tested.
VCC Range
VIL/VIH
Input Levels
VIL/VIH
Timing Level
VOL/VOH
Timing Level
IOL/IOH
2.7V ≤ VCC ≤ 5.5V
0.3V/1.8V
1.0V
0.8V/1.5V
±10µA
4.5V ≤ VCC ≤ 5.5V
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(Extended Voltage Levels)
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
FM93CS56 Rev. A
www.fairchildsemi.com
FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
Absolute Maximum Ratings (Note 1)
Program Enable (PE)
Chip Select (CS)
This is an active high input pin to the device and is used to enable
operations, that are write in nature, to the memory array and to the
Protect register. When this pin is held high, operations that are
“write” in nature are enabled. When this pin is held low, operations
that are “write” in nature are disabled. This pin operates in
conjunction with PRE pin. Refer Table1 for functional matrix of this
pin for various operations.
This is an active high input pin to FM93CS56 EEPROM (the device)
and is generated by a master that is controlling the device. A high
level on this pin selects the device and a low level deselects the
device. All serial communications with the device is enabled only
when this pin is held high. However this pin cannot be permanently
tied high, as a rising edge on this signal is required to reset the
internal state-machine to accept a new cycle and a falling edge to
initiate an internal programming after a write cycle. All activity on the
SK, DI and DO pins are ignored while CS is held low.
Microwire Interface
A typical communication on the Microwire bus is made through the
CS, SK, DI and DO signals. To facilitate various operations on the
Memory array and on the Protect Register, a set of 10 instructions
are implemented on FM93CS56. The format of each instruction is
listed in Table 1.
Serial Clock (SK)
This is an input pin to the device and is generated by the master that
is controlling the device. This is a clock signal that synchronizes the
communication between a master and the device. All input information (DI) to the device is latched on the rising edge of this clock input,
while output data (DO) from the device is driven from the rising edge
of this clock input. This pin is gated by CS signal.
Instruction
Each of the above 10 instructions is explained under individual
instruction descriptions.
Serial Input (DI)
Start Bit
This is an input pin to the device and is generated by the master
that is controlling the device. The master transfers Input information (Start bit, Opcode bits, Array addresses and Data) serially via
this pin into the device. This Input information is latched on the
rising edge of the SCK. This pin is gated by CS signal.
This is a 1-bit field and is the first bit that is clocked into the device
when a Microwire cycle starts. This bit has to be “1” for a valid cycle
to begin. Any number of preceding “0” can be clocked into the
device before clocking a “1”.
Serial Output (DO)
This is a 2-bit field and should immediately follow the start bit.
These two bits (along with PRE, PE signals and 2 MSB of address
field) select a particular instruction to be executed.
Opcode
This is an output pin from the device and is used to transfer Output
data via this pin to the controlling master. Output data is serially
shifted out on this pin from the rising edge of the SCK. This pin is
active only when the device is selected.
Address Field
This is a 8-bit field and should immediately follow the Opcode bits.
In FM93CS56, only the LSB 7 bits are used for address decoding
during READ, WRITE and PRWRITE instructions. During these
three instructions (READ, WRITE and PRWRITE), the MSB is
“don’t care” (can be 0 or 1). During all other instructions (with the
exception of PRREAD), the MSB 2 bits are used to decode
instruction (along with Opcode bits, PRE and PE signals).
Protect Register Enable (PRE)
This is an active high input pin to the device and is used to
distinguish operations to memory array and operations to Protect
Register. When this pin is held low, operations to the memory
array are enabled. When this pin is held high, operations to the
Protect Register are enabled. This pin operates in conjunction
with PE pin. Refer Table1 for functional matrix of this pin for
various operations.
Data Field
This is a 16-bit field and should immediately follow the Address
bits. Only the WRITE and WRALL instructions require this field.
D15 (MSB) is clocked first and D0 (LSB) is clocked last (both
during writes as well as reads).
TABLE 1. Instruction set
Instruction
PRE Pin
PE Pin
READ
Start Bit Opcode Field
1
10
X
A6
A5
Address Field
A4
A3
A2
A1
A0
0
X
WEN
1
00
1
1
X
X
X
X
X
X
0
1
WRITE
1
01
X
A6
A5
A4
A3
A2
A1
A0
D15-D0
0
1
WRALL
1
00
0
1
X
X
X
X
X
X
D15-D0
0
1
WDS
1
00
0
0
X
X
X
X
X
X
0
X
PRREAD
1
10
X
X
X
X
X
X
X
X
1
X
PREN
1
00
1
1
X
X
X
X
X
X
1
1
PRCLEAR
1
11
1
1
1
1
1
1
1
1
1
1
PRWRITE
1
01
X
A6
A5
A4
A3
A2
A1
A0
1
1
PRDS
1
00
0
0
0
0
0
0
0
0
1
1
5
FM93CS56 Rev. A
Data Field
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FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
Pin Description
A typical Microwire cycle starts by first selecting the device
(bringing the CS signal high). Once the device is selected, a valid
Start bit (“1”) should be issued to properly recognize the cycle.
Following this, the 2-bit opcode of appropriate instruction should
be issued. After the opcode bits, the 8-bit address information
should be issued. For certain instructions, some (or all) of these
8 bits are don’t care values (can be “0” or “1”), but they should still
be issued. Following the address information, depending on the
instruction (WRITE and WRALL), 16-Bit data is issued. Otherwise, depending on the instruction (READ and PRREAD), the
device starts to drive the output data on the DO line. Other
instructions perform certain control functions and do not deal with
data bits. The Microwire cycle ends when the CS signal is brought
low. However during certain instructions, falling edge of the CS
signal initiates an internal cycle (Programming), and the device
remains busy till the completion of the internal cycle. Each of the
10 instructions is explained in detail in the following sections.
3) Write (WRITE)
WRITE instruction allows write operation to a specified location in
the memory with a specified data. This instruction is valid only
when the following are true:
■ Device is write-enabled (Refer WEN instruction)
■ Address of the write location is not write-protected
■ PE pin is held high during this cycle
■ PRE pin should be held low during this cycle
Input information (Start bit, Opcode, Address and Data) for this
WRITE instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Memory Instructions
Following five instructions, READ, WEN, WRITE, WRALL and
WDS are specific to operations intended for memory array. The
PRE pin should be held low during these instructions.
1) Read and Sequential Read (READ)
The status of the internal programming cycle can be polled at any
time by bringing the CS signal high again, after tCS interval. When
CS signal is high, the DO pin indicates the READY/BUSY status
of the chip. DO = logical 0 indicates that the programming is still
in progress. DO = logical 1 indicates that the programming is
finished and the device is ready for another instruction. It is not
required to provide the SK clock during this status polling. While
the device is busy, it is recommended that no new instruction be
issued. Refer Write cycle diagram.
READ instruction allows data to be read from a selected location
in the memory array. Input information (Start bit, Opcode and
Address) for this instruction should be issued as listed under
Table1. Upon receiving a valid input information, decoding of the
opcode and the address is made, followed by data transfer from
the selected memory location into a 16-bit serial-out shift register.
This 16-bit data is then shifted out on the DO pin. D15 bit (MSB)
is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit
(logical 0) precedes this 16-bit data output string. Output data
changes are initiated on the rising edge of the SK clock. After
reading the 16-bit data, the CS signal can be brought low to end
the Read cycle. The PRE pin should be held low during this cycle.
Refer Read cycle diagram.
It is also recommended to follow this instruction (after the device
becomes READY) with a Write Disable (WDS) instruction to
safeguard data against corruption due to spurious noise, inadvertent writes etc.
4) Write All (WRALL)
This device also offers “sequential memory read” operation to
allow reading of data from the additional memory locations instead
of just one location. It is started in the same manner as normal read
but the cycle is continued to read further data (instead of terminating after reading the first 16-bit data). After providing 16-bit data,
the device automatically increments the address pointer to the
next location and continues to provide the data from that location.
Any number of locations can be read out in this manner, however,
after reading out from the last location, the address pointer points
back to the first location. If the cycle is continued further, data will
be read from this first location onward. In this mode of read, the
dummy-bit is present only when the very first data is read (like
normal read cycle) and is not present on subsequent data reads.
The PRE pin should be held low during this cycle. Refer Sequential Read cycle diagram.
Write all (WRALL) instruction is similar to the Write instruction
except that WRALL instruction will simultaneously program all
memory locations with the data pattern specified in the instruction.
This instruction is valid only when the following are true:
■ Protect Register has been cleared (Refer PRCLEAR
instruction)
■ Device is write-enabled (Refer WEN instruction)
■ PE pin is held high during this cycle
■ PRE pin should be held low during this cycle
Input information (Start bit, Opcode, Address and Data) for this
WRALL instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer Write All
cycle diagram.
2) Write Enable (WEN)
When VCC is applied to the part, it “powers up” in the Write Disable
(WDS) state. Therefore, all programming operations (for both
memory array and Protect Register) must be preceded by a Write
Enable (WEN) instruction. Once a Write Enable instruction is
executed, programming remains enabled until a Write Disable
(WDS) instruction is executed or VCC is completely removed from
6
FM93CS56 Rev. A
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FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
the part. Input information (Start bit, Opcode and Address) for this
WEN instruction should be issued as listed under Table1. The
device becomes write-enabled at the end of this cycle when the
CS signal is brought low. The PRE pin should be held low during
this cycle. Execution of a READ instruction is independent of WEN
instruction. Refer Write Enable cycle diagram.
Functional Description
in this case, WRITE operation to the last memory address
(0x01111111) is still enabled. PRCLEAR instruction is enabled
(valid) only when the following are true:
Write Disable (WDS) instruction disables all programming operations and is recommended to follow all programming operations.
Executing this instruction after a valid write instruction would
protect against accidental data disturb due to spurious noise,
glitches, inadvertent writes etc. Input information (Start bit, Opcode
and Address) for this WDS instruction should be issued as listed
under Table1. The device becomes write-disabled at the end of
this cycle when the CS signal is brought low. Execution of a READ
instruction is independent of WDS instruction. Refer Write Disable
cycle diagram.
■ PREN instruction was executed immediately prior to
PRCLEAR instruction
■ PE pin is held high during this cycle
■ PRE pin is held high during this cycle
Input information (Start bit, Opcode and Address) for this PRCLEAR
instruction should be issued as listed under Table1. After inputting
the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed clear cycle. It takes tWP time (Refer
appropriate DC and AC Electrical Characteristics table) for the
internal clear cycle to finish. During this time, the device remains
busy and is not ready for another instruction. Status of the internal
programming can be polled as described under WRITE instruction
description. While the device is busy, it is recommended that no
new instruction be issued. Refer Protect Register Clear cycle
diagram.
Protect Register Instructions
Following five instructions, PRREAD, PREN, PRCLEAR,
PRWRITE and PRDS are specific to operations intended for
Protect Register. The PRE pin should be held high during these
instructions.
1) Protect Register Read (PRREAD)
This instruction reads the content of the internal Protect Register.
Content of this register is 8-bit wide and is the starting address of
the “write-protected” section of the memory array. All memory
locations greater than or equal to this address are write-protected.
Input information (Start bit, Opcode and Address) for this PRREAD
instruction should be issued as listed under Table 1. Upon
receiving a valid input information, decoding of the opcode and the
address is made, followed by data transfer (address information)
from the Protect Register. This 8-bit data is then shifted out on the
DO pin with the MSB first and the LSB last. Like the READ
instruction a dummy-bit (logical 0) precedes this 8-bit data output
string. Output data changes are initiated on the rising edge of the
SK clock. After reading the 8-bit data, the CS signal can be brought
low to end the PRREAD cycle. The PRE pin should be held high
during this cycle. Refer Protect Register Read cycle diagram.
4) Protect Register Write (PRWRITE)
This instruction is used to write the starting address of the memory
section to be write-protected into the Protect register. After the
execution of PRWRITE instruction, all memory locations greater
than or equal to this address are write-protected. PRWRITE
instruction is enabled (valid) only the following are true:
■ PRCLEAR instruction was executed first (to clear the Protect
Register)
■ PREN instruction was executed immediately prior to
PRWRITE instruction
■ PE pin is held high during this cycle
■ PRE pin is held high during this cycle
Input information (Start bit, Opcode and Address) for this PRWRITE
instruction should be issued as listed under Table1. After inputting
the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer Protect
Register Write cycle diagram.
Though the content of this register is 8-bit wide, only the last 7 bits
(LSB) are valid for FM93CS56 device.
2) Protect Register Enable (PREN)
This instruction is required to enable PRCLEAR, PRWRITE and
PRDS instructions and should be executed prior to executing
PRCLEAR, PRWRITE and PRDS instructions. However, this
PREN instruction is enabled (valid) only the following are true
■ Device is write-enabled (Refer WEN instruction)
■ PE pin is held high during this cycle
■ PRE pin is held high during this cycle
5) Protect Register Disable (PRDS)
Input information (Start bit, Opcode and Address) for this PREN
instruction should be issued as listed under Table1. The Protect
Register becomes enabled for PRCLEAR, PRWRITE and PRDS
instructions at the end of this cycle when the CS signal is brought
low. Note that this PREN instruction must immediately precede
a PRCLEAR, PRWRITE or PRDS instruction. In other words, no
other instruction should be executed between a PREN instruction
and a PRCLEAR, PRWRITE or PRDS instruction. Refer Protect
Register Enable cycle diagram.
Unlike all other instructions, this instruction is a one-time-only
instruction which when executed permanently write-protects
the Protect Register and renders it unalterable in the future. This
instruction is useful to safeguard vital data (typically read only
data) in the memory against any possible corruption. PRDS
instruction is enabled (valid) only the following are true:
■ PREN instruction was executed immediately prior to PRDS
instruction
3) Protect Register Clear (PRCLEAR)
■ PE pin is held high during this cycle
This instruction clears the content of the Protect register and
therefore enables write operations (WRITE or WRALL) to all
memory locations. Executing this instruction will program the
content of the Protect Register with a pattern of all 1s. However,
■ PRE pin is held high during this cycle
Input information (Start bit, Opcode and Address) for this PRDS
7
FM93CS56 Rev. A
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FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
5) Write Disable (WDS)
When programming is in progress, the Data-Out pin will display
the programming status as either BUSY (low) or READY (high)
when CS is brought high (DO output will be tri-stated when CS is
low). To restate, during programming, the CS pin may be brought
high and low any number of times to view the programming status
without affecting the programming operation. Once programming
is completed (Output in READY state), the output is ‘cleared’
(returned to normal tri-state condition) by clocking in a Start Bit.
After the Start Bit is clocked in, the output will return to a tri-stated
condition. When clocked in, this Start Bit can be the first bit in a
command string, or CS can be brought low again to reset all
internal circuits. Refer Clearing Ready Status diagram.
Clearing of Ready/Busy status
Related Document
Application Note: AN758 - Using Fairchild’s MICROWIRE™ EEPROM.
8
FM93CS56 Rev. A
www.fairchildsemi.com
FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
instruction should be issued as listed under Table1. After inputting
the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. The Protect
Register is permanently write-protected at the end of this cycle.
Refer Protect Register Disable cycle diagram.
FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams
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SYNCHRONOUS DATA TIMING
CS
SK
tSKS
tCSS
tSKH
tSKL
tCSH
tPREH
tPRES
PRE
tPEH
tPES
PE
tDIS
tDIH
Valid
Input
DI
Valid
Input
tDH
tPD
tDF
tPD
Valid
Output
DO (Data Read)
Valid
Output
tDF
tSV
Valid Status
DO (Status Read)
NORMAL READ CYCLE (READ)
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;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
1
Star t
Bit
0
A7
A6
Opcode
Bits(2)
A1
A0
Address
Bits(8)
High - Z
DO
;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
;;;
;;;
D15
0
D1
D0
Dummy
Bit
93CS56:
Address bits patter n -> x-A6-A5-A4-A3-A2-A1-A0; (x -> Don't Care, can be 0 or 1); ( A6-A0 -> User defined )
SEQUENTIAL READ CYCLE (PRE = 0; PE = X)
;;;;
;;;;
PRE
tCS
CS
SK
DI
1
Star t
Bit
DO
1
0
A7
Opcode
Bits(2)
High - Z
A0
Address
Bits(8)
;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;
;;;
;;;
0
D u m my
Bit
D15
D0
Data(n)
D15
D0
Data(n+1)
D15
D0
Data(n+2)
93CS56:
A d d r e s s b i t s p a t t e r n - > x - A 6 - A 5 - A 4 - A 3 - A 2 - A 1 - A 0 ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 ) ; ( A 6 - A 0 - > U s e r d e f i n e d )
9
FM93CS56 Rev. A
www.fairchildsemi.com
FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams (Continued)
WRITE ENABLE CYCLE (WEN)
PRE
PE
tCS
CS
SK
DI
1
0
Star t
Bit
0
A7
A6
Opcode
Bits(2)
A1
A0
Address
Bits(8)
High - Z
DO
93CS56:
A d d r e s s b i t s p a t t e r n - > 1 - 1 - x - x - x - x - x - x ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 )
WRITE DISABLE CYCLE (WDS)
PRE
PE
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
tCS
CS
SK
DI
1
0
Star t
Bit
0
A7
A6
Opcode
Bits(2)
A1
A0
Address
Bits(8)
High - Z
DO
93CS56:
Address bits patter n -> 0-0-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
WRITE CYCLE (WRITE)
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
0
1
Opcode
Bits(2)
A7
A6
A1
A0
D15 D14
Address
Bits(8)
Data
Bits(16)
D1
D0
tWP
High - Z
DO
Ready
Busy
93CS56:
A d d r e s s b i t s p a t t e r n - > x - A 6 - A 5 - A 4 - A 3 - A 2 - A 1 - A 0 ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 ) ; ( A 6 - A 0 - > U s e r d e f i n e d )
Data bits pattern
-> User defined
10
FM93CS56 Rev. A
www.fairchildsemi.com
WRITE ALL CYCLE (WRALL)
PRE
PE
tCS
CS
SK
1
DI
0
Star t
Bit
0
A7
A6
Opcode
Bits(2)
A1
A0
D15 D14
Address
Bits(8)
D1
D0
tWP
Data
Bits(16)
High - Z
DO
Ready
Busy
93CS56:
Address bits patter n -> 0-1-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Data bits patter n
-> User defined
PROTECT REGISTER READ CYCLE (PRREAD)
;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
1
Star t
Bit
0
A7
A6
Opcode
Bits(2)
A1
A0
Address
Bits(8)
High - Z
DO
;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
;;;
;;;
D7
0
D1
D0
Dummy
Bit
93CS56:
Address bits patter n -> x-x-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
PROTECT REGISTER ENABLE CYCLE (PREN)
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
0
0
Opcode
Bits(2)
A7
A6
A1
A0
Address
Bits(8)
High - Z
DO
93CS56:
Address bits patter n -> 1-1-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
11
FM93CS56 Rev. A
www.fairchildsemi.com
FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams (Continued)
FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams (Continued)
PROTECT REGISTER CLEAR CYCLE (PRCLEAR)
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
PRE
PE
tCS
CS
SK
1
DI
1
Star t
Bit
1
A7
Opcode
Bits(2)
DO
A6
A1
A0
tWP
Address
Bits(8)
High - Z
Ready
Busy
93CS56:
Address bits patter n -> 1-1-1-1-1-1-1-1
PROTECT REGISTER WRITE CYCLE (PRWRITE)
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
0
1
Opcode
Bits(2)
DO
A7
A6
High - Z
A1
A0
tWP
Address
Bits(8)
Ready
Busy
93CS56:
Address bits pattern -> x-A6-A5-A4-A3-A2-A1-A0; (x -> Don't Care, can be 0 or 1); ( A6-A0 -> User defined )
PROTECT REGISTER DISABLE CYCLE (PRDS)
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
DO
0
0
Opcode
Bits(2)
A7
High - Z
A6
A1
Address
Bits(8)
A0
tWP
Ready
Busy
93CS56:
Address bits patter n -> 0-0-0-0-0-0-0-0
12
FM93CS56 Rev. A
www.fairchildsemi.com
FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams (Continued)
CLEARING READY STATUS
PRE
PE
;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;
CS
SK
DI
Star t
Bit
DO
High - Z
Ready
High - Z
Busy
Note: This Star t bit can also be par t of a next instr uction. Hence the cycle
can be continued(instead of getting ter minated, as shown) as if a new
instr uction is being issued.
13
FM93CS56 Rev. A
www.fairchildsemi.com
FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
8° Max, Typ.
All leads
0.04
(0.102)
All lead tips
0.053 - 0.069
(1.346 - 1.753)
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020 Typ.
(0.356 - 0.508)
Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8)
Package Number M08A
14
FM93CS56 Rev. A
www.fairchildsemi.com
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0098
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
15
FM93CS56 Rev. A
www.fairchildsemi.com
FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
+
Pin #1 IDENT
8
0.032 ± 0.005
(6.35 ± 0.127)
Pin #1
IDENT
1
Option 1
1
0.280 MIN
(7.112)
0.300 - 0.320
(7.62 - 8.128)
7
(0.813 ± 0.127)
RAD
5
2
3
0.040 Typ.
(1.016)
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
0.039
(0.991)
(3.683 - 5.080)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
Français
Tel:
+33 (0) 1-6930-3696
Italiano
Tel:
+39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
16
FM93CS56 Rev. A
www.fairchildsemi.com
FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
Physical Dimensions inches (millimeters) unless otherwise noted
FM93CS66
(MICROWIRE™ Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
General Description
Features
FM93CS66 is a 4096-bit CMOS non-volatile EEPROM organized
as 256 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compatible to many of standard Microcontrollers and Microprocessors.
FM93CS66 offers programmable write protection to the memory
array using a special register called Protect Register. Selected
memory locations can be protected against write by programming
this Protect Register with the address of the first memory location
to be protected (all locations greater than or equal to this first
address are then protected from further change). Additionally, this
address can be “permanently locked” into the device, making all
future attempts to change data impossible. In addition this device
features “sequential read”, by which, entire memory can be read
in one cycle instead of multiple single byte read cycles. There are
10 instructions implemented on the FM93CS66, 5 of which are for
memory operations and the remaining 5 are for Protect Register
operations. This device is fabricated using Fairchild Semiconductor floating-gate CMOS process for high reliability, high endurance
and low power consumption.
■ Wide VCC 2.7V - 5.5V
■ Programmable write protection
■ Sequential register read
■ Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
■ No Erase instruction required before Write instruction
■ Self timed write cycle
■ Device status during programming cycles
■ 40 year data retention
■ Endurance: 1,000,000 data changes
■ Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
“LZ” and “L” versions of FM93CS66 offer very low standby current
making them suitable for low power applications. This device is offered
in both SO and TSSOP packages for small space considerations.
Functional Diagram
VCC
CS
INSTRUCTION
DECODER
CONTROL LOGIC
AND CLOCK
GENERATORS
SK
DI
INSTRUCTION
REGISTER
ADDRESS
REGISTER
DECODER
COMPARATOR
AND
WRITE ENABLE
PROTECT
REGISTER
PRE
PE
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
EEPROM ARRAY
16
READ/WRITE AMPS
VSS
16
DATA IN/OUT REGISTER
16 BITS
DO
© 1999 Fairchild Semiconductor Corporation
FM93CS66 Rev. A
DATA OUT BUFFER
1
www.fairchildsemi.com
FM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
February 2000
FM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
Connection Diagram
Dual-In-Line Package (N)
8–Pin SO (M8) and 8–Pin TSSOP (MT8)
CS
1
8
VCC
SK
2
7
PRE
DI
3
6
PE
DO
4
5
GND
Top View
Package Number
N08E, M08A and MTC08
Pin Names
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
PE
Ground
Program Enable
PRE
Protect Register Enable
VCC
Power Supply
Ordering Information
FM
93
CS
XX
LZ
E
XXX
Letter
Description
N
M8
MT8
8-pin DIP
8-pin SO
8-pin TSSOP
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
66
4096 bits
C
CS
CMOS
Data protect and sequential
read
93
MICROWIRE
Package
Density
Interface
Fairchild Memory Prefix
2
FM93CS66 Rev. A
www.fairchildsemi.com
Operating Conditions
Ambient Storage Temperature
Ambient Operating Temperature
FM93CS66
FM93CS66E
FM93CS66V
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
-65°C to +150°C
+6.5V to -0.3V
+300°C
ESD rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
4.5V to 5.5V
2000V
DC and AC Electrical Characteristics VCC = 4.5V to 5.5V unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
ICCA
Operating Current
CS = VIH, SK=1.0 MHz
1
mA
ICCS
Standby Current
CS = VIL
50
µA
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
(Note 2)
±-1
µA
VIL
VIH
Input Low Voltage
Input High Voltage
0.8
VCC +1
V
0.4
V
0.2
V
1
MHz
-0.1
2
VOL1
VOH1
Output Low Voltage
Output High Voltage
IOL = 2.1 mA
IOH = -400 µA
2.4
VOL2
VOH2
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
VCC - 0.2
fSK
SK Clock Frequency
(Note 3)
tSKH
SK High Time
0°C to +70°C
-40°C to +125°C
250
300
ns
ns
tSKL
SK Low Time
250
tSKS
SK Setup Time
50
ns
tCS
Minimum CS Low Time
250
ns
tCSS
CS Setup Time
100
ns
tPRES
PRE Setup Time
50
ns
tDH
DO Hold Time
70
ns
tPES
PE Setup Time
50
ns
tDIS
DI Setup Time
100
ns
tCSH
CS Hold Time
0
ns
tPEH
PE Hold Time
250
ns
tPREH
ns
(Note 4)
PRE Hold Time
50
tDIH
DI Hold Time
20
tPD
Output Delay
tSV
CS to Status Valid
tDF
CS to DO in Hi-Z
tWP
Write Cycle Time
CS = VIL
3
FM93CS66 Rev. A
ns
500
ns
500
ns
100
ns
10
ms
www.fairchildsemi.com
FM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
Absolute Maximum Ratings (Note 1)
Operating Conditions
Ambient Storage Temperature
Ambient Operating Temperature
FM93CS66L/LZ
FM93CS66LE/LZE
FM93CS66LV/LZV
-65°C to +150°C
All Input or Output Voltages
with Respect to Ground
+6.5V to -0.3V
Lead Temperature
(Soldering, 10 sec.)
+300°C
ESD rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
2.7V to 5.5V
2000V
DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified
Symbol
Parameter
Conditions
ICCA
Operating Current
CS = VIH, SK=1.0 MHz
ICCS
CS = VIL
IIL
IOL
VIL
VIH
VOL
VOH
fSK
tSKH
tSKL
tSKS
Standby Current
L
LZ (2.7V to 4.5V)
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
SK Low Time
SK Setup Time
tCS
Minimum CS Low Time
(Note 4)
Min
VIN = 0V to VCC
(Note 2)
-0.1
0.8VCC
IOL = 10µA
IOH = -10µA
(Note 3)
0.9VCC
0
1
1
0.2
Max
Units
1
mA
10
1
±1
µA
µA
µA
0.15VCC
VCC +1
0.1VCC
V
250
KHz
µs
µs
µs
V
1
µs
tCSS
tPRES
tDH
tPES
tDIS
CS Setup Time
PRE Setup Time
DO Hold Time
PE Setup Time
DI Setup Time
0.2
50
70
50
0.4
µs
ns
ns
ns
µs
tCSH
tPEH
tPREH
tDIH
tPD
CS Hold Time
PE Hold Time
PRE Hold Time
DI Hold Time
Output Delay
0
250
50
0.4
2
ns
ns
ns
µs
µs
1
µs
0.4
15
µs
ms
tSV
CS to Status Valid
tDF
tWP
CS to DO in Hi-Z
Write Cycle Time
CS = VIL
Capacitance TA = 25°C, f = 1 MHz (Note 5)
Symbol
Test
Typ
Max
Units
COUT
Output Capacitance
5
pF
CIN
Input Capacitance
5
pF
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2:
Typical leakage values are in the 20nA range.
Note 3: The shortest allowable SK clock period = 1/fSK (as shown under the fSK parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not
allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
Note 5:
AC Test Conditions
This parameter is periodically sampled and not 100% tested.
VCC Range
VIL/VIH
Input Levels
VIL/VIH
Timing Level
VOL/VOH
Timing Level
IOL/IOH
2.7V ≤ VCC ≤ 5.5V
0.3V/1.8V
1.0V
0.8V/1.5V
±10µA
4.5V ≤ VCC ≤ 5.5V
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(Extended Voltage Levels)
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
FM93CS66 Rev. A
www.fairchildsemi.com
FM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
Absolute Maximum Ratings (Note 1)
Program Enable (PE)
Chip Select (CS)
This is an active high input pin to the device and is used to enable
operations, that are write in nature, to the memory array and to the
Protect register. When this pin is held high, operations that are
“write” in nature are enabled. When this pin is held low, operations
that are “write” in nature are disabled. This pin operates in
conjunction with PRE pin. Refer Table1 for functional matrix of this
pin for various operations.
This is an active high input pin to FM93CS66 EEPROM (the device)
and is generated by a master that is controlling the device. A high
level on this pin selects the device and a low level deselects the
device. All serial communications with the device is enabled only
when this pin is held high. However this pin cannot be permanently
tied high, as a rising edge on this signal is required to reset the
internal state-machine to accept a new cycle and a falling edge to
initiate an internal programming after a write cycle. All activity on the
SK, DI and DO pins are ignored while CS is held low.
Microwire Interface
A typical communication on the Microwire bus is made through the
CS, SK, DI and DO signals. To facilitate various operations on the
Memory array and on the Protect Register, a set of 10 instructions
are implemented on FM93CS66. The format of each instruction is
listed in Table 1.
Serial Clock (SK)
This is an input pin to the device and is generated by the master that
is controlling the device. This is a clock signal that synchronizes the
communication between a master and the device. All input information (DI) to the device is latched on the rising edge of this clock input,
while output data (DO) from the device is driven from the rising edge
of this clock input. This pin is gated by CS signal.
Instruction
Each of the above 10 instructions is explained under individual
instruction descriptions.
Serial Input (DI)
Start Bit
This is an input pin to the device and is generated by the master
that is controlling the device. The master transfers Input information (Start bit, Opcode bits, Array addresses and Data) serially via
this pin into the device. This Input information is latched on the
rising edge of the SCK. This pin is gated by CS signal.
This is a 1-bit field and is the first bit that is clocked into the device
when a Microwire cycle starts. This bit has to be “1” for a valid cycle
to begin. Any number of preceding “0” can be clocked into the
device before clocking a “1”.
Serial Output (DO)
This is a 2-bit field and should immediately follow the start bit.
These two bits (along with PRE, PE signals and 2 MSB of address
field) select a particular instruction to be executed.
Opcode
This is an output pin from the device and is used to transfer Output
data via this pin to the controlling master. Output data is serially
shifted out on this pin from the rising edge of the SCK. This pin is
active only when the device is selected.
Address Field
This is a 8-bit field and should immediately follow the Opcode bits.
In FM93CS66, all 8 bits are used for address decoding during
READ, WRITE and PRWRITE instructions.During all other instructions (with the exception of PRREAD), the MSB 2 bits are
used to decode instruction (along with Opcode bits, PRE and PE
signals).
Protect Register Enable (PRE)
This is an active high input pin to the device and is used to
distinguish operations to memory array and operations to Protect
Register. When this pin is held low, operations to the memory
array are enabled. When this pin is held high, operations to the
Protect Register are enabled. This pin operates in conjunction
with PE pin. Refer Table1 for functional matrix of this pin for
various operations.
Data Field
This is a 16-bit field and should immediately follow the Address
bits. Only the WRITE and WRALL instructions require this field.
D15 (MSB) is clocked first and D0 (LSB) is clocked last (both
during writes as well as reads).
TABLE 1. Instruction set
Instruction
PRE Pin
PE Pin
READ
Start Bit Opcode Field
1
10
A7
A6
A5
Address Field
A4
A3
A2
A1
A0
0
X
WEN
1
00
1
1
X
X
X
X
X
X
0
1
WRITE
1
01
A7
A6
A5
A4
A3
A2
A1
A0
D15-D0
0
1
WRALL
1
00
0
1
X
X
X
X
X
X
D15-D0
0
1
WDS
1
00
0
0
X
X
X
X
X
X
0
X
PRREAD
1
10
X
X
X
X
X
X
X
X
1
X
PREN
1
00
1
1
X
X
X
X
X
X
1
1
PRCLEAR
1
11
1
1
1
1
1
1
1
1
1
1
PRWRITE
1
01
A7
A6
A5
A4
A3
A2
A1
A0
1
1
PRDS
1
00
0
0
0
0
0
0
0
0
1
1
5
FM93CS66 Rev. A
Data Field
www.fairchildsemi.com
FM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
Pin Description
A typical Microwire cycle starts by first selecting the device
(bringing the CS signal high). Once the device is selected, a valid
Start bit (“1”) should be issued to properly recognize the cycle.
Following this, the 2-bit opcode of appropriate instruction should
be issued. After the opcode bits, the 8-bit address information
should be issued. For certain instructions, some (or all) of these
8 bits are don’t care values (can be “0” or “1”), but they should still
be issued. Following the address information, depending on the
instruction (WRITE and WRALL), 16-Bit data is issued. Otherwise, depending on the instruction (READ and PRREAD), the
device starts to drive the output data on the DO line. Other
instructions perform certain control functions and do not deal with
data bits. The Microwire cycle ends when the CS signal is brought
low. However during certain instructions, falling edge of the CS
signal initiates an internal cycle (Programming), and the device
remains busy till the completion of the internal cycle. Each of the
10 instructions is explained in detail in the following sections.
3) Write (WRITE)
WRITE instruction allows write operation to a specified location in
the memory with a specified data. This instruction is valid only
when the following are true:
■ Device is write-enabled (Refer WEN instruction)
■ Address of the write location is not write-protected
■ PE pin is held high during this cycle
■ PRE pin should be held low during this cycle
Input information (Start bit, Opcode, Address and Data) for this
WRITE instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Memory Instructions
Following five instructions, READ, WEN, WRITE, WRALL and
WDS are specific to operations intended for memory array. The
PRE pin should be held low during these instructions.
1) Read and Sequential Read (READ)
The status of the internal programming cycle can be polled at any
time by bringing the CS signal high again, after tCS interval. When
CS signal is high, the DO pin indicates the READY/BUSY status
of the chip. DO = logical 0 indicates that the programming is still
in progress. DO = logical 1 indicates that the programming is
finished and the device is ready for another instruction. It is not
required to provide the SK clock during this status polling. While
the device is busy, it is recommended that no new instruction be
issued. Refer Write cycle diagram.
READ instruction allows data to be read from a selected location
in the memory array. Input information (Start bit, Opcode and
Address) for this instruction should be issued as listed under
Table1. Upon receiving a valid input information, decoding of the
opcode and the address is made, followed by data transfer from
the selected memory location into a 16-bit serial-out shift register.
This 16-bit data is then shifted out on the DO pin. D15 bit (MSB)
is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit
(logical 0) precedes this 16-bit data output string. Output data
changes are initiated on the rising edge of the SK clock. After
reading the 16-bit data, the CS signal can be brought low to end
the Read cycle. The PRE pin should be held low during this cycle.
Refer Read cycle diagram.
It is also recommended to follow this instruction (after the device
becomes READY) with a Write Disable (WDS) instruction to
safeguard data against corruption due to spurious noise, inadvertent writes etc.
4) Write All (WRALL)
This device also offers “sequential memory read” operation to
allow reading of data from the additional memory locations instead
of just one location. It is started in the same manner as normal read
but the cycle is continued to read further data (instead of terminating after reading the first 16-bit data). After providing 16-bit data,
the device automatically increments the address pointer to the
next location and continues to provide the data from that location.
Any number of locations can be read out in this manner, however,
after reading out from the last location, the address pointer points
back to the first location. If the cycle is continued further, data will
be read from this first location onward. In this mode of read, the
dummy-bit is present only when the very first data is read (like
normal read cycle) and is not present on subsequent data reads.
The PRE pin should be held low during this cycle. Refer Sequential Read cycle diagram.
Write all (WRALL) instruction is similar to the Write instruction
except that WRALL instruction will simultaneously program all
memory locations with the data pattern specified in the instruction.
This instruction is valid only when the following are true:
■ Protect Register has been cleared (Refer PRCLEAR
instruction)
■ Device is write-enabled (Refer WEN instruction)
■ PE pin is held high during this cycle
■ PRE pin should be held low during this cycle
Input information (Start bit, Opcode, Address and Data) for this
WRALL instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer Write All
cycle diagram.
2) Write Enable (WEN)
When VCC is applied to the part, it “powers up” in the Write Disable
(WDS) state. Therefore, all programming operations (for both
memory array and Protect Register) must be preceded by a Write
Enable (WEN) instruction. Once a Write Enable instruction is
executed, programming remains enabled until a Write Disable
(WDS) instruction is executed or VCC is completely removed from
6
FM93CS66 Rev. A
www.fairchildsemi.com
FM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
the part. Input information (Start bit, Opcode and Address) for this
WEN instruction should be issued as listed under Table1. The
device becomes write-enabled at the end of this cycle when the
CS signal is brought low. The PRE pin should be held low during
this cycle. Execution of a READ instruction is independent of WEN
instruction. Refer Write Enable cycle diagram.
Functional Description
Write Disable (WDS) instruction disables all programming operations and is recommended to follow all programming operations.
Executing this instruction after a valid write instruction would
protect against accidental data disturb due to spurious noise,
glitches, inadvertent writes etc. Input information (Start bit, Opcode
and Address) for this WDS instruction should be issued as listed
under Table1. The device becomes write-disabled at the end of
this cycle when the CS signal is brought low. Execution of a READ
instruction is independent of WDS instruction. Refer Write Disable
cycle diagram.
■ PE pin is held high during this cycle
■ PRE pin is held high during this cycle
Input information (Start bit, Opcode and Address) for this PRCLEAR
instruction should be issued as listed under Table1. After inputting
the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed clear cycle. It takes tWP time (Refer
appropriate DC and AC Electrical Characteristics table) for the
internal clear cycle to finish. During this time, the device remains
busy and is not ready for another instruction. Status of the internal
programming can be polled as described under WRITE instruction
description. While the device is busy, it is recommended that no
new instruction be issued. Refer Protect Register Clear cycle
diagram.
Protect Register Instructions
Following five instructions, PRREAD, PREN, PRCLEAR,
PRWRITE and PRDS are specific to operations intended for
Protect Register. The PRE pin should be held high during these
instructions.
4) Protect Register Write (PRWRITE)
1) Protect Register Read (PRREAD)
This instruction is used to write the starting address of the memory
section to be write-protected into the Protect register. After the
execution of PRWRITE instruction, all memory locations greater
than or equal to this address are write-protected. PRWRITE
instruction is enabled (valid) only the following are true:
This instruction reads the content of the internal Protect Register.
Content of this register is 8-bit wide and is the starting address of
the “write-protected” section of the memory array. All memory
locations greater than or equal to this address are write-protected.
Input information (Start bit, Opcode and Address) for this PRREAD
instruction should be issued as listed under Table 1. Upon
receiving a valid input information, decoding of the opcode and the
address is made, followed by data transfer (address information)
from the Protect Register. This 8-bit data is then shifted out on the
DO pin with the MSB first and the LSB last. Like the READ
instruction a dummy-bit (logical 0) precedes this 8-bit data output
string. Output data changes are initiated on the rising edge of the
SK clock. After reading the 8-bit data, the CS signal can be brought
low to end the PRREAD cycle. The PRE pin should be held high
during this cycle. Refer Protect Register Read cycle diagram.
■ PRCLEAR instruction was executed first (to clear the Protect
Register)
■ PREN instruction was executed immediately prior to
PRWRITE instruction
■ PE pin is held high during this cycle
■ PRE pin is held high during this cycle
Input information (Start bit, Opcode and Address) for this PRWRITE
instruction should be issued as listed under Table1. After inputting
the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer Protect
Register Write cycle diagram.
2) Protect Register Enable (PREN)
This instruction is required to enable PRCLEAR, PRWRITE and
PRDS instructions and should be executed prior to executing
PRCLEAR, PRWRITE and PRDS instructions. However, this
PREN instruction is enabled (valid) only the following are true
■ Device is write-enabled (Refer WEN instruction)
■ PE pin is held high during this cycle
■ PRE pin is held high during this cycle
5) Protect Register Disable (PRDS)
Input information (Start bit, Opcode and Address) for this PREN
instruction should be issued as listed under Table1. The Protect
Register becomes enabled for PRCLEAR, PRWRITE and PRDS
instructions at the end of this cycle when the CS signal is brought
low. Note that this PREN instruction must immediately precede
a PRCLEAR, PRWRITE or PRDS instruction. In other words, no
other instruction should be executed between a PREN instruction
and a PRCLEAR, PRWRITE or PRDS instruction. Refer Protect
Register Enable cycle diagram.
Unlike all other instructions, this instruction is a one-time-only
instruction which when executed permanently write-protects
the Protect Register and renders it unalterable in the future. This
instruction is useful to safeguard vital data (typically read only
data) in the memory against any possible corruption. PRDS
instruction is enabled (valid) only the following are true:
■ PREN instruction was executed immediately prior to PRDS
instruction
■ PE pin is held high during this cycle
3) Protect Register Clear (PRCLEAR)
■ PRE pin is held high during this cycle
This instruction clears the content of the Protect register and
therefore enables write operations (WRITE or WRALL) to all
memory locations. Executing this instruction will program the
content of the Protect Register with a pattern of all 1s. However,
in this case, WRITE operation to the last memory address
(0x11111111) is still enabled. PRCLEAR instruction is enabled
(valid) only when the following are true:
7
FM93CS66 Rev. A
www.fairchildsemi.com
FM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
■ PREN instruction was executed immediately prior to
PRCLEAR instruction
5) Write Disable (WDS)
Clearing of Ready/Busy status
When programming is in progress, the Data-Out pin will display
the programming status as either BUSY (low) or READY (high)
when CS is brought high (DO output will be tri-stated when CS is
low). To restate, during programming, the CS pin may be brought
high and low any number of times to view the programming status
without affecting the programming operation. Once programming
is completed (Output in READY state), the output is ‘cleared’
(returned to normal tri-state condition) by clocking in a Start Bit.
After the Start Bit is clocked in, the output will return to a tri-stated
condition. When clocked in, this Start Bit can be the first bit in a
command string, or CS can be brought low again to reset all
internal circuits. Refer Clearing Ready Status diagram.
Related Document
Application Note: AN758 - Using Fairchild’s MICROWIRE™ EEPROM.
8
FM93CS66 Rev. A
www.fairchildsemi.com
FM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
Input information (Start bit, Opcode and Address) for this PRDS
instruction should be issued as listed under Table1. After inputting
the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. The Protect
Register is permanently write-protected at the end of this cycle.
Refer Protect Register Disable cycle diagram.
FM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams
;
;;
;;; ;; ;;
;;; ;; ;;
;;; ;;
;
;;;;;; ;;
;;;;;; ;;
;;;; ; ;;
;;; ;;;;;
;; ;;;;;;;;;
;;;;;;
; ;;;;;;;;
;
;;;;;;
; ;;;;;;;
;;;;;;;;
;
; ;;;;;;;
;;;;;;;;;
; ;
SYNCHRONOUS DATA TIMING
CS
tSKS
SK
tCSS
tSKH
tSKL
tCSH
tPREH
tPRES
PRE
tPEH
tPES
PE
tDIS
tDIH
Valid
Input
DI
;
;
;
; ;
;
; ;
;
; ; ;
; ;;;
;
; ;;;
;
; ;;;
;
; ;;
;
;
; ;;;;;;;;;;;;;;;;;;;
; ;
;
;;;;;;;;;;;;;;;;;;;;;
;;;;;;;
; ;;;;;;;; ;
;;;;;; ;;;;;;;; ;
;
Valid
Input
tPD
tDF
tPD
tDH
Valid
Output
DO (Data Read)
tSV
DO (Status Read)
Valid
Output
tDF
Valid Status
NORMAL READ CYCLE (READ)
;;;;
;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
1
0
A7
A6
Opcode
Bits(2)
A1
A0
Address
Bits(8)
High - Z
DO
;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
;;;
;;;
0
D15
D1
D0
D u m my
Bit
93CS66:
Address bits pattern -> User defined
SEQUENTIAL READ CYCLE (PRE = 0; PE = X)
;;;;
;;;;
PRE
tCS
CS
SK
DI
1
Star t
Bit
DO
1
0
A7
Opcode
Bits(2)
A0
Address
Bits(8)
High - Z
;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;
;;;
;;;
0
Dummy
Bit
93CS66:
Address bits patter n -> User defined
D15
D0
Data(n)
9
FM93CS66 Rev. A
D15
D0
Data(n+1)
D15
D0
Data(n+2)
www.fairchildsemi.com
FM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams (Continued)
WRITE ENABLE CYCLE (WEN)
PRE
PE
tCS
CS
SK
DI
1
0
Star t
Bit
0
A7
A6
Opcode
Bits(2)
A1
A0
Address
Bits(8)
High - Z
DO
93CS66:
A d d r e s s b i t s p a t t e r n - > 1 - 1 - x - x - x - x - x - x ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 )
WRITE DISABLE CYCLE (WDS)
PRE
PE
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
tCS
CS
SK
DI
1
0
Star t
Bit
0
A7
A6
Opcode
Bits(2)
A1
A0
Address
Bits(8)
High - Z
DO
93CS66:
Address bits patter n -> 0-0-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
WRITE CYCLE (WRITE)
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
0
1
A7
Opcode
Bits(2)
A6
A1
A0
D15 D14
Address
Bits(8)
Data
Bits(16)
D1
D0
tWP
High - Z
DO
Ready
Busy
93CS66:
Address bits pattern -> User defined
Data bits pattern
-> User defined
10
FM93CS66 Rev. A
www.fairchildsemi.com
WRITE ALL CYCLE (WRALL)
PRE
PE
tCS
CS
SK
1
DI
0
Star t
Bit
0
A7
A6
Opcode
Bits(2)
A1
A0
D15 D14
Address
Bits(8)
D1
D0
tWP
Data
Bits(16)
High - Z
DO
Ready
Busy
93CS66:
Address bits patter n -> 0-1-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Data bits patter n
-> User defined
PROTECT REGISTER READ CYCLE (PRREAD)
;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
1
Star t
Bit
0
A7
A6
Opcode
Bits(2)
A1
A0
Address
Bits(8)
High - Z
DO
;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
;;;
;;;
D7
0
D1
D0
Dummy
Bit
93CS66:
Address bits patter n -> x-x-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
PROTECT REGISTER ENABLE CYCLE (PREN)
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
0
0
Opcode
Bits(2)
A7
A6
A1
A0
Address
Bits(8)
High - Z
DO
93CS66:
Address bits patter n -> 1-1-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
11
FM93CS66 Rev. A
www.fairchildsemi.com
FM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams (Continued)
FM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams (Continued)
PROTECT REGISTER CLEAR CYCLE (PRCLEAR)
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
1
1
Opcode
Bits(2)
DO
A7
A6
A1
A0
tWP
Address
Bits(8)
High - Z
Ready
Busy
93CS66:
Address bits patter n -> 1-1-1-1-1-1-1-1
PROTECT REGISTER WRITE CYCLE (PRWRITE)
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
0
1
Opcode
Bits(2)
DO
A7
A6
A1
A0
tWP
Address
Bits(8)
High - Z
Ready
Busy
93CS66:
Address bits patter n -> User defined
PROTECT REGISTER DISABLE CYCLE (PRDS)
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
PRE
PE
tCS
CS
SK
DI
1
Star t
Bit
DO
0
0
Opcode
Bits(2)
A7
High - Z
A6
A1
Address
Bits(8)
A0
tWP
Ready
Busy
93CS66:
Address bits patter n -> 0-0-0-0-0-0-0-0
12
FM93CS66 Rev. A
www.fairchildsemi.com
FM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
Timing Diagrams (Continued)
CLEARING READY STATUS
PRE
PE
;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;
CS
SK
DI
Star t
Bit
DO
High - Z
Ready
High - Z
Busy
Note: This Star t bit can also be par t of a next instr uction. Hence the cycle
can be continued(instead of getting ter minated, as shown) as if a new
instr uction is being issued.
13
FM93CS66 Rev. A
www.fairchildsemi.com
FM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
8° Max, Typ.
All leads
0.04
(0.102)
All lead tips
0.053 - 0.069
(1.346 - 1.753)
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020 Typ.
(0.356 - 0.508)
Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8)
Package Number M08A
14
FM93CS66 Rev. A
www.fairchildsemi.com
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0098
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
15
FM93CS66 Rev. A
www.fairchildsemi.com
FM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
+
Pin #1 IDENT
8
0.032 ± 0.005
(6.35 ± 0.127)
Pin #1
IDENT
1
Option 1
1
0.280 MIN
(7.112)
0.300 - 0.320
(7.62 - 8.128)
7
(0.813 ± 0.127)
RAD
5
2
3
0.040 Typ.
(1.016)
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
0.039
(0.991)
(3.683 - 5.080)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
Français
Tel:
+33 (0) 1-6930-3696
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Tel:
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Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
16
FM93CS66 Rev. A
www.fairchildsemi.com
FM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
Physical Dimensions inches (millimeters) unless otherwise noted
FMB100
C2
E1
C1
B2
E2
pin #1 B1
SuperSOT-6
Mark: .NA
NPN Multi-Chip General Purpose Amplifier
This device is designed for general purpose amplifier applications at collector
currents to 300 mA. Sourced from Process 10.
Absolute Maximum Ratings*
Symbol
TA =25°C unless otherwise noted
Parameter
Value
Units
VCEO
Collector-Emitter Voltage
45
V
VCBO
Collector-Base Voltage
75
V
VEBO
Emitter-Base Voltage
6.0
V
IC
Collector Current - Continuous
500
mA
TJ, Tstg
Operating and Storage Junction Temperature Range
-55 to +150
°C
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150 degrees C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
Symbol
PD
RθJA
TA= 25°C unless otherwise noted
Characteristic
Total Device Dissipation
Derate above 25°C
Thermal Resistance, Junction to Ambient
 1998 Fairchild Semiconductor Corporation
Max
Units
FMB100
700
5.6
180
mW
mW/°C
°C/W
FMB100
Discrete POWER & Signal
Technologies
(continued)
Electrical Characteristics
Symbol
TA= 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max Units
OFF CHARACTERISTICS
IC = 10 µA, IB = 0
IC = 1 mA, IE = 0
75
V
45
V
6.0
V
Collector Cutoff Current
IE = 10 µA, IC = 0
VCB = 60 V
50
nA
Collector Cutoff Current
VCE = 40 V
50
nA
Emitter Cutoff Current
VEB = 4 V
50
nA
BVCBO
Collector-Base Breakdown Voltage
BVCEO
BVEBO
Collector-Emitter Breakdown
Voltage*
Emitter-Base Breakdown Voltage
ICBO
ICES
IEBO
ON CHARACTERISTICS
hFE
DC Current Gain
VCE(sat)
Collector-Emitter Saturation Voltage
VBE(sat)
Base-Emitter Saturation Voltage
IC = 100 µA, VCE = 1.0 V
IC = 10 mA, VCE = 1.0 V
IC = 100 mA, VCE = 1.0 V*
IC = 150 mA, VCE = 5.0 V*
IC = 10 mA, IB = 1.0 mA
IC = 200 mA, IB = 20 mA*
IC = 10 mA, IB = 1.0 mA
IC = 200 mA, IB = 20 mA*
80
100
100
100
450
350
0.2
0.4
0.85
1.0
V
V
V
V
SMALL SIGNAL CHARACTERISTICS
fT
Current Gain - Bandwidth Product
VCE = 20 V, IC = 20 mA
300
MHz
Cobo
NF
Output Capacitance
VCB = 5.0 V, f = 1.0 MHz
3.5
pF
Noise Figure
IC = 100 µA, VCE = 5.0 V,
RG = 2.0 kΩ, f = 1.0 kHz
2.5
dB
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
Typical Pulsed Current Gain
vs Collector Current
400
Vce = 5V
125 °C
300
25 °C
200
- 40 °C
100
0
10
20 30
50
100
200 300
I C - COLLECTOR CURRENT (mA)
500
VCESAT- COLLECTOR-EMITTER VOLTAGE (V)
h FE - TYPICAL PULSED CURRENT GAIN
Typical Characteristics
Collector-Emitter Saturation
Voltage vs Collector Current
0.4
β = 10
0.3
25 °C
0.2
125 °C
0.1
- 40 °C
1
10
100
I C - COLLECTOR CURRENT (mA)
400
FMB100
NPN Multi-Chip General Purpose Amplifier
(continued)
(continued)
Base-Emitter Saturation
Voltage vs Collector Current
1
- 40 °C
0.8
25 °C
0.6
125 °C
0.4
β = 10
0.2
0.1
1
10
100
I C - COLLECTOR CURRENT (mA)
300
VBEON- BASE-EMITTER ON VOLTAGE (V)
VBESAT- COLLECTOR-EMITTER VOLTAGE (V)
Typical Characteristics
Base-Emitter ON Voltage vs
Collector Current
1
25 °C
0.6
125 °C
0.4
V CE = 5V
0.2
1
10
100
I C - COLLECTOR CURRENT (mA)
100
10
f = 1.0 MHz
CAPACITANCE (pF)
VCB = 60V
1
0.1
25
50
75
100
125
TA - AMBIENT TEMPERATURE ( ºC)
10
Cib
Cob
1
0.1
0.1
150
1
10
Vce - COLLECTOR VOLTAGE(V)
Switching Times vs
Collector Current
1
PD - POWER DISSIPATION (W)
270
ts
240
210
180
IB1 = IB2 = Ic / 10
V cc = 10 V
150
120
90
tf
60
30
0
10
100
Power Dissipation vs
Ambient Temperature
300
TIME (nS)
500
Input and Output Capacitance
vs Reverse Voltage
Collector-Cutoff Current
vs Ambient Temperature
ICBO- COLLECTOR CURRENT (nA)
- 40 °C
0.8
tr
td
20
30
50
100
200
I C - COLLECTOR CURRENT (mA)
300
SOT-6
0.75
0.5
0.25
0
0
25
50
75
100
o
TEMPERATURE ( C)
125
150
FMB100
NPN Multi-Chip General Purpose Amplifier
FMB1020
Package: SuperSOT-6
Device Marking: .004
Note: The " . " (dot) signifies Pin 1
Transistor 1 is NPN device,
transistor 2 is PNP device.
NPN & PNP Complementary Dual Transistor
SuperSOT-6 Surface Mount Package
This dual complementary device was designed for use as a general purpose amplifier applications at
collector currents to 300mA. Sourced from Process 10 (NPN ) and Process 68 (PNP).
Absolute Maximum Ratings*
TA
= 25°C unless otherwise noted
Value
Units
Collector-Emitter Voltage
45
V
VCBO
Collector-Base Voltage
60
V
VEBO
Emitter-Base Voltage
6
V
IC
Collector Current
500
mA
TJ, TSTG
Operating and Storage Junction Temperature Range
-55 to +150
°C
Symbol
Parameter
VCEO
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150°C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
Symbol
TA
= 25°C unless otherwise noted
Characteristics
Max
Units
PD
Total Device Dissipation, total
per side
700
350
mW
RθJA
Thermal Resistance, Junction to Ambient, total
180
°C/W
 1998 Fairchild Semiconductor Corporation
Page 1 of 2
fmb1020.lwpPr10&68(Y4)
FMB1020
Discrete Power
&
Signal Technologies
(continued)
Electrical Characteristics
Symbol
TA
= 25°C unless otherwise noted
Parameter
Test Conditions
Min
Max
Units
OFF CHARACTERISTICS
BVCEO
Collector to Emitter Voltage
Ic = 1.0 mA
45
V
BVCBO
Collector to Base Voltage
Ic = 10 uA
60
V
BVEBO
Emitter to Base Voltage
Ie = 10 uA
6
V
ICBO
Collector Cutoff Current
Vcb = 50 V
50
nA
ICES
Collector Cutoff Current
Vce = 40 V
50
nA
IEBO
Emitter Cutoff Current
Veb = 4 V
50
nA
ON CHARACTERISTICS
hFE
DC Current Gain
Vce =
Vce =
Vce =
Vce =
1V,
1V,
1V,
5V,
Ic = 100uA
Ic = 10mA
Ic = 100mA
Ic = 150mA
80
100
100
100
450
350
VCE(sat)
Collector-Emitter Saturation Voltage Ic = 10mA, Ib = 1mA
Ic = 200mA, Ib = 20mA
0.2
0.4
V
VBE(sat)
Base-Emitter Saturation Voltage
0.85
1.0
V
SMALL SIGNAL CHARACTERISTICS
Output Capacitance
COB
Ic = 10mA, Ib = 1mA
Ic = 200mA, Ib = 20mA
Vcb = 10V, f = 1MHz
TYP
4.5
pF
fT
Current Gain - Bandwidth Product
Vce = 20V, Ic = 20mA, f = 100MHz
300
MHz
NF
Noise Figure
Vce = 5V, Ic = 100uA,
Rs = 2kohms, f = 1 kHz
2.5
dB
 1998 Fairchild Semiconductor Corporation
Page 2 of 2
fmb1020.lwpPr10&68(Y4)
FMB1020
NPN & PNP Complementary Dual Transistor
FMB200
C2
E1
C1
B2
E2
pin #1 B1
SuperSOT-6
Mark: .N2
PNP Multi-Chip General Purpose Amplifier
This device is designed for general purpose amplifier applications at collector
currents to 300 mA. Sourced from Process 68.
Absolute Maximum Ratings*
Symbol
TA = 25°C unless otherwise noted
Parameter
Value
Units
VCEO
Collector-Emitter Voltage
45
V
VCBO
Collector-Base Voltage
60
V
VEBO
Emitter-Base Voltage
6.0
V
IC
Collector Current - Continuous
500
mA
TJ, Tstg
Operating and Storage Junction Temperature Range
-55 to +150
°C
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150 degrees C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
Symbol
PD
RθJA
TA = 25°C unless otherwise noted
Characteristic
Total Device Dissipation
Derate above 25°C
Thermal Resistance, Junction to Ambient
 1998 Fairchild Semiconductor Corporation
Max
Units
FMB200
700
5.6
180
mW
mW/°C
°C/W
FMB200
Discrete POWER & Signal
Technologies
(continued)
Electrical Characteristics
Symbol
TA = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max Units
OFF CHARACTERISTICS
IC = 10 µA, IB = 0
IC = 1.0 mA, IE = 0
60
V
45
V
IE = 10 µA, IC = 0
VCB = 50 V, IE = 0
6.0
Collector Cutoff Current
ICES
Collector Cutoff Current
IEBO
Emitter Cutoff Current
BVCBO
Collector-Base Breakdown Voltage
BVCEO
BVEBO
Collector-Emitter Breakdown
Voltage*
Emitter-Base Breakdown Voltage
ICBO
V
50
nA
VCE = 40 V, IE = 10
50
nA
VEB = 4.0 V, IC = 0
50
nA
450
350
0.2
0.4
0.85
1.0
V
V
V
V
ON CHARACTERISTICS
hFE
DC Current Gain
VCE(sat)
Collector-Emitter Saturation Voltage
VBE(sat)
Base-Emitter Saturation Voltage
IC = 100 µA, VCE = 1.0 V
IC = 10 mA, VCE = 1.0 V
IC = 150 mA, VCE = 5.0 V*
IC = 10 mA, IB = 1.0 mA
IC = 200 mA, IB = 20 mA*
IC = 10 mA, IB = 1.0 mA
IC = 200 mA, IB = 20 mA*
80
100
100
SMALL SIGNAL CHARACTERISTICS
fT
Current Gain - Bandwidth Product
VCE = 20 V, IC = 20 mA
300
Cobo
NF
Output Capacitance
VCB = 10 V, f = 1.0 MHz
4.5
MHz
pF
Noise Figure
IC = 100 µA, VCE = 5.0 V,
RG = 2.0 kΩ, f = 1.0 kHz
2.5
dB
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
Typical Pulsed Current Gain
vs Collector Current
500
V CE = 5V
400
125 °C
300
25 °C
200
100
0
0.01
- 40 °C
0.1
1
10
100
IC - COLLECTOR CURRENT (mA)
VCESAT- COLLECTOR EMITTER VOLTAGE (V)
hFE - TYPICAL PULSED CURRENT GAIN
Typical Characteristics
Collector-Emitter Saturation
Voltage vs Collector Current
0.3
0.25
β = 10
0.2
0.15
25 °C
0.1
0.05
0
0.1
125 ºC
- 40 ºC
1
10
100
I C - COLLECTOR CURRENT (mA)
P 68
300
FMB200
PNP Multi-Chip General Purpose Amplifier
(continued)
(continued)
Base-Emitter Saturation
Voltage vs Collector Current
1.2
β = 10
1
0.8
- 40 ºC
25 °C
125 ºC
0.6
0.4
0.2
0
0.1
1
10
100
I C - COLLECTOR CURRENT (mA)
300
VBEON - BASE EMITTER ON VOLTAGE (V)
VBESAT- BASE EMITTER VOLTAGE (V)
Typical Characteristics
Base Emitter ON Voltage vs
Collector Current
1
0.8
- 40 ºC
25 °C
0.6
125 ºC
0.4
V CE = 5V
0.2
0
0.1
0.1
0.01
25
50
75
100
TA - AMBIENT TEMPERATURE ( º C)
125
BV CER - BREAKDOWN VOLTAGE (V)
1
95
90
85
80
75
70
0.1
1
10
100
Input and Output Capacitance
vs Reverse Voltage
4
100
Ta = 25°C
3
2
1000
RESISTANCE (kΩ )
Collector Saturation Region
Ic =
100 uA
300 mA
50 mA
1
f = 1.0 MHz
CAPACITANCE (pF)
VCE - COLLECTOR-EMITTER VOLTAGE (V)
ICBO- COLLECTOR CURRENT (nA)
V CB = 50V
10
100 200
Collector-Emitter Breakdown
Voltage with Resistance
Between Emitter-Base
Collector-Cutoff Current
vs. Ambient Temperature
100
1
10
I C - COLLECTOR CURRENT (mA)
10
Cib
Cob
0
100
300
700
I B - BASE CURRENT (uA)
2000 4000
0.1
1
10
Vce - COLLECTOR VOLTAGE(V)
100
FMB200
PNP Multi-Chip General Purpose Amplifier
(continued)
(continued)
Switching Times vs
Collector Current
Gain Bandwidth Product
vs Collector Current
300
40
270
Vce = 5V
ts
240
30
TIME (nS)
210
20
180
IB1 = IB2 = Ic / 10
V cc = 10 V
150
120
90
10
tf
60
30
0
1
10
20
50
100 150
0
10
20
30
50
100
200
I C - COLLECTOR CURRENT (mA)
P 68
Power Dissipation vs
Ambient Temperature
1
SOT-6
0.75
0.5
0.25
0
0
25
50
75
100
o
TEMPERATURE ( C)
tr
td
I C- COLLECTOR CURRENT (mA)
PD - POWER DISSIPATION (W)
f T - GAIN BANDWIDTH PRODUCT (MHz)
Typical Characteristics
125
150
300
FMB200
PNP Multi-Chip General Purpose Amplifier
FMB2222A
FFB2222A
E2
MMPQ2222A
C2
B2
E1
C1
C1
E1
C2
B1
B2
E3
E4
B4
B2
B1
pin #1
E2
B3
E2
E1
pin #1 B1
SC70-6
SuperSOT-6
Mark: .1P
Mark: .1P
C1
SOIC-16
C2
C1
C3
C2
C4
C4
C3
NPN Multi-Chip General Purpose Amplifier
This device is for use as a medium power amplifier and switch requiring collector
currents up to 500 mA. Sourced from Process 19.
Absolute Maximum Ratings*
Symbol
TA = 25°C unless otherwise noted
Parameter
Value
Units
VCEO
Collector-Emitter Voltage
40
V
VCBO
Collector-Base Voltage
75
V
VEBO
Emitter-Base Voltage
6.0
V
IC
Collector Current - Continuous
500
mA
TJ, Tstg
Operating and Storage Junction Temperature Range
-55 to +150
°C
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150 degrees C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
Symbol
PD
RθJA
TA = 25°C unless otherwise noted
Characteristic
Total Device Dissipation
Derate above 25°C
Thermal Resistance, Junction to Ambient
Effective 4 Die
Each Die
 1998 Fairchild Semiconductor Corporation
Max
FFB2222A
300
2.4
415
FMB2222A
700
5.6
180
Units
MMPQ2222A
1,000
8.0
125
240
mW
mW/°C
°C/W
°C/W
°C/W
FFB2222A / FMB2222A / MMPQ2222A
Discrete POWER & Signal
Technologies
(continued)
Electrical Characteristics
Symbol
TA = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max Units
OFF CHARACTERISTICS
V(BR)CEO
IC = 10 mA, IB = 0
V(BR)CBO
Collector-Emitter Breakdown
Voltage*
Collector-Base Breakdown Voltage
40
V
V(BR)EBO
Emitter-Base Breakdown Voltage
IC = 10 µA, IE = 0
75
V
IE = 10 µA, IC = 0
6.0
ICEX
Collector Cutoff Current
VCE = 60 V, VEB(OFF) = 3.0 V
ICBO
Collector Cutoff Current
IEBO
Emitter Cutoff Current
VCB = 60 V, IE = 0
VCB = 60 V, IE = 0, TA = 125°C
VEB = 3.0 V, IC = 0
IBL
Base Cutoff Current
VCE = 60 V, VEB(OFF) = 3.0 V
V
10
nA
0.01
10
10
µA
µA
nA
20
nA
ON CHARACTERISTICS
hFE
DC Current Gain
VCE(sat)
Collector-Emitter Saturation Voltage*
VBE(sat)
Base-Emitter Saturation Voltage*
IC = 0.1 mA, VCE = 10 V
IC = 1.0 mA, VCE = 10 V
IC = 10 mA, VCE = 10 V
IC= 10 mA,VCE= 10 V,TA= -55°C
IC = 150 mA, VCE = 10 V*
IC = 150 mA, VCE = 1.0 V*
IC = 500 mA, VCE = 10 V*
IC = 150 mA, IB = 15 mA
IC = 500 mA, IB = 50 mA
IC = 150 mA, IB = 1.0 mA
IC = 500 mA, IB = 50 mA
35
50
75
35
100
50
40
300
0.3
1.0
1.2
2.0
0.6
V
V
V
V
SMALL SIGNAL CHARACTERISTICS
fT
Current Gain - Bandwidth Product
300
Output Capacitance
IC = 20 mA, VCE = 20 V,
f = 100 MHz
VCB = 10 V, IE = 0, f = 100 kHz
Cobo
Cibo
NF
MHz
4.0
pF
Input Capacitance
VEB = 0.5 V, IC = 0, f = 100 kHz
20
pF
Noise Figure
IC = 100 µA, VCE = 10 V,
RS = 1.0 kΩ, f = 1.0 kHz
2.0
dB
SWITCHING CHARACTERISTICS
td
Delay Time
VCC = 30 V, VBE(OFF) = 0.5 V,
8
ns
tr
Rise Time
IC = 150 mA, IB1 = 15 mA
20
ns
ts
Storage Time
VCC = 30 V, IC = 150 mA,
180
ns
tf
Fall Time
IB1 = IB2 = 15 mA
40
ns
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
FFB2222A / FMB2222A / MMPQ2222A
NPN Multi-Chip General Purpose Amplifier
(continued)
VCE = 5V
400
125 °C
300
200
25 °C
100
- 40 °C
0
0.1
0.3
1
3
10
30
100
I C - COLLECTOR CURRENT (mA)
300
Base-Emitter Saturation
Voltage vs Collector Current
β = 10
1
- 40 °C
0.8
25 °C
0.6
125 °C
0.4
1
IC
10
100
- COLLECTOR CURRENT (mA)
500
VCESAT- COLLECTOR-EMITTER VOLTAGE (V)
500
VBE(ON)- BASE-EMITTER ON VOLTAGE (V)
Typical Pulsed Current Gain
vs Collector Current
VBESAT- BASE-EMITTER VOLTAGE (V)
h FE - TYPICAL PULSED CURRENT GAIN
Typical Characteristics
0.4
β = 10
0.3
125 °C
0.2
25 °C
0.1
- 40 °C
1
10
100
I C - COLLECTOR CURRENT (mA)
500
Base-Emitter ON Voltage vs
Collector Current
1
VCE = 5V
0.8
- 40 °C
25 °C
0.6
125 °C
0.4
0.2
0.1
1
10
I C - COLLECTOR CURRENT (mA)
25
Emitter Transition and Output
Capacitance vs Reverse Bias Voltage
500
100
V
CB
20
= 40V
CAPACITANCE (pF)
I CBO- COLLECTOR CURRENT (nA)
Collector-Cutoff Current
vs Ambient Temperature
Collector-Emitter Saturation
Voltage vs Collector Current
10
1
0.1
16
12
C te
8
4
25
50
75
100
125
T A - AMBIENT TEMPERATURE ( °C)
150
f = 1 MHz
0.1
C ob
1
10
REVERSE BIAS VOLTAGE (V)
100
FFB2222A / FMB2222A / MMPQ2222A
NPN Multi-Chip General Purpose Amplifier
(continued)
Typical Characteristics
(continued)
Turn On and Turn Off Times
vs Collector Current
Switching Times
vs Collector Current
400
400
I B1 = I B2 =
320
Ic
V cc = 25 V
TIME (nS)
240
160
t off
80
240
ts
160
tr
tf
80
t on
td
100
I C - COLLECTOR CURRENT (mA)
1000
0
10
100
I C - COLLECTOR CURRENT (mA)
Power Dissipation vs
Ambient Temperature
1
PD - POWER DISSIPATION (W)
TIME (nS)
10
320
V cc = 25 V
0
10
Ic
I B1 = I B2 =
10
SOT-6
0.75
0.5
0.25
0
0
25
50
75
100
o
TEMPERATURE ( C)
125
150
1000
FFB2222A / FMB2222A / MMPQ2222A
NPN Multi-Chip General Purpose Amplifier
(continued)
Test Circuits
30 V
200 Ω
16 V
1.0 KΩ
Ω
0
≤ 200ns
500 Ω
FIGURE 1: Saturated Turn-On Switching Time
6.0 V
- 15 V
1k
30 V
1.0 KΩ
Ω
0
≤ 200ns
50 Ω
FIGURE 2: Saturated Turn-Off Switching Time
37 Ω
FFB2222A / FMB2222A / MMPQ2222A
NPN Multi-Chip General Purpose Amplifier
FMB2227A
C2
Package: SuperSOT-6
Device Marking: .001
Note: The " . " (dot) signifies Pin 1
E1
C1
Transistor 1 is NPN device,
transistor 2 is PNP device.
B2
E2
B1
NPN & PNP Complementary Dual Transistor
SuperSOT-6 Surface Mount Package
This complementary dual device was designed for use as a medium power amplifier and switch requiring
collector currents up to 300mA. Sourced from Pr19 (NPN) and Pr63 (PNP).
Absolute Maximum Ratings
TA
= 25°C unless otherwise noted
Value
Units
Collector-Emitter Voltage
30
V
VCBO
Collector-Base Voltage
60
V
VEBO
Emitter-Base Voltage
5
V
IC
Collector Current
500
mA
PD
Power Dissipation @Ta = 25°C*
0.7
W
TSTG
Storage Temperature Range
-55 to +150
°C
TJ
Junction Temperature
150
°C
RθJA
Thermal Resistance, Junction to Ambient
180
°C/W
Symbol
Parameter
VCEO
Electrical Characteristics
TA
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
BVCEO
Collector to Emitter Voltage
Ic = 10 mA
30
V
BVCBO
Collector to Base Voltage
Ic = 10 uA
60
V
BVEBO
Emitter to Base Voltage
Ie = 10 uA
5
V
 1998 Fairchild Semiconductor Corporation
Page 1 of 2
Min
Max
Units
2227A.lwpPr19&63(Y1)
FMB2227A
Discrete Power
&
Signal Technologies
(continued)
Electrical Characteristics
TA = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
ICBO
Collector Cutoff Current
Vcb = 50V
30
nA
IEBO
Emitter Cutoff Current
Veb = 3.0V
30
nA
hFE
DC Current Gain
Vce =
Vce =
Vce =
Vce =
VCE(sat)
Collector-Emitter Saturation Voltage Ic = 150mA, Ib=15mA
Ic = 300mA, Ib=30mA
0.4
1.4
V
VBE(sat)
Base-Emitter Saturation Voltage
1.3
V
10V,
10V,
10V,
10V,
Ic = 1.0mA
Ic = 10mA
Ic = 150mA
Ic = 300mA
Min
Max
50
75
100
30
-
Ic = 150mA, Ib=15mA
Small - Signal Characteristics
Units
Typical
COB
Output Capacitance
Vcb = 10V, f = 1.0MHz
6
pF
CIB
Input Capacitance
Veb = 0.5V, f = 100kHz
20
pF
fT
Current Gain - Bandwidth Product
Vce = 20V, Ic = 50mA, f = 100MHz
250
MHz
 1998 Fairchild Semiconductor Corporation
Page 2 of 2
2227A.lwpPr19&63(Y1)
FMB2227A
NPN & PNP Complementary Dual Transistor
FMB2907A
FFB2907A
E2
MMPQ2907A
C2
B2
E1
C1
C1
E1
C2
B2
E3
E4
B4
B2
B1
pin #1
B1
E2
B3
E2
E1
pin #1 B1
SC70-6
SuperSOT-6
Mark: .2F
Mark: .2F
C1
SOIC-16
C2
C1
C3
C2
C4
C4
C3
PNP Multi-Chip General Purpose Amplifier
This device is designed for use as a general purpose amplifier and switch requiring
collector currents to 500 mA. Sourced from Process 63.
Absolute Maximum Ratings*
Symbol
TA = 25°C unless otherwise noted
Parameter
Value
Units
VCEO
Collector-Emitter Voltage
60
V
VCBO
Collector-Base Voltage
60
V
VEBO
Emitter-Base Voltage
5.0
V
IC
Collector Current - Continuous
600
mA
TJ, Tstg
Operating and Storage Junction Temperature Range
-55 to +150
°C
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150 degrees C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
Symbol
PD
RθJA
TA = 25°C unless otherwise noted
Characteristic
Total Device Dissipation
Derate above 25°C
Thermal Resistance, Junction to Ambient
Effective 4 Die
Each Die
 1998 Fairchild Semiconductor Corporation
Max
FFB2907A
300
2.4
415
FMB2907A
700
5.6
180
Units
MMPQ2907A
1,000
8.0
125
240
mW
mW/°C
°C/W
°C/W
°C/W
FFB2907A / FMBT2907A / MMPQ2907A
Discrete POWER & Signal
Technologies
(continued)
Electrical Characteristics
Symbol
TA = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max Units
OFF CHARACTERISTICS
V(BR)CEO
IC = 10 mA, IB = 0
V(BR)CBO
Collector-Emitter Breakdown
Voltage*
Collector-Base Breakdown Voltage
60
V
V(BR)EBO
Emitter-Base Breakdown Voltage
IC = 10 µA, IE = 0
60
V
IE = 10 µA, IC = 0
5.0
IB
Base Cutoff Current
VCB = 30 V, VEB = 0.5 V
ICEX
Collector Cutoff Current
VCE = 30 V, VBE = 0.5 V
ICBO
Collector Cutoff Current
VCB = 50 V, IE = 0
VCB = 50 V, IE = 0, TA = 125°C
V
50
nA
50
nA
0.02
20
µA
µA
ON CHARACTERISTICS
hFE
DC Current Gain
VCE(sat)
Collector-Emitter Saturation Voltage*
VBE(sat)
Base-Emitter Saturation Voltage
IC = 0.1 mA, VCE = 10 V
IC = 1.0 mA, VCE = 10 V
IC = 10 mA, VCE = 10 V
IC = 150 mA, VCE = 10 V*
IC = 500 mA, VCE = 10 V*
IC = 150 mA, IB = 15 mA
IC = 500 mA, IB = 50 mA
IC = 150 mA, IB = 15 mA*
IC = 500 mA, IB = 50 mA
75
100
100
100
50
300
0.4
1.6
1.3
2.6
V
V
V
V
SMALL SIGNAL CHARACTERISTICS
fT
Current Gain - Bandwidth Product
Cobo
Output Capacitance
Cibo
Input Capacitance
IC = 50 mA, VCE = 20 V,
f = 100 MHz
VCB = 10 V, IE = 0,
f = 100 kHz
VEB = 2.0 V, IC = 0,
f = 100 kHz
250
MHz
6.0
pF
12
pF
SWITCHING CHARACTERISTICS
ton
Turn-on Time
VCC = 30 V, IC = 150 mA,
30
ns
td
Delay Time
IB1 = 15 mA
8.0
ns
tr
Rise Time
20
ns
toff
Turn-off Time
VCC = 6.0 V, IC = 150 mA
80
ns
ts
Storage Time
IB1 = IB2 = 15 mA
60
ns
tf
Fall Time
20
ns
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
FFB2907A / FMBT2907A / MMPQ2907A
PNP Multi-Chip General Purpose Amplifier
(continued)
500
VCE = 5V
400
125 °C
300
200
100
0
0.1
25 °C
- 40 °C
0.3
1
3
10
30
100
I C - COLLECTOR CURRENT (mA)
300
Base-Emitter Saturation
Voltage vs Collector Current
1
0.8
- 40 ºC
25 °C
0.6
125 ºC
0.4
β = 10
0.2
0
1
10
100
I C - COLLECTOR CURRENT (mA)
500
VCESAT - COLLECTOR EMITTER VOLTAGE (V)
Typical Pulsed Current Gain
vs Collector Current
Collector-Emitter Saturation
Voltage vs Collector Current
0.5
β = 10
0.4
0.3
25 °C
0.2
125 ºC
0.1
0
VBEON - BASE EMITTER ON VOLTAGE (V)
VBESAT - BASE EMITTER VOLTAGE (V)
hFE - TYPICAL PULSED CURRENT GAIN
Typical Characteristics
- 40 ºC
1
500
Base Emitter ON Voltage vs
Collector Current
1
0.8
- 40 ºC
25 °C
0.6
125 ºC
0.4
VCE = 5V
0.2
0
0.1
1
10
I C - COLLECTOR CURRENT (mA)
25
Input and Output Capacitance
vs Reverse Bias Voltage
Collector-Cutoff Current
vs. Ambient Temperature
100
20
V CB = 35V
CAPACITANCE (pF)
ICBO- COLLECTOR CURRENT (nA)
10
100
I C - COLLECTOR CURRENT (mA)
10
1
0.1
0.01
25
50
75
100
TA - AMBIENT TEMPERATURE ( º C)
125
16
12
C ib
8
4
0
0.1
C ob
1
10
REVERSE BIAS VOLTAGE (V)
50
FFB2907A / FMBT2907A / MMPQ2907A
PNP Multi-Chip General Purpose Amplifier
(continued)
Typical Characteristics
(continued)
Switching Times
vs Collector Current
250
I B1 = I B2 =
200
Turn On and Turn Off Times
vs Collector Current
500
Ic
I B1 = I B2 =
10
400
V cc = 15 V
TIME (nS)
TIME (nS)
V cc = 15 V
ts
150
100
tr
tf
50
300
200
t off
100
td
0
10
100
I C - COLLECTOR CURRENT (mA)
t on
0
10
1000
100
I C - COLLECTOR CURRENT (mA)
Rise Time vs Collector
and Turn On Base Currents
1000
Power Dissipation vs
Ambient Temperature
50
1
PD - POWER DISSIPATION (W)
I B1 - TURN 0N BASE CURRENT (mA)
Ic
10
20
10
t r = 15 V
5
30 ns
2
60 ns
1
10
100
I C - COLLECTOR CURRENT (mA)
500
SOT-6
0.75
0.5
0.25
0
0
25
50
75
100
o
TEMPERATURE ( C)
125
150
FFB2907A / FMBT2907A / MMPQ2907A
PNP Multi-Chip General Purpose Amplifier
(continued)
Test Circuits
30 V
200 Ω
Ω
1.0 KΩ
0
- 16 V
50 Ω
≤ 200ns
FIGURE 1: Saturated Turn-On Switching Time Test Circuit
- 6.0 V
15 V
1 KΩ
Ω
37 Ω
Ω
1.0 KΩ
0
- 30 V
50 Ω
≤ 200ns
FIGURE 2: Saturated Turn-Off Switching Time Test Circuit
FFB2907A / FMBT2907A / MMPQ2907A
PNP Multi-Chip General Purpose Amplifier
FMB3904
FFB3904
E2
MMPQ3904
C2
B2
E1
C1
C1
E1
C2
B2
E3
E4
B4
B2
B1
pin #1
B1
E2
B3
E2
E1
pin #1 B1
SC70-6
SuperSOT-6
Mark: .1A
Mark: .1A
C1
SOIC-16
C2
C1
C3
C2
C4
C4
C3
NPN General Purpose Amplifier
This device is designed as a general purpose amplifier and switch.
The useful dynamic range extends to 100 mA as a switch and to
100 MHz as an amplifier. Sourced from Process 23.
Absolute Maximum Ratings*
Symbol
TA = 25°C unless otherwise noted
Parameter
Value
Units
VCEO
Collector-Emitter Voltage
40
V
VCBO
Collector-Base Voltage
60
V
VEBO
Emitter-Base Voltage
6.0
V
IC
Collector Current - Continuous
200
mA
TJ, Tstg
Operating and Storage Junction Temperature Range
-55 to +150
°C
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150 degrees C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
Symbol
PD
RθJA
TA = 25°C unless otherwise noted
Characteristic
Total Device Dissipation
Derate above 25°C
Thermal Resistance, Junction to Ambient
Effective 4 Die
Each Die
 1998 Fairchild Semiconductor Corporation
Max
FFB3904
300
2.4
415
FMB3904
700
5.6
180
Units
MMPQ3904
1,000
8.0
125
240
mW
mW/°C
°C/W
°C/W
°C/W
FFB3904 / FMB3904 / MMPQ3904
Discrete POWER & Signal
Technologies
(continued)
Electrical Characteristics
Symbol
TA = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max Units
OFF CHARACTERISTICS
V(BR)CEO
Collector-Emitter Breakdown Voltage
IC = 1.0 mA, IB = 0
40
V
V(BR)CBO
Collector-Base Breakdown Voltage
IC = 10 µA, IE = 0
60
V
V(BR)EBO
Emitter-Base Breakdown Voltage
IE = 10 µA, IC = 0
6.0
IBL
Base Cutoff Current
VCE = 30 V, VEB = 0
50
nA
ICEX
Collector Cutoff Current
VCE = 30 V, VEB = 0
50
nA
V
ON CHARACTERISTICS*
hFE
DC Current Gain
VCE(sat)
Collector-Emitter Saturation Voltage
VBE(sat)
Base-Emitter Saturation Voltage
IC = 0.1 mA, VCE = 1.0 V
IC = 1.0 mA, VCE = 1.0 V
IC = 10 mA, VCE = 1.0 V
IC = 50 mA, VCE = 1.0 V
IC = 100 mA, VCE = 1.0 V
IC = 10 mA, IB = 1.0 mA
IC = 50 mA, IB = 5.0 mA
IC = 10 mA, IB = 1.0 mA
IC = 50 mA, IB = 5.0 mA
40
70
100
60
30
300
0.2
0.3
0.85
0.95
0.65
V
V
V
V
SMALL SIGNAL CHARACTERISTICS
fT
Current Gain - Bandwidth Product
Cobo
Output Capacitance
Cibo
Input Capacitance
NF
Noise Figure (except MMPQ3904)
IC = 10 mA, VCE = 20 V,
f = 100 MHz
VCB = 5.0 V, IE = 0,
f = 1.0 MHz
VEB = 0.5 V, IC = 0,
f = 1.0 MHz
IC = 100 µA, VCE = 5.0 V,
RS =1.0kΩ, f=10 Hz to 15.7 kHz
450
MHz
2.5
pF
6.0
pF
2.0
dB
SWITCHING CHARACTERISTICS
td
Delay Time
VCC = 3.0 V, VBE = 0.5 V,
18
ns
tr
Rise Time
IC = 10 mA, IB1 = 1.0 mA
20
ns
ts
Storage Time
VCC = 3.0 V, IC = 10mA
150
ns
tf
Fall Time
IB1 = IB2 = 1.0 mA
25
ns
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
FFB3904 / FMB3904 / MMPQ3904
NPN Multi-Chip General Purpose Amplifier
(continued)
500
V CE = 5V
400
125 °C
300
25 °C
200
100
- 40º C
0
0.1
1
10
100
I C - COLLECTOR CURRENT (mA)
Base-Emitter Saturation
Voltage vs Collector Current
1
0.8
β = 10
- 40 °C
25 °C
0.6
125 °C
0.4
0.1
IC
1
10
- COLLECTOR CURRENT (mA)
100
VBE(ON)- BASE-EMITTER ON VOLTAGE (V)
vs Collector Current
VBESAT- BASE-EMITTER VOLTAGE (V)
h FE - TYPICAL PULSED CURRENT GAIN
Typical Pulsed Current Gain
VCESAT- COLLECTOR-EMITTER VOLTAGE (V)
Typical Characteristics
Collector-Emitter Saturation
Voltage vs Collector Current
0.15
125 °C
0.1
25 °C
0.05
- 40 °C
0.1
1
VCE = 5V
0.8
- 40 °C
25 °C
0.6
125 °C
0.4
0.2
0.1
1
10
I C - COLLECTOR CURRENT (mA)
100
10
f = 1.0 MHz
VCB = 30V
CAPACITANCE (pF)
ICBO- COLLECTOR CURRENT (nA)
100
Capacitance vs
Reverse Bias Voltage
500
10
1
0.1
25
1
10
I C - COLLECTOR CURRENT (mA)
Base-Emitter ON Voltage vs
Collector Current
Collector-Cutoff Current
vs Ambient Temperature
100
β = 10
50
75
100
125
TA - AMBIENT TEMPERATURE ( °C)
150
5
4
3
C ibo
2
C obo
1
0.1
1
10
REVERSE BIAS VOLTAGE (V)
100
FFB3904 / FMB3904 / MMPQ3904
NPN Multi-Chip General Purpose Amplifier
(continued)
Typical Characteristics
(continued)
Noise Figure vs Source Resistance
Noise Figure vs Frequency
12
I C = 1.0 mA
R S = 200Ω
10
V CE = 5.0V
I C = 1.0 mA
NF - NOISE FIGURE (dB)
NF - NOISE FIGURE (dB)
12
I C = 50 µA
R S = 1.0 kΩ
8
I C = 0.5 mA
R S = 200Ω
6
4
2
I C = 100 µA, R S = 500 Ω
0
0.1
1
10
f - FREQUENCY (kHz)
10
I C = 5.0 mA
I C = 50 µA
8
6
I C = 100 µA
4
2
0
0.1
100
1
10
R S - SOURCE RESISTANCE ( kΩ )
0
20
40
60
80
100
120
140
160
180
h fe
θ
V CE = 40V
I C = 10 mA
1
10
100
f - FREQUENCY (MHz)
1
PD - POWER DISSIPATION (W)
fe
h
50
45
40
35
30
25
20
15
10
5
0
Power Dissipation vs
Ambient Temperature
θ - DEGREES
- CURRENT GAIN (dB)
Current Gain and Phase Angle
vs Frequency
1000
SOT-6
0.75
0.5
0.25
0
0
Turn-On Time vs Collector Current
I B1 = I B2 =
Ic
VCC = 40V
10
TIME (nS)
15V
t r @ V CC = 3.0V
2.0V
10
10
I C - COLLECTOR CURRENT (mA)
125
150
100
I B1 = I B2 =
Ic
10
T J = 25°C
T J = 125°C
10
t d @ VCB = 0V
1
50
75
100
o
TEMPERATURE ( C)
Rise Time vs Collector Current
40V
5
25
500
t r - RISE TIME (ns)
500
100
100
100
5
1
10
I C - COLLECTOR CURRENT (mA)
100
FFB3904 / FMB3904 / MMPQ3904
NPN Multi-Chip General Purpose Amplifier
(continued)
Typical Characteristics
(continued)
Storage Time vs Collector Current
I B1 = I B2 =
T J = 25°C
Fall Time vs Collector Current
500
Ic
I B1 = I B2 =
10
t f - FALL TIME (ns)
t S - STORAGE TIME (ns)
500
100
T J = 125°C
10
5
T J = 125°C
Ic
10
VCC = 40V
100
T J = 25°C
10
1
10
I C - COLLECTOR CURRENT (mA)
100
5
1
10
I C - COLLECTOR CURRENT (mA)
Test Circuits
3.0 V
275 Ω
300 ns
10.6 V
Duty Cycle = 2%
10 KΩ
Ω
0
- 0.5 V
C1 < 4.0 pF
< 1.0 ns
FIGURE 1: Delay and Rise Time Equivalent Test Circuit
3.0 V
10 < t1 < 500 µs
t1
10.9 V
275 Ω
Duty Cycle = 2%
10 KΩ
Ω
0
C1 < 4.0 pF
1N916
- 9.1 V
< 1.0 ns
FIGURE 2: Storage and Fall Time Equivalent Test Circuit
100
FFB3904 / FMB3904 / MMPQ3904
NPN Multi-Chip General Purpose Amplifier
E2
MMPQ3906
C2
B2
E1
C1
C1
E1
C2
SC70-6
Mark: .2A
B2
E3
E4
B4
B2
B1
pin #1
B1
E2
B3
E2
E1
pin #1 B1
NOTE: The pinouts are symmetrical; pin 1 and pin
4 are interchangeable. Units inside the carrier can
be of either orientation and will not affect the
functionality of the device.
pin #1 C1
SuperSOT-6
SOIC-16
Mark: .2A
Mark: MMPQ3906
C2
C1
C3
C2
C4
C4
C3
PNP Multi-Chip General Purpose Amplifier
This device is designed for general purpose amplifier and switching
applications at collector currents of 10 µA to 100 mA. Sourced
from Process 66.
Absolute Maximum Ratings*
Symbol
TA = 25°C unless otherwise noted
Parameter
Value
Units
40
V
VCEO
Collector-Emitter Voltage
VCBO
Collector-Base Voltage
40
V
VEBO
Emitter-Base Voltage
5.0
V
IC
Collector Current - Continuous
200
mA
TJ, Tstg
Operating and Storage Junction Temperature Range
-55 to +150
°C
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150 degrees C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
Symbol
PD
RθJA
TA = 25°C unless otherwise noted
Characteristic
Total Device Dissipation
Derate above 25°C
Thermal Resistance, Junction to Ambient
Effective 4 Die
Each Die
 1998 Fairchild Semiconductor Corporation
Max
FFB3904
300
2.4
415
FMB3904
700
5.6
180
Units
MMPQ3904
1,000
8.0
125
240
mW
mW/°C
°C/W
°C/W
°C/W
FFB3906 / FMB3906 / MMPQ3906
FMB3906
FFB3906
(continued)
Electrical Characteristics
Symbol
TA = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max Units
OFF CHARACTERISTICS
V(BR)CEO
IC = 1.0 mA, IB = 0
V(BR)CBO
Collector-Emitter Breakdown
Voltage*
Collector-Base Breakdown Voltage
40
V
IC = 10 µA, IE = 0
40
V
V(BR)EBO
Emitter-Base Breakdown Voltage
IE = 10 µA, IC = 0
5.0
V
IBL
Base Cutoff Current
VCE = 30 V, VBE = 3.0 V
50
nA
ICEX
Collector Cutoff Current
VCE = 30 V, VBE = 3.0 V
50
nA
ON CHARACTERISTICS
hFE
DC Current Gain *
VCE(sat)
Collector-Emitter Saturation Voltage
VBE(sat)
Base-Emitter Saturation Voltage
IC = 0.1 mA, VCE = 1.0 V
IC = 1.0 mA, VCE = 1.0 V
IC = 10 mA, VCE = 1.0 V
IC = 50 mA, VCE = 1.0 V
IC = 100 mA, VCE = 1.0 V
IC = 10 mA, IB = 1.0 mA
IC = 50 mA, IB = 5.0 mA
IC = 10 mA, IB = 1.0 mA
IC = 50 mA, IB = 5.0 mA
60
80
100
60
30
300
0.25
0.4
0.85
0.95
0.65
V
V
V
V
SMALL SIGNAL CHARACTERISTICS
fT
Current Gain - Bandwidth Product
Cobo
Output Capacitance
Cibo
Input Capacitance
NF
Noise Figure (except MMPQ3906)
IC = 10 mA, VCE = 20 V,
f = 100 MHz
VCB = 5.0 V, IE = 0,
f = 100 kHz
VEB = 0.5 V, IC = 0,
f = 100 kHz
IC = 100 µA, VCE = 5.0 V,
RS =1.0kΩ, f=10 Hz to 15.7 kHz
450
MHz
3.0
pF
8.0
pF
2.5
dB
ns
SWITCHING CHARACTERISTICS
td
Delay Time
VCC = 3.0 V, VBE = 0.5 V,
15
tr
Rise Time
IC = 10 mA, IB1 = 1.0 mA
20
ns
ts
Storage Time
VCC = 3.0 V, IC = 10mA
110
ns
tf
Fall Time
IB1 = IB2 = 1.0 mA
40
ns
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
Spice Model
PNP (Is=1.41f Xti=3 Eg=1.11 Vaf=18.7 Bf=180.7 Ne=1.5 Ise=0 Ikf=80m Xtb=1.5 Br=4.977 Nc=2 Isc=0 Ikr=0
Rc=2.5 Cjc=9.728p Mjc=.5776 Vjc=.75 Fc=.5 Cje=8.063p Mje=.3677 Vje=.75 Tr=33.42n Tf=179.3p Itf=.4 Vtf=4
Xtf=6 Rb=10)
FFB3906 / FMB3906 / MMPQ3906
PNP Multi-Chip General Purpose Amplifier
(continued)
250
V CE = 1.0V
125 °C
200
150
25 °C
100
- 40 °C
50
0.1 0.2
0.5 1
2
5
10 20
I C - COLLECTOR CURRENT (mA)
50
100
Base-Emitter Saturation
Voltage vs Collector Current
β = 10
1
- 40 ºC
0.8
25 °C
125 ºC
0.6
0.4
0.2
0
1
10
100
I C - COLLECTOR CURRENT (mA)
200
Collector-Emitter Saturation
Voltage vs Collector Current
0.3
β = 10
0.25
0.2
0.15
25 °C
0.1
125 ºC
0.05
VBE(ON) - BASE EMITTER ON VOLTAGE (V)
V BESAT - BASE EMITTER VOLTAGE (V)
h FE - TYPICAL PULSED CURRENT GAIN
Typical Pulsed Current Gain
vs Collector Current
V CESAT - COLLECTOR EMITTER VOLTAGE (V)
Typical Characteristics
0
- 40 ºC
1
1
0.8
- 40 ºC
125 ºC
0.4
V CE = 1V
0.2
0
0.1
1
10
I C - COLLECTOR CURRENT (mA)
25
Common-Base Open Circuit
Input and Output Capacitance
vs Reverse Bias Voltage
= 25V
10
CB
C obo
10
CAPACITANCE (pF)
I CBO - COLLECTOR CURRENT (nA)
25 °C
0.6
100
1
0.1
0.01
25
200
Base Emitter ON Voltage vs
Collector Current
Collector-Cutoff Current
vs Ambient Temperature
V
10
100
I C - COLLECTOR CURRENT (mA)
50
75
100
TA - AMBIENT TEMPERATURE ( º C)
125
8
6
4
C ibo
2
0
0.1
1
REVERSE BIAS VOLTAGE (V)
10
FFB3906 / FMB3906 / MMPQ3906
PNP Multi-Chip General Purpose Amplifier
(continued)
Typical Characteristics
(continued)
Noise Figure vs Frequency
Noise Figure vs Source Resistance
6
12
NF - NOISE FIGURE (dB)
NF - NOISE FIGURE (dB)
V CE = 5.0V
5
4
3
I C = 100 µA, R S = 200Ω
2
I C = 1.0 mA, R S = 200Ω
1
I C = 100 µA, R S = 2.0 kΩ
0
0.1
1
10
f - FREQUENCY (kHz)
V CE = 5.0V
f = 1.0 kHz
10
I C = 1.0 mA
8
6
4
I C = 100 µA
2
0
0.1
100
1
10
R S - SOURCE RESISTANCE ( kΩ )
Switching Times
vs Collector Current
Turn On and Turn Off Times
vs Collector Current
500
500
ts
tf
10
I B1 = I B2 =
tr
Ic
t off
100
TIME (nS)
100
t on I
B1 =
Ic
10
t on
VBE(OFF) = 0.5V
10
Ic
t off I = I =
B1
B2
10
10
td
1
1
10
I C - COLLECTOR CURRENT (mA)
100
1
1
10
I C - COLLECTOR CURRENT (mA)
Power Dissipation vs
Ambient Temperature
1
PD - POWER DISSIPATION (W)
TIME (nS)
100
SOIC-16
SOT-6
0.75
0.5
SC70-6
0.25
0
0
25
50
75
100
TEMPERATURE (º C)
125
150
100
FFB3906 / FMB3906 / MMPQ3906
PNP Multi-Chip General Purpose Amplifier
(continued)
Typical Characteristics
Input Impedance
Voltage Feedback Ratio
)
10
100
h ie - INPUT IMPEDANCE (k Ω)
_4
h re - VOLTAGE FEEDBACK RATIO (x10
(continued)
10
1
0.1
1
I C - COLLECTOR CURRENT (mA)
1
0.1
0.1
10
1
I C - COLLECTOR CURRENT (mA)
10
Current Gain
1000
V CE = 10 V
f = 1.0 kHz
500
h fe - CURRENT GAIN
h oe - OUTPUT ADMITTANCE ( µmhos)
Output Admittance
1000
VCE = 10 V
f = 1.0 kHz
100
V CE = 10 V
f = 1.0 kHz
200
100
50
20
10
0.1
1
I C - COLLECTOR CURRENT (mA)
10
10
0.1
1
I C - COLLECTOR CURRENT (mA)
10
FFB3906 / FMB3906 / MMPQ3906
PNP Multi-Chip General Purpose Amplifier
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
CoolFET™
CROSSVOLT™
E2CMOSTM
FACT™
FACT Quiet Series™
FAST®
FASTr™
GTO™
HiSeC™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
TinyLogic™
UHC™
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
FMB3946
C2
E1
C1
Package: SuperSOT-6
Device Marking: .002
Note: The " . " (dot) signifies Pin 1
B2
E2
Transistor 1 is NPN device,
transistor 2 is PNP device.
B1
NPN & PNP Complementary Dual Transistor
SuperSOT-6 Surface Mount Package
This complementary dual device was designed for use as a general purpose amplifier and switch. The useful
dynamic range extends to 100mA as a switch and to 100MHz as an amplifier. Sourced from Process 23
(NPN) and Process 66 (PNP).
Absolute Maximum Ratings*
TA
= 25°C unless otherwise noted
Value
Units
Collector-Emitter Voltage
40
V
VCBO
Collector-Base Voltage
40
V
VEBO
Emitter-Base Voltage
5
V
IC
Collector Current
200
mA
TJ, Tstg
Operating and Storage Junction Temperature Range
-55 to +150
°C
Symbol
Parameter
VCEO
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150°C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
TA
Symbol
= 25°C unless otherwise noted
Max
Units
PD
Total Device Dissipation
Derate above 25°C
Characteristics
700
5.6
mW
mW/°C
RθJA
Thermal Resistance, Junction to Ambient
180
°C/W
 1997 Fairchild Semiconductor Corporation
Page 1 of 2
fmb3946.lwpPr23&66(Y2)
FMB3946
Discrete Power
&
Signal Technologies
Electrical Characteristics
Symbol
TA
= 25°C unless otherwise noted
Parameter
Test Conditions
Min
Max
Units
OFF CHARACTERISTICS
BVCEO
Collector to Emitter Voltage
Ic = 1.0 mA
40
V
BVCBO
Collector to Base Voltage
Ic = 10 uA
40
V
BVEBO
Emitter to Base Voltage
Ie = 10 uA
5
V
ICBO
Collector Cutoff Current
Vcb = 30 V
50
nA
IEBO
Emitter Cutoff Current
Veb = 4.0 V
50
nA
ON CHARACTERISTICS
hFE
DC Current Gain
Vce =
Vce =
Vce =
Vce =
Vce =
1V,
1V,
1V,
1V,
1V,
Ic = 100uA
Ic = 1.0mA
Ic = 10mA
Ic = 50mA
Ic = 100mA
40
70
100
60
30
VCE(sat)
Collector-Emitter Saturation Voltage Ic = 10mA, Ib = 1mA
0.25
V
VBE(sat)
Base-Emitter Saturation Voltage
0.9
V
Ic = 10mA, Ib = 1mA
-
SMALL SIGNAL CHARACTERISTICS
COB Output Capacitance
Vcb = 5V, f = 1MHz
TYP
3
pF
CIB Input Capacitance
Veb = 0.5V, f = 1MHz
7
pF
fT
Current Gain - Bandwidth Product
Vce = 20V, Ic = 10mA, f = 100MHz
450
MHz
NF
Noise Figure
Vce = 5V, Ic = 100uA,
Rs = 1kohms, f = 10Hz to 15.7kHz
2.5
dB
SWITCHING CHARACTERISTICS
td
Delay Time
tr
Rise Time
ts
Storage Time
tf
Fall Time
 1997 Fairchild Semiconductor Corporation
TYP
Vcc = 3V, Vbe = 0.5V,
Ic = 10 mA, Ib1 = 1 mA
18
ns
20
ns
Vcc = 3V,Ic = 10 mA,
Ib1 = Ib2 = 1 mA
150
ns
40
ns
Page 2 of 2
fmb3946.lwpPr23&66(Y2)
FMB3946
NPN & PNP Complementary Dual Transistor
(continued)
FMBA06
C2
E1
C1
B2
E2
pin #1 B1
SuperSOT-6
Mark: .1G
NPN Multi-Chip General Purpose Amplifier
This device is designed for general purpose amplifier applications at collector
currents to 300 mA. Sourced from Process 33.
Absolute Maximum Ratings*
Symbol
TA = 25°C unless otherwise noted
Parameter
Value
Units
VCEO
Collector-Emitter Voltage
80
V
VCBO
Collector-Base Voltage
80
V
VEBO
Emitter-Base Voltage
4.0
V
IC
Collector Current - Continuous
500
mA
TJ, Tstg
Operating and Storage Junction Temperature Range
-55 to +150
°C
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150 degrees C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
Symbol
PD
RθJA
TA = 25°C unless otherwise noted
Characteristic
Total Device Dissipation
Derate above 25°C
Thermal Resistance, Junction to Ambient
 1998 Fairchild Semiconductor Corporation
Max
Units
FMBA06
700
5.6
180
mW
mW/°C
°C/W
FMBA06
Discrete POWER & Signal
Technologies
(continued)
Electrical Characteristics
Symbol
TA = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max Units
OFF CHARACTERISTICS
V(BR)CEO
Collector-Emitter Sustaining Voltage* IC = 1.0 mA, IB = 0
80
V
V(BR)EBO
Emitter-Base Breakdown Voltage
IE = 100 µA, IC = 0
4.0
V
ICEO
Collector-Cutoff Current
VCE = 60 V, IB = 0
0.1
µA
ICBO
Collector-Cutoff Current
VCB = 80 V, IE = 0
0.1
µA
0.25
V
1.2
V
ON CHARACTERISTICS
hFE
DC Current Gain
VCE(sat)
Collector-Emitter Saturation Voltage
IC = 10 mA, VCE = 1.0 V
IC = 100 mA, VCE = 1.0 V
IC = 100 mA, IB = 10 mA
VBE(on)
Base-Emitter On Voltage
IC = 100 mA, VCE = 1.0 V
100
100
SMALL SIGNAL CHARACTERISTICS
fT
Current Gain - Bandwidth Product
IC = 10 mA, VCE = 2.0 V,
f = 100 MHz
150
MHz
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
Typical Pulsed Current Gain
vs Collector Current
200
125 °C
VCE = 1V
150
25 °C
100
- 40 ºC
50
0.001
0.01
0.1
I C - COLLECTOR CURRENT (A)
VCESAT- COLLECTOR EMITTER VOLTAGE (V)
h FE - TYPICAL PULSED CURRENT GAIN
Typical Characteristics
Collector-Emitter Saturation
Voltage vs Collector Current
0.5
β = 10
0.4
0.3
0.2
125 °C
25 °C
0.1
- 40 ºC
0
0.1
1
10
100
I C - COLLECTOR CURRENT (mA)
1000
FMBA06
NPN Multi-Chip General Purpose Amplifier
(continued)
Base-Emitter Saturation
Voltage vs Collector Current
β = 10
1
0.8
- 40 ºC
25 °C
125 °C
0.6
0.4
0.1
1
10
100
I C - COLLECTOR CURRENT (mA)
1000
ICBO- COLLECTOR CURRENT (nA)
Collector-Cutoff Current
vs. Ambient Temperature
10
V
CB
= 80 V
Base Emitter ON Voltage vs
Collector Current
1
- 40 ºC
0.8
25 °C
0.6
125 °C
0.4
VCE = 5V
0.2
0
1
10
100
I C - COLLECTOR CURRENT (mA)
1000
Collector Saturation Region
2
T A = 25°C
1.5
1
0.1
1
0.5
0.01
0.001
25
VBEON - BASE EMITTER ON VOLTAGE (V)
(continued)
V CE - COLLECTOR-EMITTER VOLTAGE (V)
VBESAT- BASE EMITTER VOLTAGE (V)
Typical Characteristics
50
75
100
TA - AMBIENT TEMPERATURE ( º C)
125
IC =
1 mA
100 mA
10 mA
0
4000
10000
20000
30000
50000
I B - BASE CURRENT (uA)
Collector-Emitter Breakdown
Voltage with Resistance
Between Emitter-Base
Input and Output Capacitance
vs Reverse Voltage
100
f = 1.0 MHz
117
CAPACITANCE (pF)
BVCER - BREAKDOWN VOLTAGE (V)
P 33
116
115
114
113
C ib
10
C ob
1
112
111
0.1
1
10
RESISTANCE (k Ω)
100
1000
0.1
0.1
1
10
V CE - COLLECTOR VOLTAGE(V)
100
FMBA06
NPN Multi-Chip General Purpose Amplifier
(continued)
(continued)
Gain Bandwidth Product
vs Collector Current
Power Dissipation vs
Ambient Temperature
1
400
Vce = 5V
PD - POWER DISSIPATION (W)
f T - GAIN BANDWIDTH PRODUCT (MHz)
Typical Characteristics
350
300
250
200
150
0.5
0.25
0
100
1
10
I
C
20
50
100
- COLLECTOR CURRENT (mA)
SOT-6
0.75
0
25
50
75
100
o
TEMPERATURE ( C)
125
150
FMBA06
NPN Multi-Chip General Purpose Amplifier
FMBA0656
Package: SuperSOT-6
Device Marking: .003
C2
E1
C1
Note: The " . " (dot) signifies Pin 1
Transistor 1 is NPN device,
transistor 2 is PNP device.
B2
E2
B1
NPN & PNP Complementary Dual Transistor
SuperSOT- 6 Surface Mount Package
This device was designed for general purpose amplifier applications at collector currents to 300mA.
Sourced from Process 33 (NPN) and Process 73 (PNP).
Absolute Maximum Ratings
TA
= 25°C unless otherwise noted
Value
Units
Collector-Emitter Voltage
80
V
VCBO
Collector-Base Voltage
80
V
VEBO
Emitter-Base Voltage
4
V
IC
Collector Current (continuous)
500
mA
PD
Power Dissipation @Ta = 25°C*
0.7
W
TSTG
Storage Temperature Range
-55 to +150
°C
TJ
Junction Temperature
150
°C
RθJA
Thermal Resistance, Junction to Ambient
180
°C/W
Symbol
Parameter
VCEO
*Pd total, for both transistors.
For each transistor, Pd = 350mW.
Electrical Characteristics
TA
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
BVCEO
Collector to Emitter Voltage
Ic = 1.0 mA
80
V
BVCBO
Collector to Base Voltage
Ic = 100 uA
80
V
BVEBO
Emitter to Base Voltage
Ie = 100 uA
4
V
 1997 Fairchild Semiconductor Corporation
Page 1 of 2
Min
Max
Units
fmba0656.lwpPr33&73(Y3)
FMBA0656
Discrete Power
&
Signal Technologies
(continued)
Electrical Characteristics
TA = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Max
Units
ICBO
Collector Cutoff Current
Vcb = 80 V
Min
100
nA
ICEO
Collector Cutoff Current
Vce = 60 V
100
nA
hFE
DC Current Gain
Vce = 1 V, Ic = 10 mA
Vce = 1 V, Ic = 100 mA
VCE(sat)
Collector-Emitter Saturation Voltage Ic = 100 mA, Ib = 10 mA
0.25
V
VBE(on)
Base-Emitter On Voltage
1.2
V
100
100
Ic = 100 mA, Vce = 1 V
-
Small - Signal Characteristics
fT
Current Gain - Bandwidth Product
 1997 Fairchild Semiconductor Corporation
Vce = 1 V, Ic = 100 mA, f = 100 MHz
Page 2 of 2
50
-
fmba0656.lwpPr33&73(Y3)
FMBA0656
NPN & PNP Complementary Dual Transistor
FMBA14
C2
E1
C1
B2
E2
pin #1 B1
SuperSOT-6
Mark: .1N
NPN Multi-Chip Darlington Transistor
This device is designed for applications requiring extremely high current
gain at collector currents to 1.0 A. Sourced from Process 05.
Absolute Maximum Ratings*
Symbol
TA = 25°C unless otherwise noted
Parameter
Value
Units
VCES
Collector-Emitter Voltage
30
V
VCBO
Collector-Base Voltage
30
V
VEBO
Emitter-Base Voltage
10
V
IC
Collector Current - Continuous
TJ, Tstg
Operating and Storage Junction Temperature Range
1.2
A
-55 to +150
°C
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150 degrees C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
Symbol
PD
RθJA
TA = 25°C unless otherwise noted
Characteristic
Total Device Dissipation
Derate above 25°C
Thermal Resistance, Junction to Ambient
 1998 Fairchild Semiconductor Corporation
Max
Units
FMBA14
700
5.6
180
mW
mW/°C
°C/W
FMBA14
Discrete POWER & Signal
Technologies
(continued)
Electrical Characteristics
Symbol
TA = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max Units
OFF CHARACTERISTICS
V(BR)CES
Collector-Emitter Breakdown Voltage
IC = 100 µA, IB = 0
ICBO
Collector-Cutoff Current
VCB = 30 V, IE = 0
100
nA
IEBO
Emitter-Cutoff Current
VEB = 10 V, IC = 0
100
nA
1.5
V
2.0
V
30
V
ON CHARACTERISTICS*
hFE
DC Current Gain
VCE(sat)
Collector-Emitter Saturation Voltage
IC = 10 mA, VCE = 5.0 V
IC = 100 mA, VCE = 5.0 V
IC = 100 mA, IB = 0.1 mA
VBE(on)
Base-Emitter On Voltage
IC = 100 mA, VCE = 5.0 V
10K
20K
SMALL SIGNAL CHARACTERISTICS
fT
Current Gain - Bandwidth Product
IC = 10 mA, VCE = 10 V,
f = 100 MHz
200
MHz
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
250
200 VCE = 5V
125 °C
150
25 °C
100
- 40 °C
50
0
0.001
0.01
0.1
I C - COLLECTOR CURRENT (A)
1
Base-Emitter Saturation
Voltage vs Collector Current
2
β = 1000
1.6
- 40 ºC
25 °C
1.2
125 ºC
0.8
0.4
0
1
10
100
I C - COLLECTOR CURRENT (mA)
1000
VCESAT- COLLECTOR EMITTER VOLTAGE (V)
Typical Pulsed Current Gain
vs Collector Current
Collector-Emitter Saturation
Voltage vs Collector Current
1.6
β = 1000
1.2
- 40 ºC
0.8
25°C
125 ºC
0.4
VBEON - BASE EMITTER ON VOLTAGE (V)
VBESAT- BASE EMITTER VOLTAGE (V)
hFE - TYPICAL PULSED CURRENT GAIN (K)
Typical Characteristics
0
1
10
100
I C - COLLECTOR CURRENT (mA)
1000
Base Emitter ON Voltage vs
Collector Current
2
1.6
- 40 ºC
25 °C
1.2
125 ºC
0.8
VCE = 5V
0.4
0
1
10
100
I C - COLLECTOR CURRENT (mA)
1000
FMBA14
NPN Multi-Chip Darlington Transistor
(continued)
(continued)
ICBO- COLLECTOR CURRENT (nA)
Collector-Cutoff Current
vs Ambient Temperature
100
VCB = 30V
10
1
0.1
0.01
25
50
75
100
T A- AMBIENT TEMPERATURE ( º C)
125
BVCER - BREAKDOWN VOLTAGE (V)
Typical Characteristics
Collector-Emitter Breakdown
Voltage with Resistance
Between Emitter-Base
62.5
62
61.5
61
60.5
60
59.5
0.1
10
Cib
5
Cob
2
0.1
1
10
100
Vce - COLLECTOR VOLTAGE(V)
Vce = 5V
40
30
20
10
0
1
10
SOT-6
0.25
0
25
50
75
100
o
TEMPERATURE ( C)
20
50
IC - COLLECTOR CURRENT (mA)
0.5
0
1000
50
1
0.75
100
Gain Bandwidth Product
vs Collector Current
Power Dissipation vs
Ambient Temperature
PD - POWER DISSIPATION (W)
CAPACITANCE (pF)
20
f T - GAIN BANDWIDTH PRODUCT (MHz)
f = 1.0 MHz
10
RESISTANCE (k Ω)
Input and Output Capacitance
vs Reverse Voltage
1
125
150
100 150
FMBA14
NPN Multi-Chip Darlington Transistor
FMBA56
C2
E1
C1
B2
E2
pin #1 B1
SuperSOT-6
Mark: .2G
PNP Multi-Chip General Purpose Amplifier
This device is designed for general purpose amplifier applications at collector
currents to 300 mA. Sourced from Process 73.
Absolute Maximum Ratings*
Symbol
TA = 25°C unless otherwise noted
Parameter
Value
Units
VCES
Collector-Emitter Voltage
80
V
VCBO
Collector-Base Voltage
80
V
VEBO
Emitter-Base Voltage
4.0
V
IC
Collector Current - Continuous
500
mA
TJ, Tstg
Operating and Storage Junction Temperature Range
-55 to +150
°C
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150 degrees C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
Symbol
PD
RθJA
TA = 25°C unless otherwise noted
Characteristic
Total Device Dissipation
Derate above 25°C
Thermal Resistance, Junction to Ambient
 1998 Fairchild Semiconductor Corporation
Max
Units
FMBA56
700
5.6
180
mW
mW/°C
°C/W
FMBA56
Discrete POWER & Signal
Technologies
(continued)
Electrical Characteristics
Symbol
TA = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max Units
OFF CHARACTERISTICS
V(BR)CEO
IC = 1.0 mA, IB = 0
V(BR)CBO
Collector-Emitter Breakdown
Voltage*
Collector-Base Breakdown Voltage
80
V
V(BR)EBO
Emitter-Base Breakdown Voltage
IC = 100 µA, IE = 0
80
V
IE = 100 µA, IC = 0
4.0
V
ICEO
Collector-Cutoff Current
VCE = 60 V, IB = 0
0.1
µA
ICBO
Collector-Cutoff Current
VCB = 80 V, IE = 0
0.1
µA
0.25
V
1.2
V
ON CHARACTERISTICS
hFE
DC Current Gain
VCE(sat)
Collector-Emitter Saturation Voltage
IC = 10 mA, VCE = 1.0 V
IC = 100 mA, VCE = 1.0 V
IC = 100 mA, IB = 10 mA
VBE(on)
Base-Emitter On Voltage
IC = 100 mA, VCE = 1.0 V
100
100
SMALL SIGNAL CHARACTERISTICS
fT
Current Gain - Bandwidth Product
IC = 100 mA, VCE = 1.0 V,
f = 100 MHz
125
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
Typical Pulsed Current Gain
vs Collector Current
300
VCE = 1V
250
125 °C
200
150
25 °C
100
- 40 ºC
50
0.001
0.01
0.1
I C - COLLECTOR CURRENT (A)
VCESAT- COLLECTOR EMITTER VOLTAGE (V)
h FE - TYPICAL PULSED CURRENT GAIN
Typical Characteristics
Collector-Emitter Saturation
Voltage vs Collector Current
0.8
β = 10
0.6
0.4
25 °C
0.2
- 40 ºC
125 °C
0
10
100
I C - COLLECTOR CURRENT (mA)
MHz
FMBA56
PNP Multi-Chip General Purpose Amplifier
(continued)
1.2
β = 10
1
- 40 ºC
0.8
25 °C
125 °C
0.6
0.4
10
100
I C - COLLECTOR CURRENT (mA)
1000
I CBO- COLLECTOR CURRENT (nA)
Collector-Cutoff Current
vs. Ambient Temperature
VCB = 60Vz
1
0.1
0.01
50
75
100
TA - AMBIENT TEMPERATURE ( º C)
125
Input and Output Capacitance
vs Reverse Voltage
f = 1.0 MHz
CAPACITANCE (pF)
100
C ib
Cob
0.1
1
10
V CE - COLLECTOR VOLTAGE(V)
Base Emitter ON Voltage vs
Collector Current
1.2
1
- 40 ºC
0.8
25 °C
0.6
125 °C
0.4
V CE = 1V
0.2
0
0.1
1
10
100
I C - COLLECTOR CURRENT (mA)
1000
Collector Saturation Region
10
10
0.001
25
V CE - COLLECTOR-EMITTER VOLTAGE (V)
Base-Emitter Saturation
Voltage vs Collector Current
VBEON - BASE EMITTER ON VOLTAGE (V)
(continued)
100
f T - GAIN BANDWIDTH PRODUCT (MHz)
VBESAT- BASE EMITTER VOLTAGE (V)
Typical Characteristics
T
8
A
= 25°C
6
IC =
1 mA
10 mA
100 mA
4
2
0
3000
5000
10000
20000
30000
50000
I B - BASE CURRENT (uA)
Gain Bandwidth Product
vs Collector Current
40
VCE = 5V
30
20
10
0
1
10
I
C
20
50
- COLLECTOR CURRENT (mA)
100
FMBA56
PNP Multi-Chip General Purpose Amplifier
(continued)
Typical Characteristics
(continued)
Power Dissipation vs
Ambient Temperature
PD - POWER DISSIPATION (W)
1
SOT-6
0.75
0.5
0.25
0
0
25
50
75
100
o
TEMPERATURE ( C)
125
150
FMBA56
PNP Multi-Chip General Purpose Amplifier
FMKA140
DISCRETE POWER AND SIGNAL
TECHNOLOGIES
SCHOTTKY POWER RECTIFIER
General Description:
Features:
Schottky Barrier Diodes make use of the rectification effect
of a metal to silicon barrier. They are ideally suited for high
frequency rectification in switching regulators & converters.
This device offers a low forward voltage performance in a
power surface mount package in applications where size and
weight are critical.
• Compact surface mount package with J-bend leads (SMA).
• 1.2 Watt Power Dissipation package.
• 1.0 Ampere, forward voltage less than 600 mv
Ordering:
• 13 inch reel (330 mm); 12 mm Tape; 5,000 units per reel.
Absolute Maximum Ratings*
TA = 25OC unless otherwise noted
Parameter
Value
Units
Storage Temperature
-65 to +150
O
C
Maximum Junction Temperature
-65 to +125
O
C
Repetitive Peak Reverse Voltage (VRRM)
40
V
Average Rectified Forward Current (TL = 120OC)
1.0
A
Surge Non Repetitive Forward Current
30
A
(Half wave, single phase, 60 Hz)
Junction to Case for Thermal Resistance (RØJL)
9.6
O
C/W
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired
SMA Package
(DO-214AC)
Top Mark: A140
Electrical Characteristics
SYM
1
2
Actual Size
TA = 25OC unless otherwise noted
CHARACTERISTICS
MIN
MAX
UNITS
TEST CONDITIONS
IR
Reverse Leakage Current
PW 300 us, <2% Duty Cycle
1.0
10
mA
mA
VR = 40 V; Tj = 25OC
VR = 40 V; Tj = 100OC
VF
Forward Voltage
PW 300 us, <2% Duty Cycle
600
mV
IF = 1.0 A; Tj = 25OC
© 1997 Fairchild Semiconductor Corporation
o
25oC
100 C
1
0.5
0.1
0.05
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
V F - FORWARD VOLTAGE (V)
1
I R - REVERSE LEAKAGE CURRENT (mA)
2
Reverse Leakage Current
vs. Temperature
5
2
1
o
125 C
o
100 C
0.1
75 C
0.01
25oC
0.001
o
0
5
10
15
20
25
30
35
V R - REVERSE VOLTAGE (V)
Capacitance
vs. Reverse Bias Voltage
130
120
CAPACITANCE (pF)
I F - FORWARD CURRENT (A)
5
110
100
90
80
70
60
50
40
30
0
FMKA140
Forward Voltage
vs. Temperature
5
10
15
20
25
30
35
V R - REVERSE BIAS VOLTAGE (V)
40
40
DISCRETE POWER AND SIGNAL
TECHNOLOGIES
DIM
MIN
(mils)
MAX
(mils)
MIN
(mm)
MAX
(mm)
A
90
115
2.286
2.921
B
160
180
4.064
4.572
C
79
103
2.007
2.616
D
190
220
4.826
5.588
E
---
---
---
---
F
50
64
1.270
1.626
G
4
8
0.102
0.203
H
30
60
0.762
1.524
I
6
12
0.152
0.305
Actual Size
A
1
2
B
D
D
I
H
C
G
SMA PACKAGE
PACKAGE CODE = (MA)
Fairchild Semiconductor's Criteria
F
FMMT449
FMMT449
C
E
B
SuperSOTTM-3
NPN Low Saturation Transistor
These devices are designed with high current gain and low saturation voltage with collector currents up to 2A
continuous. Sourced from Process NB.
Absolute Maximum Ratings*
Symbol
TA = 25°C unless otherwise noted
Parameter
FMMT449
Units
VCEO
Collector-Emitter Voltage
30
V
VCBO
Collector-Base Voltage
50
V
VEBO
Emitter-Base Voltage
5
V
IC
Collector Current - Continuous
- Peak Pulse Current
1
2
A
TJ, Tstg
Operating and Storage Junction Temperature Range
-55 to +150
°C
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150°C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
TA = 25°C unless otherwise noted
Max
Characteristic
Symbol
Units
FMMT449
PD
Total Device Dissipation*
Derate above 25°C
500
4
mW
mW/°C
RθJA
Thermal Resistance, Junction to Ambient
250
°C/W
*Device mounted on FR-4 PCB 4.5” X 5”; mounting pad 0.02 in2 of 2oz copper.
 1998Fairchild Semiconducto Corporation
Page 1 of 2
fmmt449.lwpPrNB revA
(continued)
Electrical Characteristics
Symbol
TA = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Max
Units
OFF CHARACTERISTICS
BVCEO
Collector-Emitter Breakdown Voltage
IC = 10 mA
30
V
BVCBO
Collector-Base Breakdown Voltage
IC = 1mA
50
V
BVEBO
Emitter-Base Breakdown Voltage
IE = 100 µA
5
V
ICBO
Collector Cutoff Current
VCB = 40 V
100
10
VCB = 40 V, Ta=100°C
IEBO
Emitter Cutoff Current
100
VEB = 4V
nA
uA
nA
ON CHARACTERISTICS*
hFE
VCE(sat)
DC Current Gain
Collector-Emitter Saturation Voltage
IC = 50 mA, VCE = 2V
70
IC = 500 mA, VCE = 2V
100
IC = 1A, VCE = 2V
80
IC = 2A, VCE = 2V
40
300
IC = 1 A, IB = 100 mA
500
mV
IC = 2 A, IB = 200 mA
1.0
V
1.25
V
VBE(sat)
Base-Emitter Saturation Voltage
IC = 1 A, IB = 100 mA
VBE(on)
Base-Emitter On Voltage
IC = 1 A, VCE = 2 V
1
V
15
pF
SMALL SIGNAL CHARACTERISTICS
Cobo
Output Capacitance
VCB = 10 V, IE = 0, f = 1MHz
fT
Transition Frequency
IC = 50mA,VCE = 10 V, f=100MHz
150
MHz
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
 1998Fairchild Semiconducto Corporation
Page 2 of 2
fmmt449.lwpPrNB revA
FMMT449
NPN Low Saturation Transistor
SuperSOTTM-3 Tape and Reel Data and Package Dimensions
SSOT-3 Packaging
Configuration: Figure 1.0
Customize Label
Packaging Description:
SSOT-3 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
3,000 units per 7" or 177cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 10,000 units per 13"
or 330cm diameter reel. This and some other options are
described in the Packaging Information table.
Antistatic Cover Tape
These full reels are individually labeled and placed inside
a standard intermediate made of recyclable corrugated
brown paper with a Fairchild logo printing. One pizza box
contains eight reels maximum. And these intermediate
boxes are placed inside a labeled shipping box which
comes in different sizes depending on the number of parts
shipped.
Human Readable Embossed
Label
Carrier Tape
3P
3P
3P
3P
SSOT-3 Std Packaging Information
Packaging Option
Packaging type
Qty per Reel/Tube/Bag
Reel Size
Box Dimension (mm)
Standard
(no flow code)
TNR
D87Z
SSOT-3 Std Unit Orientation
TNR
3,000
10,000
7" Dia
13"
187x107x183 343x343x64
Max qty per Box
24,000
30,000
Weight per unit (gm)
0.0097
0.0097
Weight per Reel (kg)
0.1230
0.4150
343mm x 342mm x 64mm
Intermediate box for D87Z Option
Human Readable Label
Note/Comments
Human Readable Label sample
Human Readable
Label
187mm x 107mm x 183mm
Intermediate Box for Standard Option
SSOT-3 Tape Leader and Trailer
Configuration: Figure 2.0
Carrier Tape
Cover Tape
Components
Trailer Tape
300mm minimum or
75 empty pockets
Leader Tape
500mm minimum or
125 empty pockets
August 1999, Rev. C
SuperSOTTM-3 Tape and Reel Data and Package Dimensions, continued
SSOT-3 Embossed Carrier Tape
Configuration: Figure 3.0
P0
P2
D0
D1
T
E1
W
F
E2
Wc
B0
Tc
A0
P1
K0
User Direction of Feed
Dimensions are in millimeter
Pkg type
A0
B0
SSOT-3
(8mm)
3.15
+/-0.10
2.77
+/-0.10
W
8.0
+/-0.3
D0
D1
E1
E2
1.55
+/-0.05
1.125
+/-0.125
1.75
+/-0.10
F
6.25
min
3.50
+/-0.05
P1
P0
4.0
+/-0.1
4.0
+/-0.1
K0
T
1.30
+/-0.10
0.228
+/-0.013
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
Wc
0.06
+/-02
0.5mm
maximum
20 deg maximum
Typical
component
cavity
center line
B0
5.2
+/-0.3
Tc
0.5mm
maximum
20 deg maximum component rotation
Typical
component
center line
Sketch A (Side or Front Sectional View)
A0
Component Rotation
Sketch C (Top View)
Component lateral movement
Sketch B (Top View)
SSOT-3 Reel Configuration: Figure 4.0
Component Rotation
W1 Measured at Hub
Dim A
Max
Dim A
max
See detail AA
Dim N
7" Diameter Option
B Min
Dim C
See detail AA
W3
13" Diameter Option
Dim D
min
W2 max Measured at Hub
DETAIL AA
Dimensions are in inches and millimeters
Tape Size
Reel
Option
Dim A
Dim B
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
2.165
55
0.331 +0.059/-0.000
8.4 +1.5/0
0.567
14.4
0.311 – 0.429
7.9 – 10.9
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
4.00
100
0.331 +0.059/-0.000
8.4 +1.5/0
0.567
14.4
0.311 – 0.429
7.9 – 10.9
8mm
7" Dia
7.00
177.8
8mm
13" Dia
13.00
330
Dim C
Dim D
Dim N
Dim W1
Dim W2
Dim W3 (LSL-USL)
July 1999, Rev. C
SuperSOTTM-3 Tape and Reel Data and Package Dimensions, continued
SuperSOT-3 (FS PKG Code 32)
1:1
Scale 1:1 on letter size paper
Di mensions shown below are in:
inches [mil limeters]
Part Weight per unit (gram): 0.0097
September 1998, Rev. A
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
CoolFET™
CROSSVOLT™
E2CMOSTM
FACT™
FACT Quiet Series™
FAST®
FASTr™
GTO™
HiSeC™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
TinyLogic™
UHC™
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
FMMT549
FMMT549
C
E
B
TM
SuperSOT -3 (SOT-23)
PNP Low Saturation Transistor
These devices are designed with high current gain and low saturation voltage with collector currents up to 2A
continuous.
Absolute Maximum Ratings*
TA = 25°C unless otherwise noted
FMMT549
Units
VCEO
Collector-Emitter Voltage
30
V
VCBO
Collector-Base Voltage
35
V
VEBO
Emitter-Base Voltage
5
V
IC
Collector Current - Continuous
- Peak Pulse Current
1
2
A
TJ, Tstg
Operating and Storage Junction Temperature Range
-55 to +150
°C
Symbol
Parameter
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150°C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
TA = 25°C unless otherwise noted
Max
Characteristic
Symbol
Units
FMMT549
PD
Total Device Dissipation*
Derate above 25°C
500
4
mW
mW/°C
RθJA
Thermal Resistance, Junction to Ambient
250
°C/W
*Device mounted on FR-4 PCB 4.5” X 5”; mounting pad 0.02 in2 of 2oz copper.
 1998 Fairchild Semiconducto Corporation
Page 1 of 2
fmmt549.lwpPrPB 7/10/98 revB
Electrical Characteristics
Symbol
TA = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Max
Units
OFF CHARACTERISTICS
BVCEO
Collector-Emitter Breakdown Voltage
IC = 10 mA
30
V
BVCBO
Collector-Base Breakdown Voltage
IC = 100 µA
35
V
BVEBO
Emitter-Base Breakdown Voltage
IE = 100 µA
5
V
ICBO
Collector Cutoff Current
VCB = 30 V
100
10
VCB = 30 V, Ta=100°C
IEBO
Emitter Cutoff Current
100
VEB = 4V
nA
uA
nA
ON CHARACTERISTICS*
hFE
VCE(sat)
DC Current Gain
Collector-Emitter Saturation Voltage
IC = 50 mA, VCE = 2V
70
-
IC = 500 mA, VCE = 2V
100
IC = 1A, VCE = 2V
80
IC = 2A, VCE = 2V
40
300
IC = 1 A, IB = 100 mA
500
mV
IC = 2 A, IB = 200 mA
750
mV
1.25
V
VBE(sat)
Base-Emitter Saturation Voltage
IC = 1 A, IB = 100 mA
VBE(on)
Base-Emitter On Voltage
IC = 1 A, VCE = 2 V
1
V
25
pF
SMALL SIGNAL CHARACTERISTICS
Cobo
Output Capacitance
VCB = 10 V, IE = 0, f = 1MHz
fT
Transition Frequency
IC = 100 mA,VCE = 5 V, f=100MHz
100
MHz
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
 1998 Fairchild Semiconducto Corporation
Page 2 of 2
fmmt549.lwpPrPB 7/10/98 revB
FMMT549
PNP Low Saturation Transistor
(continued)
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
CoolFET™
CROSSVOLT™
E2CMOSTM
FACT™
FACT Quiet Series™
FAST®
FASTr™
GTO™
HiSeC™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
TinyLogic™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
July 1998
FMMT560 / FMMT560A
C
E
B
TM
SuperSOT -3 (SOT-23)
NPN Low Saturation Transistor
These devices are designed with high current gain and low saturation voltage with collector currents up to 2A
continuous.
Absolute Maximum Ratings*
Symbol
TA = 25°C unless otherwise noted
Parameter
FMMT560/FMMT560A
Units
VCEO
Collector-Emitter Voltage
60
V
VCBO
Collector-Base Voltage
80
V
VEBO
Emitter-Base Voltage
5
V
IC
Collector Current - Continuous
2
A
TJ, Tstg
Operating and Storage Junction Temperature Range
-55 to +150
°C
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150°C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
TA = 25°C unless otherwise noted
Max
Symbol
Characteristic
Units
FMMT560/FMMT560A
PD
Total Device Dissipation
500
mW
RθJA
Thermal Resistance, Junction to Ambient
250
°C/W
 1998 Fairchild Semiconductor Corporation
Page 1 of 2
fmmt560.lwpPrNA 7/1098 RevB
FMMT560/FMMT560A
Discrete Power & Signal
Technologies
(continued)
Electrical Characteristics
Symbol
TA = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Max
Units
OFF CHARACTERISTICS
BVCEO
Collector-Emitter Breakdown Voltage
IC = 10 mA
60
V
BVCBO
Collector-Base Breakdown Voltage
IC = 100 µA
80
V
BVEBO
Emitter-Base Breakdown Voltage
IE = 100 µA
5
V
ICBO
Collector Cutoff Current
VCB = 30 V
100
VCB = 30 V, TA=100°C
10
nA
uA
VEB = 4V
100
nA
IEBO
Emitter Cutoff Current
ON CHARACTERISTICS*
hFE
DC Current Gain
IC = 100 mA, VCE = 2 V
70
IC=500mA, VCE =2V FMMT560
100
FMMT560A
VCE(sat)
Collector-Emitter Saturation Voltage
250
IC = 1 A, VCE = 2 V
80
IC = 2 A, VCE = 2 V
40
300
550
IC = 1 A, IB = 100 mA
300
IC = 2 A, IB=200 mA FMMT560
FMMT560A
350
mV
1.25
V
300
VBE(sat)
Base-Emitter Saturation Voltage
IC = 1 A, IB = 100 mA
VBE(on)
Base-Emitter On Voltage
IC = 1 A, VCE = 2 V
1
V
30
pF
SMALL SIGNAL CHARACTERISTICS
Cobo
Output Capacitance
VCB = 10 V, IE = 0, f = 1MHz
fT
Transition Frequency
IC = 100 mA,VCE = 5 V, f=100MHz
75
-
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
 1998 Fairchild Semiconductor Corporation
Page 2 of 2
fmmt560.lwpPrNA 7/1098 RevB
FMMT560/FMMT560A
NPN Low Saturation Transistor
July 1998
FMMT660 / FMMT660A
C
E
B
TM
SuperSOT -3 (SOT-23)
PNP Low Saturation Transistor
These devices are designed with high current gain and low saturation voltage with collector currents up to 2A
continuous.
Absolute Maximum Ratings*
TA = 25°C unless otherwise noted
FMMT660/FMMT660A
Units
VCEO
Collector-Emitter Voltage
60
V
VCBO
Collector-Base Voltage
80
V
VEBO
Emitter-Base Voltage
5
V
IC
Collector Current - Continuous
2
A
TJ, Tstg
Operating and Storage Junction Temperature Range
-55 to +150
°C
Symbol
Parameter
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150°C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
TA = 25°C unless otherwise noted
Max
Characteristic
Symbol
Units
FMMT660/FMMT660A
PD
Total Device Dissipation
500
mW
RθJA
Thermal Resistance, Junction to Ambient
250
°C/W
 1998 Fairchild Semiconductor Corporation
Page 1 of 2
fmmt660.lwpPrPA 7/10/98 RevB
FMMT660/FMMT660A
Discrete Power & Signal
Technologies
Electrical Characteristics
Symbol
TA = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Max
Units
OFF CHARACTERISTICS
BVCEO
Collector-Emitter Breakdown Voltage
IC = 10 mA
60
V
BVCBO
Collector-Base Breakdown Voltage
IC = 100 µA
80
V
BVEBO
Emitter-Base Breakdown Voltage
IE = 100 µA
5
V
ICBO
Collector Cutoff Current
VCB = 30 V
100
VCB = 30 V, TA=100°C
10
nA
uA
VEB = 4V
100
nA
IEBO
Emitter Cutoff Current
ON CHARACTERISTICS*
hFE
DC Current Gain
IC = 100 mA, VCE = 2 V
70
IC=500mA, VCE =2V FMMT660
100
FMMT660A
VCE(sat)
Collector-Emitter Saturation Voltage
250
IC = 1 A, VCE = 2 V
80
IC = 2 A, VCE = 2 V
40
300
550
IC = 1 A, IB = 100 mA
300
IC = 2 A, IB=200 mA FMMT660
FMMT660A
350
mV
1.25
V
300
VBE(sat)
Base-Emitter Saturation Voltage
IC = 1 A, IB = 100 mA
VBE(on)
Base-Emitter On Voltage
IC = 1 A, VCE = 2 V
1
V
30
pF
SMALL SIGNAL CHARACTERISTICS
Cobo
Output Capacitance
VCB = 10 V, IE = 0, f = 1MHz
fT
Transition Frequency
IC = 100 mA,VCE = 5 V, f=100MHz
75
-
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
Page 2 of 2
fmmt660.lwpPrPA 7/10/98 RevB
FMMT660/FMMT660A
PNP Low Saturation Transistor
(continued)
www.fairchildsemi.com
FMS2701
Temperature and Power Supply Voltage Monitor
Description
•
•
•
•
•
•
•
•
•
The FMS2701 is a temperature- and voltage-monitoring
device that can be interrogated and controlled through an
SMBus serial interface. Outputs are an analog fan control
voltage, thermal alarm and interrupts.
Remote diode temperature sensing
Ambient (on-chip) temperature sense
Dual 3.3 volt supply monitoring
SMBus interface to internal registers
Status registers
Thermal trip output
Interrupt output
Fan speed control output
ACPI Thermal Management compliant
Remote (DIODE+ and DIODE-) and ambient diode temperature sensor inputs are selected in sequence at a 1Hz rate by
a multiplexer that drives an A/D converter. Digitized diode
temperatures are stored in registers. Violation of a programmable limit or trip point will set an interrupt register bit and/
or assert a digital output.
Applications
Power supply voltages are monitored through two pins:
VCCAUX3 monitors the power to the FMC2701; VCC3 is a
separate 3.3 volt sense voltage input. AUXRST and RST outputs indicate the status of voltage monitoring.
• PCs and Servers, Workstations
• Office Equipment
• Test and Measurement Instruments
Analog output, FAN_SPD can be used as an input to a fan
speed control circuit while THERM, INT and FAN_OFF are
additional digital control outputs.
Power is derived from a +3.3V supply. Package is 16-lead
Quad Small Outline Pack (QSOP).
Block Diagram
VCC3AUX
Aux Reset
AUXRST
Main Reset
RST
D/A
Converter
FAN_SPD
Oscillator
INTRST
VCC3
Timing
and Control
MR
Current
Generators
DIODE+
DIODE-
D/A
Register
Low-pass
Filter
Mux
On-chip
Bias &
Diode
A/D
Converter
DSP
Limit
Comparators
Interrupt
Status
Registers
Value & Limit
Registers
Interrupt
Mask
Register
THERM
ADD
SDA
SCL
SMBus
Interface
Internal Bus
Mask
Gating
INT
GPI
Configuration
Register
Lit. No. 600402-001
FAN_OFF
Rev. 1.0.3
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals
and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
Preliminary Information
Features
PRODUCT SPECIFICATION
Architectural Overview
Preliminary Information
Overall operation of the FMS2701 is controlled by the
SMBus which sets register values and interrupt masking.
Four sensing inputs are monitored:
1. Remote temperature diode voltage
2. Ambient temperature sensing diode voltage
3. Remote 3.3 volt power supply voltage
4. Local 3.3 volt power supply
Following comparisons against either preset or programmable thresholds, the following hardware outputs are set:
1. Master reset
2. Auxiliary reset
3. Temperature trip point violated (THERM)
4. Interrupt (INT)
Also set are the following register bits:
1. GPI active (General Purpose Input)
2. Remote Temperature limit exceeded
3. THERM input asserted
4. Remote diode fault
Fan Speed control voltage, FAN_SPD is set in the range
0–2.5V by loading the D/A Register through the SMBus.
External THERM = L forces FAN_SPD = 2.5V. A Master
Reset clears the D/A Register.
Temperature Channel
There are two temperature sense inputs: one for remote sensing; the other for measuring ambient temperature. Both
inputs utilize the thermal variation of the voltage drop across
a diode, to derive the diode temperature.
Instead of sensing the change in VD at one current, which is
approximately –2mV/°C, VD is sampled at two currents
(IMAX = 10 and IMIN = 100 µA) to cancel out common error
voltages. Difference voltage between the two currents is
proportional to absolute temperature:
nkT
I
∆VD = q ⋅ ln MAX
IMIN
Where:
n = PN junction ideality factor, typically 1.0065 for the
Pentium II thermal diode. Nominal diode sensitivity is
199.7 µV/°C.
2
FMS2701
Following the A/D converter is a DSP block which averages
digitized temperature over several samples.
Upper and lower temperature limits are loaded into the limit
registers. If a limit is violated, an interrupt is generated. Remote
diode open or short circuit fault condition is also sensed.
Power Supply Voltage Monitors
Two Voltage Monitors operating over a 1.0 to 3.8 volt
supply range, sense VCC3 and VCC3AUX voltages. If
input VCC3 < 2.93 volt or master reset input, MR = L, then
RST= L until 140 msec after sensing the fault condition.
If the FMS2701 supply, VCC3AUX < 2.93 volt, AUXRST = L
until 140 msec. after sensing the fault condition, and the main
reset RST = L until 180 msec. after AUXRST is cleared.
When AUXRST = L, internal reset, INTRST =L. AUXRST
is bi-directional, accepting a hard reset input.
SMBus Interface
FMS2701 Registers are accessed through the SMBus interface located at the address 0x2C + n; where n = 0, 1, 2
depending upon the state of ADD, a tri-level input. Within
the FMS2701, registers are accessed through an 8-bit bus.
Addressable Memory
Within the FMS2701, there are three sections of addressable
memory which implement the following functions.
Command Register (5 locations)
•
•
•
•
•
Configuration
Interrupt status
Interrupt mask
Interrupt status mirror
Extended function
Read only RAM (2 locations)
• Company ID
• Revision No.
Value RAM (13 locations)
•
•
•
•
Diode temperature, °C
THERM temperature trip points, °C
INT temperature limits, °C
Analog output D/A converter
Write accessible locations have default values that may be
overridden by programming through the SMBus interface.
FMS2701
PRODUCT SPECIFICATION
Pin Assignment
FAN_OFF
1
16
SDA
MR
2
15
SCL
AUXRST
3
14
INT
GND
4
13
ADD/NTESTOUT
VCC3AUX
5
12
GPI
VCC3
6
11
THERM
RST
7
10
DIODE(+)
FAN_SPD/NTEST_IN
8
9
DIODE(-)
Pin No.
Pin Name
Reset
7
RST
Type/Value
Output
3
AUXRST
Bi-directional
2
MR
Input
Analog I/O
10
DIODE+
Voltage input/
current source
9
DIODE-
Voltage input/
current sink
8
FAN_SPD/NTEST_IN
Analog output/
digital input
Pin Function Description
Reset. Output pulse from Main Reset Generator, which
is tripped by either MR =L or Internal Reset or VCC3 <
2.93 V. When active, RST = L and register D7-0 is
cleared.
Auxiliary Reset Input/Output. As an output, AUXRST =
L pulse is triggered by VCC3AUX < 2.93 V. As an input,
AUXRST = L trips Internal Reset. NAND test input,
NTEST_IN is sampled by trailing edge of AUXRST pulse.
Manual Reset. Input to Master Reset Generator. If MR =
L, a master reset cycle is initiated. MR pin has a 20 kΩ
pull-up to VCC3AUX.
Positive diode sense input. Current source to remote
temperature sensing diode anode and upper voltage
sense input.
Negative diode sense input. Current sink from remote
temperature sensing diode cathode and lower voltage
sense input.
Fan speed control voltage output/NAND Test Input.
Proportional to the value in register 0x19, output is
0–2.5V. External THERM = L forces a 2.5 volt output. If
NTEST_IN = H, the NAND tree test input is enabled for
ATE.
Serial Port
16
SDA
15
SCL
13
ADD/NTEST_OUT
Bi-directional
Input
Tri-level
Data. SMBus data to/from FMS2701
Clock. SMBus clock into FMS2701
SMBus Address Input/NAND Test Output. Lowest two
bits of serial port address with three states: 00, 01 and
10, corresponding to H, L and Z inputs. If NTEST_IN is
sampled HIGH, the NAND tree test output is enabled.
Digital I/O
11
THERM
I//O (Open drain)
Thermal Overload. THERM = L indicates that a
temperature trip point has been exceeded. Input THERM
= L sets the THERM bit in the Interrupt Status Register.
System interrupt. INT = L when a voltage, temperature
limit or temperature trip point is violated and bit 1 of the
Configuration Register is set H.
14
INT
Open drain
3
Preliminary Information
Pin Descriptions
PRODUCT SPECIFICATION
FMS2701
Pin No.
Pin Name
12
GPI
1
Type/Value
Input
Open Drain Output
FAN_OFF
Power and Ground
6
VCC3
Preliminary Information
4
5
+3.3 V Input
GND
VCC3AUX
0V
+3.3 V Power
Pin Function Description
General Purpose Input. Sets a bit in the interrupt
registers. Assertion polarity is set by the GPI_INV bit.
(default is GPI = H causes interrupt)
Fan off request. FAN_OFF reflects the state of the
Configuration Register FAN_OFF bit. FAN_OFF = L is a
request to shut the fan off.
Voltage Monitor Input. Voltage monitor input to Main
Reset Generator. If VCC3 drops below 2.93V. a Main
Reset cycle is initiated.
Ground. Return for 3.3 volt supply, VCC3AUX.
Auxiliary 3.3 volt. Power source for FMS2701. If
VCC3AUX drops below 2.93 volt, an Auxiliary Reset
cycle is initiated.
Addressable Memory
Addressable memory is divided into two sections:
1. Command, consisting of five registers
2. Value RAM, consisting of thirteen locations, of which: eleven are used to store temperature data, limits and trip points;
two are used to store the company ID, version and revision number.
Table 1. Addressable Memory Map
Name
Configuration Register
Interrupt Status Register
Interrupt Mask Register
Interrupt Status Register Mirror
PTA7-0
PTR7-0
FTA7-0
FTR7-0
DAC7-0
TR7-0
TA7-0
TRHI7-0
TRLO7-0
TAHI7-0
TALO7-0
Manufacturer ID
Version, Revision
Address
0x40
0x41
Power-up Value, [7:0]
0x25
0x00
0x43
0x4C
0x13
0x14
0x00
0x00
0x46
0x64
0x17
0x18
0x46
0x64
0x19
0x26
0x27
0x37
0x38
0x39
0x3A
0x3E
0x3F
0x00
0x46
0x3C
0x50
0x3C
0x46
0x32
0xFC
0xCn
Register Definitions
Configuration Register (0x40)
BIT#
0
4
Name
START
Type
R/W
Description
Start Temperature and Voltage Monitoring
0: Standby mode. (INT is not cleared)
1: Run (Power-up default). All limit and trip values should be entered into
FMS2701 registers prior to setting START = 1.
FMS2701
PRODUCT SPECIFICATION
BIT#
1
Name
INT_EN
Type
R/W
2
INT_CLR
R/W
TRIP_LOCK
R/(W-once)
4
SOFT_RST
R/W
5
FAN_OFF
R/W
6
GPI_INV
R/W
7
Reserved
R/W
Interrupt Enable
0: Disabled (Power-up default)
1: Enables the INT output.
Interrupt Clear
0: INT output unaffected.
1: Clears the INT output. Contents of the Interrupt Status Register
preserved. (Power-up default = 1)
Temperature Trip Point Lock
0: THERM trip points set by fixed value registers FTA7-0 and FTR7-0.
Writes to programmable registers PTA7-0 and PTR7-0 are enabled.
(Power-up default = 0)
1: THERM trip points set by values preserved in programmable registers
PTA7-0 and PTR7-0, while RST = H.
Soft Reset
0: Power-up default restored by SOFT_RST cycle.
1: Restore power-up values to the Configuration, Interrupt Status,
Interrupt Status Mirror and Interrupt Mask registers.
Fan Off
0: Set output pin FAN_OFF = L. (fan-off)
1: Set output pin FAN_OFF = Z. (Power-up default, fan-on)
If pin THERM = L, then FAN_OFF = H.
GPI Polarity Invert
0: GPI input passed to Interrupt registers. (Power-up default)
1: Invert the GPI input passed to Interrupt registers
Reserved (Default=0)
Interrupt Status Register1 (0x41)
BIT#
0
Name
ATV
Type
R
1
2
3
4
Reserved
Reserved
Reserved
GPI
R
R
R
R
Description
Ambient Temperature Violation
0: On-chip temperature within limits.
1: On-chip temperature limit violated
Reserved for Remote Thermal Diode 2 temp error
Reserved for Remote Thermal Diode 2 fault
Undefined
General Purpose Input Status.
GPI is set according to the following truth table:
GPI pin
0
1
0
1
5
RTV
R
6
THERM
R
GPI_INV
0
0
1
1
GPI bit
0
1
1
0
Reading this register will not clear the GPI bit.
Remote Temperature Violation.
0: Remote temperature within limits.
1: Remote temperature limit violated
THERM input status.
0: THERM input negated. (THERM = H)
1: THERM input asserted. (THERM = L)
5
Preliminary Information
3
Description
PRODUCT SPECIFICATION
BIT#
7
Name
FAULT
FMS2701
Type
R
Description
Remote Diode Fault.
0: Diode functional
1: Remote temperature sensing diode short or open circuit.
Note:
1.
Reading this register will clear ATV, RTV THERM and FAULT bits.
Preliminary Information
Interrupt Mask Register (0x43)
BIT#
0
Name
MSKATV
Type
R/W
1
2
3
4
Reserved
Reserved
Reserved
MSKGPI
R
R
R
R/W
5
MSKRTV
R/W
6
MSKTHERM
R/W
7
MSKFAULT
R/W
Description
Mask Ambient Temperature Violation bit.
0: Allow ATV bit to affect INT output.
1: Prohibit ATV bit from affecting the INT output.
Undefined
Undefined
Undefined
Mask GPI bit
0: Allow GPI bit to affect INT output.
1: Prohibit GPI bit from affecting the INT output.
Mask Remote Temperature Violation bit.
0: Allow RTV bit to affect INT output.
1: Prohibit RTV bit from affecting the INT output.
Mask THERM bit.
0: Allow THERM bit to affect INT output.
1: Prohibit THERM bit from affecting the INT output.
Mask Remote Fault bit.
0: Allow FAULT bit to affect INT output.
1: Prohibit FAULT bit from affecting the INT output.
Note:
1.
An error that causes continuous interrupts to be generated may be masked using the mask register, until the error can be
alleviated.
Interrupt Status Mirror Register1 (0x4C)
BIT#
Name
Read/Write
Description
0
MATV
R
Mirrored Ambient Temperature Violation
0: On-chip temperature within limits.
1: On-chip temperature limit violated
1
Reserved
R
Reserved for Remote Thermal Diode 2 temp error
2
Reserved
R
Reserved for Remote Thermal Diode 2 fault
3
Reserved
R
Undefined
4
MGPI
R
Mirrored General Purpose Input Status.
MGPI is set according to the following ????? table:
GPI pin
0
1
0
1
GPI_INV
0
0
1
1
MGPI
0
1
1
0
Reading this register will not clear the GPI bit.
5
6
MRTV
R
Mirrored Remote Temperature Violation.
0: Remote temperature within limits.
1: Remote temperature limit violated
FMS2701
PRODUCT SPECIFICATION
BIT#
Name
Read/Write
Description
6
MTHERM
R
Mirrored THERM input status.
0: THERM input negated. (THERM = H)
1: THERM input asserted. (THERM = L)
7
MFAULT
R
Mirrored Remote Diode Fault.
0: Diode functional
1: Remote temperature sensing diode short or open circuit.
Note:
1. Reading this register will clear MATV, MRTV, MTHERM and MFAULT bits.
Extended Function Register (0x15)
Name
Type
R
-
N/A
MIT
7–1
Description
Mask Internal THERM
0: Internally generated THERM affects INT output.
1: Internally generated THERM does not impact INT output.
Reserved
Value RAM (0x13–0x4A)
Unless stated otherwise, Power-on defaults are not defined,.
Address
0x13
0x14
0x17
0x18
0x19
0x20
0x26
0x27
0x2B
0x2C
0x37
0x38
0x39
0x3A
0x3E
0x3F
0x44 – 0x4A
0x4D – 0x53
Name
PTA7-0
Type
Description
R/W Programmable Ambient Temperature Automatic Trip Point. If TA7-0 > PTA70, then THERM = L. Write access is disabled if the TRIP_LOCK bit in the
Configuration Register been set. (default: 46h (70°C)
PTR7-0 R/W Programmable Remote Thermal Diode Automatic Trip Point. If TR7- > PTR70, then THERM = L. Write access is disabled if the TRIP_LOCK bit in the
Configuration Register been set. (default: 64h (100°C)
R
Fixed Ambient Temperature Automatic Trip Point. (default: 46h (70°C)
FTA7-0
FTR7-0
R
Fixed Remote Thermal Diode Automatic Trip Point. (default: 64h (100°C)
DAC7-0 R/W D/A Converter Input. Value supplied to D/A converter to generate fan speed
control voltage. (default: 00h)
N/A Reserved
TR7-0
R
Remote Thermal Diode Temperature. Temperature output derived from
remote thermal diode.
TA7-0
R
Ambient Temperature. Temperature output derived from on-chip thermal
diode.
N/A Reserved
N/A Reserved
TRHI7-0 R/W Remote Thermal Diode High Temperature Limit. TR7-0 > TRHI7-0 will set
the RTV and MRTV bits in the Interrupt and Mirrored Interrupt registers.
TRLO7-0 R/W Remote Thermal Diode Low Temperature Limit. TR7-0 < TRLO7-0 will set
the RTV and MRTV bits in the Interrupt and Mirrored Interrupt registers.
TAHI7-0 R/W Ambient Temperature High Temperature Limit. TA7-0 > TAHI7-0 will set the
ATV and MATV bits in the Interrupt and Mirrored Interrupt registers.
TALO7-0 R/W Ambient Temperature Low Temperature Limit. TA7-0 < TALO7-0 will set the
ATV and ARTV bits in the Interrupt and Mirrored Interrupt registers.
MFR7-0
R
Manufacturer ID. Value is FC.
NUM7-0
R
Version and Revision. NUM7-4 = C, the FMS2701 version number. NUM3-0 =
revision number
N/A Reserved
N/A Reserved
7
Preliminary Information
BIT#
0
PRODUCT SPECIFICATION
FMS2701
Functional Description
Temperature Processor
Operation of the FMS2701 is divided into three sections:
• Temperature Processor
• Reset Generators
• Data Processor
Remote and ambient thermal diode voltages are processed
by the Temperature Processor which outputs values of
remote and ambient temperature alternately. Inputs are
derived from a remote diode that is connected by two wires
to the input of the processor; and the ambient diode, which is
located on-chip. Output is supplied to the Data Processor
which loads the TA7-0 and TR7-0 registers with the digitized
ambient and remote temperatures.
Preliminary Information
Current
Generators
Remote
PN
Junction
A/D
Converter
TEMP7-0
DSP
RMT_ERROR
Mux
Ambient
PN
Junction
29220
XDIODE
Figure 1. Temperature Processor Block Diagram
A multiplexer selects the thermal diode to be sensed. Voltage
of the diode is sensed at two currents:10 and 100 µA. During
the diode sampling interval, the A/D converter digitizes low
and high current samples. DSP averages and subtracts the
samples to output an 8-bit temperature that is updated a rate
greater than 1 Hz. Remote and Ambient diode temperatures
are outputted alternately on the TEMPR[7:0] bus which is
connected to the Data Processor.
Remote Diode fault sensing is included within the DSP
block. If the remote diode voltage indicates either a short or
an open circuit, the RMT_ERROR signal causes the
RMT_FAULT bit to be set in the Interrupt Status Register.
Temperature data format is 8-bit, two’s complement with the
LSB equivalent to 1.0°C. Range and conversion between °C
and equivalent binary and hexadecimal data is exemplified in
Table 2.
8
Table 2. Temperature/Data Conversion/Format
Temperature
Digital Output
Binary
Hex
+125°C
0111 1101
0x7D
+25°C
0001 1001
0x19
+1.0°C
0000 0001
0x01
0°C
0000 0000
0x00
-1.0°C
1111 1111
0xFF
-25°C
1110 0111
0xE7
-55°C
1100 1001
0xC9
FMS2701
PRODUCT SPECIFICATION
Reset Generators
In Figure 2, VCC3AUX<2.93V represents the state of the
VCC3AUX power supply voltage.
There are two reset generators:
1. Auxiliary Reset
2. Main Reset
Auxiliary Reset responds to the power supply voltage,
VCC3AUX applied to the FMS2701. Main Reset responds
to a separate power supply voltage level, VCC3. Threshold
level of both reset generators is 2.93 volt. If 1.0 V < VCC3AUX
< 2.93 both generators output an active L reset level.
1.
VCC3AUX < 2.93 volt. After a VCC3AUX < 2.93
transition:
a) AUXRST(OUT) = L, continuing low for 140 msec.
after VCC3AUX > 2.93 volt.
b) INTRST = L, while AUXRST(OUT) = L.
2.
AUXRST(IN) = L. In response, INTRST = L,
continuing low until AUXRST(IN) = H
Internal reset, INTRST tracks AUXRST_OUT. To terminate a
reset cycle, VCC3AUX must rise above 2.93 volt. During
power-up, the AUXRST output remains low until the 2.93
volt threshold is reached.
140 mS
VCC3AUX<2.93V
tDAUXRST
AUXRST(IN)
tDVRST
AUXRST(OUT)
tDINTRST
INTRST
Figure 2. Timing Diagram, Auxiliary Reset
Main Reset
Depending upon the source of reset, the Main Reset
Generator outputs either a 140 or a 180 msec. pulse as shown
in Figure 3. VCC3 < 2.9 represents the state of the VCC3
power supply voltage. RST = L clears the D/A Converter
register.
tDMR
MR
tDVR
VCC3<2.9
tDIR
INTRST
140 mS
180 mS
180 mS
RST
Figure 3. Timing Diagram, Main Reset
9
Preliminary Information
Auxiliary Reset Generator
The Auxillary Reset Generator responds to either a low value
of VCC3AUX by outputting an AUXRST = L pulse and an
internal reset pulse, INTRST; or to an external AUXRST
input by emitting an internal reset. Internal reset restores
power-up register values (except DAC7-0 which is cleared by
RST) and initiates a Master Reset Cycle.
AUXRST is a bi-directional pin. AUXRST(OUT) signifies
an outgoing signal. AUXRST(IN) signifies an incoming signal. Auxiliary Reset is triggered by either of two events:
PRODUCT SPECIFICATION
FMS2701
Data Processor
Preliminary Information
Internal Reset
Internal reset, INTRST originates from the Auxiliary Reset
Generator. When power is supplied to the FMS2701 via
VCC3AUX, output INTRST = L for 140 msec. after
VCC3AUX transitions >2.93 volt. INTRST = L instigates
four events:
1. Configuration, Interrupt and Mask registers are reset to
default values.
2. THERM Temperature Trip Point registers: PTA7-0,
PTR7-0, FTA7-0, FTR7-0 are set to default values.
3. DAC7-0 register is set to 0x00.
4. Temperature Processor and Data Processor are reset.
Trip & Limit
Registers
TR7-0
Temperature
TA7-0
Registers
T7-0
Limit
Corporators
Based upon setup commands via the SMBus, the Data Processor gathers sensor inputs from the Temperature Processor
and Reset Generators. Temperature inputs are compared
against values stored in the Trip and Limit registers. Fault
conditions set flags in the interrupt registers and activate the
THERM and INT outputs. Temperature and interrupt status
are passed to the host via the SMBus interface. Host commands set the FMS2701 configuration, interrupt masking
and the fan speed.
RST
Fan Speed
Register
Ambient Error
Remote Error
Remote Fault
D/A
Converter
FAN_SPD
Interrupt
Status
Registers
Bypass/
Invert
GPI
DAC7-0
THERM
Interrupt
Mask
Registers
NADD
Test Logic
NTEST_IN
Configuration
Registers
INTEST_OUT
Mask
Gating
INT
ADD/NTEST_OUT
FAN_OFF
ADD
Interface
SCA
Test
Registers
Pointer
Register
SMBus
Interface
Data Bus
Compare ID
and Version
Registers
SCL
MCLK
Master
Oscillator
Timing
and Control
Figure 4. Data Processor Block Diagram
10
FMS2701
PRODUCT SPECIFICATION
SMBus Interface
FMS2701 register access is via a 2-wire SMBus interface.
Base address is 0x2C + n, where n is an offset defined by the
state of the ADD pin: Z, H, L == 0, 1, 2. (see Table 3) State Z
corresponds to the ADD pin being open circuit.
Data received or transmitted on the SDA line must be stable
for the duration of the positive-going SCL pulse. Data on
SDA may change only when SCL = L. An SDA transition
while SCL = H is interpreted as a start or stop signal.
Table 3. Serial Port Slave Addresses
ADD
Address
Z
2C
H
2D
L
2E
Two signals comprise the bus: clock (SCL) and bi-directional data (SDA). When receiving and transmitting data
through the serial interface, the FMS2701 acts as a slave,
responding only to commands by the SMBus master.
Preliminary Information
SDA
tBUFF
tDHO
tSTAH
tDSU
tSTASU
tSTOSU
tDAL
SCL
tDAH
24469B
Figure 5. SMBus: Read/Write Timing
SDA
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ACK
SCL
24470B
Figure 6. SMBus: Typical Byte Transfer
SDA
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
SCL
Figure 7. SMBus: Slave Address with Read/Write Bit
11
Preliminary Information
PRODUCT SPECIFICATION
FMS2701
There are five steps within an SMBus cycle:
1. Start signal
2. Slave address byte
3. Pointer register address byte
4. Data byte to read or write
5. Stop signal
A repeated start signal occurs when the master device driving the serial interface generates a start signal without first
generating a stop signal to terminate the current communication. This is used to change the mode of communication
(read, write) between the slave and master without releasing
the serial interface lines.
When the SMBus interface is inactive (SCL = H and SDA = H)
communications are initiated by sending a start signal. The
start signal (Figure 5, left waveform) is a HIGH-to-LOW
transition on SDA while SCL is HIGH. This signal alerts all
slaved devices that a data transfer sequence is imminent.
Serial Interface Read/Write Examples
Examples below show how serial bus cycles can be linked
together for multiple register read and write access cycles.
For sequential register accesses, each ACK handshake initiates further SCL clock cycles from the master to transfer
the next data byte.
After a start signal, the first eight bits of data that are transferred,
comprise a seven bit slave address followed a single R/W bit
(Read = H, Write = L). As shown in Figure 6, the R/W bit
indicates the direction of data transfer: read from; or write to
the slave device. If the transmitted slave address matches the
address of the FMS2701 which set by the state of the ADD
pin, the FMS2701 acknowledges by pulling SDA LOW on
the 9th SCL pulse (see Figure 7) to send an acknowledge bit,
ACK. If the addresses do not match, the FMS2701 does not
acknowledge.
For each byte of data read or written, the MSB is the first bit
of the sequence.
DATA TRANSFER
If a slave device such as the FMS2701 does not acknowledge
the master device during a write sequence, SDA remains HIGH
so that the master can generate a stop signal. During a read
sequence, if the master device does not acknowledge (ACK = L),
the FMS2701 interprets this as “end of data.” SDA remains
HIGH so the master can generate a stop signal.
To write data to a specific FMS2701 control register, three
bytes are sent:
1. Write the slave address byte with bit R/W = L.
2. Write the pointer byte.
3. Write to the control register indexed by the pointer.
Data is read from the control registers of the FMS2701 in a
similar manner, except that two data transfer operations are
required:
1. Write the slave address byte with bit R/W = L.
2. Write the pointer byte.
3. Write the slave address byte with bit R/W = H
4. Read the control register indexed by the pointer.
Preceding each slave write, there must be a start cycle. Following the pointer byte there should be a stop cycle. After the last
read, there must be a stop cycle comprising a LOW-to-HIGH
transition of SDA while SCL is HIGH. (see Figure 5, right
waveform)
12
Write to one control register
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte
4. Data byte to base address
5. Stop signal
Read from one control register
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte (= base address)
4. Stop signal
5. Start signal
6. Slave Address byte (R/W bit = HIGH)
7. Data byte from base address
8. Stop signal
Addressable Memory
Although the FMS2701 will respond to external inputs, control of the operation of the FMS2701 is through the internal
registers. Following power-up, registers are set to default
values. After a 140 msec. power up reset delay, the FMS2701
will begin checking sensor inputs to determine if the temperature in voltages fall within default limits.
These default values may be overridden by changing the values stored in the Value RAM. If the PTA7-0 and PTR7-0 values are changed, then the TRIP_LOCK (Temperature Trip
Point Lock) bit in the Configuration Register must be set to
enable temperature values to be compared against the programmable rather than the fixed trip point values. If the temperature limit values are changed, then the changes are
effective immediately. Interrupt masking (register 0x43),
enabling (INT_EN bit) and clearing (INT_CLR bit) can be
used to disable interrupts during register setup.
There are four control registers and 21 Value RAM locations,
with functions and bit assignments defined in the Addressable Memory section.
FMS2701
PRODUCT SPECIFICATION
THERM Processing
THERM is a bi-directional pin with an open drain output.
When the THERM output is asserted L, the THERM input is
disabled. Figure 8 depicts the logical flow of the internal and
external THERM signals, showing the origins and destinations.
D/A Converter
An 8-bit D/A converter supplies a voltage to the FAN_SPD
pin which, can be used to control the speed of a fan. Input of
the D/A converter is connected to the DAC7-0 register.
DAC7-0 value is loaded from the SMBus. In the event of a
THERM condition, the DAC7-0 output remains unchanged
but the D/A converter output is set full scale, equivalent to
DAC7-0 = 0xFF. RST = L clears DAC7-0 in the fan speed
register.
INTRSTb
Interrupt
Status
Register
Mirror
TEMPVALID
PTR 7-0
FRY7-0
Fixed Trip
Point
Registers
THERM
XTHERM
PTA 7 0-
FTR 7-0
HOT7-0
ITHERM
THERM
Comparators
Interrupt
Status
Register
FTA 7-0
Other
Interrupts
THERM
Interrupt
Mask
Register
ITHERM
Restore
MSKTHERM
Mask
Gating
Interrupt
OR-gate
INT
TRIPLOCK
TR[7:0]
Configuration
Register
TA[7:0]
FAN_OFF
DACFF==THERM
RST
D/A
Register
D/A
Converter
FAN_SPD
Figure 8. THERM I/O Structure/Detail
As an input, if THERM = L the following events occur:
1. If the mask bit, MSKTHERM = L, output pin, INT = L
2. Configuration Register bit, FAN_ON = H.
3. Output pin, FAN_SPD = 2.5 V for maximum fan speed
but register DAC7-0 is unchanged.
4. Interrupt Status Register bit, THERM = H.
5. Interrupt Status Register Mirror bit, MTHERM = H.
As an output, ITHERM = H, causes THERM = L; ITHERM
= L, causes THERM = Z, open drain. ITHERM = H, if any
of the following conditions occur:
1.
2.
If Configuration Register bit, TRIPLOCK = H and
Programmable Ambient Temperature Automatic Trip
Point PTA7-0 is exceeded.
If Configuration Register bit, TRIPLOCK = H and
Programmable Remote Temperature Automatic Trip
Point PTR7-0 is exceeded.
3.
4.
If Configuration Register bit, TRIPLOCK = L and Fixed
Ambient Temperature Automatic Trip Point FTA7-0 is
exceeded.
If Configuration Register bit, TRIPLOCK = L and Fixed
Remote Temperature Automatic Trip Point
FTR7-0 is exceeded.
TRIPLOCK is Temperature Trip Point Lock bit in the
Configuration Register.
After a Trip Point has been exceeded, to restore the open
drain output, THERM = Z, the temperature must fall 5°C
below the trip point.
13
Preliminary Information
Programmable
Trip Point
Registers
PRODUCT SPECIFICATION
FMS2701
INT Processing
INT is a hardware interrupt output. INT operation is controlled by the Configuration Register bits: INT_EN and
INT_CLR bits, which enable and clear the open drain INT
output. Subject to the setting of the Interrupt Mask Register,
INT =L, if any bit in the Interrupt Register is active. Otherwise INT = Z, open drain. Figure 9 depicts the logical flow
of the interrupt sources to the INT output.
THERM
XTHERM
ITHERM
Preliminary Information
ATV, RTV
Interrupt
Sources
INT
Interrupt
Status
Register
Interrupt
Status
Register
ITHERM
GPI, THERM,
RMT_FAULT
Interrupt
OR-gate
Interrupt
Control
Mask
Gating
Interrupt
Mask
Register
Interrupt
Status
Register
Mirror
INT_EN
INT
Configuration
Register
INT_RST
INT_CLR
SOFT_RST
Figure 9. INT Output Structure
With Configuration Register bits INT_EN = 1 and INT_CLR
= 0, output pin INT = L, if any of the following bits are set in
the Interrupt Register:
1. ATV: An ambient temperature limit is violated indicating
that the on-chip temperature falls outside the boundaries
established by TALO7-0 and TAHI7-0.
2. GPI: General Purpose Input, GPI is asserted. Polarity
of the GPI pin is determined by the setting of the
GPI_INVT bit in the Configuration Register.
3. RTV: A remote thermal diode temperature limit is violated, indicating that the temperature falls outside the
boundaries established by TRLO7-0 and TRHI7-0.
4. THERM: Temperature exceeds an selected automatic
trip point (PTA7-0, PTR7-0, FTA7-0, or FTR7-0) causing
output THERM = L or the THERM input = L even if the
THERM bit in the Interrupt Register is masked.
14
5.
RMT_FAULT: Remote diode is either open or short circuit.
Output pin INT = Z, clearing the interrupt output, if any of
the following events occur:
1. Interrupt Status Register is read, causing this register to
be cleared to the default state.
2. Configuration Register bit INT_CLR = 1, which is the
default condition following an internal reset.
3. Configuration Register bit INT_EN = 0, which is the
default condition following an internal reset.
Status of the INT_CLR and INT_EN bits does not impact the
contents of the Interrupt Status or the Interrupt Status Mirror
Registers. Reading the Interrupt Status Registers clears only
that register. Reading the Interrupt Status Mirror Register,
clears only that register.
FMS2701
PRODUCT SPECIFICATION
Note that setting the INT output by exceeding a temperature
limit is an edge-driven event. Only when the temperature
actually crosses the limit boundary does INT\ transition LOW.
An example of interrupts caused by a series of temperature,
T transitions across temperature limits is shown in Figure 10.
Temperature limits are fixed for the first series of temperature
excursions. Then, for the second series, following the THI1
violation, the THI limit is raised from THI1 to THI2. If THI
is reprogrammed from a value above T to a value below THI,
then an interrupt is generated. INT is cleared by reading the
Interrupt Status Register (ISRread).
THI2
THI3
THI1
TLO1
ISRread
INT
Figure 10. Profile of Temperature Driven Interrupts
ATV and RTV bits operate in conjunction with the INT
output and Interrupt status Register as follows:
that are stored in the Limit Registers. Out of range TA7-0 and
TR7-0 values set the INT bit in the Interrupt Status Register.
1.
TR7-0 and TA7-0 are also compared with the values in Trip
Point Registers, PTA7-0 and PTR7-0 if these registers have
been loaded or FTA7-0 and FTR7-0, which contain power up
default values. If a trip point is violated, two outputs are
asserted: THERM = L and FAN_SPD = H.
2.
3.
4.
5.
6.
7.
When the temperature exceeds a high limit, the corresponding Interrupt Status Register bit, either ATV or
RTV is set.
Reading the Interrupt Status Register clears ATV and RTV.
Once the high limit has been exceeded, a subsequent
transitions through the high level will not cause an
interrupt, unless:
a) The temperature passes through the low limit.
b) Or, the high temperature limit is changed.
If the high temperature limit is changed from a level
above the temperature to a level below, then the relevant
Interrupt Status Register bit, either ATV or RTV is set.
If the temperature falls below a low limit, the corresponding Interrupt Status Register bit, either ATV or
RTV is set.
Once the low limit has been exceeded, a subsequent
transitions through the low level will not cause an interrupt, unless:
a) The temperature passes through the high limit.
b) Or, the low temperature limit is changed.
If the low temperature limit is changed from a level
below the ambient/remote temperature to a level above,
then the ATV/RTV bit is set.
GPI—General Purpose Input
GPI is a General Purpose Input that can be used to trigger an
interrupt. Configuration Register bit GPI_INVT determines
the polarity of the GPI input. Interrupt Register bit, GPI = H
sets output INT = L if Mask Register bit MSK_GPI = L.
Limit and Trip Point Comparators
Temperature register outputs, TR7-0 and TA7-0 are compared
with the limit values TRHI7-0, TRLO7-0, TAHI7-0 and TALO7-0
Mask Gating
Setting the corresponding bit in the Interrupt Mask Register
can mask any bit in the Interrupt Status Register.
Timing and Control
Timing and Control logic generates a master clock and
orchestrates on-chip timing.
NAND Gate Test
A selectable NAND tree test is provided for Automated Test
Equipment (ATE) board level connectivity testing. NAND
tree test mode is enabled by setting the input pin, FAN_SPD
NTEST_IN = H, while the AUXRST output transitions L to H,
causing the output of a D flip-flop to:
1. Enable the NAND tree output, connecting it to the
ADD/NTEST_OUT pin.
2. Disable the D/A converter output to the FAN/SPD
NTEST_IN.
To perform a NAND tree test, NAND tree pins should be
driven high.
Each pin is toggled in turn to generate an output pattern with
values that can be verified against those shown in Table 4.
15
Preliminary Information
TLO2
T
PRODUCT SPECIFICATION
FMS2701
NTEST_IN
NTEST_EN
INTRST
GPI
SCL
SDA
NTEST_OUT
MR
Preliminary Information
Figure 11. NAND Tree Test Logic
Table 4. NAND Tree Truth Table
GPI
SCL
SDA
MR
ADD/NTESTOUT
0
0
0
0
1
0
0
0
1
0
0
0
1
1
1
0
1
1
1
0
1
1
1
1
1
16
To implement the NAND-TREE test on a PWB, no pins
listed in the tree should be connected directly to power or
ground. Instead, pins should be biased through a low load
resistor with a value of 1.0 k to 100 k to allow ATE to drive
pins high/low.
FMS2701
PRODUCT SPECIFICATION
Equivalent Circuits
VCC3AUX
VDD
DIODE+
Digital
Input
DIODE–
GND
27014B
Figure 12. Equivalent Digital Input Circuit
Figure 14. Equivalent Remote Diode Interface Circuit
V DD
V DD
Digital
Output
p
n
Digital
Output
n
GND
29232
Figure 15. Equivalent Open Drain Output Circuit
GND
27011B
Figure 13. Equivalent Digital and D/A Output Circuit
17
Preliminary Information
GND
29233
PRODUCT SPECIFICATION
FMS2701
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter
Min
Typ
Max
Unit
-0.5
3.3
5.75
V
Power Supply Voltages
VCC3AUX (Measured to GND)
VCC3AUX (Measured to GND)
3.3
V
Digital Inputs
3.3 V logic applied voltage (Measured to GND)2
-0.3
VCC3AUX + 0.3
V
-5.0
5.0
mA
-0.5
VCC3AUX + 0.5
V
-10.0
10.0
mA
3.3 V logic applied voltage (Measured to GND)2
-0.5
VDD3AUX + 0.5
V
Forced current3, 4
-10.0
10.0
mA
1
second
125
°C
3, 4
Forced current
Analog Inputs
Applied Voltage (Measured to GND)2
3, 4
Preliminary Information
Forced current
Digital Outputs
Short circuit duration (single output in HIGH state to ground)
Temperature
Operating, Ambient
-40
Junction
150
°C
Lead Soldering (10 seconds)
300
°C
Vapor Phase Soldering (1 minute)
220
°C
150
°C
±150
V
Storage
Electrostatic
-65
Discharge5
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only
if Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
5. EIAJ test method.
Operating Conditions
Parameter
Min
VCC3AUX
Digital Power Supply Voltage
TA
Ambient Temperature, Still Air
18
Nom
Max
3.3
-40
Units
V
125
°C
FMS2701
PRODUCT SPECIFICATION
Electrical Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
1
2
mA
Power Supply Currents
IVCC3AUX
3.3 volt current
Operating
Standby
0.5
mA
Digital Inputs/Outputs
CI
Input Capacitance
5
Output Capacitance
Input Current, HIGH
IIL
Input Current, LOW
IILR
Input Current, LOW, Master Reset
VIH
Input Voltage
VIL
Input Voltage
IOZH
Output Current, HIGH, open drain
IOH
Output Current, HIGH
IOL
Output Current, LOW
Other / FAN_OFF
VOH
Output Voltage, HIGH
IOH = max.
VOL
Output Voltage, LOW
IOL = max.
-1
10
pF
0.005
µA
0.005
MR = L
pF
+1
µA
200
µA
2.0
V
-0.1
0.8
V
100
µA
-2
mA
3/6
mA
2.4
V
0.4
V
SMBus I/O
VSMIH
Input Voltage, HIGH
VSMIL
Input Voltage, LOW
VSMOL
Output Voltage, LOW
ISMOH
Output Current, HIGH
ISMOL
Output Voltage, LOW
2.1
V
ISMOL = max.
-0.1
0.8
V
0.4
V
-100
µA
4
mA
Diode Inputs
IDH
Source Current, High
80
100
120
µA
IDL
Source Current, Low
8
10
12
µA
Analog Output
VAH
Output Voltage, high
DAC7-0 = 0xFF
2.5
V
VAL
Output Voltage, low
DAC7-0 = 0xOO
0
V
IAH
Output Current , source
2
mA
IAL
Output Current , sink
1
mA
Switching Characteristics
Parameter
Conditions
Min
Typ1
Max
Unit
500
ms
Digital Inputs
tDGPI
Delay, GPI input to register
tTHERM
Delay THERM input to register
tNAND
Delay, NAND input to NTEST_OUT
Reset Generators
tDVA
Delay, VCC3AUX < 2.93 V to AUXRST output
tWVA
Pulsewidth, AUXRST after VCC3AUX > 2.93 V
tDVAR
Delay, VCC3AUX < 2.93 V to RST\ output
ns
140
ns
19
Preliminary Information
CO
IIH
10
PRODUCT SPECIFICATION
FMS2701
Parameter
Conditions
tDAR
Delay, input AUXRST ↓ to RST\ output
Min
Typ1
Max
Unit
ns
tWAR
Pulsewidth, RST after VCC3AUX > 2.93 V or AUXRST ↓
tDR
Delay, MR ↓ to RST = L
tWR
Pulsewidth, MR ↑ to RST = H
tDVR
Delay, VCC3 < 2.93 V to RST output
tDVW
Pulsewidth, RST after VCC3 > 2.93 V
180
500
ms
ns
180
500
ms
ns
140
500
ms
Preliminary Information
SMBus Interface
tDAL
SCL Pulse Width, LOW
4.7
µs
tDAH
SCL Pulse Width, HIGH
4.0
µs
tSTAH
SDA Start Hold Time
4.0
µs
tSTASU
SCL to SDA Setup Time (Stop)
4.0
µs
tSTOSU
SCL to SDA Setup Time (Start)
4.7
µs
tBUFF
SDA Stop Hold Time Setup
4.7
µs
tDSU
SDA to SCL Data Setup Time
250
ns
tDHO
SDA to SCL Data Hold Time
300
ns
Notes:
1. ↓ is a H to L transition.
2. ↑ is a L to H transition.
System Performance Characteristics
Parameter
Conditions
Min
Typ1
Max
Unit
Temperature Channel
Remote Accuracy
Ambient Accuracy
-40°C ≤ TA ≤ +125°C
±5
°C
+60°C ≤ TA ≤ +100°C
±3
°C
0°C ≤ TA ≤ +85°C
±5
°C
20°C ≤ TA ≤ +50°C
±3
°C
A/D Converter
ETUADC
Error, Total Unadjusted
±1
%
ELDADC
Differential Linearity Error
±1
LSB
PSS
Power Supply Sensitivity
±1
%/V
tC
Total Monitoring Cycle Time
Remote and Ambient samples
1.0
1.4
Sec.
D/A Converter Output
ETUDAC
Error, Total Unadjusted
-3
+3
%
ELDDAC
Differential Linearity Error
-1
+1
LSB
VRES
Threshold Voltage
Notes:
1. Values shown in Typ column are typical for Vcc3AUX5 = 3.3V and TA = 25°C.
20
2.93
V
FMS2701
PRODUCT SPECIFICATION
Application Information
Input pin MR and bi-directional pins AUXRST and THERM,
should be biased to VCC3AUX through a pull-up resistor to
prevent spurious triggering.
Since the FMS2701 is intended to be embedded on a Pentium motherboard, external connections cannot be specifically defined. Although in Figure 16, only the schematic
symbol and power supply connections are shown, there are
several guidelines that should be adopted.
If unused, GPI shold be connected to ground through a pulldown resistor, unless the bit: GPI_INV = H, in which case GPI
should be connected to VCC3AUX through a pull-up resistor.
Power is supplied to the VCC3AUX pin which should be decoupled to ground through a local 0.1 µF chip capacitor. To
minimize the effects of noise, locate the FMS2701 over a
ground plane.
The FAN_SPD/INTESTOUT pin should be biased to ground
through a pull-down resistor to ensure that the NAND Test is
not inadvertently enabled.
VCC3 must be maintained at 3.3 volts to avoid tripping the
Main Reset Generator. If VCC3 is not used, connect it to
VCC3AUX.
VCC3AUX
JP1
R1
10K
R2
10K
C1
0.1
R3
10K
U1
R4
10K
MRb
VCC3
2
6
CATHODE
ANODE
9
10
12
GPI
SCL
SDA
FAN_OFF
REMOTE_DIODE–
REMOTE_DIODE+
AUXRST
RST
3
7
FAN_SDP
8
GPI
THERM
INT
ADD
SCL
SDA
1
FMS2701
AUXRSTb
RSTb
FAN_SPD
THERMb
INTb
10K
4
JP2
FAN_OFFb
11
14
GND
13
15
16
MR
VCC3
R5
10K
Figure 16. FMS2701 Reference Schematic
21
Preliminary Information
SMBus pins SCL SDA require pull-up resistors along the bus
which are not necessarily local to the FMS2701. ADD must
be set H, L or open to match the FMS2701 address to the
assigned SMBus address.
Cleanly route the DIODE± analog traces as a pair over the
ground plane. Segregate DIODE± traces from digital traces
and areas of noise. Sensitivity to noise is approiximately
1°C/200µV.
PRODUCT SPECIFICATION
FMS2701
Pin Assignments
16-lead QSOP Package
Inches
Symbol
Min.
Preliminary Information
A
A1
B
C
D
E
e
H
K
L
φ
Max.
Millimeters
Min.
.061
.068
.004
.010
.008
.012
.007
.010
.189
.196
.150
.157
.025 BSC
1.55
1.73
0.10
0.25
0.20
0.30
0.18
0.25
4.80
4.98
3.81
3.99
0.63 BSC
.230
–
.016
0°
5.84
–
0.41
0°
.244
–
.035
8°
16
Notes
Max.
6.19
–
0.89
8°
9
C
E
H
L
1
8
φ
D
K A
B
22
e
A1
FMS2701
PRODUCT SPECIFICATION
Notes
Preliminary Information
23
PRODUCT SPECIFICATION
FMS2701
Ordering Information
Temperature Range
Screening
Package
Package Marking
FMS2701QSC
-40°C to 125°C
Commercial
16 Lead QSOP
2701QS
Preliminary Information
Product Number
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
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DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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