Fairchild FQB4P25 250v p-channel mosfet Datasheet

QFET
TM
FQB4P25 / FQI4P25
250V P-Channel MOSFET
General Description
Features
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology is especially tailored to minimize
on-state
resistance,
provide
superior
switching
performance, and withstand a high energy pulse in the
avalanche and commutation modes. These devices are
well suited for high efficiency switching DC/DC converters.
•
•
•
•
•
•
-4.0A, -250V, RDS(on) = 2.1Ω @VGS = -10 V
Low gate charge ( typical 10 nC)
Low Crss ( typical 10.3 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
S
D
!
●
●
G!
▶ ▲
●
G
S
D2-PAK
G D S
FQB Series
Absolute Maximum Ratings
Symbol
VDSS
ID
I2-PAK
!
FQI Series
D
TC = 25°C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
FQB4P25 / FQI4P25
-250
- Continuous (TC = 100°C)
IDM
Drain Current
VGSS
Gate-Source Voltage
EAS
Single Pulsed Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TA = 25°C) *
dv/dt
PD
- Pulsed
TL
-4.0
A
-2.53
A
-16
A
± 30
V
(Note 2)
280
mJ
(Note 1)
-4.0
A
(Note 1)
7.5
-5.5
3.13
mJ
V/ns
W
75
0.6
-55 to +150
W
W/°C
°C
300
°C
(Note 1)
(Note 3)
Power Dissipation (TC = 25°C)
TJ, TSTG
Units
V
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8” from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
Parameter
Thermal Resistance, Junction-to-Case
Typ
--
Max
1.67
Units
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient *
--
40
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient
--
62.5
°C/W
* When mounted on the minimum pad size recommended (PCB Mount)
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
FQB4P25 / FQI4P25
December 2000
Symbol
TC = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
-250
--
--
V
--
-0.21
--
V/°C
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = -250 µA
∆BVDSS
/
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = -250 µA, Referenced to 25°C
IDSS
IGSSF
IGSSR
VDS = -250 V, VGS = 0 V
--
--
-1
µA
VDS = -200 V, TC = 125°C
--
--
-10
µA
Gate-Body Leakage Current, Forward
VGS = -30 V, VDS = 0 V
--
--
-100
nA
Gate-Body Leakage Current, Reverse
VGS = 30 V, VDS = 0 V
--
--
100
nA
Zero Gate Voltage Drain Current
On Characteristics
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
-3.0
--
-5.0
V
RDS(on)
Static Drain-Source
On-Resistance
VGS = -10 V, ID = -2.0 A
--
1.63
2.1
Ω
gFS
Forward Transconductance
VDS = -40 V, ID = -2.0 A
--
2.3
--
S
--
325
420
pF
--
65
85
pF
--
10
13
pF
--
9.5
30
ns
--
60
130
ns
--
14
40
ns
--
27
65
ns
--
10.3
14
nC
(Note 4)
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = -25 V, VGS = 0 V,
f = 1.0 MHz
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = -125 V, ID = -4.0 A,
RG = 25 Ω
(Note 4, 5)
VDS = -200 V, ID = -4.0 A,
VGS = -10 V
(Note 4, 5)
--
2.7
--
nC
--
5.2
--
nC
A
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
-4.0
ISM
--
--
-16
A
VSD
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = -4.0 A
Drain-Source Diode Forward Voltage
--
--
-5.0
V
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = -4.0 A,
dIF / dt = 100 A/µs
(Note 4)
--
140
--
ns
--
0.64
--
µC
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 28mH, IAS = -4.0A, VDD = -50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ -4.0A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
FQB4P25 / FQI4P25
Electrical Characteristics
FQB4P25 / FQI4P25
Typical Characteristics
VGS
-15.0 V
-10.0 V
-8.0 V
-7.0 V
-6.5 V
-6.0 V
Bottom : -5.5 V
1
Top :
0
10
1
10
-I D , Drain Current [A]
-I D, Drain Current [A]
10
-1
10
※ Notes :
1. 250μs Pulse Test
2. TC = 25℃
25℃
※ Notes :
1. VDS = -50V
2. 250μs Pulse Test
-55℃
-2
10
150℃
0
10
-1
-1
0
10
10
1
10
2
10
4
6
8
10
-VGS , Gate-Source Voltage [V]
-VDS, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
8
1
6
-I DR , Reverse Drain Current [A]
RDS(on) [ Ω ],
Drain-Source On-Resistance
10
VGS = - 10V
VGS = - 20V
4
2
※ Note : TJ = 25℃
0
150℃
※ Notes :
1. VGS = 0V
2. 250μs Pulse Test
25℃
-1
0
3
6
9
10
12
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-ID , Drain Current [A]
-VSD , Source-Drain Voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
700
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
500
Ciss
400
Coss
300
※ Notes :
200
1. VGS = 0 V
2. f = 1 MHz
Crss
100
0
-1
10
VDS = -50V
10
-V GS , Gate-Source Voltage [V]
600
Capacitance [pF]
0
10
VDS = -125V
VDS = -200V
8
6
4
2
※ Note : ID = -4.0 A
0
0
10
1
10
-VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
©2000 Fairchild Semiconductor International
0
2
4
6
8
10
12
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Rev. A2, December 2000
FQB4P25 / FQI4P25
Typical Characteristics
(Continued)
3.0
1.2
RDS(ON) , (Normalized)
Drain-Source On-Resistance
-BV DSS , (Normalized)
Drain-Source Breakdown Voltage
2.5
1.1
1.0
0.9
※ Note :
1. VGS = 0 V
2. ID = -250 μA
0.8
-100
-50
0
50
100
150
2.0
1.5
1.0
※ Notes :
1. VGS = -10 V
2. ID = -2.0 A
0.5
0.0
-100
200
-50
o
0
50
100
150
200
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
4
Operation in This Area
is Limited by R DS(on)
100 µs
1
3
1 ms
-I D, Drain Current [A]
-I D, Drain Current [A]
10
10 ms
DC
0
10
※ Notes :
2
1
o
1. TC = 25 C
o
2. TJ = 150 C
3. Single Pulse
-1
10
0
1
10
0
25
2
10
10
50
150
D = 0 .5
※ N o te s :
1 . Z θ J C ( t ) = 1 . 6 7 ℃ /W M a x .
2 . D u ty F a c t o r , D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C( t )
0 .1
0 .0 5
-1
PDM
0 .0 2
0 .0 1
t1
Z
s in g le p u ls e
10
125
Figure 10. Maximum Drain Current
vs. Case Temperature
0 .2
10
100
0
θ JC
( t) , T h e r m a l R e s p o n s e
Figure 9. Maximum Safe Operating Area
10
75
TC, Case Temperature [℃]
-VDS, Drain-Source Voltage [V]
t2
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
FQB4P25 / FQI4P25
Gate Charge Test Circuit & Waveform
VGS
Same Type
as DUT
50KΩ
Qg
200nF
12V
-10V
300nF
VDS
VGS
Qgs
Qgd
DUT
-3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
RL
t on
VDD
VGS
RG
td(on)
VGS
t off
tr
td(off)
tf
10%
DUT
-10V
VDS
90%
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
1
EAS = ---- L IAS2 -------------------2
BVDSS - VDD
L
VDS
tp
ID
RG
VDD
DUT
-10V
tp
©2000 Fairchild Semiconductor International
VDD
Time
VDS (t)
ID (t)
IAS
BVDSS
Rev. A2, December 2000
FQB4P25 / FQI4P25
Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
VDS
DUT
_
I SD
L
Driver
RG
VGS
VGS
( Driver )
I SD
( DUT )
Compliment of DUT
(N-Channel)
VDD
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
Body Diode Reverse Current
IRM
di/dt
IFM , Body Diode Forward Current
VDS
( DUT )
VSD
Body Diode
Forward Voltage Drop
VDD
Body Diode Recovery dv/dt
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
FQB4P25 / FQI4P25
Package Dimensions
4.50 ±0.20
9.90 ±0.20
+0.10
2.00 ±0.10
2.54 TYP
(0.75)
°
~3
0°
0.80 ±0.10
1.27 ±0.10
2.54 ±0.30
15.30 ±0.30
0.10 ±0.15
2.40 ±0.20
4.90 ±0.20
1.40 ±0.20
9.20 ±0.20
1.30 –0.05
1.20 ±0.20
(0.40)
D2PAK
+0.10
0.50 –0.05
2.54 TYP
9.20 ±0.20
(2XR0.45)
4.90 ±0.20
15.30 ±0.30
10.00 ±0.20
(7.20)
(1.75)
10.00 ±0.20
(8.00)
(4.40)
0.80 ±0.10
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
FQB4P25 / FQI4P25
Package Dimensions
(Continued)
I2PAK
4.50 ±0.20
(0.40)
9.90 ±0.20
+0.10
MAX13.40
9.20 ±0.20
(1.46)
1.20 ±0.20
1.30 –0.05
0.80 ±0.10
2.54 TYP
2.54 TYP
10.08 ±0.20
1.47 ±0.10
MAX 3.00
(0.94)
13.08 ±0.20
)
5°
(4
1.27 ±0.10
+0.10
0.50 –0.05
2.40 ±0.20
10.00 ±0.20
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
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Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
©2000 Fairchild Semiconductor International
Rev. A, January 2000