Fairchild FQP33N10L 100v logic n-channel mosfet Datasheet

FQP33N10L
September 2000
QFET
TM
FQP33N10L
100V LOGIC N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for low voltage applications such as high efficiency
switching DC/DC converters, and DC motor control.
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•
•
•
•
•
•
33A, 100V, RDS(on) = 0.052Ω @VGS = 10 V
Low gate charge ( typical 30 nC)
Low Crss ( typical 70 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
175°C maximum junction temperature rating
D
!
"
G!
! "
"
"
TO-220
G DS
FQP Series
!
S
Absolute Maximum Ratings
Symbol
VDSS
ID
TC = 25°C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
- Continuous (TC = 100°C)
IDM
Drain Current
- Pulsed
(Note 1)
FQP33N10L
100
Units
V
33
A
23
A
132
A
± 20
V
430
mJ
VGSS
Gate-Source Voltage
EAS
Single Pulsed Avalanche Energy
(Note 2)
IAR
Avalanche Current
(Note 1)
33
A
EAR
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TC = 25°C)
(Note 1)
12.7
6.0
127
0.85
-55 to +175
mJ
V/ns
W
W/°C
°C
300
°C
dv/dt
PD
TJ, TSTG
TL
(Note 3)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
Parameter
Thermal Resistance, Junction-to-Case
Typ
--
RθCS
Thermal Resistance, Case-to-Sink
0.5
--
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient
--
62.5
°C/W
©2000 Fairchild Semiconductor International
Max
1.18
Units
°C/W
Rev. A, September 2000
Symbol
TC = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
100
--
--
V
--
0.09
--
V/°C
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
∆BVDSS
/
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = 250 µA, Referenced to 25°C
VDS = 100 V, VGS = 0 V
--
--
1
µA
VDS = 80 V, TC = 150°C
--
--
10
µA
Gate-Body Leakage Current, Forward
VGS = 20 V, VDS = 0 V
--
--
100
nA
Gate-Body Leakage Current, Reverse
VGS = -20 V, VDS = 0 V
--
--
-100
nA
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
1.0
--
2.0
V
RDS(on)
Static Drain-Source
On-Resistance
VGS = 10 V, ID = 16.5 A
VGS = 5 V, ID = 16.5 A
--
0.039
0.043
0.052
0.055
Ω
gFS
Forward Transconductance
VDS = 30 V, ID = 16.5 A
--
27
--
S
--
1250
1630
pF
--
305
400
pF
--
70
90
pF
IDSS
IGSSF
IGSSR
Zero Gate Voltage Drain Current
On Characteristics
VGS(th)
(Note 4)
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = 50 V, ID = 33 A,
RG = 25 Ω
(Note 4, 5)
VDS = 80 V, ID = 33 A,
VGS = 5 V
(Note 4, 5)
--
17
45
ns
--
470
950
ns
--
70
150
ns
--
120
250
ns
--
30
40
nC
--
4.7
--
nC
--
16
--
nC
Drain-Source Diode Characteristics and Maximum Ratings
(Note 6)
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
33
A
ISM
--
--
132
A
VSD
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = 33 A
Drain-Source Diode Forward Voltage
--
--
1.5
V
trr
Reverse Recovery Time
--
90
--
ns
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = 33 A,
dIF / dt = 100 A/µs
--
0.26
--
µC
(Note 4)
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 0.59mH, IAS = 33A, VDD = 25V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 33A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Rev. A, September 2000
FQP33N10L
Electrical Characteristics
10
Top :
ID, Drain Current [A]
ID, Drain Current [A]
2
VGS
10.0 V
8.0 V
6.0 V
5.0 V
4.5 V
4.0 V
3.5 V
Bottom : 3.0 V
2
10
1
10
1
10
175℃
25℃
0
10
-55℃
※ Notes :
1. VDS = 30V
2. 250μs Pulse Test
※ Notes :
1. 250μs Pulse Test
2. TC = 25℃
0
-1
10
-1
10
0
10
1
10
0
10
2
4
6
8
10
VGS, Gate-Source Voltage [V]
VDS, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
0.20
2
10
0.16
IDR , Reverse Drain Current [A]
RDS(ON) [Ω ],
Drain-Source On-Resistance
VGS = 5V
0.12
VGS = 10V
0.08
0.04
1
10
0
10
175℃
25℃
※ Notes :
1. VGS = 0V
2. 250μs Pulse Test
※ Note : TJ = 25℃
-1
0.00
0
30
60
90
10
120
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
ID, Drain Current [A]
VSD, Source-Drain voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
3600
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
2400
※ Notes :
1. VGS = 0 V
2. f = 1 MHz
Ciss
1800
Coss
1200
Crss
600
10
VGS, Gate-Source Voltage [V]
3000
Capacitance [pF]
FQP33N10L
Typical Characteristics
VDS = 50V
8
VDS = 80V
6
4
2
※ Note : ID = 33A
0
-1
10
0
0
10
1
10
VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
©2000 Fairchild Semiconductor International
0
10
20
30
40
50
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Rev. A, September 2000
FQP33N10L
Typical Characteristics
(Continued)
1.2
3.0
RDS(ON) , (Normalized)
Drain-Source On-Resistance
BV DSS , (Normalized)
Drain-Source Breakdown Voltage
2.5
1.1
1.0
※ Notes :
1. VGS = 0 V
2. ID = 250 μA
0.9
0.8
-100
-50
0
50
100
150
2.0
1.5
1.0
※ Notes :
1. VGS = 10 V
2. ID = 16.5 A
0.5
0.0
-100
200
-50
0
50
100
150
200
o
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
35
Operation in This Area
is Limited by R DS(on)
2
25
100 µ s
ID , Drain Current [A]
ID , Drain Current [A]
10
30
1 ms
10 ms
10
1
DC
※ Notes :
20
15
10
o
1. TC = 25 C
10
10
5
o
0
2. TJ = 175 C
3. Single Pulse
0
10
1
0
25
2
10
50
VDS, Drain-Source Voltage [V]
100
125
150
175
Figure 10. Maximum Drain Current
vs. Case Temperature
0
D = 0 .5
※ N otes :
1 . Z θ J C ( t ) = 1 . 1 8 ℃ /W M a x .
2 . D u t y F a c t o r , D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C( t )
0 .2
0 .1
10
-1
0 .0 5
PDM
0 .0 2
θ JC
(t), T h e rm a l R e s p o n s e
Figure 9. Maximum Safe Operating Area
10
75
TC, Case Temperature [℃]
t1
0 .0 1
t2
Z
s in g le p u ls e
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t1 , S q u a r e W a v e P u ls e D u r a tio n [s e c ]
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. A, September 2000
FQP33N10L
Gate Charge Test Circuit & Waveform
VGS
Same Type
as DUT
50KΩ
Qg
200nF
12V
5V
300nF
VDS
VGS
Qgs
Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
RL
VDS
90%
VDD
VGS
RG
VGS
DUT
5V
10%
td(on)
tr
td(off)
t on
tf
t off
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
1
EAS = ---- L IAS2 -------------------2
BVDSS - VDD
L
VDS
BVDSS
IAS
ID
RG
VDD
DUT
10V
tp
©2000 Fairchild Semiconductor International
ID (t)
VDS (t)
VDD
tp
Time
Rev. A, September 2000
FQP33N10L
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
I SD
L
Driver
RG
VGS
VGS
( Driver )
Same Type
as DUT
VDD
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
IFM , Body Diode Forward Current
I SD
( DUT )
di/dt
IRM
Body Diode Reverse Current
VDS
( DUT )
Body Diode Recovery dv/dt
VSD
VDD
Body Diode
Forward Voltage Drop
©2000 Fairchild Semiconductor International
Rev. A, September 2000
TO-220
4.50 ±0.20
2.80 ±0.10
(3.00)
+0.10
1.30 –0.05
18.95MAX.
(3.70)
ø3.60 ±0.10
15.90 ±0.20
1.30 ±0.10
(8.70)
(1.46)
9.20 ±0.20
(1.70)
9.90 ±0.20
1.27 ±0.10
1.52 ±0.10
0.80 ±0.10
2.54TYP
[2.54 ±0.20]
10.08 ±0.30
(1.00)
)
(45°
13.08 ±0.20
FQP33N10L
Package Dimensions
+0.10
0.50 –0.05
2.40 ±0.20
2.54TYP
[2.54 ±0.20]
10.00 ±0.20
©2000 Fairchild Semiconductor International
Rev. A, September 2000
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Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
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First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
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The datasheet is printed for reference information only.
©2000 Fairchild Semiconductor International
Rev. F1