Fairchild FQP70N10 100v n-channel mosfet Datasheet

FQP70N10
August 2000
QFET
TM
FQP70N10
100V N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for low voltage applications such as audio amplifier,
high efficiency switching DC/DC converters, and DC motor
control.
•
•
•
•
•
•
•
57A, 100V, RDS(on) = 0.023Ω @VGS = 10 V
Low gate charge ( typical 85 nC)
Low Crss ( typical 150 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
175°C maximum junction temperature rating
D
!
"
G!
Symbol
VDSS
ID
!
FQP Series
S
TC = 25°C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
- Continuous (TC = 100°C)
IDM
Drain Current
"
"
TO-220
G DS
Absolute Maximum Ratings
! "
- Pulsed
FQP70N10
100
Units
V
57
A
40.3
A
(Note 1)
228
A
VGSS
Gate-Source Voltage
± 25
V
EAS
Single Pulsed Avalanche Energy
(Note 2)
1300
mJ
IAR
Avalanche Current
(Note 1)
57
A
EAR
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TC = 25°C)
(Note 1)
16
6.0
160
1.06
-55 to +175
mJ
V/ns
W
W/°C
°C
300
°C
dv/dt
PD
TJ, TSTG
TL
(Note 3)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
Parameter
Thermal Resistance, Junction-to-Case
Typ
--
RθCS
Thermal Resistance, Case-to-Sink
0.5
--
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient
--
62.5
°C/W
©2000 Fairchild Semiconductor International
Max
0.94
Units
°C/W
Rev. B, August 2000
Symbol
TC = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
100
--
--
V
--
0.1
--
V/°C
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
∆BVDSS
/
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = 250 µA, Referenced to 25°C
IDSS
IGSSF
IGSSR
VDS = 100 V, VGS = 0 V
--
--
1
µA
VDS = 80 V, TC = 150°C
--
--
10
µA
Gate-Body Leakage Current, Forward
VGS = 25 V, VDS = 0 V
--
--
100
nA
Gate-Body Leakage Current, Reverse
VGS = -25 V, VDS = 0 V
--
--
-100
nA
Zero Gate Voltage Drain Current
On Characteristics
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
2.0
--
4.0
V
RDS(on)
Static Drain-Source
On-Resistance
VGS = 10 V, ID = 28.5 A
--
0.019
0.023
Ω
gFS
Forward Transconductance
VDS = 40 V, ID = 28.5 A
--
45
--
S
--
2500
3300
pF
--
720
940
pF
--
150
200
pF
(Note 4)
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = 50 V, ID = 70 A,
RG = 25 Ω
(Note 4, 5)
VDS = 80 V, ID = 70 A,
VGS = 10 V
(Note 4, 5)
--
30
70
ns
--
470
950
ns
--
130
270
ns
--
160
330
ns
--
85
110
nC
--
16
--
nC
--
42
--
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
57
A
ISM
--
--
228
A
VSD
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = 57 A
Drain-Source Diode Forward Voltage
--
--
1.5
V
trr
Reverse Recovery Time
--
110
--
ns
Qrr
Reverse Recovery Charge
--
430
--
nC
VGS = 0 V, IS = 70 A,
dIF / dt = 100 A/µs
(Note 4)
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 0.6mH, IAS = 57A, VDD = 25V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 70A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Rev. B, August 2000
FQP70N10
Electrical Characteristics
VGS
15.0 V
10.0 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom : 4.5 V
Top :
ID, Drain Current [A]
2
10
ID , Drain Current [A]
2
10
1
10
1
10
175℃
25℃
0
10
-55℃
※ Notes :
1. 250μs Pulse Test
2. TC = 25℃
※ Notes :
1. VDS = 40V
2. 250μs Pulse Test
-1
0
10
-1
10
0
10
1
10
2
10
4
6
8
10
VGS , Gate-Source Voltage [V]
VDS, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
80
2
64
IDR , Reverse Drain Current [A]
RDS(ON) [mΩ ],
Drain-Source On-Resistance
10
VGS = 10V
48
VGS = 20V
32
16
1
10
0
10
※ Notes :
1. VGS = 0V
2. 250μs Pulse Test
25℃
175℃
※ Note : TJ = 25℃
-1
0
0
60
120
180
240
300
10
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
ID , Drain Current [A]
VSD , Source-Drain Voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
7000
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
5000
Ciss
4000
※ Notes :
1. VGS = 0 V
2. f = 1 MHz
Coss
3000
2000
Crss
1000
10
VGS, Gate-Source Voltage [V]
6000
Capacitance [pF]
FQP70N10
Typical Characteristics
VDS = 50V
VDS = 80V
8
6
4
2
※ Note : ID = 70A
0
-1
10
0
0
10
1
10
VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
©2000 Fairchild Semiconductor International
0
10
20
30
40
50
60
70
80
90
100
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Rev. B, August 2000
FQP70N10
Typical Characteristics
(Continued)
3.0
1.2
RDS(ON) , (Normalized)
Drain-Source On-Resistance
BV DSS , (Normalized)
Drain-Source Breakdown Voltage
2.5
1.1
1.0
※ Notes :
1. VGS = 0 V
2. ID = 250 μA
0.9
0.8
-100
-50
0
50
100
150
2.0
1.5
1.0
※ Notes :
1. VGS = 10 V
2. ID = 35 A
0.5
0.0
-100
200
-50
o
0
50
100
150
200
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
60
3
10
Operation in This Area
is Limited by R DS(on)
50
100 µs
ID, Drain Current [A]
10
10 µs
ID, Drain Current [A]
2
1 ms
10 ms
DC
1
10
0
10
40
30
20
※ Notes :
10
o
1. TC = 25 C
o
2. TJ = 175 C
3. Single Pulse
-1
10
0
1
10
0
25
2
10
10
50
100
125
150
175
Figure 10. Maximum Drain Current
vs. Case Temperature
0
D = 0 .5
※ N o te s :
1 . Z θ J C ( t) = 0 .9 4 ℃ / W M a x .
2 . D u ty F a c to r , D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C ( t)
0 .2
10
0 .1
-1
0 .0 5
PDM
0 .0 2
0 .0 1
θ JC
( t) , T h e r m a l R e s p o n s e
Figure 9. Maximum Safe Operating Area
10
75
TC, Case Temperature [℃]
VDS, Drain-Source Voltage [V]
t1
Z
s i n g le p u ls e
10
t2
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. B, August 2000
FQP70N10
Gate Charge Test Circuit & Waveform
VGS
Same Type
as DUT
50KΩ
Qg
200nF
12V
10V
300nF
VDS
VGS
Qgs
Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
RL
VDS
90%
VDD
VGS
RG
VGS
DUT
10V
10%
td(on)
tr
td(off)
t on
tf
t off
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
1
EAS = ---- L IAS2 -------------------2
BVDSS - VDD
L
VDS
BVDSS
IAS
ID
RG
VDD
DUT
10V
tp
©2000 Fairchild Semiconductor International
ID (t)
VDS (t)
VDD
tp
Time
Rev. B, August 2000
FQP70N10
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
I SD
L
Driver
RG
VGS
VGS
( Driver )
Same Type
as DUT
VDD
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
IFM , Body Diode Forward Current
I SD
( DUT )
di/dt
IRM
Body Diode Reverse Current
VDS
( DUT )
Body Diode Recovery dv/dt
VSD
VDD
Body Diode
Forward Voltage Drop
©2000 Fairchild Semiconductor International
Rev. B, August 2000
TO-220
4.50 ±0.20
2.80 ±0.10
(3.00)
+0.10
1.30 –0.05
18.95MAX.
(3.70)
ø3.60 ±0.10
15.90 ±0.20
1.30 ±0.10
(8.70)
(1.46)
9.20 ±0.20
(1.70)
9.90 ±0.20
1.27 ±0.10
1.52 ±0.10
0.80 ±0.10
2.54TYP
[2.54 ±0.20]
10.08 ±0.30
(1.00)
)
(45°
13.08 ±0.20
FQP70N10
Package Dimensions
+0.10
0.50 –0.05
2.40 ±0.20
2.54TYP
[2.54 ±0.20]
10.00 ±0.20
©2000 Fairchild Semiconductor International
Rev. B, August 2000
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Advance Information
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This datasheet contains the design specifications for
product development. Specifications may change in
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The datasheet is printed for reference information only.
©2000 Fairchild Semiconductor International
Rev. F1