G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) Features : Description : ∗ ∗ ∗ ∗ ∗ The GLT44016 is a 262,144 x 16 bit high-performance CMOS dynamic random access memory. The GLT44016 offers Fast Page mode with Extended Data Output, and has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. The GLT44016 has symmetric address and accepts 512-cycle refresh in 8ms interval. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 512 x 16 bits within a page, with cycle times as short as 10ns. The GLT44016 is best suited for graphics, and DSP applications requiring high performance memories. 262,144 words by 16 bits organization. Fast access time and cycle time. Dual CAS Input. Low power dissipation. Read-Modify-Write, RAS -Only Refresh, CAS -Before- RAS Refresh, Hidden Refresh and Test Mode Capability. 512 refresh cycles per 8ms. Available in 40-Pin 400 mil SOJ and 40/44 Pin TSOP(II) ∗ Single 5.0V±10% Power Supply. ∗ All inputs and Outputs are TTL compatible. ∗ Extended Data-Out(EDO) Page Mode operation. ∗ ∗ HIGH PERFORMANCE 25 28 30 35 40 50 Max. RAS Access Time, (tRAC) 25 ns 28 ns 30 ns 35 ns 40 ns 50 ns Max. Column Address Access Time, (tCAA) 13 ns 13 ns 16 ns 18 ns 20 ns 25 ns Min. Extended Data Out Page Mode Cycle Time, (tPC) 10 ns 10 ns 12 ns 13 ns 15 ns 20 ns Min. Read/Write Cycle Time, (tRC) 45 ns 45 ns 60 ns 65 ns 70 ns 85 ns Max. CAS Access Time (tCAC) 8 ns 8 ns 10 ns 11 ns 12 ns 14 ns G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -1- G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) Pin Configuration : GLT44016 SOJ Top View TSOP(Type II) Top View Pin Descriptions: Name A0 - A8 Function RAS Address Inputs Row Address Strobe UCAS Column Address Strobe/Upper Byte Control LCAS Column Address Strobe/Lower Byte Control WE Write Enable OE Output Enable DQ1 - DQ16 VCC VSS NC Data Inputs / Outputs +5V Power Supply Ground No Connection G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -2- G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) Absolute Maximum Ratings* Capacitance* TA=25°C, VCC=5V±10%, VSS=0V Operating Temperature, TA (ambient) Symbol .......................................-0°C to +70°C Storage Temperature(plastic)....-55°C to +150°C Voltage Relative to VSS...............-1.0V to + 7.0V Short Circuit Output Current......................50mA Power Dissipation......................................1.0W *Note:Operation above Absolute Maximum Ratings can abversely affect device reliability. Parameter Max. Unit CIN1 Address Input 5 pF CIN2 RAS , LCAS , UCAS , WE , OE 7 pF COUT Data Input/Output 7 pF *Note: Capacitance is sampled and not 100% tested Electrical Specifications l l l CAS means UCAS and LCAS . All voltages are referenced to GND. After power up, wait more than 100µs and then, execute eight CAS -before- RAS or RAS -only refresh cycles as dummy cycles to initialize internal circuit. Block Diagram : OE WE UCAS LCAS RAS CLOCK GENERATOR RAS CAS CLOCK GENERATOR WE CLOCK GENERATOR OE CLOCK GENERATOR V CC V SS Data I/O BUS COLUMN DECODERS REFRESH COUNTER SENSE AMPLIFIERS I/O BUFFER Y 0 - Y8 512 × 16 9 A0 A1 A7 . . ADDRESS BUFFERS AND PREDECODERS A8 ROW DECODERS X 0 - x8 MEMORY ARRAY 512 G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -3- I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) Truth Table: GLT44016 Function ADDRESS DQs RAS CASL CASH WE OE Stanby H H→X H→X X X Read: Word L L L H L ROW/COL Data Out Read: Lower Byte L L H H L Read: Upper Byte L H L H L Write: Word(Early Write) Write: Lower Byte (Early) L L L L X ROW/COL Lower Byte,Data-Out Upper Byte,High-Z ROW/COL Lower Byte,High-Z Upper Byte,Data-Out ROW/COL Data-In L L H L X Write: Upper Byte (Early) L H L L X Read Write L L L H→L L→H EDO-Page- 1st Cycle L H→L H→L H L Mode Read 2nd Cycle L H→L H→L H L EDO-Page- 1st Cycle L H→L H→L L X Mode Write 2nd Cycle L H→L H→L L X EDO-Page- 1st Cycle L H→L H→L H→L L→H L H→L H→L H→L L→H Read L→H→L L L H L ROW/COL Data-Out Write L→H→L L L L L X ROW/COL Data-In H H X X H→L L L X X Notes High-Z ROW/COL Lower Byte,Data-In Upper Byte,High-Z ROW/COL Lower Byte,High-Z Upper Byte,Data-In ROW/COL Data-Out,Data-In ROW/COL Data-Out COL Data-Out ROW/COL Data-In COL Data-In ROW/COL Data-Out,Data-In 1,2 1 1 2 2 1,2 Mode ReadWrite Hidden Refresh 2nd Cycle RAS -Only Refresh CBR Refresh COL ROW Data-Out,Data-In 1 2,3 High-Z High-Z Notes: 1. These READ cycles may also be BYTE READ cycles (either UCAS or LCAS active). 2. These WRITE cycles may also be BYTE READ cycles (either UCAS or LCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active ( UCAS or LCAS ). G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -4- 1,2 4 G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) DC and Operating Characteristics (1-2) TA = 0°C to 70°C, VCC=5V±10%, VSS=0V, unless otherwise specified. Sym. Parameter ILI Input Leakage Current (any input pin) ILO Output Leakage Current (for High-Z State) Operating Current, Random READ/WRITE ICC1 ICC2 ICC3 Standby Current,(TTL) Refresh Current, RAS -Only Test Conditions 0V ≤ VIN ≤ 5.5V (All other pins not under test=0V) 0V ≤ Vout ≤ 5.5V Output is disabled (Hiz) ICC5 Operating Current, EDO Page Mode Refresh Current, CAS Before RAS ICC6 Standby Current, (CMOS) Min. LCAS at VIH RAS at VIL, UCAS , LCAS address cycling:tPC=tPC(min.) RAS , UCAS , LCAS address cycling: tRC=tRC (min.) Max. Unit Notes +10 µA -10 +10 µA 270 270 250 210 190 170 RAS , UCAS , LCAS at VIH other inputs ≥VSS RAS cycling, UCAS , Typ -10 tRAC = 25ns tRAC = 28ns tRAC = 30ns tRAC = 35ns tRAC = 40ns tRAC = 50ns tRC = tRC (min.) tRC = tRC (min.) ICC4 Access Time 4 270 270 250 210 190 170 270 270 250 210 190 170 270 270 250 210 190 170 tRAC = 25ns tRAC = 28ns tRAC = 30ns tRAC = 35ns tRAC = 40ns tRAC = 50ns tRAC = 25ns tRAC = 28ns tRAC = 30ns tRAC = 35ns tRAC = 40ns tRAC = 50ns tRAC = 25ns tRAC = 28ns tRAC = 30ns tRAC = 35ns tRAC = 40ns tRAC = 50ns RAS ≥VCC-0.2V, mA 1,2 mA mA 2 mA 1,2 mA 1 2 mA +0.8 VCC+1 0.4 V V V V UCAS ≥VCC-0.2V, LCAS ≥VCC-0.2V, All other inputs VSS VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage -1 2.4 IOL = 4.2mA IOH = -5.0mA 2.4 3 3 Notes: 1.ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output open. 2.ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle in random Read/Write and EDO Fast Page Mode. 3.Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1.0V for a period not to exceed 20ns. All AC parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC. G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -5- G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) AC Characteristics TA = 0°C to 70°C , VCC = 5 V ± 10%, VIH/VIL = 2.4/0.8 V, VOH/VOL = 2.0/0.8V An initial pause of 100 µs and 8 CAS -before- RAS or RAS -only refresh cycles are required after power-up. 25 28 30 35 40 50 Parameter Symbol Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes Read or Write Cycle Time tRC 45 45 60 65 70 85 ns Read Modify Write Cycle Time tRWC 67 67 79 86 91 106 ns tRP 15 15 25 25 25 30 ns tRAS 25 50 100k ns RAS Precharge Time RAS Pulse Width Access Time from RAS Access Time from CAS Access Time from Column Address CAS to Output Low-Z CAS to Output High-Z RAS Hold Time RAS Hold Time Referenced to OE CAS Hold Time CAS Pulse Width RAS to CAS Delay Time RAS to Column Address Delay Time 100k 28 100k 30 100k 35 100k 40 100k tRAC 25 28 30 35 40 50 ns tCAC 8 8 10 11 12 14 ns 1,5,10 tAA 13 13 16 18 20 25 ns tCLZ 0 0 0 5 3 5 0 0 7 3 0 8 3 0 8 3 1,2,3 1,5,6 ns tCEZ 0 8 ns tRSH 7 7 7 8 8 8 ns tROH 4 4 7 8 8 8 ns tCSH 25 25 25 30 35 42 ns tCAS 4 4 4.5 5 6 8 ns tRCD 10 17 10 17 10 20 11 24 12 28 13 36 ns tRAD 8 12 8 12 8 14 9 17 10 20 11 25 ns 7 CAS to RAS Precharge Time Row Address Set-Up Time tCRP 5 5 5 5 5 5 ns tASR 0 0 0 0 0 0 ns Row Address Hold Time tRAH 4 4 6 7 8 9 ns Column Address Set-Up Time tASC 0 0 0 0 0 0 ns Column Address Hold Time tCAH 4 4 5 6 6 7 ns Column Address to RAS Lead Time tRAL 13 13 16 18 20 25 ns tAR 19 19 25 30 34 35 ns tRCS 0 0 0 0 0 0 ns tRCH 0 0 0 0 0 0 ns 4 tRRH 0 0 0 0 0 0 ns 4 tWCS 0 0 0 0 0 0 ns 8,9 Write Command Hold Time tWCH 4 4 5 6 6 6 ns Write Command Pulse Width tWP 4 4 5 6 6 6 ns tRWL 7 7 7 8 8 8 ns tCWL 5 5 6 7 7 7 ns Column Address Hold Time Referenced to RAS Read Command Set-Up Time Read Command Hold Time Referenced to CAS Read Command Hold Time Referenced to RAS Write Command Set-Up Time Write Command to RAS Lead Time Write Command to CAS Lead Time G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -6- G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) AC Characteristics 25 28 30 35 40 50 Parameter Symbol Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes Data Set-Up Time tDS 0 Data Hold Time tDH 4 tDHR Data Hold Time Referenced to RAS RAS to WE E Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to CAS Precharge Time Access Time from CAS Precharge EDO Page Mode Cycle Time EDO Page Mode Read-Modify-Write Cycle Time CAS Precharge Time (EDO Page Mode) RAS Pulse Width (EDO Page Mode Only) Access Time from OE OE to Data Delay Time OE to Output High-Z OE Command Hold Time Data Output Hold after CAS low RAS to Output High-Z WE to Output High-Z OE to CAS Hold Time CAS Hold Time to OE OE Precharge Time CAS Set-Up Time for CAS -before- RAS Cycle CAS Hold Time for CAS -before- RAS Cycle Transition Time Refresh Period 0 0 0 0 ns 4 7 8 8 8 ns 19 19 27 32 36 37 ns tRWD 36 36 43 49 54 64 ns tCWD 19 19 21 23 24 26 ns tAWD 24 24 27 30 32 37 ns tRPC 0 0 0 0 0 0 ns tCPA 15 15 tPC 10 10 12 13 15 20 ns tPRWC 35 35 39 43 45 50 ns tCP 3 3 4.5 5 6 8 ns tRASP 25 50 100k ns tOEA 0 100k 0 28 8 0 18 100k 30 8 35 10 40 11 12 tOEH 5 5 6 6 7 7 ns tDOH 4 4 5 5 5 5 ns tREZ 3 7 3 7 3 7 3 8 3 8 3 8 ns tWEZ 3 10 3 10 3 10 3 10 3 10 3 12 ns tOCH 8 8 8 8 8 8 ns tCHO 8 8 8 8 8 8 ns tOEP 8 8 8 8 8 8 ns tCSR 5 5 10 10 10 10 ns tCHR 6 6 7 8 8 10 ns tREF 1.5 50 1.5 8 50 8 3 1.5 7 50 8 3 1.5 8 50 8 3 1.5 8 ns 3 7 8 14 ns tOEZ 3 8 100k 27 5 7 7 100k 22 tOED tT 5 100K 20 8 50 8 0 2 ns 8 50 ns 8 ms G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -7- ns G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) Notes: 1. Measure with a load equivalent to one TTL inputs and 50 pF. 2. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), access time will be tAA dominant. 3. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRCD (max.), access time will be controlled by tCAC. 4. Either tRRH or tRCH must be satisfied for a Read Cycle. 5. Access time is determined by the longest of tCAA, tCAC and tCPA. 6. Assumes that tRAD ≥ tRAD (max.). 7. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 8. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 9. tWCS (min.) must be satisfied in an Early Write Cycle. 10. tDS and tDH are referenced to the latter occurrence of CAS of WE . tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 1.5 ns. G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -8- G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) Read Cycle tRC tRAS tRP VIH- RAS VIL- tCSH tCRP tRCD tCRP tRSH VIH- CAS tCAS VIL- tRAD tASR V IH- Address V IL- tRAL tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tAR tRCH tRRH tRCS VIH- WE VIL- tCEZ tAA tOEZ VIH- OE tOEA VIL- tCAC tCLZ tRAC DQ VOHDATA-OUT VOLDon't Care Early Write Cycle NOTE : DOUT = Open tRC tRP tRAS VIH- RAS VIL- tCSH tCRP tRCD tRSH VIH- tCRP tCAS CAS VIL- VIH- Address VIL- tASR tRAH tRAD tRAL tCAH tASC ROW ADDRESS COLUMN ADDRESS tCWL tRWL tAR VIH- tWCS tWCR tWCH tWP tDS tDH WE VIL- VIH- OE VIL- tDHR VIH- DQ VIL- DATA - IN Don't Care G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -9- G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) Late Write Cycle ( OE Controlled Write) NOTE : DOUT = Open tRC tRP tRAS VIH- RAS VIL- tCSH tCRP tRCD CAS tCRP tRSH VIH- tCAS VIL- VIH- Address VIL- tRAD tASC tASR tRAH tRAL tCAH ROW ADDRESS COLUMN ADDRESS tCWL tRWL tRCS tWP VIH- WE VIL- OE VIH- tOEH tOED VIL- tDS VIH- DQ tDH COLUMN ADDRESS VIL- Don't Care Read - Modify - Write Cycle tRC tRP RAS tRAS VIHVIL- tCRP CAS tRCD tCRP tRSH VIH- tCAS VIL- tCSH tASR Address VIHVIL- tRAH ROW ADDR. tRAD tCAH tASC COLUMN ADDRESS tAWD tCWD WE OE VIH- tWP VIL- VIH- tOEA VIL- tCLZ tAA DQ tRWL tCWL VI/OHVI/OL- tRAC tCAC tOED tOEZ VALID DATA-OUT tDS tDH VALID DATA-IN Don't Care G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 10 - G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) Fast Page Read Cycle tRASP tRP VIH- RAS VIL- tPC tCRP tRCD tCAS tCP tPC tCAS tCP tRSH tCAS VIH- CAS VIL- tRAD tCSH tASR VIH- Address VIL- tRAH tASC ROW ADDR. tCAH tASC COLUMN ADDRESS tRCS tRCH tCAH tCAH tASC COLUMN ADDRESS COLUMN ADDRESS tRCS tRCS tRRH tRCH VIH- WE VIL- tCAC tCAC tOEA tOEA VIH- OE VIL- tAA tRAC tCLZ DQ tAA tOFF tCLZ tOEZ VIH- tOFF tOEZ tAA tOFF tCLZ tOEZ VILVALID DATA-UOT Fast Page Write Cycle VALID DATA-UOT VALID DATA-UOT tRASP t RP VIH- RAS tRHCP VIL- tPC tCRP tRCD tCAS tPC tCP tCAS tRSH tCP tCAS VIH- CAS VIL- tRAD tASR Address VIHVIL- tRAH tASC ROW ADDR. tCSH tCAH COLUMN ADDRESS tWCS VIH- WE Don't Care NOTE : DOUT = Open tASC tCAH COLUMN ADDRESS tWCH tWCS tWP tWP tWCH tCAH tASC COLUMN ADDRESS tWCS tWCH tWP VIL- tCWL tCWL tCWL tRWL VIH- OE VIL- tDS VIH- DQ VIL- tDH VALID DATA-IN tDS VALID DATA-IN tDS tDS tDS VALID DATA-IN Don't Care G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 11 - G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) Fast Page Mode Late Write Cycle tRASP t RP VIH- RAS tRHCP VIL- tCSH tCRP CAS tRCD t PC tCAS tCP tCAS tCP tRSH tCRP tCAS VIHVIL- tRAD tASR Address VIH- tCAH tASC tRAH COLUMN ADDRESS ROW ADDR. VIL- VIH- COLUMN ADDRESS tCWL tRCS tRAL tCAH tASC COLUMN ADDRESS tCWL tRCS WE tCAH tASC tCWL tRWL tRCS tWP tWP tWP tOEH tOEH tOEH VIL- VIH- OE VIL- tOED tDS Hi-Z VIH- tDH Hi-Z VALID DATA-IN DQ VIL- tOED tDS tOED tDS tDH VALID DATA-IN Hi-Z tDH VALID DATA-IN Don't Care Fast Page Read - Modify - Write Cycle tRASP VIH- RAS tRP tCSH VIL- tRCD tCAS tRSH tCAS tCP tCRP VIH- CAS VIL- tASR VIH- Address VIL- tRAD tRAH tASC ROW ADDR. tPRWC tRAL tCAH tCAH tASC COL. ADDR. COL. ADDR. tRWL tCWL tCWL tRCS VIH- WE tCWD tWP tCWD VIL- tAWD tCPWD tOEH tRWD VIH- OE tOEA tRAC tOEA tDH VIL- tCAC tAA tWP tAWD tCAC tAA tOED tOEZ tDS tOED tOEZ tDH VALID DATA-OUT VALID DATA-IN tDS VI/OH- DQ VI/OL- tCLZ tCLZ VALID DATA-OUT VALID DATA-IN Don't Care G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 12 - G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) CAS Before RAS Refresh Cycle tRC tRC tRP tRAS tRAS tRP V IH- RAS V IL- tCSR CAS tCHR tRPC tCSR tCHR tRPC tCRP V IHV IL- RAS -Only Refresh Cycle tRC tRC tRP tRAS RAS tRAS tRP VIHVIL- tCRP CAS tRPC tCRP VIHVIL- tASR tRAH tASR tRAH VIH- Address ROW ROW VIL- Hidden Refresh Cycle ( Read ) tRC tRC tRP tRAS RAS tRAS tRP VIHVIL- tRCD tCRP tRSH tCHR VIH- CAS VIL- tRAD tASR Address VIHVIL- tRAL tCAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRCS tWHR VIH- WE tAA VIL- tOEA VIH- OE VIL- tCAC tRAC DQ VIH- tCLZ OPEN tOEZ tOFF DATA-OUT VIL- Don't Care G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 13 - G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) Hidden Refresh Cycle ( Write ) NOTE : DOUT =Open tRC tRC tRP tRAS RAS tRAS tRP VIHVIL- tCRP tRCD tRSH tCHR VIH- CAS VIL- tRAD tASC Address VIHVIL- tCAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWCS tWCH tWP VIH- WE VIL- VIH- OE VIL- tDS DQ tDH VIHDATA-IN VIL- Don't Care G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 14 - G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) CAS - Before RAS Refresh Counter Test Cycle tRP tRAS VIH- RAS VIL- tCSR tRSH tCAS tCPT tCHR VIHCAS VIL- tRAL tASC AddressVIH- COLUMN ADDRESS VIL- Read Cycle tCAH tWRP tAA tCAC tWRH VIHWE VIL- tRRH tRCH tRCS tOEA VIH- OE VIL- tOEZ tCLZ VOH- DQ VOL- Write Cycle tCEZ VALID DATA-OUT tWRP tWRH tRWL tCWL tWCH tWCS VIHWE VIL- tWP VIH- OE VIL- tDS VIHDQ VIL- OPEN tDH VALID DATA-IN Read-Modify-Write tRCS tAWD tCWD tCWL tRWL tWP VIH- WE VIL- tCAC tAA tOEA VIH- OE VIL- tOED tCLZ tOEZ tDH tDS VI/OH- DQ VI/OL- VALID DATA-OUT VALID DATA-IN Don't Care G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 15 - G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) Ordering Information Part Number SPEED POWER FEATURE PACKAGE GLT44016-25J4 GLT44016-28J4 GLT44016-30J4 GLT44016-35J4 GLT44016-40J4 GLT44016-50J4 GLT44016-25TC GLT44016-28TC GLT44016-30TC GLT44016-35TC GLT44016-40TC GLT44016-50TC 25ns 28ns 30ns 35ns 40ns 50ns 25ns 28ns 30ns 35ns 40ns 50ns Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO 40L 400mil SOJ 40L 400mil SOJ 40L 400mil SOJ 40L 400mil SOJ 40L 400mil SOJ 40L 400mil SOJ 44L 400mil TSOP 44L 400mil TSOP 44L 400mil TSOP 44L 400mil TSOP 44L 400mil TSOP 44L 400mil TSOP Parts Numbers (Top Mark) Definition : GLT 4 40 4 : DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM -SRAM 064 : 8K 256 : 256K 512 : 512K 100 : 1M -DRAM 10 : 1M(C/EDO)* 11 : 1M(C/FPM)* 12 : 1M(H/EDO)* 13 : 1M(H/FPM)* 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) *See note 16 - 40 J4 CONFIG. 04 : x04 08 : x08 16 : x16 32 : x32 VOLTAGE Blank : 5V L : 3.3V M : Mix Voltage SPEED -SRAM 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -DRAM 25 : 25ns 30 : 30ns 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns PACKAGE T : PDIP(300mil) TS : TSOP(Type I) TC : TSOP(Type ll) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP Note : CÙCDROM , HÙHDD. Example : 1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type. 2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type. G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 16 - G -LINK GLT44016 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug, 2000(Rev.3.1) Package Information 40/44 Lead Thin Small Outline Package SOJ 40/44 Lead Thin Small Outline Package TSOP(Type II) G-Link Technology Corporation G-Link Technology Corporation,Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 17 -