ETC1 GM2120 Xga/sxga lcd controller Datasheet

Genesis Microchip Publication
PRELIMINARY DATA SHEET
gm5110/gm5110-H
gm5120/gm5120-H
XGA/SXGA LCD Controller
*** Genesis Microchip Confidential ***
NOTE: Sections in this data sheet that mention HDCP apply only to the HDCP-enabled chip
versions (gm5110-H and gm5120-H). All other sections apply to all chip versions (gm5110,
gm5110-H, gm5120, and gm5120-H).
Publication number: C5110-DAT-01C
Publication date: June 2002
Genesis Microchip Inc.
2150 Gold Street, Alviso, P.O. Box 2150, CA USA 95002 Tel: (408) 262-6599 Fax: (408) 262-6365
165 Commerce Valley Dr. West, Thornhill, ON Canada L3T 7V8 Tel: (905) 889-5400 Fax: (905) 889-5422
1096, 12thA Main, Hal II Stage, Indira Nagar, Bangalore-560 008, India, Tel: (91)-80-526-3878, Fax: (91)-80-529-6245
4F, No. 24, Ln 123, Sec 6, Min-Chuan E. Rd., Taipei, Taiwan, ROC Tel: 886-2-2791-0118 Fax: 886-2-2791-0196
143-37 Hyundai Tower, #902, Samsung-dong, Kangnam-gu, Seoul, Korea 135-090 Tel 82-2-553-5693 Fax 82-2-552-4942
Rm2614-2618 Shenzhen Office Tower, 6007 Shennan Blvd, 518040, Shenzhen, Guandong, P.R.C., Tel (0755)386-0101, Fax (0755)386-7874
2-9-5 Higashigotanda, Shinagawa-ku, Tokyo, 141-0022, Japan, Tel 81-3-5798-2758, Fax 81-3-5798-2759
www.genesis-microchip.com / [email protected]
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
Revision History
Document
C5110-DAT-01A
C5110-DAT-01B
Description
• Initial release
• Added note on Front Cover regarding HDCP enabled versions.
• Added section 4.12 - Energy Spectrum Management (ESM).
• In section 4.15 clarified that ROM_ADDR[15:0] have internal 60KΩ pull-down
resistor.
• Changes to Table 21– DC Characteristics:
– Renamed parameters θJA_XGA, θJA_SXGA, θJC_XGA and θJC_SXGA to θJA_5110, θJA_5120,
θJC_5110 and θJC_5120 and revised their values.
– Added note (4) regarding the maximum case temperature.
• Changes to Table 22– Maximum Speed of Operation:
– Renamed parameters P5110 and P5120 and revised their values.
– Renamed parameters I5110, I5110_2.5_VDD, etc.
– Added note (6).
• Removed the clock speed column from section 6 - Ordering Information and
added the ordering information for gm5110-H and gm5120-H.
Date
Aug 2001
Oct 2001
D5110-DAT-01C
•
June
2002
Pins 143 ~ 146: changed xxx_SDDS or xxxx_SDDS to xxx_DDDS or xxxx_DDDS
respectively
•
Pins 138 ~ 141: changed xxx_DDDS or xxxx_DDDS to xxx_SDDS or xxxx_SDDS
respectively
•
Pins 147 ~ 148: changed xxx_DPLL to xxx_RPLL
Related documents
Chip documents
C5110-PBR-01
C5120-PBR-01
C5115-APB-01
C5115-APB-02
C5115-TOP-01
C5115-DSL-01
C5115-DSR-02
Preliminary Product Brief gm5110
Preliminary Product Brief gm5120
gm5115 Product Family On-chip Microcontroller (OCM) Firmware Configurations
gm5115 Product Family Support for Standard RGB (sRGB)
gm5115 Theory of Operation
gm5115 Register Listing
gm5115 Input Processing Programming Guide
Reference design documents
B0108-GUD-01
5110RD1 Reference Design Users Guide
B0108-SCH-01
5110RD1 Reference Design Schematics
B0108-BOM-01
5110RD1 Reference Design Bill of Materials
Firmware / tools documents
B0092-SWT-01
gm5115 Product Family Firmware Theory of Operation for Full Custom Configuration
B0092-SUG-01
gm5115 Product Family Firmware User Guide for Full-Custom
B0092-PRN-01
gm5115 Product Family Firmware Release Notes for Full-Custom
B0108-SUG-01
gm5115 Product Family Firmware User Guide for Standalone
B0108-PRN-01
gm5115 Product Family Firmware Release Notes for Standalone
S0006-GUD-01
G-Probe Debug Software User Guide
S0014-GUD-01
G-Wizard Software User Guide
Trademarks: RealColor, Real Recovery, and Ultra-Reliable DVI are trademarks of Genesis Microchip Inc.
© Copyright 2001, Genesis Microchip Inc. All Rights Reserved.
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
Genesis Microchip Inc. reserves the right to change or modify the information contained herein without notice.
Please obtain the most recent revision of this document. Genesis Microchip Inc. makes no warranty for the use of
its products and bears no responsibility for any errors or omissions that may appear in this document.
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
Table Of Contents
1. Overview ............................................................................................................................................ 1
1.1 gm5110/20 System Design Example ........................................................................................... 1
1.2 gm5110/20 Features..................................................................................................................... 2
2. gm5110/20 Pinout .............................................................................................................................. 3
3. gm5110/20 Pin List ............................................................................................................................ 4
4. Functional Description ..................................................................................................................... 10
4.1 Clock Generation ....................................................................................................................... 10
4.1.1 Using the Internal Oscillator with External Crystal............................................................ 11
4.1.2 Using an External Clock Oscillator .................................................................................... 13
4.1.3 Clock Synthesis................................................................................................................... 14
4.2 Hardware Reset .......................................................................................................................... 16
4.3 Analog to Digital Converter....................................................................................................... 16
4.3.1 ADC Pin Connection .......................................................................................................... 17
4.3.2 ADC Characteristics ........................................................................................................... 17
4.3.3 Clock Recovery Circuit ...................................................................................................... 18
4.3.4 Sampling Phase Adjustment ............................................................................................... 19
4.3.5 ADC Capture Window........................................................................................................ 19
4.4 DVI Receiver Block................................................................................................................... 20
4.4.1 DVI Receiver Characteristics ............................................................................................. 20
4.4.2 DVI Capture Window ......................................................................................................... 21
4.4.3 HDCP (High-Bandwidth Digital Content Protection) ........................................................ 21
4.5 Test Pattern Generator (TPG) .................................................................................................... 21
4.6 Input Format Measurement........................................................................................................ 22
4.6.1 HSYNC / VSYNC Delay.................................................................................................... 22
4.6.2 Horizontal and Vertical Measurement ................................................................................ 23
4.6.3 Format Change Detection ................................................................................................... 23
4.6.4 Watchdog ............................................................................................................................ 24
4.6.5 Internal Odd/Even Field Detection (For Interlaced Inputs to ADC Only).......................... 24
4.6.6 Input Pixel Measurement .................................................................................................... 24
4.6.7 Image Phase Measurement ................................................................................................. 24
4.6.8 Image Boundary Detection ................................................................................................. 25
4.6.9 Image Auto Balance............................................................................................................ 25
4.7 RealColorTM Digital Color Controls .......................................................................................... 25
4.7.1 RealColor™ Flesh tone Adjustment ................................................................................... 25
4.7.2 Color Standardization and sRGB Support .......................................................................... 26
4.8 High-Quality Scaling ................................................................................................................. 26
4.8.1 Variable Zoom Scaling ....................................................................................................... 26
June 2002
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C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
4.8.2 Horizontal and Vertical Shrink ........................................................................................... 26
4.8.3 Moiré Cancellation ............................................................................................................. 27
4.9 Bypass Options .......................................................................................................................... 27
4.10 Gamma LUT ............................................................................................................................ 27
4.11 Display Output Interface.......................................................................................................... 27
4.11.1 Display Synchronization................................................................................................... 27
4.11.2 Programming the Display Timing .................................................................................... 28
4.11.3 Panel Power Sequencing (PPWR, PBIAS) ....................................................................... 29
4.11.4 Output Dithering ............................................................................................................... 30
4.12 Energy Spectrum Management (ESM) .................................................................................... 30
4.13 OSD.......................................................................................................................................... 30
4.13.1 On-Chip OSD SRAM ....................................................................................................... 31
4.13.2 Color Look-up Table (LUT) ............................................................................................. 32
4.14 On-Chip Microcontroller (OCM)............................................................................................. 32
4.14.1 Standalone Configuration ................................................................................................. 33
4.14.2 Full-Custom Configuration............................................................................................... 34
4.14.3 General Purpose Inputs and Outputs (GPIO’s)................................................................. 35
4.15 Bootstrap Configuration Pins................................................................................................... 35
4.16 Host Interface........................................................................................................................... 36
4.16.1 Host Interface Command Format...................................................................................... 37
4.16.2 2-wire Serial Protocol ....................................................................................................... 37
4.17 Miscellaneous Functions.......................................................................................................... 39
4.17.1 Low Power State............................................................................................................... 39
4.17.2 Pulse Width Modulation (PWM) Back Light Control ...................................................... 39
5. Electrical Specifications ................................................................................................................... 40
5.1 Preliminary DC Characteristics ................................................................................................. 40
5.2 Preliminary AC Characteristics ................................................................................................. 41
6. Ordering Information ....................................................................................................................... 43
7. Mechanical Specifications................................................................................................................ 44
June 2002
iv
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
List Of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
June 2002
Analog Input Port...................................................................................................4
DVI Input Port .......................................................................................................5
RCLK PLL Pins .....................................................................................................5
Analog HSYNC/VSYNC Inputs............................................................................6
System Interface and GPIO Signals.......................................................................6
Display Output Port ...............................................................................................7
Parallel ROM Interface Port ..................................................................................8
Reserved Pins.........................................................................................................8
Power Pins for ADC Sampling Clock DDS ..........................................................9
Power Pins for Display Clock DDS.......................................................................9
I/O Power and Ground Pins ...................................................................................9
Core Power and Ground Pins.................................................................................9
TCLK Specification .............................................................................................14
Pin Connection for RGB Input with HSYNC/VSYNC .......................................17
ADC Characteristics ............................................................................................18
DVI Receiver Characteristics ..............................................................................20
gm5110/20 GPIOs and Alternate Functions ........................................................35
Bootstrap Signals .................................................................................................36
Instruction Byte Map ...........................................................................................37
Absolute Maximum Ratings ................................................................................40
DC Characteristics ...............................................................................................41
Maximum Speed of Operation.............................................................................42
Display Timing and DCLK Adjustments ............................................................42
2-Wire Host Interface Port Timing ......................................................................42
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C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
List Of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
June 2002
gm5110/20 System Design Example .....................................................................1
gm5110/20 Pin Out Diagram .................................................................................3
gm5110/20 Functional Block Diagram................................................................10
Using the Internal Oscillator with External Crystal.............................................11
Internal Oscillator Output ....................................................................................12
Sources of Parasitic Capacitance .........................................................................13
Using an External Single-ended Clock Oscillator ...............................................14
Internally Synthesized Clocks..............................................................................15
On-chip Clock Domains ......................................................................................16
Example ADC Signal Terminations.....................................................................17
gm5110/20 Clock Recovery.................................................................................18
ADC Capture Window .........................................................................................19
Some of gm5110/20 built-in test patterns ............................................................21
HSYNC Delay......................................................................................................22
Active Data Crosses HSYNC Boundary ..............................................................23
ODD/EVEN Field Detection................................................................................24
RealColorTM Digital Color Controls.....................................................................25
Display Windows and Timing..............................................................................28
Single Pixel Width Display Data..........................................................................29
Double Pixel Wide Display Data .........................................................................29
Panel Power Sequencing ......................................................................................29
OSD Cell Map ......................................................................................................31
OCM Full-Custom and Standalone Configurations .............................................32
Programming OCM in Standalone Configuration................................................33
Programming the OCM in Full-Custom Configuration .......................................34
Factory Calibration and Test Environment ..........................................................36
2-Wire Protocol Data Transfer .............................................................................38
2-Wire Write Operations (0x1x and 0x2x)...........................................................38
2-Wire Read Operation (0x9x and 0xAx) ............................................................39
gm5110/gm5120 208-pin PQFP Mechanical Drawing .......................................44
vi
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
1. OVERVIEW
The gm5110/20 is a graphics processing IC for Liquid Crystal Display (LCD) monitors at
XGA/SXGA resolution. It provides all key IC functions required for the highest quality LCD
monitors. On-chip functions include a high-speed triple-ADC and PLL, Ultra-Reliable DVI
TM
receiver, a high quality zoom and shrink scaling engine, an on-screen display (OSD)
controller, digital color controls and an on-chip microcontroller (OCM). With this level of
integration, the gm5110/20 devices simplify and reduce the cost of LCD monitors while
maintaining a high-degree of flexibility and quality.
1.1 gm5110/20 System Design Example
Figure 1 below shows a typical dual interface LCD monitor system based on the gm5110/20.
Designs based on the gm5110/20 have reduced system cost, simplified hardware and
firmware design and increased reliability because only a minimal number of components are
required in the system.
Analog
RGB
LCD Module
gm5110 /
gm5120
DVI
Back-light
NVRAM
Figure 1.
June 2002
EEPROM
(optional)
gm5110/20 System Design Example
1
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
1.2 gm5110/20 Features
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Zoom (from VGA) and shrink (from UXGA) scaling
Integrated 8-bit triple-channel ADC / PLL
Integrated Ultra-Reliable DVI 1.0-compliant receiver
High-Bandwidth Digital Content Protection (HDCP)
Embedded microcontroller with parallel ROM interface
On-chip versatile OSD engine
All system clocks synthesized from a single external crystal
Programmable gamma correction (CLUT)
RealColor controls provide sRGB compliance
PWM back light intensity control
5-Volt tolerant inputs
Low EMI and power saving features
•
High-Quality Advanced Scaling
•
•
•
•
•
Auto-Configuration / Auto-Detection
•
•
•
•
•
•
On-chip RAM for downloadable menus
1, 2 and 4-bit per pixel character cells
Horizontal and vertical stretch of OSD menus
Blinking, transparency and blending
On-chip Microcontroller
•
•
•
•
•
Requires no external micro-controller
External parallel ROM interface allows firmware customization
with little additional cost
21 general-purpose inputs/outputs (GPIO's) available for
managing system devices (keypad, back-light, NVRAM, etc)
Industry-standard firmware embedded on-chip, requires no
external ROM (configuration settings stored in NVRAM)
Programmable Output Format
•
•
•
Single / double wide up to XGA 75Hz output for gm5110
and up to SXGA 75Hz output for gm5120
Pin swap, odd / even swap and red / blue group swap of
RGB outputs for flexibility in board layout
Support for 8 or 6-bit panels (with high-quality dithering)
•
Highly Integrated System-on-a-Chip
Reduces Component Count for Highly Cost
Effective Solution
•
Stand-alone operation requires no external
ROM and no firmware development for Fast
Time to Market
Input format detection
Phase and image positioning
Ultra-Reliable DVI Compliant Input Port
•
•
Supports up to 162MHz (SXGA 75Hz / UXGA 60Hz)
On-chip high-performance PLLs
(only a single reference crystal required)
On-chip OSD Controller
•
•
•
•
Analog RGB Input Port
•
•
•
Fully programmable zoom ratios
High-quality shrink capability from UXGA resolution
Real Recovery function provides full color recovery
image for refresh rates higher than those supported by
the LCD panel
Moire cancellation
•
Operating up to 165 MHz (up to UXGA 60Hz)
Direct connect to all DVI compliant digital transmitters
High-bandwidth Digital Content Protection (HDCP)
• Pin and register compatible Family of Products:
- gm5110/gm5120 Dual-Interface XGA/SXGA
- gm3110/gm3120 Digital-Interface XGA/SXGA
- gm2110/gm2120 Analog-Interface XGA/SXGA
RealColor Technology
•
•
•
•
Digital brightness and contrast controls
TV color controls including hue and saturation controls
Flesh-tone adjustment
Full color matrix allows end-users to experience the
same colors as viewed on CRTs and other displays
(e.g. sRGB compliance)
June 2002
2
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
2. GM5110/20 PINOUT
gm5110 and gm5120 are pin-compatible. These devices are available in a 208-pin Plastic
Quad Flat Pack (PQFP) package. Figure 2 provides the pin locations for all signals.
gm5110/20 Pin Out Diagram
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
GND1_ADC
VDD1_ADC_2.5
GND2_ADC
VDD2_ADC_2.5
TCLK
XTAL
AVDD_RPLL
AVSS_RPLL
VDD_RPLL
VSS_RPLL
AVDD_DDDS
AVSS_DDDS
VDD_DDDS
VSS_DDDS
N/C
AVDD_SDDS
AVSS_SDDS
VDD_SDDS
VSS_SDDS
HSYNC
VSYNC
CVSS
CVDD_2.5
CVSS
Reserved
Reserved
RVSS
RVDD
N/C
N/C
GP07
GP06
GP05
GP04
GP03
GP02
GP01
GP00
DCLK
DVS
DHS
DEN
PBIAS
PPWR
RVSS
RVDD
PD47/OB7
PD46/OB6
PD45/OB5
PD44/OB4
PD43/OB3
PD42/OB2
RVDD
RVSS
PD0/ER0
PD1/ER1
PD2/ER2
PD3/ER3
PD4/ER4
PD5/ER5
PD6/ER6
PD7/ER7
PD8/EG0
PD9/EG1
PD10/EG2
PD11/EG3
RVDD
RVSS
PD12/EG4
PD13/EG5
PD14/EG6
PD15/EG7
PD16/EB0
PD17/EB1
PD18/EB2
PD19/EB3
PD20/EB4
PD21/EB5
PD22/EB6
PD23/EB7
RVDD
RVSS
PD24/OR0
PD25/OR1
PD26/OR2
PD27/OR3
PD28/OR4
CVDD_2.5
CVSS
PD29/OR5
PD30/OR6
PD31/OR7
PD32/OG0
PD33/OG1
PD34/OG2
PD35/OG3
RVDD
RVSS
PD36/OG4
PD37/OG5
PD38/OG6
PD39/OG7
PD40/OB0
PD41/OB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
gm5110/20
GPIO17
RVDD
RVSS
GPIO21/IRQn
RESETn
GPIO14/DDC_SCL
GPIO15/DDC_SDA
ROM_ADDR15
ROM_ADDR14
ROM_ADDR13
ROM_ADDR12
ROM_ADDR11
ROM_ADDR10
ROM_ADDR9
ROM_ADDR8
ROM_ADDR7
ROM_ADDR6
ROM_ADDR5
ROM_ADDR4
RVDD
RVSS
ROM_ADDR3
ROM_ADDR2
ROM_ADDR1
ROM_ADDR0
CVDD_2.5
CVSS
GPI7/ROM_DATA7
GPI6/ROM_DATA6
GPI5/ROM_DATA5
GPI4/ROM_DATA4
GPI3/ROM_DATA3
GPI2/ROM_DATA2
GPI1/ROM_DATA1
GPI0/ROM_DATA0
ROM_Oen
RVDD
RVSS
GPIO8/IRQINn
GPIO0/PWM0
GPIO1/PWM1
GPIO2/PWM2
GPIO3/TIMER1
GPIO4/UART_D1
GPIO5/UART_D0
GPIO6
GPIO7
GPIO9
GPIO10
GPIO11/ROM_WEn
GPIO12/NVRAM_SDA
GPIO13/NVRAM_SCL
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
GPIO18
GPIO19
GPIO20
GPIO16/HFSn
GPIO22/HCLK
CVDD_2.5
CVSS
CLKOUT
N/C
VDD_RXPLL_2.5
AGND_RXPLL
AGND_RXC
AVDD_RXC
RXCRXC+
AVDD_RX0
RX0RX0+
AGND_RX0
GND_RX0
VDD_RX0_2.5
AVDD_RX1
RX1RX1+
AGND_RX1
GND_RX1
VDD_RX1_2.5
AVDD_RX2
RX2RX2+
AGND_RX2
GND_RX2
VDD_RX2_2.5
AGND_IMB
REXT
AVDD_IMB
AVDD_RED
RED+
REDAGND_RED
AVDD_GREEN
GREEN+
GREENAGND_GREEN
AVDD_BLUE
BLUE+
BLUEAGND_BLUE
AVDD_ADC
ADC_TEST
AGND_ADC
SGND_ADC
Figure 2.
June 2002
3
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
3. GM5110/20 PIN LIST
I/O Legend: A = Analog, I = Input, O = Output, P = Power, G= Ground
Table 1.
Pin Name
No.
I/O
Description
Analog power (3.3V) for the red channel. Must be bypassed with decoupling capacitor to
AGND_RED pin on system board (as close as possible to the pin).
Positive analog input for Red channel.
Negative analog input for Red channel.
Analog ground for the red channel.
Must be directly connected to the analog system ground plane.
Analog power (3.3V) for the green channel. Must be bypassed with decoupling capacitor to
AGND_GREEN pin on system board (as close as possible to the pin).
Positive analog input for Green channel.
Negative analog input for Green channel.
Analog ground for the green channel.
Must be directly connected to the analog system ground plane.
Analog power (3.3V) for the blue channel. Must be bypassed with decoupling capacitor to
AGND_BLUE pin on system board (as close as possible to the pin).
Positive analog input for Blue channel.
Negative analog input for Blue channel.
Analog ground for the blue channel.
Must be directly connected to the analog system ground plane.
Analog power (3.3V) for ADC analog blocks that are shared by all three channels. Includes
band gap reference, master biasing and full-scale adjust. Must be bypassed with
decoupling capacitor to AGND_ADC pin on system board (as close as possible to the pin).
Analog test output for ADC Do not connect.
Analog ground for ADC analog blocks that are shared by all three channels. Includes band
gap reference, master biasing and full-scale adjust.
Must be directly connected to analog system ground plane.
Dedicated pad for substrate guard ring that protects the ADC reference system.
Must be directly connected to the analog system ground plane.
Digital GND for ADC clocking circuit.
Must be directly connected to the digital system ground plane
Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to
GND1_ADC pin on system board (as close as possible to the pin).
Digital GND for ADC clocking circuit.
Must be directly connected to the digital system ground plane.
Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to
GND2_ADC pin on system board (as close as possible to the pin).
AVDD_RED
172
AP
RED+
REDAGND_RED
171
170
169
AI
AI
AG
AVDD_GREEN
168
AP
GREEN+
GREENAGND_GREEN
167
166
165
AI
AI
AG
AVDD_BLUE
164
AP
BLUE+
BLUEAGND_BLUE
163
162
161
AI
AI
AG
AVDD_ADC
160
AP
ADC_TEST
AGND_ADC
159
158
AO
AG
SGND_ADC
157
AG
GND1_ADC
156
G
VDD1_ADC_2.5
155
P
GND2_ADC
154
G
VDD2_ADC_2.5
153
P
June 2002
Analog Input Port
4
C5110-DAT-01C
*** Genesis Microchip Confidential ***
Table 2.
Pin Name
173
AP
REXT
174
AI
AGND_IMB
175
AG
VDD_RX2_2.5
176
P
GND_RX2
177
G
AGND_RX2
178
AG
RX2+
RX2AVDD_RX2
179
180
181
AI
AI
AP
VDD_RX1_2.5
182
P
GND_RX1
183
G
AGND_RX1
184
AG
RX1+
RX1AVDD_RX1
185
186
187
AI
AI
AP
VDD_RX0_2.5
188
P
GND_RX0
189
G
AGND_RX0
190
AG
RX0+
RX0AVDD_RX0
191
192
193
AI
AI
AP
RXC+
RXCAVDD_RXC
194
195
196
AI
AI
AP
AGND_RXC
197
AG
GND_RXPLL
198
G
VDD_RXPLL_2.5
199
AP
CLKOUT
201
AO
Analog VDD (3.3V) for internal biasing circuits.
Must be bypassed with decoupling capacitors (as close as possible to the pin).
External reference resistor.
An external 1Kohm (1%) resistor should be connected from this pin to AVDD_IMB pin.
Analog GND for internal biasing circuits.
Must be connected directly to the ground plane.
VDD (2.5V) for DVI input pair 2 logic circuits. Must be bypassed with decoupling capacitor to
GND_RX2 pin (as close as possible to the pin).
GND for DVI input pair 2 logic circuits.
Must be connected directly to the ground plane.
Analog GND for DVI input pair 2 input buffer.
Must be connected directly to the analog ground plane.
DVI input pair 2
DVI input pair 2
Analog VDD (3.3V) for DVI input pair 2 input buffer. Must be bypassed with decoupling
capacitor to AGND_RX2 pin (as close as possible to the pin).
VDD (2.5V) for DVI input pair 1 logic circuits. Must be bypassed with decoupling capacitor to
GND_RX1 pin (as close as possible to the pin).
GND for DVI input pair 1 input buffer.
Must be connected directly to the analog ground plane.
Analog GND for DVI input pair 1 input buffer.
Must be connected directly to the analog ground plane.
DVI input pair 1
DVI input pair 1
Analog VDD (3.3V) for DVI input pair 1 input buffer. Must be bypassed with decoupling
capacitor to AGND_RX1 pin (as close as possible to the pin).
VDD (2.5V) for DVI input pair 0 logic circuits. Must be bypassed with decoupling capacitor to
GND_RX0 pin (as close as possible to the pin).
GND for DVI input pair 0 logic circuits.
Must be connected directly to the ground plane.
Analog GND for DVI input pair 0 input buffer.
Must be connected directly to the analog ground plane.
DVI input pair 0
DVI input pair 0
Analog VDD (3.3V) for DVI input pair 0 input buffer. Must be bypassed with decoupling
capacitor to AGND_RX0 pin (as close as possible to the pin).
DVI input clock pair
DVI input clock pair
Analog VDD (3.3V) for DVI input clock pair input buffer. Must be bypassed with 100pF
capacitor to AGND_RXC pin (as close as possible to the pin).
Analog GND for DVI input clock pair input buffer.
Must be connected directly to the analog ground plane.
Digital GND for the DVI receiver internal PLL.
Must be connected directly to the system ground plane.
Analog VDD (2.5V) for the DVI receiver internal PLL. Must be bypassed with a decoupling
capacitor to AGND_RXPLL pin (as close as possible to the pin).
For test purposes only. Do not connect.
Table 3.
RCLK PLL Pins
No I/O Description
AVDD_RPLL
150
AP
AVSS_RPLL
149
AG
TCLK
152
AI
XTAL
VDD_RPLL
VSS_RPLL
151
148
147
AO
P
G
June 2002
DVI Input Port
No I/O Description
AVDD_IMB
Pin Name
gm5110/20 Preliminary Data Sheet
Analog power for the Reference DDS PLL. Connect to 3.3V supply. Must be bypassed with a
0.1uF capacitor to pin AVSS_RPLL (as close to the pin as possible).
Analog ground for the Reference DDS PLL.
Must be directly connected to the analog system ground plane.
Reference clock (TCLK) from the 14.3MHz crystal oscillator, or from single-ended
CMOS/TTL clock oscillator (refer to Figure 7). This is a 5V-tolerant input.
Crystal oscillator output.
Digital power for RCLK PLL. Connect to 3.3V supply.
Digital ground for RCLK PLL.
5
C5110-DAT-01C
*** Genesis Microchip Confidential ***
Table 4.
Pin Name
137
I
VSYNC
136
I
ADC input horizontal sync input.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
ADC input vertical sync input.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
Table 5.
System Interface and GPIO Signals
No I/O Description
RESETn
5
I
GPIO0/PWM0
40
IO
GPIO1/PWM1
41
IO
GPIO2/PWM2
42
IO
GPIO3/TIMER1
43
IO
GPIO4/UART_DI
44
IO
GPIO5/UART_DO
45
IO
GPIO6
46
IO
GPIO7
47
IO
GPIO8/IRQINn
39
IO
GPIO9
48
IO
GPIO10
49
IO
GPIO11/ROM_WEn
50
IO
GPIO12/NVRAM_SDA
GPIO13/NVRAM_SCL
51
52
IO
IO
GPIO14/DDC_SCL
GPIO15/DDC_SDA
GPIO16/HFSn
6
7
205
I
IO
IO
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21/IRQn
1
208
207
206
4
IO
IO
IO
IO
IO
GPIO22/HCLK
204
IO
GPO0
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
119
120
121
122
123
124
125
126
O
O
O
O
O
O
O
O
June 2002
Analog HSYNC/VSYNC Inputs
No I/O Description
HSYNC
Pin Name
gm5110/20 Preliminary Data Sheet
Active-low hardware reset signal. The reset signal must be held low for at least 1µS.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
General-purpose input/output signal or PWM0. Open drain option via register setting.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
General-purpose input/output signal or PWM1. Open drain option via register setting.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
General-purpose input/output signal or PWM2. Open drain option via register setting.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
General-purpose input/output signal. Open drain option via register setting. This pin is also
connected to Timer 1 clock input of the OCM.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
General-purpose input/output signal. Open drain option via register setting. This pin is also
connected to the OCM UART data input signal by programming an OCM register.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
General-purpose input/output signal. Open drain option via register setting. This pin is also
connected to the OCM UART data output signal by programming an OCM register.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
General-purpose input/output signal.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
General-purpose input/output signal.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
General-purpose input/output signal. This is also active-low interrupt input to OCM and is
directly wired to OCM int_0n.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
General-purpose input/output signal. Open drain option via register setting.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
General-purpose input/output signal. Open drain option via register setting.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
General-purpose input/output or PROM write enable signal. Open drain option via register
setting. [Bi-directional Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
General-purpose input/output or master 2-wire serial interface to NVRAM in standalone
operation. Open drain option via register setting. [Bi-directional Input, Schmitt trigger
(400mV typical hysteresis), 5V-tolerant]
DDC Interface for DVI-HDCP communication. This is 5V-tolerant SCL pin.
DDC Interface for DVI-HDCP communication. This is 5V-tolerant SDA pin.
General-purpose input/output signal when host interface is disabled, or host interface
framing signal.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), slew rate limited, 5V tolerant]
General-purpose input/output signal.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
General-purpose input/output signal when host port is disabled, or active-low and opendrain interrupt output pin.
[Bi-directional, 5V-tolerant]
General-purpose input/output signal when host interface is disabled, or host clock signal.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
General-purpose output signals.
6
C5110-DAT-01C
*** Genesis Microchip Confidential ***
Table 6.
Pin Name
Display Output Port
No I/O Description
DCLK
118
O
DVS
117
O
DHS
116
O
DEN
115
O
PBIAS
114
O
PPWR
113
O
PD47
PD46
PD45
PD44
PD43
PD42
PD41
PD40
PD39
PD38
PD37
PD36
PD35
PD34
PD33
PD32
PD31
PD30
PD29
PD28
PD27
PD26
PD25
PD24
PD23
PD22
PD21
PD20
PD19
PD18
PD17
PD16
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
110
109
108
107
106
105
104
103
102
101
100
99
96
95
94
93
92
91
90
87
86
85
84
83
80
79
78
77
76
75
74
73
72
71
70
69
66
65
64
63
62
61
60
59
58
57
56
55
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
June 2002
gm5110/20 Preliminary Data Sheet
Panel output clock.
[Tri-state output, Programmable Drive]
Panel Vertical Sync.
[Tri-state output, Programmable Drive]
Panel Horizontal Sync.
[Tri-state output, Programmable Drive]
Panel Display Enable, which frames the output background.
[Tri-state output, Programmable Drive]
Panel Bias Control (back light enable)
[Tri-state output, Programmable Drive]
Panel Power Control
[Tri-state output, Programmable Drive]
Panel output data.
[Tri-state output, Programmable Drive]
7
C5110-DAT-01C
*** Genesis Microchip Confidential ***
Table 7.
Pin Name
ROM_ADDR15
ROM_ADDR14
ROM_ADDR13
ROM_ADDR12
ROM_ADDR11
ROM_ADDR10
ROM_ADDR9
ROM_ADDR8
ROM_ADDR7
ROM_ADDR6
ROM_ADDR5
ROM_ADDR4
ROM_ADDR3
ROM_ADDR2
ROM_ADDR1
ROM_ADDR0
GPI7/ROM_DATA7
GPI6/ROM_DATA6
GPI5/ROM_DATA5
GPI4/ROM_DATA4
GPI3/ROM_DATA3
GPI2/ROM_DATA2
GPI1/ROM_DATA1
GPI0/ROM_DATA0
ROM_OEn
Parallel ROM Interface Port
No I/O Description
8
9
10
11
12
13
14
15
16
17
18
19
22
23
24
25
28
29
30
31
32
33
34
35
36
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
I
I
I
I
I
I
I
O
ROM address output. These pins also serve as 5V-tolerant bootstrap inputs on power up.
5V-tolerant external PROM data input, or general-purpose input in standalone operation.
External PROM data Output Enable
Table 8.
Pin Name
N/C
N/C
Reserved
Reserved
N/C
N/C
June 2002
gm5110/20 Preliminary Data Sheet
Reserved Pins
No I/O Description
127
128
131
132
142
200
O
O
I
I
O
O
No connect.
No connect.
Tie to GND.
Tie to GND.
No connect.
No connect.
8
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
Note that VDD pins having "_2.5" in their names should be connected to 2.5V power supplies. All
other VDD pins should be connected to 3.3V power supplies.
Table 9.
Pin Name
Power Pins for ADC Sampling Clock DDS
No I/O Description
AVDD_DDDS
146
AP
AVSS_DDDS
145
AG
VDD_DDDS
VSS_DDDS
144
143
P
G
Analog power for the Destination DDS. Connect to 3.3V supply.
Must be bypassed with a 0.1uF capacitor to AVSS_DDDS pin
(as close to the pin as possible).
Analog ground for the Destination DDS.
Must be directly connected to the analog system ground.
Digital power for the Destination DDS. Connect to 3.3V supply.
Digital ground for the Destination DDS.
Table 10. Power Pins for Display Clock DDS
Pin Name
No I/O Description
AVDD_SDDS
141
AP
AVSS_SDDS
140
AG
VDD_SDDS
VSS_SDDS
139
138
P
G
Analog power for Source DDS. Connect to 3.3V supply.
Must be bypassed with a 0.1uF capacitor to AVSS_SDDS pin
(as close to the pin as possible).
Analog ground for Source DDS.
Must be directly connected to the analog system ground plane.
Digital power for the Source DDS. Connect to 3.3V supply.
Digital ground for the Source DDS.
Table 11. I/O Power and Ground Pins
Pin Name
RVDD
RVSS
No I/O Description
2
20
37
53
67
81
97
111
129
3
21
38
54
68
82
98
112
130
P
P
P
P
P
P
P
P
P
G
G
G
G
G
G
G
G
G
Connect to 3.3V supply.
Must be bypassed with a 0.1uF capacitor to RVSS (as close to the pin as possible).
Connect to digital ground.
Table 12. Core Power and Ground Pins
Pin Name
CVDD_2.5
CVSS
June 2002
No I/O Description
26
88
134
203
27
89
133
135
202
P
P
P
P
G
G
G
G
G
Connect to 2.5V supply.
Must be bypassed with a 0.1uF capacitor to CVSS (as close to the pin as possible).
Connect to digital ground.
9
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
4. FUNCTIONAL DESCRIPTION
A functional block diagram is illustrated below. Each of the functional units shown is
described in the following sections.
NVRAM
Serial I/F Serial Host I/F
Parallel
ROM IF
Crystal
Reference
GPIO
Host
Interface
8051-style
Microcontroller
MCU
RAM
DVI-Compliant
DVI Input
Clock
Generation
OSD
Controller
OSD
RAMs
Internal
ROM
DVI Rx
HDCP
Analog
RGB
External
ROM I/F
Image
Capture /
Measurement
Triple
ADC
Figure 3.
Brightness /
Contrast /
Hue / Sat /
RealColorTM /
Moire
Zoom /
Shrink /
Filter
Gamma
Control
Output
Data
Path
Panel Data
and Control
gm5110/20 Functional Block Diagram
4.1 Clock Generation
The gm5110/20 features three clock inputs. All additional clocks are internal clocks derived
from one or more of these:
1. Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal
oscillator and corresponding logic. A 14.3 MHz TV crystal is recommended. Other
crystal frequencies may be used, but require custom programming. This is illustrated in
Figure 4 below. Alternatively, a single-ended TTL/CMOS clock oscillator can be driven
into the TCLK pin (leave XTAL as N/C in this case). This is illustrated in Figure 7
below. This option is selected by connecting a 10KΩ pull-up to ROM_ADDR13 (refer to
Table 18). See also Table 14.
2. DVI Differential Input Clock (RC+ and RC-)
3. Host Interface Transfer Clock (HCLK)
June 2002
10
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
The gm5110/20 TCLK oscillator circuitry is a custom designed circuit to support the use of
an external oscillator or a crystal resonator to generate a reference frequency source for the
gm5110/20 device.
4.1.1 Using the Internal Oscillator with External Crystal
The first option for providing a clock reference is to use the internal oscillator with an
external crystal. The oscillator circuit is designed to provide a very low jitter and very low
harmonic clock to the internal circuitry of the gm5110/20. An Automatic Gain Control
(AGC) is used to insure startup and operation over a wide range of conditions. The oscillator
circuit also minimizes the overdrive of the crystal, which reduces the aging of the crystal.
When the gm5110/20 is in reset, the state of the ROM_ADDR13 pin (pin number 10) is
sampled. If the pin is left unconnected (internal pull-down) then internal oscillator is enabled.
In this mode a crystal resonator is connected between TCLK (pin 152) and the XTAL (pin
151) with the appropriately sized loading capacitors CL1 and CL2. The size of CL1 and CL2 are
determined from the crystal manufacturer’s specification and by compensating for the
parasitic capacitance of the gm5110/20 device and the printed circuit board traces. The
loading capacitors are terminated to the analog VDD power supply. This connection
increases the power supply rejection ratio when compared to terminating the loading
capacitors to ground.
gm5115
Vdda
CL1
152
Vdd
TCLK
151
Vdda
XTAL
CL2
OSC_OUT
TCLK Distribution
100 K
180 uA
10
N/C
Reset State Logic
ROM_ADDR13
Internal Oscillator Enable
Internal Pull Down
Resistor
~ 60K
Figure 4.
June 2002
Using the Internal Oscillator with External Crystal
11
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
The TCLK oscillator uses a Pierce Oscillator circuit. The output of the oscillator circuit,
measured at the TCLK pin, is an approximate sine wave with a bias of about 2 volts above
ground (see Figure 5). The peak-to-peak voltage of the output can range from 250 mV to
1000 mV depending on the specific characteristics of the crystal and variation in the
oscillator characteristics. The output of the oscillator is connected to a comparator that
converts the sine wave to a square wave. The comparator requires a minimum signal level of
about 50-mV peak to peak to function correctly. The output of the comparator is buffered and
then distributed to the gm5110/20 circuits.
3.3 Volts
250 mV peak to peak
to
1000 mV peak to peak
~ 2 Volts
time
Figure 5.
Internal Oscillator Output
One of the design parameters that must be given some consideration is the value of the
loading capacitors used with the crystal as shown in Figure 6. The loading capacitance (Cload)
on the crystal is the combination of CL1 and CL2 and is calculated by Cload = ((CL1 * CL2) /
(CL1 + CL2)) + Cshunt. The shunt capacitance Cshunt is the effective capacitance between the
XTAL and TCLK pins. For the gm5110/20 this is approximately 9 pF. CL1 and CL2 are a
parallel combination of the external loading capacitors (Cex), the PCB board capacitance
(Cpcb), the pin capacitance (Cpin), the pad capacitance (Cpad), and the ESD protection
capacitance (Cesd). The capacitances are symmetrical so that CL1 = CL2 = Cex + CPCB + Cpin +
Cpad + CESD. The correct value of Cex must be calculated based on the values of the load
capacitances. Approximate values are provided in Figure 6.
June 2002
12
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
CL1 = Cex1 + Cpcb + Cpin + Cpad + Cesd
Vdda
Cex1
Cpcb
Cpin
141
Cpad
Cesd
Internal Oscillator
TCLK
gm5115
Cshunt
Vdda
142
XTAL
Cex2
Cpcb
Cpin
CL2 = Cex1 + Cpcb + Cpin + Cpad + Cesd
Figure 6.
Cpad
Cesd
Approximate values:
CPCB ~ 2 pF to 10 pF (layout dependent)
Cpin ~ 1.1 pF
Cpad ~ 1 pF
Cesd ~ 5.3 pF
Cshunt ~ 9 pF
Sources of Parasitic Capacitance
Some attention must be given to the details of the oscillator circuit when used with a crystal
resonator. The PCB traces should be as short as possible. The value of Cload that is specified
by the manufacturer should not be exceeded because of potential start up problems with the
oscillator. Additionally, the crystal should be a parallel resonate-cut and the value of the
equivalent series resistance must be less then 90 Ohms.
4.1.2 Using an External Clock Oscillator
Another option for providing the reference clock is to use a single-ended external clock
oscillator. When the gm5110/20 is in reset, the state of the ROM_ADDR13 (pin 10) is
sampled. If ROM_ADDR13 is pulled high by connecting to VDD through a pull-up resistor
(15KΩ recommended, 15KΩ maximum) then external oscillator mode is enabled. In this
mode the internal oscillator circuit is disabled and the external oscillator signal that is
connected to the TCLK pin (pin number 152) is routed to an internal clock buffer. This is
illustrated in Figure 7.
June 2002
13
C5110-DAT-01C
*** Genesis Microchip Confidential ***
Vdd
14 to 24 MHz
gm5110/20 Preliminary Data Sheet
gm5110/20
152
Vdd
OSC_OUT
TCLK Distribution
TCLK
Oscillator
GND
151
Vdd
Internal
Oscillator
XTAL
Disable
10 K
10
Reset State Logic
External Oscillator Enable
ROM_ADDR13
Internal Pull Down
Resistor
~ 60 K
Figure 7.
Using an External Single-ended Clock Oscillator
Frequency
Jitter Tolerance
Rise Time (10% to 90%)
Maximum Duty Cycle
14 to 24 MHz
250 ps
5 ns
40-60
Table 13. TCLK Specification
4.1.3 Clock Synthesis
The gm5110/20 synthesizes all additional clocks internally as illustrated in Figure 8 below.
The synthesized clocks are as follows:
1. Main Timing Clock (TCLK) is the output of the chip internal crystal oscillator. TCLK is
derived from the TCLK/XTAL pad input.
2. Reference Clock (RCLK) synthesized by RCLK PLL (RPLL) using TCLK as the
reference.
3. DVI Input Clock (DVI_CLK) synthesized by DVI receiver PLL using RC+/RC- pair as
the reference.
4. Input Source Clock (SCLK) synthesized by Source DDS (SDDS) PLL using input
HSYNC as the reference. The SDDS internal digital logic is driven by RCLK.
June 2002
14
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
5. Display Clock (DCLK) synthesized by Destination DDS (DDDS) PLL using IP_CLK as
the reference. The DDDS internal digital logic is driven by RCLK.
6. Half Reference Clock (RCLK/2) is the RCLK (see 2, above) divided by 2. Used as
OCM_CLK domain driver.
7. Quarter Reference Clock (RCLK/4) is the RCLK (see 2, above) divided by 4. Used as
alternative clock (faster than TCLK) to drive IFM.
8. ADC Output Clock (SENSE_ACLK) is a delay-adjusted ADC sampling clock, ACLK.
ACLK is derived from SCLK.
HSYNC
SCLK
SDDS
IP_CLK
TCLK
DDDS
DCLK
RCLK
PLL
/2
RCLK/2
/4
RCLK/4
RC+
DVI Rx
DVI_CLK
RC-
Figure 8.
Internally Synthesized Clocks
The on-chip clock domains are selected from the synthesized clocks as shown in Figure 9
below. These include:
1. Input Domain Clock (IP_CLK). Max = 165MHz
2. Host Interface and On-Chip Microcontroller Clock (OCM_CLK). Max = 100MHz
3. Filter and Display Pixel Clock (DP_CLK). Max = 135MHz
4. Source Timing Measurement Domain Clock (IFM_CLK). Max = 50MHz
5. ADC Domain Clock (ACLK). Max = 165MHz.
The clock selection for each domain as shown in the figure below is controlled using the
CLOCK_CONFIG registers (index 0x03 and 0x04).
June 2002
15
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
SCLK
DCLK
SENSE_ACLK
IP_CLK
DP_CLK
IP_CLK
DVI_CLK
RCLK/2
SCLK
RCLK/4
IFM_CLK
OCM_CLK
ACLK
TCLK
TCLK
Figure 9.
On-chip Clock Domains
4.2 Hardware Reset
Hardware Reset is performed by holding the RESETn pin low for a minimum of 1µs. A
TCLK input (see Clock Options above) must be applied during and after the reset. When the
reset period is complete and RESETn is de-asserted, the power-up sequence is as follows:
1. Reset all registers of all types to their default state (this is 00h unless otherwise specified
in the gm5110/20 Register Listing).
2. Force each clock domain into reset. Reset will remain asserted for 64 local clock domain
cycles following the de-assertion of RESETn.
3. Operate the OCM_CLK domain at the TCLK frequency.
4. Preset the RCLK PLL to output ~200MHz clock (assumes 14.3MHz TCLK crystal
frequency).
5. Wait for RCLK PLL to Lock. Then, switch the OCM_CLK domain to operate from the
bootstrap selected clock.
6. If a pull-up resistor is installed on ROM_ADDR9 pin (see Table 18), then the OCM
becomes active as soon as OCM_CLK is stable. Otherwise, the OCM remains in reset
until OCM_CONTROL register (0x22) bit 1 is enabled.
4.3 Analog to Digital Converter
The gm5110/20 chip has three ADC’s (analog-to-digital converters), one for each color (red,
green, and blue).
June 2002
16
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
4.3.1 ADC Pin Connection
The analog RGB signals are connected to the gm5110/20 as described below:
Table 14. Pin Connection for RGB Input with HSYNC/VSYNC
Pin Name
Red+
RedGreen+
GreenBlue+
BlueHSYNC
VSYNC
ADC Signal Name
Red
Terminate as illustrated in Figure 10
Green
Terminate as illustrated in Figure 10
Blue
Terminate as illustrated in Figure 10
Horizontal Sync (Terminate as illustrated in Figure 10)
Vertical Sync (Terminate as with HSYNC illustrated in Figure 10)
gm5110/20
100Ω
RED
RED +
0.01uF
75Ω
DB15
100Ω
RED -
GND
0.01uF
HSYNC
Figure 10.
HS
Example ADC Signal Terminations
Please note that it is very important to follow the recommended layout guidelines for the
circuit shown in Figure 10. These are described in "gm5115 Layout Guidelines" document
number C5115-SLG-01A.
4.3.2 ADC Characteristics
The table below summarizes the characteristics of the ADC:
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Table 15. ADC Characteristics
MIN
Track & Hold Amp Bandwidth
TYP
MAX
290 MHz
Full Scale Adjust Range at RGB Inputs
Full Scale Adjust Sensitivity
Zero Scale Adjust Sensitivity
Sampling Frequency (Fs)
Differential Non-Linearity (DNL)
0.55 V
0.90 V
+/- 1 LSB
Measured at ADC Output.
Independent of full scale RGB input.
Measured at ADC Output.
+/- 1 LSB
10 MHz
+/-0.5 LSB
No Missing Codes
Integral Non-Linearity (INL)
Channel to Channel Matching
NOTE
Guaranteed by design. Note that the Track &
Hold Amp Bandwidth is programmable. 290
MHz is the maximum setting.
162.5 MHz
+/-0.9 LSB Fs = 135 MHz
Guaranteed by test.
Fs =135 MHz
+/- 1.5 LSB
+/- 0.5 LSB
The gm5110/20 ADC has a built in clamp circuit for AC-coupled inputs. By inserting series
capacitors (about 10 nF), the DC offset of an external video source can be removed. The
clamp pulse position and width are programmable.
4.3.3 Clock Recovery Circuit
The SDDS (Source Direct Digital Synthesis) clock recovery circuit generates the clock used
to sample analog RGB data (IP_CLK or source clock). This circuit is locked to HSYNC of
the incoming video signal.
Patented digital clock synthesis technology makes the gm5110/20 clock circuits resistant to
temperature/voltage drift. Using DDS (Direct Digital Synthesis) technology, the clock
recovery circuit can generate any IP_CLK clock frequency within the range of 10MHz to
165MHz.
Image Phase
Measurement
R
G
B
ADC
24
Window
Capture
Phase
HSYNC
HSYNC
(delayed)
Figure 11.
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SDDS
IPCLK
gm5110/20 Clock Recovery
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4.3.4 Sampling Phase Adjustment
The programmable ADC sampling phase is adjusted by delaying the HSYNC input to the
SDDS. The accuracy of the sampling phase is checked and the result read from a register.
This feature enables accurate auto-adjustment of the ADC sampling phase.
4.3.5 ADC Capture Window
Figure 12 below illustrates the capture window used for the ADC input. In the horizontal
direction the capture window is defined in IP_CLKs (equivalent to a pixel count). In the
vertical direction it is defined in lines.
All the parameters beginning with “Source” are programmed gm5110/20 registers values.
Note that the input vertical total is solely determined by the input and is not a programmable
parameter.
Source Horizontal Total (pixels)
Reference
Point
Source
Hstart
Source Height
Input Vertical Total (lines)
Source
Vstart
Source Width
Capture Window
Figure 12.
ADC Capture Window
The Reference Point marks the leading edge of the first internal HSYNC following the
leading edge of an internal VSYNC. Both the internal HSYNC and the internal VSYNC are
derived from external HSYNC and VSYNC inputs.
Horizontal parameters are defined in terms of single pixel increments relative to the internal
horizontal sync. Vertical parameters are defined in terms of single line increments relative to
the internal vertical sync.
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For ADC interlaced inputs, the gm5110/20 may be programmed to automatically determine
the field type (even or odd) from the VSYNC/HSYNC relative timing. See Input Format
Measurement, Section 4.5.
4.4 DVI Receiver Block
The Ultra-Reliable DVITM receiver block of the gm5110/20 is compliant with DVI1.0 single
link specifications. Digital Visual Interface (DVI) is a standard that uses Transition
Minimized Differential Signaling protocol (TMDS). This block supports an input clock
frequency ranging from 20 MHz to 165 MHz.
4.4.1 DVI Receiver Characteristics
Table 16 summarizes the characteristics of the four Receiver Pair inputs. Please note that it is
very important to follow the recommended layout guidelines for these signals. These are
described in "gm5115 Layout Guidelines" document number C5115-SLG-01A.
Table 16. DVI Receiver Characteristics
MIN
TYP
MAX
NOTE
DC Characteristics
Differential Input Voltage
Input Common Mode Voltage
Behavior when Transmitter Disable
Input clock frequency
Input differential sensitivity (Peak-to-peak)
Max differential input (peak-to-peak)
Allowable Intra-Pair skew at Receiver
Allowable Inter-Pair skew at Receiver
Worst case differential input clock jitter
tolerance
150mV
AVDD
–300m V
AVDD
-10mV
AC Characteristics
20 MHz
150mV
1200mV
AVDD
-37mV
AVDD
+10mV
165 MHz
1560 mV
250 ps
4.0 ns
188 ps
Input clock = 160 MHz
Through register programming, the receiver unit may be placed in one of three states:
•
Active: The receiver block is fully on and running.
•
Standby: Only the RC (clock) channel remains active. Data and other control signals are
not decoded.
•
Off: The receiver block is powered down.
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4.4.2 DVI Capture Window
DE (Display Enable), HSYNC and VSYNC are synthesized internally by examining the
active regions of each line and compensating for possible source timing errors and/or
embedded HSYNC / VSYNC jitter.
There are two ways to define the DVI capture region:
CREF Capture - In this mode the usual active window parameters must be programmed as
with ADC inputs (see Section 4.3.5.).
DE Capture - In this mode the active window code embedded in the DVI signal defines the
active window automatically. Only the active width and active length parameters obtained
by performing Input Format Measurement (IFM) need be programmed.
4.4.3 HDCP (High-Bandwidth Digital Content Protection)
The HDCP system allows authentication of a video receiver by a video transmitter,
decryption of transmitter-encoded video data by the receiver, and periodic renew-ability of
authentication during transmission. The gm5110/20 implements circuitry to allow full
support of the HDCP 1.0 protocol for DVI inputs.
For enhanced security, Genesis provides a means of storing and accessing the secret key
given to individual monitor units in an encrypted format. To use HDCP it is necessary to
obtain the HDCP key encryption tool, called Gencrypt, from Genesis. Gencrypt will only be
made available to HDCP licensed customers.
Further details of the protocol and theory of the system can be found in the High-bandwidth
Digital Content Protection System specification (see www.digital-cp.com).
Note that this section applies to the HDCP enabled chip versions gm5110-H and gm5120-H
but not the standard versions gm5110 and gm5120.
4.5 Test Pattern Generator (TPG)
The gm5110/20 contains hundreds of test patterns, some of which are shown in Figure 13.
Once programmed, the gm5110/20 test pattern generator can replace a video source (e.g. a
PC) during factory calibration and test. This simplifies the test procedure and eliminates the
possibility of image noise being injected into the system from the source. The foreground and
background colors are programmable. In addition, the gm5110/20 OSD controller can be
used to produce other patterns.
Figure 13.
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Some of gm5110/20 built-in test patterns
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gm5110/20 Preliminary Data Sheet
4.6 Input Format Measurement
The gm5110/20 has an Input Format Measurement block (the IFM) providing the capability
of measuring the horizontal and vertical timing parameters of the input video source. This
information may be used to determine the video format and to detect a change in the input
format. It is also capable of detecting the field type of interlaced formats.
The IFM features a programmable reset, separate from the regular gm5110/20 soft reset.
This reset disables the IFM, reducing power consumption. The IFM is capable of operating
while gm5110/20 is running in power down mode.
Horizontal measurements are measured in terms of the selected IFM_CLK (either TCLK or
RCLK/4), while vertical measurements are measured in terms of HSYNC pulses.
For an overview of the internally synthesized clocks, see section 4.1.
4.6.1 HSYNC / VSYNC Delay
The active input region captured by the gm5110/20 is specified with respect to internal
HSYNC and VSYNC. By default, internal syncs are equivalent to the HSYNC and VSYNC
at the input pins and thus force the captured region to be bounded by external HSYNC and
VSYNC timing. However, the gm5110/20 provides an internal HSYNC and VSYNC delay
feature that removes this limitation. This feature is available for use with both the ADC input
and the DVI Rx (DE-regeneration mode). By delaying the sync internally, the gm5110/20
can capture data that spans across the sync pulse.
It is possible to use HSNYC and VSYNC delay for image positioning. (Alternatively,
Source_HSTART and Source_VSTART in Figure 12 are used for image positioning of
analog input.) Taken to an extreme, the intentional movement of images across apparent
HSYNC and VSYNC boundaries creates a horizontal and/or vertical wrap effect.
HSYNC is delayed by a programmed number of selected input clocks.
active
HS(system)
HS(internal)
active
capture
capture
programmable
delay
capture
input block actually
captures across HSYNC
Figure 14.
HSYNC Delay
Delayed horizontal sync may be used to solve a potential problem with VSYNC jitter with
respect to HSYNC. VSYNC and HSYNC are generally driven active coincidentally, but
with different paths to the gm5110/20 (HSYNC is often regenerated from a PLL). As a
result, VSYNC may be seen earlier or later. Because VSYNC is used to reset the line
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gm5110/20 Preliminary Data Sheet
counter and HSYNC is used to increment it, any difference in the relative position of
HSYNC and VSYNC is seen on-screen as vertical jitter. By delaying the HSYNC a small
amount, it can be ensured that VSYNC always resets the line counter prior to it being
incremented by the “first” HSYNC.
active data crosses HS boundary
delayed HS placed safely within blanking
Data
HS (system)
Internal Delayed HS
Figure 15.
Active Data Crosses HSYNC Boundary
4.6.2 Horizontal and Vertical Measurement
The IFM is able to measure the horizontal period and active high pulse width of the HSYNC
signal, in terms of the selected clock period (either TCLK or RCLK/4.). Horizontal
measurements are performed on only a single line per frame (or field). The line used is
programmable. It is able to measure the vertical period and VSYNC pulse width in terms of
rising edges of HSYNC.
Once enabled, measurement begins on the rising VSYNC and is completed on the following
rising VSYNC. Measurements are made on every field / frame until disabled.
4.6.3 Format Change Detection
The IFM is able to detect changes in the input format relative to the last measurement and
then alert both the system and the on-chip microcontroller. The microcontroller sets a
measurement difference threshold separately for horizontal and vertical timing. If the current
field / frame timing is different from the previously captured measurement by an amount
exceeding this threshold, a status bit is set. An interrupt can also be programmed to occur.
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4.6.4 Watchdog
The watchdog monitors input VSYNC / HSYNC. When any HSYNC period exceeds the
programmed timing threshold (in terms of the selected IFM_CLK), a register bit is set. When
any VSYNC period exceeds the programmed timing threshold (in terms of HSYNC pulses),
a second register bit is set. An interrupt can also be programmed to occur.
4.6.5 Internal Odd/Even Field Detection (For Interlaced Inputs to ADC Only)
The IFM has the ability to perform field decoding of interlaced inputs to the ADC. The user
specifies start and end values to outline a “window” relative to HSYNC. If the VSYNC
leading edge occurs within this window, the IFM signals the start of an ODD field. If the
VSYNC leading edge occurs outside this window, an EVEN field is indicated (the
interpretation of odd and even can be reversed). The window start and end points are
selected from a predefined set of values.
HS
window
Window
Start
Window End
VS - even
VS - odd
Figure 16.
ODD/EVEN Field Detection
4.6.6 Input Pixel Measurement
The gm5110/20 provides a number of pixel measurement functions intended to assist in
configuring system parameters such as pixel clock, SDDS sample clocks per line and phase
setting, centering the image, or adjusting the contrast and brightness.
4.6.7 Image Phase Measurement
This function measures the sampling phase quality over a selected active window region.
This feature may be used when programming the source DDS to select the proper phase
setting. Please refer to the gm5110/20 Programming Guide for the optimized algorithm.
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4.6.8 Image Boundary Detection
The gm5110/20 performs measurements to determine the image boundary. This information
is used when programming the Active Window and centering the image.
4.6.9 Image Auto Balance
The gm5110/20 performs measurements on the input data that is used to adjust brightness
and contrast.
4.7 RealColorTM Digital Color Controls
The gm5110/20 provides high-quality digital color controls. These consist of a subtractive
"black level" stage, followed by a full 3x3 RGB matrix multiplication stage, followed by an
signed offset stage as shown in Figure 17.
Subtractive
Offset
(Black Level)
Red In
-
Green In
-
Blue In
Figure 17.
3x3 Color
Conversion
X
Additive
Offset
(Brightness)
+/-
Red Out
+/-
Green Out
+/-
Blue Out
RealColorTM Digital Color Controls
This structure can accommodate all RGB color controls such as black-level (subtractive
stage), contrast (multiplicative stage), and brightness (signed additive offset). In addition, it
supports all YUV color controls including brightness (additive factor applied to Y), contrast
(multiplicative factor applied to Y), hue (rotation of U and V through an angle) and
saturation (multiplicative factor applied to both Y and V).
To provide the highest color purity all mathematical functions use 10 bits of accuracy. The
final result is then dithered to eight or six bits (as required by the LCD panel).
4.7.1 RealColor™ Flesh tone Adjustment
The human eye is more sensitive to variations of flesh tones than other colors; for example,
the user may not care if the color of grass is modified slightly during image capture and/or
display. However, if skin tones are modified by even a small amount, it is unacceptable. The
gm5110/20 features flesh tone adjustment capabilities. This feature is not based on lookup
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gm5110/20 Preliminary Data Sheet
tables, but rather a manipulation of YUV-channel parameters. Flesh tone adjustment is
available for all inputs.
4.7.2 Color Standardization and sRGB Support
Internet shoppers may be very picky about what color they experience on the display.
gm5110/20 RealColorTM digital color controls can be used to make the color response of an
LCD monitor compliant with standard color definitions, such as sRGB. sRGB is a standard
for color exchange proposed by Microsoft and HP (see www.srgb.com). gm5110/20
RealColor controls can be used to make LCD monitors sRGB compliant, even if the native
response of the LCD panel itself is not. For more information on sRGB compliance using
gm5110/20 family devices please refer to the sRGB application brief C5115-APB-02A.
4.8 High-Quality Scaling
The gm5110/20 zoom scaler uses an adaptive scaling technique proprietary to Genesis
Microchip Inc., and provides high quality scaling of real time video and graphics images. An
input field/frame is scalable in both the vertical and horizontal dimensions.
Interlaced fields may be spatially de-interlaced by vertically scaling and repositioning the
input fields to align with the output display’s pixel map.
4.8.1 Variable Zoom Scaling
The gm5110/20 scaling filter can combine its advanced scaling with a pixel-replication type
scaling function. This is useful for improving the sharpness and definition of graphics when
scaling at high zoom factors (such as VGA to XGA).
4.8.2 Horizontal and Vertical Shrink
A shrink function may be performed on the input data. This is an arbitrary horizontal active
resolution reduction to between (50% + 1 pixel) to 100% of the input. For example, this
allows SXGA 1280 pixels to be displayed as 1024 (XGA).
The gm5110/20 provides an arbitrary vertical shrink down to (50% + 1 line) of the original
image size. Together with the arbitrary horizontal shrink, this allows the gm5110/20 to
capture and display images one VESA standard format larger than the native display
resolution. For example, SXGA may be captured and displayed on an XGA panel.
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4.8.3 Moiré Cancellation
The gamma curve and other non-linearities can affect the energy distribution of pixels when
scaled to different areas of the screen. This is an example of the Moiré effect. The
gm5110/20 has hardware features to negate the Moiré effect, improving the scaling quality.
4.9 Bypass Options
The gm5110/20 has the capability to completely bypass internal processing. In this case,
captured input signals and data are passed, with a small register latency, straight through to
the display output.
The gm5110/20 is also able to bypass the zoom filter.
4.10 Gamma LUT
The gm5110/20 provides an 8 to 10-bit look-up table (LUT) for each input color channel
intended for Gamma correction and to compensate for a non-linear response of the LCD
panel. A 10-bit output results in an improved color depth control. The 10-bit output is then
dithered down to 8 bits (or 6 bits) per channel at the display (see section 4.11.3 below). The
LUT is user programmable to provide an arbitrary transfer function. Gamma correction
occurs after the zoom / shrink scaling block.
The LUT has bypass enable. If bypassed, the LUT does not require programming.
4.11 Display Output Interface
The Display Output Port provides data and control signals that permit the gm5110/20 to
connect to a variety of flat panel or CRT devices. The output interface is configurable for 18
or 24-bit RGB pixels, either single or double pixel wide. All display data and timing signals
are synchronous with the DCLK output clock.
4.11.1 Display Synchronization
Refer to section 4.1 for information regarding internal clock synthesis.
The gm5110/20 supports the following display synchronization modes:
•
•
Frame Sync Mode: The display frame rate is synchronized to the input frame or
field rate. This mode is used for standard operation.
Free Run Mode: No synchronization. This mode is used when there is no valid input
timing (i.e. to display OSD messages or a splash screen) or for testing purposes. In
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free-run mode, the display timing is determined only by the values programmed into
the display window and timing registers.
4.11.2 Programming the Display Timing
Display timing signals provide timing information so the Display Port can be connected to an
external display device. Based on values programmed in registers, the Display Output Port
produces the horizontal sync (DHS), vertical sync (DVS), and data enable (DEN) control
signals. The figure below provides the registers that define the output display timing.
DH_BKGND_START
DVS
Horizontal values are programmed in single pixel increments relative to the leading edge of
the horizontal sync signal. Vertical values are programmed in line increments relative to the
leading edge of the vertical sync signal.
DH_BKGND_END
DV_VS_END
VSYNC Region
Vertical Blanking (Back Porch)
DV_BKGND_START
DV_ACTIVE_START
DV_TOTAL
Display Active Window
Horizontal Blanking (Front Porch)
Horizontal Blanking (Back Porch)
HSYNC region
Display Background Window
DV_ACTIVE_LENGTH
DV_BKGND_END
Vertical Blanking (Front Porch)
DH_TOTAL
DHS
DEN **
DH_HS_END
** DEN is not asserted during vertical blanking
DH_ACTIVE_WIDTH
DH_ACTIVE_START
Figure 18.
Display Windows and Timing
The double-wide output only supports an even number of horizontal pixels.
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DCLK (Output)
DEN (Output)
ER/EG/EB
(Output)
XXX
rgb0
OR/OG/OB
(Output)
Figure 19.
rgb1
rgb2
rgb3
rgb4
XXX
Single Pixel Width Display Data
DCLK (Output)
DEN (Output)
ER/EG/EB
(Output)
XXX
rgb0
rgb2
rgb4
rgb6
rgb8
OR/OG/OB
(Output)
XXX
rgb1
rgb3
rgb5
rgb7
rgb9
Figure 20.
Double Pixel Wide Display Data
4.11.3 Panel Power Sequencing (PPWR, PBIAS)
gm5110/20 has two dedicated outputs PPWR and PBIAS (pins 113 and 114) to control LCD
power sequencing once data and control signals are stable. The timing of these signals is
fully programmable.
TMG1
TMG2
<State1>
<State2>
TMG2
TMG1
PPWR Output
Panel Data and Control Signals
PBIAS Output
<State0>
<State3>
POWER_SEQ_EN = 1
Figure 21.
June 2002
<State2>
<State1>
<State0>
POWER_SEQ_EN = 0
Panel Power Sequencing
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4.11.4 Output Dithering
The Gamma LUT outputs a 10-bit value for each color channel. This value is dithered down
to either 8-bits for 24-bit per pixel panels, or 6-bits for 18-bit per pixel panels.
The benefit of dithering is that the eye tends to average neighboring pixels and a smooth
image free of contours is perceived. Dithering works by spreading the quantization error over
neighboring pixels both spatially and temporally. Two dithering algorithms are available:
random or ordered dithering. Ordered dithering is recommended when driving a 6-bit panel.
All gray scales are available on the panel output whether using 8-bit panel (dithering from 10
to 8 bits per pixel) or using 6-bit panel (dithering from 10 down to 6 bits per pixel).
4.12 Energy Spectrum Management (ESM)
High spikes in the EMI power spectrum may cause LCD monitor products to violate
emissions standards. The gm5110/20 has many features that can be used to reduce
electromagnetic interference (EMI). These include drive strength control and clock spectrum
modulation. These features help to eliminate the costs associated with EMI reducing
components and shielding.
4.13 OSD
The gm5110/20 has a fully programmable, high-quality OSD controller. The graphics are
divided into “cells” 12 by 18 pixels in size. The cells are stored in an on-chip static RAM
(4096 words by 24 bits) and can be stored as 1-bit per pixel data, 2-bit per pixel data or 4-bit
per pixel data. This permits a good compression ratio while allowing more than 16 colors in
the image.
Some general features of the gm5110/20 OSD controller include:
OSD Position – The OSD menu can be positioned anywhere on the display region. The
reference point is Horizontal and Vertical Display Background Start (DH_BKGND_START
and DV_BKGND_START in Figure 18).
OSD Stretch – The OSD image can be stretched horizontally and/or vertically by a factor of
two, three, or four. Pixel and line replication is used to stretch the image.
OSD Blending – Sixteen levels of blending are supported for the character-mapped and
bitmapped images. One host register controls the blend levels for pixels with LUT values of
128 and greater, while another host register controls the blend levels for pixels with LUT
values of 127 and lower. OSD color LUT value 0 is reserved for transparency and is
unaffected by the blend attribute.
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4.13.1 On-Chip OSD SRAM
The on-chip static RAM (4096 words by 24 bits) stores the cell map and the cell definitions.
In memory, the cell map is organized as an array of words, each defining the attributes of one
visible character on the screen starting from upper left of the visible character array. These
attributes specify which character to display, whether it is stored as 1, 2 or 4 bits per pixel,
the foreground and background colors, blinking, etc.
Registers CELLMAP_XSZ and CELLMAP_YSZ are used to define the visible area of the
OSD image. For example, Figure 22 shows a cell map for which CELLMAP_XSZ =25 and
CELLMAP_YSZ =10.
Address 1:
Cell Attributes for
upper-left hand cell
Address 25:
Attributes for
upper-right hand cell
CELLMAP_XSZ
Address26:
Cell attributes for
st
1 cell, 2nd row
Brightness
Contrast
CELLMAP_YSZ
Figure 22.
OSD Cell Map
Cell definitions are stored as bit map data. On-chip registers point to the start of 1-bit per
pixel definitions, 2-bit per pixel definitions and 4-bit per pixel definitions respectively. 1, 2
and 4-bit per pixel cell definitions require 9, 18 and 36 words of the OSD RAM respectively.
Note that the cell map and the cell definitions share the same on-chip RAM. Thus, the size of
the cell map can be traded off against the number of different cell definitions. In particular,
the size of the OSD image and the number of cell definitions must fit in OSD SRAM. That is,
the following inequality must be satisfied. (Note, the ROUND operation rounds 3.5 to 4).
(CELLMAP_XSZ+1) * CELLMAP_YSZ +
18 * ROUND(Number of 1-bit per pixel fonts / 2) +
18 * (Number of 2-bit per pixel fonts) +
36 * (Number of 4-bit per pixel fonts)
<= 4096
For example, an OSD menu 360 pixels wide by 360 pixels high is 30 cells in width and 20
cells in height. Many of these cells would be the same (e.g. empty). In this case, the menu
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could contain more than 32 1-bit per pixel cells, 100 2-bit per pixel cells, and 16 4-bit per
pixel cells. Of course, different numbers of each type can also be used.
4.13.2 Color Look-up Table (LUT)
Each pixel of a displayed cell is resolved to an 8-bit color code. This selected color code is
then transformed to a 24-bit value using a 256 x 24-bit look up table. This LUT is stored in
an on-chip RAM that is separate from the OSD RAM. Color index value 0x00 is reserved for
transparent OSD pixels.
4.14 On-Chip Microcontroller (OCM)
The gm5110/20 on-chip microcontroller (OCM) serves as the system microcontroller. It
programs the gm5110/20 and manages other devices in the system such as the keypad, the
back light and non-volatile RAM (NVRAM) using general-purpose input/output (GPIO)
pins.
The OCM can operate in two configurations, Standalone configuration and Full-Custom
configuration, as illustrated in Figure 23.
Factory
Port
Analog
RGB
Input
Factory
Port
Analog
RGB
Input
gm5110/20
Output to
LCD Panel
OCM
DVI
Input
ROM
NVRAM
gm5110/20
OCM
Output to
LCD Panel
DVI
Input
On-chip ROM:
• Auto mode detection
• Auto-configuration
• Standard high-quality OSD menus
• Factory test / calibration functions
NVRAM
Configuration settings in NVRAM:
• OSD Colors, Logo and other configuration
• Panel Parameters
• Additional input modes
• Code patches
User settings in NVRAM:
• Brightness/contrast settings, etc
• On mode-by-mode basis
PROM
External ROM:
• Contains firmware code and data
for all firmware functions
Figure 23A - Standalone Configuration
Figure 23B - Full-Custom Configuration
Figure 23.
OCM Full-Custom and Standalone Configurations
(No external ROM)
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4.14.1 Standalone Configuration
Standalone configuration offers the most simple and inexpensive system solution for generic
LCD monitors. In this configuration the OCM executes firmware stored internally in
gm5110/20. This is illustrated in Figure 23A. The on-chip firmware provides all the standard
functions required in a high-quality generic LCD monitor. This includes mode-detection,
auto-configuration and a high-quality standard OSD menu system. No external ROM is
required (which reduces BOM cost) and no firmware development effort is required (which
reduces time-to-market).
In Standalone configuration many customization parameters are stored in NVRAM. These
include the LCD panel timing parameters (including TCON programming), the color scheme
and logos used in the OSD menus, the functions provided by the OSD menus, and arbitrary
firmware modifications. These customization parameters are described in the Standalone
User’s Guide (B0108-SUG-01). Based on the customization parameters, G-Wizard (a GUIbased development tool used to program Genesis devices) produces the hex image file for
NVRAM. G-Probe is then used to download the NVRAM image file into the NVRAM
device. This is illustrated in Figure 24 below.
Specify Configurable Parameters
(See Standalone Users Guide)
G-Wizard
NVRAM
Image File
(.nvram_image. hex)
G-Probe
LCD
Controller
Board
NVRAM
gm5110/20
OCM
Figure 24.
June 2002
Programming OCM in Standalone Configuration
33
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
4.14.2 Full-Custom Configuration
In full-custom configuration the OCM executes a firmware program running from external
ROM. This is illustrated in Figure 23B. A parallel port with separate address and data busses
is available for this purpose. This port connects directly to standard, commercially available
ROM or programmable Flash ROM devices. Normally 64KB or 128KB of ROM is required.
Both instructions and data are fetched from external ROM on a cycle-by-cycle basis. The
speed of the accesses on the parallel port is determined by the gm5110/20 internal
OCM_CLK. This in turn determines the speed of the external ROM device. For example, if a
14.3 MHz crystal is being used to produce TCLK, and the OCM_CLK is derived from
TCLK, then a 45ns ROM can be used.
To program gm5110/20 in full-custom configuration the content of the external ROM is
generated using Genesis software development tools G-Wizard and OSD-Workbench. This is
illustrated in Figure 25. G-Wizard is a GUI-based tool for capturing system information such
as panel timing, support modes, system configuration, etc. OSD-Workbench is a GUI based
tool for defining OSD menus and functionality.
G-Wizard
gm5110/20 Driver
OSD Workbench
gm5110/20 Driver
Firmware source files (*.c *.h)
Keil Compiler
External ROM
Image File (.hex)
ROM Programmer
LCD
Controller
Board
ROM
gm5110/20
OCM
Figure 25.
June 2002
Programming the OCM in Full-Custom Configuration
34
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
Genesis recommends using Keil compiler (http://www.keil.com/) to compile the firmware
source code into a hex file. This hex file is then downloaded into the external ROM using
commercially available ROM programmers.
For development purposes it may be useful to use a ROM emulator. For example, a
PROMJET ROM emulator can be used (http://www.emutec.com/pjetmain.html).
4.14.3 General Purpose Inputs and Outputs (GPIO’s)
The gm5110/20 has 21 general-purpose input/output (GPIO) pins. These are used by the
OCM to communicate with other devices in the system such as keypad buttons, NVRAM,
LEDs, audio DAC, etc. Each GPIO has independent direction control, open drain enable, for
reading and writing. Note that the GPIO pins have alternate functionality as described in
Table 17 below.
Pin Name
GPIO0/PWM0
GPIO1/PWM1
GPIO2/PWM2
GPIO3/TIMER1
GPIO4/UART_DI
GPIO5/UARD_D0
GPIO6
GPIO7
GPIO8/IRQINn
GPIO9
GPIO10
GPIO11/ROM_WEn
GPIO12/NVRAM_SDA
GPIO13/NVRAM_SCL
GPIO14/DDC_SCL
GPIO15/DDC_SDA
GPIO16/HFSn
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21/IRQn
GPIO22/HCLK
GPO0
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
Pin Number
40
41
42
43
44
45
46
47
39
48
49
50
51
52
6
7
205
1
208
207
206
4
204
119
120
121
122
123
124
125
126
Alternate function
PWM0, PWM1 and PWM2 back light intensity controls, as described in section 4.17.2 below.
Timer1 input of the OCM.
OCM UART data in/out signals respectively.
OCM external interrupt source (IRQINn).
Write enable for external ROM if programmable FLASH device is used.
Data and clock lines for master 2-wire serial interface to NVRAM when gm5110/20 is used in
standalone configuration (section Figure 23).
Clock and data lines for 2-wire serial interface connected to the Direct Data Channel (DDC) of the DVI
input, for passing HDCP keys.
Serial data line for 2-wire host interface.
OCM interrupt output pin.
Serial input clock for 2-wire host interface.
General-purpose outputs.
Table 17. gm5110/20 GPIOs and Alternate Functions
4.15 Bootstrap Configuration Pins
During hardware reset, the external ROM address pins ROM_ADDR[15:0] are configured as
inputs. On the negating edge of RESETn, the value on these pins is latched and stored. This
value is readable by the on-chip microcontroller (or an external microcontroller via the host
June 2002
35
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
interface). Install a 10K pull-up resistor to indicate a ‘1’, otherwise a ‘0’ is indicated because
ROM_ADDR[15:0] have a 60KΩ internal pull-down resistor.
Signal Name
Pin Name
Description
HOST_ADDR(6:0)
HOST_PROTOCOL
HOST_PORT_EN
OCM_START
ROM_ADDR(6:0)
ROM_ADDR7
ROM_ADDR8
ROM_ADDR9
USER_BITS(7:5)
ROM_ADDR(12:10)
OSC_SEL
ROM_ADDR13
OCM_ROM_CNFG(1)
ROM_ADDR14
If using 2-wire host protocol, these are the serial bus device address.
Program this bit to 0 for 2-wire host interface operation.
Program this bit to 0 for 2-wire host interface operation.
Determines the operating condition of the OCM after HW reset:
0 = OCM remains in reset until enabled by register bit.
1 = OCM becomes active after OCM_CLK is stable.
These settings are available for reading from a status register but are otherwise unused by the
gm5110/20. Used to allow the OCM or external MCU access configuration settings.
Selects reference clock source (refer to Figure 7):
0 = XTAL and TCLK pins are connected to a crystal oscillator.
1 = TCLK input is driven with a single-ended TTL/CMOS clock oscillator.
Together with OCM_CONTROL register (0x22) bit 4, this bit selects internal/external ROM
configuration.
0 = All 48K of ROM is internal.
1 = All 48K of ROM is in external ROM using ROM_ADDR15:0 address outputs if
register 0x22 bit 4 is 0. If register 0x22 bit 4 is 1, 0-32K ROM is internal, and
32K~48K ROM is external using ROM_ADDR13:0 address outputs.
Table 18. Bootstrap Signals
4.16 Host Interface
A serial host interface is provided to allow an external device to peek and poke registers in
the gm5110/20. This is done using a 2-wire serial protocol. Note that 2-wire host interface
requires bootstrap settings as described in Table 18.
The 2-wire host interface is suitable for connection to a factory interrogation port. This is
illustrated in Figure 26. The factory test station connects to the gm5110/20 through the Direct
Data Channel (DDC) of the DSUB15 or DVI connectors. For example, the PC can make
gm5110/20 display test patterns (see section 4.5). A camera can be used to automate the
calibration of the LCD panel.
DDC
Factory Test Station
Device-Under-Test
Camera
Figure 26.
Factory Calibration and Test Environment
An arbitration mechanism ensures that register accesses from the OCM and the 2-wire host
interface port are always serviced (time division multiplexing).
June 2002
36
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
4.16.1 Host Interface Command Format
Transactions on the 2-wire host protocol occurs in integer multiples of bytes (i.e. 8 bits or
two nibbles respectively). These form an instruction byte, a device register address and/or
one or more data bytes. This is described in Table 19.
The first byte of each transfer indicates the type of operation to be performed by the
gm5110/20. The table below lists the instruction codes and the type of transfer operation. The
content of bytes that follow the instruction byte will vary depending on the instruction
chosen. By utilizing these modes effectively, registers can be quickly configured.
The two LSBs of the instruction code, denoted 'A9' and 'A8' in Table 19 below, are bits 9 and
8 of the internal register address respectively. Thus, they should be set to ‘00’ to select a
starting register address of less than 256, ‘01’ to select an address in the range 256 to 511,
and '10' to select an address in the range 512 to 767. These bits of the address increment in
Address Increment transfers. The unused bits in the instruction byte, denoted by 'x', should be
set to ‘1’.
Table 19. Instruction Byte Map
Bit
765432 1 0
0 0 0 1 x x A9 A8
0 0 1 0 x x A9 A8
Operation Mode
Write Address Increment
Write Address No Increment
(for table loading)
1 0 0 1 x x A9 A8
1 0 1 0 x x A9 A8
Read Address Increment
Read Address No Increment
(for table reading)
0 0 1 1 x x A9 A8
0 1 0 0 x x A9 A8
1 0 0 0 x x A9 A8
1 0 1 1 x x A9 A8
1 1 0 0 x x A9 A8
0 0 0 0 x x A9 A8
0 1 0 1 x x A9 A8
0 1 1 0 x x A9 A8
0 1 1 1 x x A9 A8
1 1 0 1 x x A9 A8
1 1 1 0 x x A9 A8
1 1 1 1 x x A9 A8
Reserved
Spare
Description
Allows the user to write a single or multiple bytes to a specified starting
address location. A Macro operation will cause the internal address pointer to
increment after each byte transmission. Termination of the transfer will cause
the address pointer to increment to the next address location.
Allows the user to read multiple bytes from a specified starting address
location. A Macro operation will cause the internal address pointer to
increment after each read byte. Termination of the transfer will cause the
address pointer to increment to the next address location.
No operation will be performed
4.16.2 2-wire Serial Protocol
The 2-wire protocol consists of a serial clock HCLK (pin number 204) and bi-directional
serial data line HFSn (pin number 205). The bus master drives HCLK and either the master
or slave can drive the HFSn line (open drain) depending on whether a read or write operation
is being performed. The gm5110/20 operates as a slave on the interface.
The 2-wire protocol requires each device be addressable by a 7-bit identification number.
The gm5110/20 is initialized on power-up to 2-wire mode by asserting bootstrap pins
HOST_PROTOCOL=0 and the device identification number on HOST_ADDR(6:0) on the
rising edge of RESETn (see Table 18). This provides flexibility in system configuration with
multiple devices that can have the same address.
June 2002
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C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
A 2-wire data transfer consists of a stream of serially transmitted bytes formatted as shown in
the figure below. A transfer is initiated (START) by a high-to-low transition on HFSn while
HCLK is held high. A transfer is terminated by a STOP (a low-to-high transition on HFSn
while HCLK is held high) or by a START (to begin another transfer). The HFSn signal must
be stable when HCLK is high, it may only change when HCLK is low (to avoid being
misinterpreted as START or STOP).
HCLK
1
2
3
4
5
6
7
8
9
1
2
8
9
HFSn
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
D7
D6
D0
ACK
START
STOP
DATA BYTE
ADDRESS BYTE
Receiver acknowledges by holding SDA low
Figure 27.
2-Wire Protocol Data Transfer
Each transaction on the HFSn is in integer multiples of 8 bits (i.e. bytes). The number of
bytes that can be transmitted per transfer is unrestricted. Each byte is transmitted with the
most significant bit (MSB) first. After the eight data bits, the master releases the HFSn line
and the receiver asserts the HFSn line low to acknowledge receipt of the data. The master
device generates the HCLK pulse during the acknowledge cycle. The addressed receiver is
obliged to acknowledge each byte that has been received.
The Write Address Increment and the Write Address No Increment operations allow one or
multiple registers to be programmed with only sending one start address. In Write Address
Increment, the address pointer is automatically incremented after each byte has been sent and
written. The transmission data stream for this mode is illustrated in Figure 28 below. The
highlighted sections of the waveform represent moments when the transmitting device must
release the HFSn line and wait for an acknowledgement from the gm5110/20 (the slave
receiver).
HCLK
1
2
HFSn
3
4
5
DEVICE ADDRESS
6
7
8
9
R/W ACK
START
1
2
3
4
5
6
OPERATION CODE
7
8
A9 A8
9
ACK
1
2
3
4
5
6
REGISTER ADDRESS
7
8
9
ACK
1
2
9
DATA
DATA
Figure 28.
ACK
STOP
Two MSBs of register address
2-Wire Write Operations (0x1x and 0x2x)
The Read Address Increment (0x90) and Read Address No Increment (0xA0) operations are
illustrated in Figure 29. The highlighted sections of the waveform represent moments when
the transmitting device must release the HFSn line and waits for an acknowledgement from
the master receiver.
June 2002
38
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
Note that on the last byte read, no acknowledgement is issued to terminate the transfer.
HCLK
HFSn
DEVICEADDRESS
R/W ACK
OPERATIONCODE
ACK
REGISTERADDRESS
ACK
DEVICEADDRESS
R/W ACK
DATA
DATA
ACK
DATA
START
START
Figure 29.
STOP
2-Wire Read Operation (0x9x and 0xAx)
Please note that in all the above operations the operation code includes two address bits, as
described in Table 19.
4.17 Miscellaneous Functions
4.17.1 Low Power State
The gm5110/20 provides a low power state in which the clocks to selected parts of the chip may
be disabled (see Table 21).
4.17.2 Pulse Width Modulation (PWM) Back Light Control
Many of today’s LCD back light inverters require both a PWM input and variable DC
voltage to minimize flickering (due to the interference between panel timing and inverter’s
AC timing), and adjust brightness. Most LCD monitor manufactures currently use a
microcontroller to provide these control signals. To minimize the burden on the external
microcontroller, the gm5110/20 generates these signals directly.
There are three pins available for controlling the LCD back light, PWM0 (GPIO0), PWM1
(GPIO1) and PWM2 (GPIO2). The duty cycle of these signals is programmable. They may
be connected to an external RC integrator to generate a variable DC voltage for a LCD back
light inverter. Panel HSYNC is used as the clock for a counter generating this output signal.
June 2002
39
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
5. ELECTRICAL SPECIFICATIONS
The following targeted specifications have been derived by simulation.
5.1 Preliminary DC Characteristics
Table 20. Absolute Maximum Ratings
PARAMETER
(1,2)
3.3V Supply Voltages
2.5V Supply Voltages (1.2)
Input Voltage (5V tolerant inputs) (1,2)
Input Voltage (non 5V tolerant inputs) (1,2)
Electrostatic Discharge
Latch-up
SYMBOL
MIN
VVDD_3.3
VVDD_2.5
VIN5Vtol
VIN
VESD
-0.3
-0.3
-0.3
-0.3
Storage Temperature
Operating Junction Temp.
Thermal Resistance (Junction to Air) Natural Convection (3)
gm5110
gm5120
(4)
Thermal Resistance (Junction to Case) Convection
gm5110
gm5120
Soldering Temperature (30 sec.)
Vapor Phase Soldering (30 sec.)
MAX
UNITS
3.6
2.75
5.5
3.6
V
V
V
V
kV
±2.0
TA
0
±100
70
TSTG
-40
125
°C
TJ
0
125
°C
θJA_5110
θJA_5120
32.4
22.0
°C/W
θJC_5110
θJC_5120
°C/W
TSOL
13.9
10.1
220
TVAP
220
°C
ILA
Ambient Operating Temperature
TYP
mA
°C
NOTE (1): All voltages are measured with respect to GND
NOTE (2): Absolute maximum voltage ranges are for transient voltage excursions.
NOTE (3): Package thermal resistance is based on a PCB with one signal plane and two power planes. Package θJA is improved on a PCB with
four or more layers
NOTE (4): Based on the figures for the Operating Junction Temperature, θJC and Power Consumption in Table 21, the typical case temperature
is calculated as TC = TJ - P x θJC. This equals 104 degrees Celsius for gm5110 and 106 degrees Celsius for gm5120.
June 2002
40
C5110-DAT-01C
°C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
Table 21. DC Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
POWER
Power Consumption @ 96 MHz (gm5110)
Power Consumption @ 135 MHz (gm5120)
Power Consumption @ Low Power Mode (1)
3.3V Supply Voltages (AVDD and RVDD)
2.5V Supply Voltages (VDD and CVDD)
Supply Current @ CLK = 96 MHz (gm5110)
• 2.5V digital supply (2)
(3)
• 2.5V analog supply
(4)
• 3.3V digital supply
(5)
• 3.3V analog supply
Supply Current @ CLK =135MHz (gm5120)
• 2.5V digital supply (2)
(3)
• 2.5V analog supply
(4)
• 3.3V digital supply
(5)
• 3.3V analog supply
Supply Current @ Low Power Mode*
P5110
P5120
PLP
VVDD_3.3
VVDD_2.5
I5110
3.15
2.35
1.5
1.8
0.15
3.3
2.5
400
3.45
2.65
W
W
W
V
V
mA
360(6)
(6)
40
50(6)
150(6)
I5110_2.5_VDD
I5110_2.5_AVDD
I5110_3.3_VDD
I5110_3.3_AVDD
I5120
I5120_2.5_VDD
I5120_2.5_AVDD
I5120_3.3_VDD
I5120_3.3_AVDD
500
ILP
50
mA
500(6)
50(6)
60(6)
150(6)
mA
INPUTS
High Voltage
Low Voltage
Clock High Voltage
Clock Low Voltage
High Current (VIN = 5.0 V)
Low Current (VIN = 0.8 V)
Capacitance (VIN = 2.4 V)
VIH
VIL
VIHC
VILC
IIH
IIL
CIN
High Voltage (IOH = 7 mA)
Low Voltage (IOL = -7 mA)
Tri-State Leakage Current
VOH
VOL
IOZ
2.0
GND
2.4
GND
-25
-25
VDD
0.8
VDD
0.4
25
25
8
V
V
V
V
µA
µA
pF
2.4
GND
-25
VDD
0.4
25
V
V
µA
OUTPUTS
NOTE (1): Low power figures result from setting the ADC, DVI, and clock power down bits so that only the micro-controller is running.
NOTE (2): Includes pins CVDD_2.5, VDD1_ADC_2.5, VDD2_ADC_2.5, VDD_RX0_2.5, VDD_RX1_2.5 and VDD_RX2_2.5.
NOTE (3): Includes only VDD_RXPLL_2.5.
NOTE (4): Includes pins VDD_DPLL, VDD_SDDS, VDD_DDDS and RVDD.
NOTE (5): Includes pins AVDD_RED, AVDD_GREEN, AVDD_BLUE, AVDD_IMB, AVDD_RX0, AVDD_RX1, AVDD_RX2,
AVDD_RXC, AVDD_RPLL, AVDD_SDDS and AVDD_DDDS.
NOTE (6): Maximum current figures are provided for the purposes of selecting an appropriate power supply circuit.
5.2 Preliminary AC Characteristics
The following targeted specifications have been derived by simulation.
All timing is measured to a 1.5V logic-switching threshold. The minimum and maximum
operating conditions used were: TDIE = 0 to 125° C, Vdd = 2.35 to 2.65V, Process = best to worst, CL =
16pF for all outputs.
June 2002
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C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
Table 22. Maximum Speed of Operation
Clock Domain
Main Input Clock (TCLK)
DVI Differential Input Clock
ADC Clock (ACLK)
HCLK Host Interface Clock (6-wire protocol)
Input Format Measurement Clock (IFM_CLK)
Reference Clock (RCLK)
On-Chip Microcontroller Clock (OCM_CLK)
Display Clock (DCLK)
Max Speed of Operation
24 MHz (14.3MHz recommended)
165MHz
162.5MHz
5 MHz
50MHz (14.3MHz recommended)
200MHz (200MHz recommended)
100 MHz
135 MHz
Table 23. Display Timing and DCLK Adjustments
DP_TIMING ->
Propagation delay from DCLK to DA*/DB*
Propagation delay from DCLK to DHS
Propagation delay from DCLK to DVS
Propagation delay from DCLK to DEN
Tap 0 (default)
Min
Max
(ns)
(ns)
1.0
4.5
1.0
4.5
0.5
4.5
1.0
4.5
Tap 1
Min
Max
(ns)
(ns)
0.5
3.5
0.5
3.5
0.0
3.5
0.5
3.5
Tap 2
Min
Max
(ns)
(ns)
-0.5
2.5
-0.5
2.5
-1.0
2.5
-0.5
2.5
Tap 3
Min
Max
(ns)
(ns)
-1.5
1.5
-1.5
1.5
-2.0
1.5
-1.5
1.5
Note: DCLK Clock Adjustments are the amount of additional delay that can be inserted in the DCLK path, in order to reduce the propagation
delay between DCLK and its related signals.
Table 24. 2-Wire Host Interface Port Timing
Parameter
SCL HIGH time
SCL LOW time
SDA to SCL Setup
SDA from SCL Hold
Propagation delay from SCL to SDA
Symbol
MIN
TSHI
TSLO
TSDIS
TSDIH
TSDO3
1.25
1.25
30
20
10
TYP
MAX
Units
150
us
us
ns
ns
ns
Note: The above table assumes OCM_CLK = R_CLK / 2 = 100 MHz (default) (ie 10ns / clock)
June 2002
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C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
6. ORDERING INFORMATION
Order Code
Application
Package
Temperature
Range
gm5110
XGA
208-pin PQFP
0-70°C
XGA
208-pin PQFP
0-70°C
SXGA
208-pin PQFP
0-70°C
SXGA
208-pin PQFP
0-70°C
gm5110-H
(1)
gm5120
gm5120-H
(1)
Note (1): gm5110-H and gm5120-H versions will only be sold to HDCP licensed customers.
June 2002
43
C5110-DAT-01C
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
7. MECHANICAL SPECIFICATIONS
Figure 30.
gm5110/gm5120 208-pin PQFP Mechanical Drawing
HD
D
208
157
E
HE
156
1
105
52
53
e
104
c
A1
A2
A
b
See Detail A
y
Seating Plane
L
L1
Detail A
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
0
June 2002
Dimension in mm
Min
Nom
3.92
Max
4.07
0.25
3.15
3.23
0.18
0.28
0.23
0.13
27.90
27.90
3.30
28.00
28.10
28.00
28.10
0.50 BSC
30.95
31.20
31.45
30.95
31.20
31.45
0.65
0.80
0.95
1.60 REF
0.10
0
7
44
C5110-DAT-01C