GM71V16163C GM71VS16163CL 1,048,576 WORDS x 16 BIT CMOS DYNAMIC RAM Description Features The GM71V(S)16163C/CL is the new generation dynamic RAM organized 1,048,576 x 16 bit. GM71V(S)16163C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71V(S)16163C/CL offers Extended Data out(EDO) Mode as a high speed access mode. Multplexed address inputs permit the GM71V(S)16163C/CL to be packaged in standard 400 mil 42pin plastic SOJ, and standard 400mil 44(50)pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. * 1,048,576 Words x 16 Bit Organization * Extended Data Out Mode Capability * Single Power Supply (3.3V+/-0.3V) * Fast Access Time & Cycle Time (Unit: ns) Pin Configuration 42 SOJ VCC 1 42 VSS 2 41 3 40 I/O15 I/O14 I/O2 I/O3 4 39 5 38 I/O13 I/O12 VCC 6 37 VSS I/O4 I/O5 7 36 8 35 I/O11 I/O10 I/O6 I/O7 NC 9 34 10 33 I/O9 I/O8 11 32 NC 12 31 13 30 LCAS UCAS RAS 14 29 OE A11 A10 A0 15 28 16 27 17 26 A9 A8 A7 A1 A2 A3 VCC 18 25 19 24 20 23 21 22 A6 A5 A4 VSS 50 60 70 80 13 15 18 20 84 104 124 144 tHPC 20 25 30 35 * Low Power Active : 396/360/324/288mW (MAX) Standby : 7.2mW (MAX) 0.83mW (L-series : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 4096 Refresh Cycles/64ms * 4096 Refresh Cycles/128ms (L-series) * Self Refresh Operation (L-version) * Battery Back Up Operation (L-series) * 2 CAS byte Control VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC (Top View) Rev 0.1 / Apr’01 GM71V(S)16163C/CL-5 GM71V(S)16163C/CL-6 GM71V(S)16163C/CL-7 GM71V(S)16163C/CL-8 44(50) TSOP II I/O0 I/O1 NC WE tRAC tCAC tRC 1 50 2 49 3 48 4 47 5 46 6 45 7 44 8 43 9 42 10 41 11 40 NC NC 15 36 16 35 WE RAS A11 A10 A0 A1 A2 A3 VCC 17 34 18 33 19 32 20 31 21 30 22 29 23 28 24 27 25 26 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS GM71V16163C GM71VS16163CL Pin Description Pin Function Pin Function A0-A11 Address Inputs WE Write Enable A0-A11 Refresh Address Inputs OE Output Enable Data-In/Out VCC Power (+3.3V) RAS Row Address Strobe VSS Ground CAS Column Address Strobe NC No Connection I/O0-I/O15 Ordering Information Type No. Access Time Package GM71V(S)16163CJ/CLJ -5 GM71V(S)16163CJ/CLJ -6 GM71V(S)16163CJ/CLJ -7 GM71V(S)16163CJ/CLJ -8 50ns 60ns 70ns 80ns 400 Mil 42 Pin Plastic SOJ GM71V(S)16163CT/CLT -5 GM71V(S)16163CT/CLT -6 GM71V(S)16163CT/CLT -7 GM71V(S)16163CT/CLT -8 50ns 60ns 70ns 80ns 400 Mil 44(50) Pin Plastic TSOP II (Normal Type) Absolute Maximum Ratings* Symbol Parameter Rating Unit 0 ~ 70 C -55 ~ 125 C -0.5 ~ Vcc+0.5 (<=4.6V(MAX)) V -0.5 ~ 4.6 V TA Ambient Temperature under Bias TSTG Storage Temperature VT Voltage on any Pin Relative to VSS VCC Supply Voltage Relative to VSS IOUT Short Circuit Output Current 50 mA PT Power Dissipation 1.0 W Recommended DC Operating Conditions (TA = 0 ~ 70C) Symbol Parameter Min Typ Max Unit VCC Supply Voltage 3.0 3.3 3.6 V VIH Input High Voltage 2.0 - VCC + 0.3 V VIL Input Low Voltage -0.3 - 0.8 V *Note: All voltage referred to Vss. Rev 0.1 / Apr’01 GM71V16163C GM71VS16163CL Truth Table RAS LCAS UCAS WE OE Output H D D D D Open L L H H L Valid Lower byte L H L H L Valid Upper byte L L L H L Valid Word L L H L D Open Lower byte L H L L D Open Upper byte L L L L D Open Word L L H L H Undefined Lower byte L H L L H Undefined Upper byte L L L L H Undefined Word L L H H to L L to H Valid Lower byte L H L H to L L to H Valid Upper byte L L L H to L L to H Valid Word H to L H L D D Open Word H to L L H D D Open Word H to L L L D D Open Word L H H D D Open Word L L L H H Open Operation Standby 1,3 Read cycle 1,3 Early write cycle 1,2,3 Delayed Write cycle 1,2,3 Read-modify -write cycle 1,3 CBR Refresh or Self Refresh (L-series) 1,3 LAS-only Refresh cycle 1,3 Read cycle (Output disabled) Notes: 1. H: High (inactive) L: Low(active) D: H or L 2. tWCS >= 0ns Early write cycle tWCS < 0ns Delayed write cycle 3. Mode is determined by the OR fuction of the UCAS and LCAS. (Mode is set by earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edgs.) However write OPERATION and output HIZ control are done independently by each UACS,LCAS. ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected. Rev 0.1 / Apr’01 Notes 1,3 GM71V16163C GM71VS16163CL DC Electrical Characteristics (VCC = 3.3V+/-0.3V, Vss = 0V, TA = 0 ~ 70C) Symbol Parameter Min Max Unit VOH Output Level Output "H" Level Voltage (IOUT = -2mA) 2.4 VCC V VOL Output Level Output "L" Level Voltage (IOUT = 2mA) 0 0.4 V ICC1 Operating Current Average Power Supply Operating Current (RAS, CAS Cycling: tRC = tRC min) - 110 100 90 80 mA - 2 mA - - 110 100 90 80 105 95 85 75 - 1 mA - 150 uA 50ns - 110 60ns - 100 70ns - ICC2 ICC3 ICC4 ICC5 ICC6 50ns 60ns 70ns 80ns Standby Current (TTL) Power Supply Standby Current (RAS, CAS = VIH, DOUT = High-Z) RAS Only Refresh Current Average Power Supply Current RAS Only Refresh Mode (tRC = tRC min) EDO Page Mode Current Average Power Supply Current EDO Page Mode (tHPC = tHPC min) 50ns 60ns 70ns 80ns 50ns 60ns 70ns 80ns Standby Current (CMOS) Power Supply Standby Current (RAS, CAS >VCC - 0.2V, Dout = High-Z) CAS-before-RAS Refresh Current (tRC = tRC min) - 80ns ICC7 ICC8 ICC9 Standby Current RAS = VIH CAS = VIL DOUT = Enable Battery Back Up Operating Current(Standby with CBR Ref.) (CBR refresh, tRC=31.3us, tRAS<=0.3us, DOUT=High-Z,CMOS interface) Self-Refresh Mode Current (RAS, CAS<=0.2V, DOUT=High-Z, CMOS interface) Note 1, 2 mA 2 mA 1, 3 5 mA 90 80 - 5 mA 1 - 400 uA 4,5 - 250 uA 5 ILI Input Leakage Current Any Input (0V<=VIN<= 4.6V) -10 10 uA ILO Output Leakage Current (DOUT is Disabled, 0V<=VOUT<= 4.6V) -10 10 uA Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L (<=0.2V) while RAS = L (<=0.2V). 5. L - Series. Rev 0.1 / Apr’01 GM71V16163C GM71VS16163CL Capacitance (VCC = 3.3V+/-0.3V, TA = 25C) Symbol Parameter Min Max Unit Note CI1 Input Capacitance (Address) - 5 pF 1 CI2 Input Capacitance (Clocks) - 7 pF 1 CI/O Output Capacitance (Data-In/Out) - 7 pF 1, 2 Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable DOUT. AC Characteristics (VCC = 3.3V+/-0.3V, TA = 0 ~ +70C, Vss = 0V) Note 1, 2, 18, 19, 20 Test Conditions Input rise and fall times : 2 ns Input timing reference levels : 0.8V, 2.0V Output timing reference levels : 0.8V, 2.0V Output load : 1TTL gate + CL (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Symbol Parameter GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 C/CL-6 C/CL-7 C/CL-5 C/CL-8 Unit Note Min Max Min Max Min Max Min Max tRC Random Read or Write Cycle Time 84 - 104 - 124 - 144 - ns tRP RAS Precharge Time 30 - 40 - 50 - 60 - ns tCP CAS Precharge Time 8 - 10 - 13 - 15 - ns tRAS RAS Pulse Width 50 10,000 60 10,000 70 10,000 80 10,000 ns tCAS CAS Pulse Width 8 10,000 10 10,000 13 10,000 15 10,000 ns tASR Row Address Set up Time 0 - 0 - 0 - 0 - ns tRAH Row Address Hold Time 8 - 10 - 10 - 10 - ns tASC Column Address Set-up Time 0 - 0 - 0 - 0 - ns 21 tCAH tRCD tRAD tRSH tCSH Column Address Hold Time 8 - 10 - 13 - 15 - ns 21 RAS to CAS Delay Time 12 37 14 45 14 52 20 60 ns 3 RAS to Column Address Delay Time 10 25 12 30 12 35 15 40 ns 4 RAS Hold Time 10 - 13 - 13 - 18 - ns CAS Hold Time 35 - 40 - 45 - 50 - ns 23 tCRP tOED CAS to RAS Precharge Time 5 - 5 - 5 - 5 - ns 22 13 - 15 - 18 - 20 - ns 5 tDZO tDZC tT OE Delay Time from DIN 0 - 0 - 0 - 0 - ns 6 CAS Delay Time from DIN 0 - 0 - 0 - 0 - ns 6 TransitionTime (Rise and Fall) 2 50 2 50 2 50 2 50 ns 7 OE to DIN Delay Time Rev 0.1 / Apr’01 GM71V16163C GM71VS16163CL Read Cycle Symbol Parameter GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 C/CL-5 C/CL-6 C/CL-7 C/CL-8 Min Max Unit Note Min Max Min Max Min Max tRAC Access Time from RAS - 50 - 60 - 70 - 80 ns 8,9 tCAC Access Time from CAS - 13 - 15 - 18 - 20 ns 9,10,17 tAA Access Time from Address - 25 - 30 - 35 - 40 ns 9,11,17 tOEA Access Time from OE - 13 - 15 - 18 - 20 ns 9 tRCS Read Command Setup Time 0 - 0 - 0 - 0 - ns 21 tRCH Read Command Hold Time to CAS 0 - 0 - 0 - 0 - ns 12,22 tRRH tRAL Read Command Hold Time to RAS 5 - 5 - 5 - 5 - ns Column Address to RAS Lead Time 25 - 30 - 35 - 40 - ns tCAL Column Address to CAS Lead Time 15 - 18 - 23 - 28 - ns tCLZ CAS to Output in Low-Z 0 - 0 - 0 - 0 - ns tOH Output Data Hold Time 3 - 3 - 3 - 3 - ns tOHO Output Data Hold Time from OE 3 - 3 - 3 - 3 - ns tOFF Output Buffer Turn-off Time - 13 - 15 - 15 - 15 ns 13,27 tOEZ Output Buffer Turn-off Time to OE - 13 - 15 - 15 - 15 ns 13 tCDD CAS to DIN Delay Time 13 - 15 - 18 - 20 - ns 5 tRCHR Read Command Hold Time from RAS 50 - 60 - 70 - 80 - ns tOHR Output Data hold Time from RAS 3 - 3 - 3 - 3 - ns 27 tOFR Output Buffer turn off to RAS - 13 - 15 - 15 - 15 ns 27 tWEZ Output Buffer turn off to WE - 13 - 15 - 15 - 15 ns tWED WE to DIN Deray Time 13 - 15 - 18 - 20 - ns tROD RAS to DIN Delay Time 13 - 15 - 18 - 20 - ns Rev 0.1 / Apr’01 12 27 GM71V16163C GM71VS16163CL Write Cycle Symol Parameter GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 C/CL-5 C/CL-6 C/CL-7 C/CL-8 Unit Note Min Max Min Max Min Max Min Max tWCS Write Command Setup Time 0 - 0 - 0 - 0 - ns 14,21 tWCH Write Command Hold Time 8 - 10 - 13 - 15 - ns 21 tWP Write Command Pulse Width 8 - 10 - 10 - 10 - ns tRWL Write Command to RAS Lead Time 8 - 10 - 13 - 15 - ns tCWL Write Command to CAS Lead Time 8 - 10 - 13 - 15 - ns 23 tDS tDH Data-in Setup Time 0 - 0 - 0 - 0 - ns 15,23 Data-in Hold Time 8 - 10 - 13 - 15 - ns 15,23 Read- Modify-Write Cycle Symbol Parameter GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 C/CL-5 C/CL-6 C/CL-7 C/CL-8 Unit Note Min Max Min Max Min Max Min Max tRWC Read-Modify-Write Cycle Time tRWD 111 - 136 - 161 - 185 - ns RAS to WE Delay Time 67 - 79 - 92 - 104 - ns 14 tCWD CAS to WE Delay Time 30 - 34 - 40 - 44 - ns 14 tAWD Column Address to WE Delay Time 42 - 49 - 57 - 64 - ns 14 tOEH OE Hold Time from WE 13 - 15 - 18 - 20 - ns Rev 0.1 / Apr’01 GM71V16163C GM71VS16163CL Refresh Cycle Symbol Parameter GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 C/CL-5 C/CL-6 C/CL-7 C/CL-8 Unit Note Min Max Min Max Min Max Min Max tCSR CAS Setup Time (CAS-before-RAS Refresh Cycle) 5 - 5 - 5 - 5 - ns 21 tCHR CAS Hold Time (CAS-before-RAS Refresh Cycle) 8 - 10 - 10 - 10 - ns 22 tWRP WE Setup Time (CAS-before-RAS Refresh Cycle) 0 - 0 - 0 - 0 - ns tWRH WE Hold Time (CAS-before-RAS Refresh Cycle) 10 - 10 - 10 - 10 - ns tRPC RAS Precharge to CAS Hold Time 5 - 5 - 5 - 5 - ns 21 EDO Page Mode Cycle Symbol Parameter GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 C/CL-5 C/CL-6 C/CL-7 C/CL-8 Unit Note Min Max Min Max Min Max Min Max tHPC EDO Page Mode Cycle Time tRASP EDO Page Mode RAS Pulse Width - tACP Access Time from CAS Precharge - 30 - 35 - 40 - tRHCP RAS Hold Time from CAS Precharge 30 - 35 - 40 - tDOH Output data Hold Time from CAS low 3 - 3 - tCOL CAS Hold Time referred OE 8 - 10 tCOP CAS to OE Setup Time 5 - tRCHP Read command Hold Time from CAS Precharge 30 - Rev 0.1 / Apr’01 20 100,000 25 ns 25 ns 16 45 ns 9,17,22 45 - ns 3 3 - ns - 13 15 - ns 5 - 5 5 - ns 35 - 40 45 - ns - 100,000 30 - 100,000 35 - 100,000 9 GM71V16163C GM71VS16163CL EDO Page Mode Read-Modify-Write Cycle Symbol GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 C/CL-6 C/CL-7 C/CL-8 C/CL-5 Parameter Unit Note Min Max Min Max Min Max Min Max tHPRWC EDO Page Mode Read-Modify-Write Cycle Time 57 - 68 - 79 - 88 - ns tCPW WE Delay Time from CAS Precharge 45 - 54 - 62 - 69 - ns 14,22 Refresh Symbol Parameter GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 C/CL-6 C/CL-7 C/CL-8 C/CL-5 Unit Note Min Max Min Max Min Max Min Max tREF Refresh period - 64 - 64 - 64 - 64 ms 4096 cycles tREF Refresh period (L -Series) - 128 - 128 - 128 - 128 ms 4096 cycles Self Refresh Mode ( L-version ) GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 C/CL-5 C/CL-6 C/CL-7 C/CL-8 Symbol Parameter Min Max tRASS RAS Pulse Width(Self-Refresh) tRPS tCHS Unit Note Min Max Min Max Min Max 100 - 100 - 100 - 100 - us RAS Precharge Time(Self-Refresh) 90 - 110 - 130 - 150 - ns CAS Hold Time(Self-Refresh) -50 - -50 - -50 - -50 - ns Rev 0.1 / Apr’01 29 GM71V16163C GM71VS16163CL Notes: 1. AC measurements assume tT = 5ns. 2. An intial pause of 200us is required after power up followd by a minimum of eight initialization cycles(any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD(max)limit insures that tRAC(max)can be met, tRCD(max)is specified as a reference point only; if tRCD >= tRAD(max) + tAA(max) - tCAC(max), then access time is controlled exclusively by tCAC. 4. Operation with the tRAD(max) limit insures that tRAC(max)can be met, tRAD(max)is specified as a reference point only; if tRAD is greater than the specified tRAD(max)limit, then access time is controlled exclusively by tAA. 5. Either tOED or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH(min) and VIL(max). 8. Assumes that tRCD <= tRCD(max) and tRAD <= tRAD(max). If tRCD ot tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL load and 100pF. 10. Assumes that tRCD >= tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max). 11. Assumes that tRAD >= tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operationg parameters. They are included in the data sheet as electrical characteristics only; if tWCS >= tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedence) throughout the entire cycle ; if tRWD >= tRWD(min), tCWD >=tCWD(min), and tAWD >= tAWD(min), or tCWD >= tCWD(min),tAWD >= tAWD(min) and tCPW >= tCPW(min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of data out (at access time)is indeterminate. 15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. tRASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among tAA,tCAC,and tACP. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH >= tCWL, the I/O pin will remain open circuit (high impedence); if tOEH< tCWL, invalid data will be out at each I/O. 19. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 20. All the VCC and VSS pins shall be supplied with the same voltages. Rev 0.1 / Apr’01 GM71V16163C GM71VS16163CL 21. tASC, tCAH, tRCS, tWCS,tWCH,tCSR and tRPC are determined by the earlier falling edge of UCAS or LCAS. 22. tCRP,tCHR, tRCH, tACP and tCPW are determned by the later rising edge of UCAS or LCAS. 23. tCWL, tDH,tDS and tCSH should be satisfied by both UCAS and LCAS. 24. tCP is determined by that time the both UCAS and LCAS are high. 25. When output buffers are enabled once, sustain the low impedence state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 26. Please do not use tRASS timing, 10us <= tRASS <=100us. During this period, the device is in transition state from normal operation mode to self refresh mode. If tRASS >=100us, then RAS precharge time should use tRPS instead of tRP. 27. If you use distributed CBR refresh within 15.6us inteval in normal read/write cycle, CBR refresh should be executed within 15.6us immediately after exiting from and before entering into self refresh mode. 28. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle,4096 or 1024 cycles of distributed CBR refresh with 15.6us interval should be executed within 64 or 16ms immediately after exiting from and before entering into the self refresh mode. 29. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 30. H or L (H: VIH(min) <= VIN <= VIH(max), L: VIL(min) <= VIN <= VIL(max)) Rev 0.1 / Apr’01 GM71V16163C GM71VS16163CL Notes concerning 2CAS control Please do not separate the UCAS / LCAS operation timing intentionally. However skew between UCAS / LCAS are allowed under the following conditions. 1. Each of the UCAS / LCAS should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed;such as following. RAS Delayed write UCAS Early write LCAS WE 3. Closely separated upper/lower byte control is not allowed. However when the condition (tcp < tUL)is satisfied,EDO page mode can be performed. RAS UCAS LCAS tUL 4. Byte control operation by remaining UCAS or LCAS high is guaranteed. Rev 0.1 / Apr’01 GM71V16163C GM71VS16163CL Package Dimensions Unit : Inches (mm) 42 SOJ 1.058(26.89) MIN 1.072(27.23) MAX 0.360(9.15) MIN 0.093(2.38) MIN 0.128(3.25) MIN 0.148(3.75) MAX 0.050(1.27) TYP 0.015(0.38) MIN 0.020(0.50) MAX 0.026(0.66) MIN 0.032(0.81) MAX 44(50) TSOP (TYPE II) o 0.471(11.96) MAX 0.016(0.40) MIN 0.024(0.60) MAX 0.445(11.56) MIN 0.405(10.29) MAX 0.394(10.03) MIN 0~5 0.819(20.82) MIN 0.829(21.08) MAX 0.037(0.95) MIN 0.041(1.05) MAX 0.047(1.20) MAX 0.011(0.30) MIN 0.017(0.45) MAX Rev 0.1 / Apr’01 0.031(0.80 ) TYP 0.001(0.05) MIN 0.005(0.15) MAX 0.004(0.12) MIN 0.008(0.21) MAX 0.380(9.65) MAX 0.435(11.05) MIN 0.445(11.30) MAX 0.395(10.03) MIN 0.405(10.29) MAX 0.025(0.64) MIN