GENNUM GS1503

GS1503
HD EMBEDDED AUDIO CODEC
DATA SHEET
DESCRIPTION
• complies with SMPTE 292M and SMPTE 299M
The GS1503 is a highly integrated, single chip solution for
embedding/extracting digital audio streams into and out of
high definition digital video signals. The GS1503 supports
insertion/extraction of 24-bit synchronous audio data with a
48kHz sample rate. Audio signals with different sample
rates may be converted to 48kHz by using audio sample
rate converters before or after the GS1503.
• single chip HD embedded audio solution
• operates as an embedded audio multiplexer or
demultiplexer
• full support for 48kHz synchronous 24-bit audio
• support for 8 channels of audio per device
• cascadable architecture supports up to 16 audio channels
• integrated scrambler/descrambler and word alignment
• CRC error detection and insertion
• audio control packet insertion and extraction
• arbitrary data packet insertion and extraction
Each GS1503 supports all processing required for
embedding/extracting up to eight digital audio channels in
the horizontal ancillary data space of the video chroma
channel. Two GS1503’s can be cascaded for insertion/
extraction of up to 16 audio channels with no external glue
logic.
• 3.3V power supply with 5V tolerant I/O
The GS1503 supports embedding/extracting of audio
control and arbitrary data packets in the horizontal ancillary
data space of the video luma channel. It also supports line
CRC detection and insertion.
• 144 pin LQFP package
APPLICATIONS
HD SDI Embedded Audio
The GS1503 supports HD video standards at 74.25MHz
and 74.25/1.001MHz rates. It has an on chip SMPTE
compliant scrambler/de-scrambler, and integrated word
alignment. Use the GS1503 with Gennum’s GS1545 or
GS1522 for two chip HD SDI receive or transmit solutions.
ORDERING INFORMATION
PART NUMBER
PACKAGE
TEMPERATURE
GS1503-CFZ
144 pin LQFP
0°C to 70°C
The GS1503 operates from a single 3.3V power supply with
5V tolerant I/O and is packaged in a 144 pin LQFP
package.
DSCBYPASS
VIN[19:0]
VM[3:0]
CPUADR[8:0]
CPUDAT[7:0]
CPUCS, CPUWE,
CPURE
PKT[7:0]
PKTEN
AIN1/2
AIN3/4
AIN5/6
AIN7/8
WCINA/B
20
EXTH
De-scrambler &
Word Alignment
EXTF
SCRBYPASS
20
20
TRS
Inserter
20
CRC Inserter &
Scrambler
Video Detection &
Synchronization
4
9
Host
Interface
8
3
8
ANCI Timing
Generation
20
4
Control
Packet
Mux
HOST INTERFACE
Arbitrary
Packet
Mux
HOST INTERFACE
VOUT[19:0]
VIDEO_DET
OPERATE
ERROR
CRC_ERR
PKTENO
4
Audio
Input
Interface
2
Audio
Packet
Mux
2
AM[1:0]
MUTE
MULTIPLEX MODE BLOCK DIAGRAM
Revision Date: May 2005
Document No. 15879 - 4
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
GS1503
FEATURES
DSCBYPASS
VIN[19:0]
VM[3:0]
20
ANCI
De-scrambler &
Word Alignment
SCRBYPASS
Delete
ANCI
20
Video Detection &
Synchronization
4
PKT[7:0]
PKTEN
HOST INTERFACE
HOST INTERFACE
AOUT1/2
AOUT3/4
AOUT5/6
AOUT7/8
4
Audio
Packet
Demux
Host
Interface
3
CPUCS, CPUWE,
CPURE
VIDEO_DET
OPERATE
ERROR
CRC_ERR
8
9
8
VOUT[19:0]
Audio
Output
Interface
2
WCOUTA/B
2
AM[1:0]
MUTE
DEMULTIPLEX MODE BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
Supply Voltage
-0.3V to 4.0V
Input Voltage (any input)
-0.3 to 5.5V
Operating Temperature
0°C to 70°C
Storage temperature
-65°C to 150°C
Lead Temperature (soldering, 10 sec.)
230°C
DC ELECTRICAL CHARACTERISTICS
TA = 0°C to 70°C unless otherwise shown.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3.0
3.3
3.6
V
Supply Voltage
VDD
3.3V operating range
Supply Current
IDD
VDD = 3.3V
Input Current
IIN
-1
-
1
µA
Hi-Z Output Leakage Current
IOZ
-1
-
1
µA
Output Voltage, Logic High
VOH
IOH = -12mA
VDD-0.4
-
-
V
Output Voltage, Logic Low
VOL
IOL = 12mA
-
-
0.4
V
Input Voltage, Logic High
VIH
TTL Level
2.0
-
-
V
Input Voltage, Logic Low
VIL
TTL Level
-
-
0.8
V
Input Capacitance
CI
f = 1MHz, VDD = 0V
-
-
10
pF
Output Capacitance
CO
f = 1MHz, VDD = 0V
-
-
10
pF
I/O Capacitance
CIO
f = 1MHz, VDD = 0V
-
-
10
pF
270
mA
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GS1503
Arbitrary
Packet
Demux
Control
Packet
Demux
CPUDAT[7:0]
20
4
ANCI Timing
Generation
CPUADR[8:0]
CRC Inserter &
Scrambler
20
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V ± 5%, TA = 0°C to 70°C unless otherwise shown.
PARAMETER
SYMBOL
CONDITIONS
Video Clock Frequency
MIN
TYP
MAX
UNITS
-
74.25
80
MHz
tVPWL
5.0
-
-
ns
Video Clock Pulse Width High
tVPWH
5.0
-
-
ns
Video Input Data Setup Time
tVS
3.5
-
-
ns
Video Input Data Hold Time
tVH
1.0
-
-
ns
Video Output Data Delay Time
tVOD
With 10pF loading
-
-
8.5
ns
Video Output Data Hold Time
tVOH
With 10pF loading
1.0
-
-
ns
-
6.144
-
MHz
Audio Clock Frequency
GS1503
Video Clock Pulse Width Low
Audio Clock Pulse Width Low
tAPWL
60
-
-
ns
Audio Clock Pulse Width High
tAPWH
60
-
-
ns
Audio Input Data Setup Time
tAS
10.5
-
-
ns
Audio Input Data Hold Time
tAH
1.0
-
-
ns
Audio Output Data Delay Time
tAOD
With 10pF loading
-
-
20.0
ns
Audio Output Data Hold Time
tAOH
With 10pF loading
1.0
-
-
ns
1
-
-
ms
Multiplexer Mode
53
53
53
PCLKs
Demultiplexer Mode
53
53
53
Reset Pulse Width
tRESET
Device Latency
t VS
t VH
VCLK
Data*
* VIN[19:0],
EXTF, EXTH, PKTEN, PKT[7:0]
Fig. 1 Video Data Input Setup & Hold Time
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t VOH
t VOD
VCLK
GS1503
Data*
* VOUT[19:0], EXTF, EXTH, PKTEN, PKT[7:0]
Fig. 2 Video Data Output Delay & Hold Time
t AS
t AH
ACLKA/B
Data*
* WCINA, AIN1/2, AIN3/4, WCINB, AIN5/6, AIN7/8
Fig. 3 Audio Data Input Setup & Hold Time
t AOH
t AOD
ACLKA/B
Data*
* AOUT1/2, AOUT3/4, AOUT5/6, AOUT7/8
Fig. 4 Audio Data Output Delay & Hold Time
VDD(min)
VDD
t RESET
t RESET
RESET
Fig. 5 Reset Timing
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HOST INTERFACE
Mode A (CPU_SEL set HIGH)
PARAMETER
MIN
TYP
MAX
UNITS
Read Cycle Time
1
50
-
-
ns
Read Chip Select Setup Time
2
0
-
-
ns
Read Address Setup Time
3
15
-
-
ns
Read Data Output Delay Time
4
-
-
15
ns
Read Data Hold Time
5
0
-
-
ns
Write Cycle Time
6
50
-
-
ns
Write Chip Select Setup Time
7
10
-
-
ns
Write Address Setup Time
8
10
-
-
ns
Write Data Setup Time
9
10
-
-
ns
Write Data Hold Time
10
0
-
-
ns
Read Cycle
CPUADR[8:0]
GS1503
NUMBER
Write Cycle
1
6
Address
Address
2
7
CPUCS
CPURE
3
CPUWE
8
Valid Data
CPUDAT[7:0]
4
Valid Data
5
9
10
Fig. 6 Host Interface Mode A Timing (CPU_SEL set HIGH)
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Mode B Read Cycle (CPU_SEL set LOW)
PARAMETER
MIN
TYP
MAX
UNITS
Read Address Cycle Time
1
80
-
-
ns
Read Cycle Time
2
80
-
-
ns
Read Enable Setup Time
3
20
-
-
ns
Read Address Setup Time
4
20
-
-
ns
Read Chip Select Setup Time
5
10
-
-
ns
Read Chip Select Hold Time
6
0
-
-
ns
Read Data Output Delay Time
7
-
-
10
ns
Read Data Hold Time
8
0
-
-
ns
CPUADR[1:0]
1
1
2
01
00
11
GS1503
NUMBER
8
Upper Address
CPUDAT[7:0]
Read
Data
Lower Address
7
CPUCS
CPUWE
5
5
4
4
3
6
5
6
3
6
3
Fig. 7 Host Interface Mode B Read Cycle Timing (CPU_SEL set LOW)
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Mode B Write Cycle (CPU_SEL set LOW)
PARAMETER
MIN
TYP
MAX
UNITS
Write Address Cycle Time
1
80
-
-
ns
Write Cycle Time
2
80
-
-
ns
Write Enable Setup Time
3
20
-
-
ns
Write Address Setup Time
4
20
-
-
ns
Write Chip Select Setup Time
5
10
-
-
ns
Write Chip Select Hold Time
6
0
-
-
ns
Write Data Setup Time
7
30
-
-
ns
Write Data Hold Time
8
0
-
-
ns
CPUADR[1:0]
1
1
2
01
00
10
GS1503
NUMBER
8
Upper Address
CPUDAT[7:0]
Write
Data
Lower Address
7
CPUCS
CPUWE
5
5
4
4
3
6
3
5
6
6
3
Fig. 8 Host Interface Mode B Write Cycle Timing (CPU_SEL set LOW)
Table 1: Host Interface Mode B Control Codes
CPUADR[1:0]
Data Bus Operation
01
Upper Address
00
Lower Address
11
Read Data
10
Write Data
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108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
GS1503
GND
CPUWE
CPURE
CPUCS
VDD
CPUDAT7
CPUDAT6
CPUDAT5
CPUDAT4
CPUDAT3
CPUDAT2
VDD
CPUDAT1
CPUDAT0
CPUADR4
CPUADR3
CPUADR2
CPUADR1
CPUADR0
CPUADR5
GND
VCLK
GND
DEC_MODE
VDD
CPUADR6
CPUADR7
CPUADR8
GND
AOUT7/8
AOUT5/6
AOUT3/4
AOUT1/2
WCOUTB
WCOUTA
VDD
PIN CONNECTIONS
GS1503
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
GND
VOUT19
VOUT18
VOUT17
VDD
VOUT16
VOUT15
VOUT14
GND
VOUT13
VOUT12
VOUT11
VDD
VOUT10
VOUT9
VOUT8
GND
VOUT7
VOUT6
VOUT5
VDD
VOUT4
VOUT3
VOUT2
GND
VOUT1
VOUT0
VIDEO_DET
EXTF
EXTH
RSV
RSV
RSV
RSV
SCRBYPASS
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VDD
AIN7/8
AIN5/6
AIN3/4
AIN1/2
WCINB
WCINA
DSCBYPASS
PLLCNTB
PLLCNTA
CASCADE
MUTE
ANCI
VDD
MUX/DEMUX
GND
ACLKA
GND
ACLKB
GND
ERROR
OPERATE
CRC_ERROR
PKTENO
PKTEN
PKT7
VDD
PKT6
PKT5
PKT4
VDD
PKT3
PKT2
PKT1
PKT0
GND
VDD
VIN19
VIN18
VIN17
GND
VIN16
VIN15
VIN14
VDD
VIN13
VIN12
VIN11
GND
VIN10
VIN9
VIN8
VDD
VIN7
VIN6
VIN5
GND
VIN4
VIN3
VIN2
VDD
VIN1
VIN0
CPU_SEL
AM1
AM0
VM3
VM2
VM1
VM0
RESET
GND
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PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
1, 14, 27,
31, 37, 52,
60, 68, 73,
84, 97, 104,
109, 117,
125, 133
VDD
-
+3.3V power supply pins.
2
AIN7/8
I
Audio signal input for channels 7 and 8. AES/EBU digital audio data is bi-phase mark
encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required.
3
AIN5/6
I
Audio signal input for channels 5 and 6. AES/EBU digital audio data is bi-phase mark
encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required.
4
AIN3/4
I
Audio signal input for channels 3 and 4. AES/EBU digital audio data is bi-phase mark
encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required.
5
AIN1/2
I
Audio signal input for channels 1 and 2. AES/EBU digital audio data is bi-phase mark
encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required.
6
WCINB
I
48kHz word clock for channels 5 to 8. Used only when operating in Multiplex Mode and
when the audio source is not an AES/EBU data stream. This pin should be grounded
when inputting AES/EBU digital audio data or when operating in Demultiplex Mode
(DEC_MODE set LOW).
7
WCINA
I
48kHz word clock for channels 1 to 4. Used only when operating in Multiplex Mode and
when the audio source is not an AES/EBU data stream. This pin should be grounded
when inputting AES/EBU digital audio data or when operating in Demultiplex Mode
(DEC_MODE set LOW).
8
DSCBYPASS
I
Descrambler bypass. When set LOW, the internal SMPTE 292M descrambler is enabled.
When set HIGH, the internal SMPTE 292M descrambler is bypassed. The video input to
the device must be word aligned.
9
PLLCNTB
O
Audio clock PLL control signal for channels 5 to 8.
10
PLLCNTA
O
Audio clock PLL control signal for channels 1 to 4.
11
CASCADE
I
Cascade mode select. When set HIGH, the GS1503 will default to audio groups 3 and 4.
Two GS1503 devices can then be cascaded in series to allow up to 16 channels of audio
to be multiplexed or demultiplexed (only one device requires CASCADE to be set HIGH).
When set LOW, the GS1503 will default to audio groups 1 and 2.
12
MUTE
I
Audio mute. In Multiplex Mode, when set HIGH, the embedded audio packets are forced
to '0'. In Demultiplex Mode, when set HIGH, the audio output data is forced to "0".
13
ANCI
I
Ancillary data delete select. Valid in Demultiplex Mode only. When set HIGH, all ancillary
data packets are removed from both the Luma and Chroma channels of the input video
signal. The data contained in the packets are output at the corresponding pins. When set
LOW, all ancillary data packets remain in the video signal. See Section 2-11.
15
MUX/DEMUX
I
Mode of operation. When set LOW, the GS1503 operates in Multiplex Mode.
When set HIGH, the GS1503 operates in Demultiplex Mode.
GND
-
Device ground.
17
ACLKA
I
Input audio signal clock at 6.144 MHz (128 fs) for channels 1 to 4.
19
ACLKB
I
Input audio signal clock at 6.144 MHz (128 fs) for channels 5 to 8.
21
ERROR
O
Format error indicator. When HIGH, the incoming video data stream contains TRS errors
or there are errors within the incoming ancillary data packets.
16, 18, 20,
36, 48, 56,
64, 72, 80,
86, 88, 108,
113, 121,
129, 144
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GS1503
NUMBER
PIN DESCRIPTIONS (Continued)
NUMBER
TYPE
22
OPERATE
O
Audio processing indicator. When HIGH, audio data is being multiplexed or
demultiplexed.
23
CRC_ERROR
O
CRC error indicator. Will be set HIGH when a CRC error is detected in the incoming video
data stream.
24
PKTENO
O
Arbitrary data packet timing signal. Valid in Multiplex Mode only. Will be HIGH when
arbitrary data packets can be input to the device. This signal is only valid when
multiplexing arbitrary data packets via the PKT[7:0] bus. See Figure 30 for timing.
25
PKTEN
I/O
Arbitrary data packet enable. In Multiplex Mode, PKTEN is an input and must be set HIGH
two VCLK cycles after the PKTENO signal goes HIGH. Arbitrary packet data is input to the
device two VCLK cycles after PKTEN is set HIGH. In Demultiplex Mode, PKTEN is an
output and is set HIGH two VCLK cycles before the device outputs arbitrary packet data.
See Figures 30 and 42.
PKT[7:0]
I/O
Arbitrary data I/O bus. PKT[7] is the MSB and PKT[0] is the LSB. In Multiplex Mode, the
user must input the arbitrary data packet words starting from the data identification (DID)
to the last user data word (UDW) according to SMPTE 291M. The GS1503 internally
converts the data to 10 bits by generating the parity bit (bit 8) and inversion bit (bit 9). The
checksum (CS) word is also generated internally. In Demultiplex Mode, the GS9023
outputs the arbitrary data packet words starting from the DID to the last UDW.
See Figures 30 and 42.
SCRBYPASS
I
Scrambler bypass. When set LOW, the output video stream is scrambled according to
SMPTE 292M and NRZ(I) encoded. When set HIGH, the scrambler and NRZ(I) encoder
are bypassed.
RSV
-
Connect to ground.
43
EXTH
I/O
Horizontal sync signal. The GS1503 outputs a horizontal sync signal derived from the
incoming TRS. In Multiplex Mode, with EXT_SEL set HIGH in the Host Interface, a
horizontal sync signal can be input to the device for TRS and line number insertion.
44
EXTF
I/O
Field sync signal. The GS1503 outputs a field sync signal derived from the incoming TRS.
In Multiplex Mode, with EXT_SEL set HIGH in the Host Interface, a field sync signal can be
input to the device for TRS and line number insertion. For progressive formats, a signal
with a high to low transition at the position of line one must be provided.
See Figures 14 and 15.
45
VIDEO_DET
O
Video input signal detection. Indicates that the device has detected a valid video input stream.
26, 28, 29,
30, 32, 33,
34, 35
38
39, 40, 41,
42
DESCRIPTION
NOTE: When EXT_SEL is set HIGH in the Host Interface, VIDEO_DET will indicate when
valid EXTH and EXTF signals have been detected.
VOUT[19:0]
O
Parallel digital video signal output. VOUT[19] is the MSB and VOUT[0] is the LSB.
74
WCOUTA
O
48kHz word clock for channels 1 to 4. Valid only when operating in Demultiplex Mode.
75
WCOUTB
O
48kHz word clock for channels 5 to 8. Valid only when operating in Demultiplex Mode.
76
AOUT1/2
O
Audio signal output for channels 1 and 2. The AES/EBU digital audio output is bi-phase
mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded.
77
AOUT3/4
O
Audio signal output for channels 3 and 4. The AES/EBU digital audio output is bi-phase
mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded.
78
AOUT5/6
O
Audio signal output for channels 5 and 6. The AES/EBU digital audio output is bi-phase
mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded.
71, 70, 69,
67, 66, 65,
63, 62, 61,
59, 58, 57,
55, 54, 53,
51, 50, 49,
47, 46
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GS1503
SYMBOL
PIN DESCRIPTIONS (Continued)
NUMBER
TYPE
DESCRIPTION
79
AOUT7/8
O
Audio signal output for channels 7 and 8. The AES/EBU digital audio output is bi-phase
mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded.
85
DEC_MODE
I
Demultiplex Mode select. Valid in Demultiplex Mode only. When set HIGH, the GS1503
requires a 48kHz word clock input at WCINA and WCINB. This word clock must be
synchronous to the word clock used to embed the audio data. The embedded audio
clock phase information in the ancillary data packet will be ignored. See Section 2-11.
87
VCLK
I
Video clock signal input.
81, 82, 83,
89, 94, 93,
92, 91, 90
CPUADR[8:0]
I
Host Interface address bus. CPUADR[8] is the MSB and CPUADR[0] is the LSB.
In Host Interface Mode B (CPU_SEL set LOW), CPUADR[1:0] are used as the Host
Interface control bus. See Table 1.
103, 102,
101, 100,
99, 98, 96,
95
CPUDAT[7:0]
I/O
Host Interface data bus. CPUDAT[7] is the MSB and CPUDAT[0] is the LSB.
In Host Interface Mode B (CPU_SEL set LOW), CPUDAT[7:0] are used as the Host
Interface address and data bus.
105
CPUCS
I
Chip select for Host Interface. Active LOW.
106
CPURE
I
Read enable for Host Interface. Active LOW. In Host Interface Mode B (CPU_SEL set
LOW), this input is not used.
107
CPUWE
I
Write enable for Host Interface. Active LOW. In Host Interface Mode B (CPU_SEL set
LOW), this input is used as the Host Interface control enable.
110, 111,
112, 114,
115, 116,
118, 119,
120, 122,
123, 124,
126, 127,
128, 130,
131, 132,
134, 135
VIN[19:0]
I
Parallel digital video signal input. VIN[19] is the MSB and VIN[0] is the LSB.
136
CPU_SEL
I
Host Interface mode select. When set HIGH, the GS1503 is configured for Host Interface
Mode A. When set LOW, the GS1503 is configured for Host Interface Mode B.
137, 138
AM[1:0]
I
Audio format select. In Multiplex Mode, AM[1:0] indicates the input audio data format.
In Demultiplex Mode, AM[1:0] indicates the output audio data format. AM[1] is the MSB
and AM[0] is the LSB. See Tables 3 and 11.
139, 140,
141, 142
VM[3:0]
I
Video standard select. VM[3] is the MSB and VM[0] is the LSB. See Table 2 or 10.
143
RESET
I
Device reset. Active LOW.
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GS1503
SYMBOL
DETAILED DESCRIPTION
Up to a maximum of 8 channels of 48kHz digital audio can
be multiplexed per device. The audio input format can be
selected as either AES/EBU, or one of two serial audio data
input modes. A maximum of 16 channels of audio can be
multiplexed by serially cascading two devices.
1. MULTIPLEX MODE
1.1 FUNCTIONAL OVERVIEW
The video input format can be one of the following
configurations:
10-bit Y and Cb/Cr input with TRS and Line Numbers
8-bit Y and Cb/Cr input with TRS and Line Numbers
10-bit or 8-bit Y and Cb/Cr input without TRS and Line
Numbers (GS1503 will insert TRS and Line Numbers based
on EXTF and EXTH inputs)
20-bit scrambled input
Audio control packets, as defined in SMPTE 299M, can also
be multiplexed to provide information to receivers about the
nature of the embedded audio data. The contents of the
audio control packet can be programmed via the Host
Interface.
The GS1503 will also multiplex arbitrary data packets as
defined in SMPTE 291M. The arbitrary data packets can
serve as an auxiliary data signal for proprietary
applications. The GS1503 can be configured to multiplex
arbitrary data packets, input via the Host Interface or using
dedicated external pins. Up to a maximum of 255 8-bit
words can be multiplexed (excluding Ancillary Data Flags
and Checksum).
To use the GS1503 in Multiplex Mode, set the MUX/DEMUX
external pin LOW.
1.2 VIDEO STANDARD
The video output format can be one of the following
configurations:
20-bit scrambled output
10-bit Y and Cb/Cr output
The video standard is selected from the VM[3:0] external
pins or VM[3:0] bits 3-0 in Host Interface register 000h. To
configure the video standard via the Host Interface,
VM_SEL bit 7 in Host Interface register 000h must be set
HIGH. The GS1503 will default to the VM[3:0] external pin
setting. The supported video standards are listed in Table 2.
Table 2: Supported Video Standards
VM [3:0]
INPUT FORMAT
REFERENCE SMPTE DOCUMENT
SMPTE 292M LEVEL
1110b
1035i (30 & 30/1.001 Hz)
260M
A, B
1100b
1080i (25 Hz)
295M
C
1000b
1080i/1080sF (30 & 30/1.001 Hz)
274M, RP211
D, E
1010b
1080i/1080sF (25 Hz)
274M, RP211
F
1111b
1080sF (24 & 24/1.001 Hz)
RP211
0010b
1080p (30 & 30/1.001 Hz)
274M
G, H
0100b
1080p (25 Hz)
274M
I
0110b
1080p (24 & 24/1.001 Hz)
274M
J, K
0000b
720p (60 & 60/1.001 Hz)
296M
L, M
0001b
720p (30 & 30/1.001 Hz)
296M
0011b
720p (50 Hz)
296M
0101b
720p (25 Hz)
296M
0111b
720p (24 & 24/1.001 Hz)
296M
All other settings are reserved
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GS1503
The GS1503 HD Embedded Audio CODEC fully supports
the multiplexing of Audio Data Packets, Audio Control
Packets and Arbitrary Data Packets as per SMPTE 291M
and 299M. The device can be configured to operate with all
video standards defined in SMPTE 292M, levels A through
M. The GS1503 also supports the 1080/24PsF, 25PsF and
30PsF video formats as described in SMPTE RP211.
Register Settings
NAME
DESCRIPTION
VM_SEL
0: External pin select
ADDRESS
BIT
SETTING
DEFAULT
000
7
1
0
See
0
1: Register select
VM[3:0]
Video formal selection (VM[3] is MSB)
3-0
Table 2
GS1503
1.3 VIDEO INPUT FORMAT
1.3.1 10-bit Y and Cb/Cr Input Video with TRS and Line Numbers
GS1503
Y[9:0]
VIN[19:10]
Cb / Cr [9:0]
VIN[9:0]
EXTF
+3.3V
EXTH
DSCBYPASS
EAV
Vn
V0
000
XYZ
000
3FF
CRC1
CRC0
LN0
LN1
3
000
XYZ
0
000
3FF
10-bit
Y, C b/Cr
8
Fig. 9 Configuration for 10-bit Y and Cb/Cr Input Video with TRS and Line Numbers
Video
SAV
Fig. 10 Video Input Format 10-bit with TRS and Line Numbers
Register Settings
NAME
EXT_SEL
DESCRIPTION
0: EXTH/EXTF output select
ADDRESS
BIT
SETTING
DEFAULT
001
3
0
0
1
0
0
0
1
0
1: EXTH/EXTF input select
8BIT_SEL
0: 10-bit mode select
1: 8-bit mode select
DSCBYPASS
0: Descrambling enabled
1: Bypass descrambling
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1.3.2 8-bit Y and Cb/Cr Input Video with TRS and Line Numbers
GS1503
Y[9:0]
VIN[19:12]
VIN[11:10]
GS1503
C b/ C r[9:0]
VIN[9:2]
EXTF
VIN[1:0]
+3.3V
EXTH
DSCBYPASS
Vn
V0
00
XY
FF
EAV
00
8
LN0
LN1
00
XY
00
FF
Y, C b/Cr
8-bit
0
3
Fig. 11 Configuration for 8-bit Y and Cb/Cr Input Video with TRS and Line Numbers
Video
SAV
Fig. 12 Video Input Format 8-bit with TRS and Line Numbers
Register Settings
NAME
EXT_SEL
DESCRIPTION
0: EXTH/EXTF output select
ADDRESS
BIT
SETTING
DEFAULT
001
3
0
0
1
1
0
0
1
0
1: EXTH/EXTF input select
8BIT_SEL
0: 10-bit mode select
1: 8-bit mode select
DSCBYPASS
0: Descrambling enabled
1: Bypass descrambling
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1.3.3
10-bit or 8-bit Y and Cb/Cr Input without TRS and Line Numbers
The GS1503 will insert TRS and Line Numbers based on
EXTF and EXTH inputs. See Figure 14 for timing. In
progressive format video standards, a high-to-low edge
signal must be input at the EXTF external pin on every
frame to indicate the position of line 1. See Figure 15.
GS1503
GS1503
Y[9:0]
VIN[19:10]
C b / Cr [9:0]
VIN[9:0]
EXTF
EXTH
+3.3V
DSCBYPASS
V0
Video
Vn
8
8/10-bit
Y, Cb /C r
3
0
Fig. 13 Configuration for 10-bit or 8-bit Y and Cb/Cr Input Video without TRS and Line Numbers
4 VCLK
EXTH
EXTF
V0
Video
Vn
8
8/10-bit
Y, C b/C r
3
0
Fig. 14 Video Input Format (8/10-bit without TRS and Line Numbers)
4 VCLK
EXTH
EXTF
Line 1
Fig. 15 Video Input Format (Progressive)
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Register Settings
NAME
EXT_SEL
DESCRIPTION
0: EXTH/EXTF output select
ADDRESS
BIT
SETTING
DEFAULT
001
3
1
0
1
0 or 1
0
0
1
0
ADDRESS
BIT
SETTING
DEFAULT
001
3
0
0
1
0
0
0
0
0
1: EXTH/EXTF input select
8BIT_SEL
0: 10-bit mode select
1: 8-bit mode select
0: Descrambling enabled
GS1503
DSCBYPASS
1: Bypass descrambling
1.3.4 20-bit Scrambled Input
GS1503
Y/C b / Cr [19:0]
VIN[19:0]
DSCBYPASS
Fig. 16 Configuration for 20-bit Scrambled Input
Register Settings (Default Mode)
NAME
EXT_SEL
DESCRIPTION
0: EXTH/EXTF output select
1: EXTH/EXTF input select
8BIT_SEL
0: 10-bit mode select
1: 8-bit mode select
DSCBYPASS
0: Descrambling enabled
1: Bypass descrambling
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1.4 VIDEO OUTPUT FORMAT
1.4.1 20-bit Scrambled Output
GS1503
VOUT[19:0]
Y/Cb / C r [19:0]
GS1503
SCRBYPASS
Fig. 17 Configuration for 20-bit Scrambled Output
Register Settings (Default Mode)
NAME
SCRBYPASS
DESCRIPTION
0: SMPTE 292M scrambling enabled
ADDRESS
BIT
SETTING
DEFAULT
001
2
0
0
1: Bypass SMPTE 292M scrambling
1.4.2 10-bit Y and Cb/Cr Output
GS1503
Y[9:0]
VOUT[19:10]
VOUT[9:0]
C b / Cr [9:0]
+3.3V
SCRBYPASS
Fig. 18 Configuration for 10-bit Y and Cb/Cr Output
Register Settings
NAME
SCRBYPASS
DESCRIPTION
0: SMPTE 292M scrambling enabled
ADDRESS
BIT
SETTING
DEFAULT
001
2
1
0
1: Bypass SMPTE 292M scrambling
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1.5 VIDEO DATA PROCESSING
1.5.1 Video Signal Input Detection
The GS1503 will set the VIDEO_DET external pin HIGH
when three consecutive TRS are detected in the input video
signal. Also, the VIDEO_DET bit of Host Interface register
000h is set HIGH.
NAME
VIDEO_DET
DESCRIPTION
Video input signal detection (1: Detection)
ADDRESS
BIT
SETTING
DEFAULT
000
6
-
0
1.5.2 Video Input CRC Error Detection
The GS1503 will set the CRC_ERR external pin HIGH when
a CRC error is detected in the input video signal. Also, the
CRC_ERR bit 5 of Host Interface register 000h is set HIGH.
The number of CRC errors accumulated in one video frame
can be read form CRC_CNT[11:0] in Host Interface
registers 006h and 007h.
Register Settings
NAME
DESCRIPTION
ADDRESS
BIT
SETTING
DEFAULT
CRC_ERR
Video input signal CRC error detection (1: Detection)
000
5
-
0
CRC_CNT[11:0]
Video input signal CRC error accumulation in 1 video
frame
006
3-0
-
0
007
7-0
1.5.3 Video Output CRC Insertion
When the CRC_INS bit 4 of Host Interface register 000h is
set HIGH, the GS1503 will re-calculate the video line CRC
words. The re-calculated CRC words are inserted in the
video output signal. When CRC_INS is set LOW, the line
CRC words are not updated and existing CRC words at the
input of the device will be output unchanged.
Register Settings
NAME
CRC_INS
DESCRIPTION
Video line CRC insertion (1: Insertion)
ADDRESS
BIT
SETTING
DEFAULT
000
4
1
1
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GS1503
Register Settings
1.5.4 Illegal Code Re-mapping
When LIMIT_ON bit 4 of Host Interface register 008h is set
HIGH, input video words between 000-003 are re-mapped
to 004, and values between 3FC-3FF are re-mapped to
3FB. Valid only when the EXT_SEL bit 3 of Host Interface
register 000h is set HIGH.
NAME
EXT_SEL
DESCRIPTION
0: EXTH/EXTF output select
ADDRESS
BIT
SETTING
DEFAULT
001
3
1
0
008
4
1
0
1: EXTH/EXTF input select
LIMIT_ON
Illegal code re-mapping (1: Enabled)
1.5.5 Input Blanking
When VBLK_INS bit 3 of Host Interface register 008h is set
HIGH, the input video vertical blanking will be set to 040h for
the Luma channel and 200h for the Chroma channel.
The blanking function is performed at the output of the
GS1503 video data stream. If the HBLK_INS bit is set HIGH,
any multiplexed audio will be replaced with blanking codes.
When HBLK_INS bit 2 of Host Interface register 008h is set
HIGH, the input video horizontal blanking will be set to 040h
for the Luma channel and 200h for the Chroma channel. The
TRS, line number and CRC words will also be set to blanking
values.
Register Settings
NAME
DESCRIPTION
VBLK_INS
Input vertical blanking (1: Enabled)
HBLK_INS
Input horizontal blanking (1: Enabled)
1.5.6 Line Number Insertion
When LN_INS bit 1 of Host Interface register 008h is set
HIGH, the GS1503 will insert line numbers into the video
data stream. When set LOW, existing line numbers will
remain in the output video stream.
ADDRESS
BIT
SETTING
DEFAULT
008
3
1
0
2
1
0
When EXT_SEL bit 3 of Host Interface register 001h is set
HIGH, line numbers will be inserted based on the timing of
EXTH and EXTF input signals.
Register Settings
NAME
LN_INS
DESCRIPTION
Line number insertion (1: Enabled)
ADDRESS
BIT
SETTING
DEFAULT
008
1
1
1
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GS1503
Register Settings
When EXT_SEL bit 3 of Host Interface register 001h is set
HIGH, TRS codes will be inserted based on the timing of
EXTH and EXTF input signals.
1.5.7 TRS Word Insertion
When TRS_INS bit 0 of Host Interface register 008h is set
HIGH, the GS1503 will insert TRS codes into the video data
stream. When set LOW, existing TRS codes will remain in
the output video stream.
Register Settings
DESCRIPTION
TRS_INS
ADDRESS
BIT
SETTING
DEFAULT
008
0
1
1
TRS word insertion (1: Enabled)
Table 3: Audio Input Formats
1.6 AUDIO DATA PROCESSING
AM[1:0]
1.6.1 Digital Audio Input Format
The GS1503 will accept two audio input formats, AES/EBU
digital audio input and serial input, as listed in Table 3.
Serial input can be formatted in the following two modes.
See Figure 19:
AUDIO INPUT FORMAT
0
Serial audio input: 24-bit Left Justified; MSB first
1
Serial audio input: 24-bit Right Justified; MSB last
2
AES/EBU audio input
24-bit Left Justified; MSB first
24-bit Right Justified; MSB last
The audio input format is configured using the AM[1:0]
external pins or via AM[1:0] bits 1-0 in Host Interface
register 010h. To configure the audio input format via the
Host Interface, AM_SEL bit 7 in Host Interface register 010h
must be set HIGH. The GS1503 will default to the AM[1:0]
external pin setting.
Register Settings
NAME
DESCRIPTION
AM_SEL
ADDRESS
BIT
SETTING
DEFAULT
010
7
1
0
See
0
0: External pin setting
1: Register setting
AM[1:0]
Audio input format selection (AM[1] is MSB)
1-0
Table 3
Channel 1
Channel 2
WCINA/WCINB
MSB
MODE0
MSB
23
0
23
0
LSB
0
MODE2
(AES/EBU)
LSB
0
MODE1
23
3 4
Sync
Preamble
2728293031 0
0
3 4
Sync
V U C P Preamble
24-bit Audio Sample Word
23
2728293031
24-bit Audio Sample Word
V UC P
Validity Bit
User Data Bit
Channel Status Bit
Parity Bit
Fig. 19 Audio Input Formats
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GS1503
NAME
1.6.2 Digital Audio Input Timing
1.6.2.1 AES/EBU Format Input
GS1503
A 6.144MHz (128fs) audio clock must be supplied to the
ACLKA and ACLKB inputs. ACLKA is used to clock the
AES/EBU digital audio signal for channels 1 to 4 (AIN1/2
and AIN3/4) into the device. ACLKB is used to clock the
AES/EBU digital audio signal for channels 5 to 8 (AIN5/6
and AIN7/8) into the device. In AES/EBU input mode, the
WCINB and WCINB external pins should be grounded.
See Figure 20 for timing.
GS1503
Y/C b / Cr [19:0]
VIN[19:0]
Audio Channels 1 & 2
AIN1/2
Audio Channels 3 & 4
AIN3/4
6.144MHz (128 fs)
ACLKA
WCINA
Audio Channels 5 & 6
AIN5/6
Audio Channels 7 & 8
AIN7/8
6.144MHz (128 fs)
ACLKB
WCINB
6.144MHz
ACLKA/B
AIN1/2, AIN3/4
AIN5/6, AIN7/8
Fig. 20 AES/EBU Input Configuration and Timing
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1.6.2.2
Serial Audio Input Modes
GS1503
A 6.144MHz (128fs) audio clock must be supplied to the
ACLKA and ACLKB inputs. The GS1503 divides this clock
by 2 to clock the 3.072MHz audio data. An audio word
clock at 48kHz (fs) must also be supplied to the WCINA
and WCINB inputs, as shown in Figure 21. The
AUDIO_CS[183:0] bits in Host Interface registers 058h to
06Eh can be used to enter the 23 8-bit bytes of the Audio
Channel Status Block, as defined in AES3-1992. NOTE: The
CRC byte is generated internally by the GS1503. The
GS1503 will default to Professional audio mode with 24-bit
word length and emphasis off. See Table 9.
GS1503
Y/C b / Cr [19:0]
VIN[19:0]
Audio Channels 1 & 2
AIN1/2
Audio Channels 3 & 4
AIN3/4
6.144MHz (128 fs)
ACLKA
48kHz (fs)
WCINA
Audio Channels 5 & 6
AIN5/6
Audio Channels 7 & 8
AIN7/8
6.144MHz (128 fs)
ACLKB
48kHz (fs)
WCINB
64 CLKs
64 CLKs
ACLKA/B
WCINA/B
AIN1/2, AIN3/4
AIN5/6, AIN7/8
Fig. 21 Serial Audio Input Configuration and Timing
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1.6.3 Audio Clock Phase Locked Loop
GS1503
Figure 22 shows the configuration for deriving the
6.144MHz audio clock in AES/EBU audio input mode. The
GS1503 will internally synchronize the AES/EBU audio input
to the corresponding ACLK, using the clock extracted from
the AES/EBU bi-phase mark encoding. This configuration is
not required for serial audio input modes. See the
Reference Design Section 3 for circuit specifics.
6.144MHz (128 fs)
GS1503
Y/C b / Cr [19:0]
VIN[19:0]
Audio Channels 1 & 2
AIN1/2
Audio Channels 3 & 4
AIN3/4
ACLKA
Audio Channels 5 & 6
PLLCNTA
Low
Pass
Filter
24.576MHz
Low
Pass
Filter
24.576MHz
VCXO
÷4
AIN5/6
Audio Channels 7 & 8
AIN7/8
ACLKB
PLLCNTB
VCXO
÷4
6.144MHz (128 fs)
Fig. 22 Block Diagram of GS1503 Audio Clock PLL
1.6.4 Audio Signal Input Detection
The audio input signal detect registers will be set HIGH in
AES/EBU audio mode when the preamble of the audio input
data is detected 3 times consecutively. In serial audio input
mode, the GS1503 will set the audio input signal detect
registers HIGH when a 48kHz word clock is detected at the
corresponding inputs. Audio channels 1 to 4 will be set
when WCINA is validated, and audio channels 5 to 8 when
WCINB is validated. Host Interface register 010h, bits 6-3,
report the individual audio channels pairs detected.
Register Settings
NAME
DESCRIPTION
ADDRESS
BIT
SETTING
DEFAULT
010
6
-
0
AUD7/8_DET
Ch7/8 Audio input signal detection (1:Detection)
AUD5/6_DET
Ch5/6 Audio input signal detection (1:Detection)
5
-
0
AUD3/4_DET
Ch3/4 Audio input signal detection (1:Detection)
4
-
0
AUD1/2_DET
Ch1/2 Audio input signal detection (1:Detection)
3
-
0
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1.6.5 Audio Channel Status CRC Error Detection
In AES/EBU audio mode, the GS1503 will check the
Channel Status CRC for errors. If any Channel Status CRC
errors are detected in an AES/EBU audio input channel pair,
the corresponding bit in Host Interface register 011h will be
set HIGH. In serial audio input mode, the CRC error flags
are always set LOW.
NAME
ACRC7/8_ERR
DESCRIPTION
Ch7/8 Audio Channel Status CRC error detection
ADDRESS
BIT
SETTING
DEFAULT
011
3
-
0
2
-
0
1
-
0
0
-
0
(1: Detection)
ACRC5/6_ERR
Ch5/6 Audio Channel Status CRC error detection
(1: Detection)
ACRC3/4_ERR
Ch3/4 Audio Channel Status CRC error detection
(1: Detection)
ACRC1/2_ERR
Ch1/2 Audio Channel Status CRC error detection
(1: Detection)
1.6.6 Audio Input Parity Error Detection
In AES/EBU audio mode, the GS1503 will check for Audio
Parity errors. If any Audio Parity errors are detected in an
AES/EBU audio input channel pair, the corresponding bit in
Host Interface register 012h will be set HIGH. In serial audio
input mode, the Audio Parity error flags are always set
LOW.
Register Settings
NAME
DESCRIPTION
ADDRESS
BIT
SETTING
DEFAULT
012
3
-
0
AP7/8_ERR
Ch7/8 Audio parity error detection (1: Detection)
AP5/6_ERR
Ch5/6 Audio parity error detection (1: Detection)
2
-
0
AP3/4_ERR
Ch3/4 Audio parity error detection (1: Detection)
1
-
0
AP1/2_ERR
Ch1/2 Audio parity error detection (1: Detection)
0
-
0
1.6.7 Audio Channel Status CRC Insert Function
When bits 7-4 of Host Interface register 011h are set HIGH,
the GS1503 will re-calculate the Channel Status CRC word
for the corresponding audio input channel pair. The recalculated Channel Status CRC word is multiplexed into the
audio data packet as per SMPTE 299M. When bits 3-0 of
Host Interface register 011h are set LOW, the Channel
Status CRC word is not updated and the existing Channel
Status CRC word will be multiplexed. In serial audio input
mode, these registers should be set LOW.
Register Settings
NAME
DESCRIPTION
ADDRESS
BIT
SETTING
DEFAULT
ACRC7/8_INS
Ch7/8 Audio Channel Status CRC insertion (1: Insertion)
011
7
1
0
ACRC5/6_INS
Ch5/6 Audio Channel Status CRC insertion (1: Insertion)
6
1
0
ACRC3/4_INS
Ch3/4 Audio Channel Status CRC insertion (1: Insertion)
5
1
0
ACRC1/2_INS
Ch1/2 Audio Channel Status CRC insertion (1: Insertion)
4
1
0
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GS1503
Register Settings
1.7 AUDIO DATA PACKETS
1.7.1 Audio Data Packet Structure
GS1503
Figure 23 shows the structure of the audio data packets as
defined in SMPTE 299M. The audio data packets are
multiplexed into the Chroma channel of the video data
stream. Table 4 lists the description of the individual audio
data packet words. Note that the GS1503 will automatically
generate certain audio data packet words.
CS
ECC5
ECC3
ECC4
ECC2
ECC0
ECC1
CH4
CH3
CH2
CH1
CLK
DC
DID
DBN
ADF
10-bit
User Data Words
ECC Protected
Fig. 23 Audio Data Packet Structure
Table 4: Audio Data Packet Word Descriptions
NAME
NO OF
WORDS
ADF
3
DESCRIPTION
Ancillary Data Flag
DATA
AUTO-GENERATION
000h
Yes
3FFh
3FFh
DID
1
Audio Group Data ID
2E7h
See Table 5 in
1E6h
Section 1-7-2
1E5h
2E4h
DBN
1
Data Block Number
Repeat 1-255
Yes
DC
1
Data Count
218h
Yes
CLK
2
Audio Clock Phase Data
-
Yes
CH1
4
Channel 1 audio data
-
CH2
4
Channel 2 audio data
-
CH3
4
Channel 3 audio data
-
CH4
4
Channel 4 audio data
-
ECC0-5
6
Error correction code for lower 8 bits of first 24 words
-
Yes
CS
1
Checksum. Calculates the sum of lower 9 bits of 22
words from DID
-
Yes
1.7.2 Audio Data Packet DID Setting
The audio group DID for audio input channels 1 to 4 (AIN1/
2 and AIN3/4) is set in DATAIDA[1:0] bits 1-0 of Host
Interface register 014h. The audio group DID for audio input
channels 5 to 8 (AIN5/6 and AIN7/8) is set in DATAIDB[1:0]
bits 3-2 of Host Interface register 014h. Table 5 shows the
2-bit Host Interface setting for the corresponding audio
group DID.
When CASCADE is set LOW (external pin or register), the
GS1503 will default to audio groups 1 and 2, where AIN1/2
and AIN3/4 will be multiplexed with audio group 1 DID, and
AIN5/6 and AIN7/8 with audio group 2 DID.
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Table 5: Audio Data Packet Group DID Host
Interface Setting
10-BIT DATA
HOST INTERFACE
REGISTER SETTING (2-BIT)
1
2E7h
11b
2
1E6h
10b
3
1E5h
01b
4
2E4h
00b
GS1503
AUDIO
GROUP
Register Settings (CASCADE set LOW)
NAME
DATAIDA [1-0]
DATAIDB [1-0]
DESCRIPTION
Ch1-4 Audio data packet DID setting
ADDRESS
BIT
014
1-0
Ch5-8 Audio data packet DID setting
3-2
SETTING
DEFAULT
See
11b
Table 5
10b
When CASCADE is set HIGH (external pin or register), the
GS1503 will default to audio groups 3 and 4, where AIN1/2
and AIN3/4 will be multiplexed with audio group 3 DID, and
AIN5/6 and AIN7/8 with audio group 4 DID.
Register Settings (CASCADE set HIGH)
NAME
DATAIDA [1-0]
DATAIDB [1-0]
1.7.3
DESCRIPTION
Ch1-4 Audio data packet DID setting
ADDRESS
BIT
014
1-0
Ch5-8 Audio data packet DID setting
3-2
Audio Channel Multiplex Enable
Multiplexing of individual audio channels is enabled using
the CHACT[7:0] bits 7-0 of Host Interface register 013h.
When set HIGH, the corresponding audio channel is
multiplexed into the audio data packet in the Chroma video
SETTING
DEFAULT
See
01b
Table 5
00b
data stream. CHACT7 corresponds to audio input channel 8
and CHACT0 corresponds to audio input channel 1. When
all bits are set LOW, no audio data packets will be
multiplexed and the GS1503 will be in bypass mode.
Register Settings
NAME
DESCRIPTION
ADDRESS
BIT
SETTING
DEFAULT
013
7
-
1
CHACT7
Ch8 multiplex enable (1: Enabled)
CHACT6
Ch7 multiplex enable (1: Enabled)
6
1
CHACT5
Ch6 multiplex enable (1: Enabled)
5
1
CHACT4
Ch5 multiplex enable (1: Enabled)
4
1
CHACT3
Ch4 multiplex enable (1: Enabled)
3
1
CHACT2
Ch3 multiplex enable (1: Enabled)
2
1
CHACT1
Ch2 multiplex enable (1: Enabled)
1
1
CHACT0
Ch1 multiplex enable (1: Enabled)
0
1
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1.8 VIDEO SWITCHING LINE SETTING
The GS1503 will not multiplex any audio data packets in the
line immediately after the video switching point. For
example, with the default setting of line 7 field 1, there will
be no audio data packets in line 8. The next packets will
appear on line 9. Audio control packets will be multiplexed
once per field, two lines after the video switching point (on
line 9, using the previous example). Arbitrary data packets
will not be multiplexed in the two lines following the video
switching point .
For reliable operation, non-SMPTE 299M compliant video
data streams with embedded audio should not be used in
conjunction with the GS1503 in Multiplex Mode.
Register Settings
NAME
SW_LNA[12:0]
SW_LNB[12:0]
DESCRIPTION
ADDRESS
BIT
SETTING
DEFAULT
004
4-0
-
7d
005
7-0
002
4-0
-
569d
003
7-0
Video Field 1 switching point setting
Video Field 2 switching point setting
1.9 MULTIPLEX CASCADE MODE
Two GS1503 devices can be cascaded in series to allow up
to 16 channels of audio to be multiplexed (only one device
requires CASCADE to be set HIGH). Figure 24 shows the
cascade architecture for a 16-channel system. To configure
the GS1503 for cascade mode, the CASCADE external pin
or CASCADE bit 7 of Host Interface register 014h is set
HIGH. When set HIGH, the GS1503 will default to audio
groups 3 and 4. When set LOW, the GS1503 will default to
audio groups 1 and 2.
GS1503
Y/Cb /Cr [19:0]
Audio Channels 1 & 2
Audio
Group 1
Audio Channels 3 & 4
Audio Channels 5 & 6
Audio
Group 2
Audio Channels 7 & 8
VIN[19:0]
GS1503
Y/C b /Cr [19:0]
VOUT[19:0]
Audio
AIN1/2
Group 3
AIN3/4
Audio
AIN5/6
Group 4
AIN7/8
VIN[19:0]
Audio Channels 9 & 10
Y/C b /C r [19:0]
VOUT[19:0]
AIN1/2
Audio Channels 11 & 12
AIN3/4
Audio Channels 13 & 14
AIN5/6
Audio Channels 15 & 16
AIN7/8
+3.3V
CASCADE
CASCADE
Fig. 24 Multiplexing 16 Channels of Audio using Cascade Architecture
Register Settings
NAME
CASCADE
DESCRIPTION
Cascade enable (1: Enabled)
ADDRESS
BIT
SETTING
DEFAULT
014
7
1
0
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GS1503
The video switching point for field 1 and field 2 can be
configured via the GS1503 Host Interface. The
SW_LNA[12:0] register is used to configure the video
switching line for field 1, and SW_LNB[12:0] to set video
switching line for field 2. In progressive format video
standards, only the SW_LNA[12:0] register is used. The
default settings are line 7 for field 1 and line 569 for field 2
as defined in SMPTE 299M.
NOTE: The SMPTE 299M standard defines the video
switching point as lines 7 and 569. If the SW_LNA[12:0] and
SW_LNB[12:0] registers are programmed with values other
than lines 7 and 569, the output of the GS1503 is not
guaranteed to be compatible with all HD audio demultiplex
systems. With non-SMPTE 299M compliant switch line
settings, the user should avoid inputting a video data
stream to the GS1503, which already contains embedded
audio data and control packets.
When CASCADE is set LOW, the GS1503 will multiplex
audio data and control packets as shown in Figure 25
(NOTE: Only the Chroma channel of the video data stream
is shown). Any existing audio data or control packets will be
deleted and replaced with blanking data before the new
packets are multiplexed. New packets are multiplexed
immediately after the two video line CRC words.
When CASCADE is set HIGH, the GS1503 will multiplex the
audio data and control packets immediately after the
existing packets, as shown in Figure 26. Avoid multiplexing
new ancillary data packets with the same audio group DID
as existing packets.
SAV
LN
CRC
EAV
GS1503
Blank (200 h )
SAV
Audio
Group 2
Audio
Group 1
LN
CRC
EAV
Video Signal before GS1503 (no existing Audio Data Packets)
Blank (200h)
SAV
Audio
Group 2
(New)
Audio
Group 1
(New)
LN
CRC
EAV
Video Signal before GS1503 (with existing Audio Data Packets)
Blank (200h )
Video Signal after GS1503 Insertion of Audio Groups 1 & 2 (CASCADE = 0)
SAV
Audio
Group 2
Audio
Group 1
LN
CRC
EAV
Fig. 25
Blank (200h)
Blank (200 h)
SAV
Audio
Group 4
(New)
Audio
Group 3
(New)
Audio
Group 2
(Old)
Audio
Group 1
(Old)
LN
CRC
EAV
Video Signal before GS1503 (with existing Audio Data Packets)
Video Signal after GS1503 Insertion of Audio Groups 3 & 4 (CASCADE = 1)
Fig. 26
28 of 83
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SAV
Audio
Group 2
Audio
Group 1
LN
CRC
Blank
(200h)
GS1503
EAV
The GS1503 assumes that the ancillary data space from the
first blanking location to the SAV contains no ancillary data
packets. Existing ancillary data packets must be
contiguous from the beginning of the HANC space or the
GS1503 will overwrite existing packets with blanking before
multiplexing new packets. See Figure 27.
Blank (200 h)
SAV
Audio
Group 4
(New)
Audio
Group 3
(New)
LN
CRC
EAV
Video Signal before GS1503 (with space between EAV and existing Audio Data Packets)
Blank (200 h )
Video Signal after GS1503 Insertion of Audio Groups 3 & 4 (CASCADE = 1)
Fig. 27
1.10 AUDIO CONTROL PACKETS
1.10.1 Audio Control Packet Structure
Figure 28 shows the structure of the audio control packet as
defined in SMPTE 299M. An audio control packet is
multiplexed once per field in the Luma channel of the video
data stream. Table 6 lists descriptions of the individual
audio control packet words. The GS1503 will automatically
generate certain audio control packet words.
CS
RSRV
DEL3-4
DEL1-2
ACT
AF
RATE
DC
DID
DBN
ADF
10-bit
User Data Words
Fig. 28 Audio Control Packet Structure
29 of 83
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Table 6: Audio Control Packet Word Descriptions
NAME
NO OF WORDS
ADF
3
DESCRIPTION
Ancillary Data Flag
DATA
AUTOGENERATION
000h
Yes
3FFh
3FFh
1
Audio Group Data ID
1E3h
2E2h
See Table 7 in
Section 1-10-2
GS1503
DID
2E1h
1E0h
DBN
1
Data Block Number
200h
Yes
DC
1
Data Count
10Bh
Yes
AF
1
Audio Frame Number
-
9-bit Host Interface
Setting
RATE
1
Sampling Frequency
-
4-bit Host Interface
Setting
ACT
1
Active Channel
-
CHACT[7:0] setting
DEL1-2
3
Ch1/2 Delay Data
-
26-bit Host
Interface setting
DEL3-4
3
Ch3/4 Delay Data
-
26-bit Host
Interface setting
RSRV
2
Reserved Words
200h
18-bit Host
Interface setting
CS
1
Checksum. Calculates the sum of lower 9 bits of 15
words from DID
-
Yes
1.10.2 Audio Control Packet DID Setting
To multiplex audio control packets for audio channels 1 to 4
(inputs AIN1/2 and AIN3/4), the CTRONA bit 2 of Host
Interface register 02Fh must be set HIGH. To multiplex
audio control packets for audio channels 5 to 8 (inputs
AIN5/6 and AIN7/8), the CTRONB bit 2 of Host Interface
register 020h must be set HIGH.
Control packet data can be programmed
corresponding registers in the Host Interface.
via
the
Table 7: Audio Control Packet Group DID Host
Interface Settings
The audio control packet group DID for audio input
channels 1 to 4 is set in CTRIDA[1:0] bits 1-0 of Host
Interface register 02Fh. The audio control packet group DID
for audio input channels 5 to 8 is set in CTRIDB[1:0] bits 3-2
of Host Interface register 020h. Table 7 shows the 2-bit Host
Interface setting for the corresponding audio control packet
group DID.
AUDIO
GROUP
10-BIT DATA
HOST INTERFACE
REGISTER SETTING (2-BIT)
1
1E3h
11b
2
2E2h
10b
3
2E1h
01b
4
1E0h
00b
When CASCADE is set LOW (external pin or register), the
GS1503 will default to audio groups 1 and 2, where the
audio control packet for AIN1/2 and AIN3/4 will be
multiplexed with group 1 DID, and AIN5/6 and AIN7/8 with
group 2 DID.
30 of 83
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Register Settings
NAME
CTRONA
CTRIDA[1:0]
DESCRIPTION
Ch1-4 Audio control packet multiplex enable
(1: Enabled)
ADDRESS
BIT
SETTING
DEFAULT
02F
2
1
1
See
11b
Ch1-4 Audio control packet DID set
1-0
Table 7
RATEA[2:0]
ASXA
Ch1-4 Audio frame number
Ch1-4 Sampling frequency data
030
0
031
7-0
032
3-1
-
0
0
-
0
-
0
-
0
-
0
1
1
See
10b
Ch1-4 Synchronization
0
(0:Synchronous; 1: Non-synchronous)
DEL1-2A[25:0]
DEL3-4A[25:0]
RSRVA[17:0]
CTRONB
CTRIDB[1:0]
Ch1/2 Delay data
Ch3/4 Delay data
Ch1-4 Reserved words
Ch5-8 Audio control packet multiplex enable
(1: Enabled)
033
1-0
034
7-0
035
7-0
036
7-0
037
1-0
038
7-0
039
7-0
03A
7-0
03B
1-0
03C
7-0
03D
7-0
020
2
Ch5-8 Audio control packet DID set
1-0
Table 7
AF_NOB[8:0]
RATEB[2:0]
ASXB
DEL1-2B[25:0]
DEL3-4B[25:0]
RSRVB[17:0]
Ch5-8 Audio frame number
Ch5-8 Sampling frequency data
021
0
022
7-0
023
Ch5-8 Synchronization
(0:Synchronous; 1: Non-synchronous)
Ch5/6 Delay data
Ch7/8 Delay data
Ch5-8 Reserved words
-
0
3-1
-
0
0
-
0
-
0
-
0
-
0
024
1-0
025
7-0
026
7-0
027
7-0
028
1-0
029
7-0
02A
7-0
02B
7-0
02C
1-0
02D
7-0
02E
7-0
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GS1503
AF_NOA[8:0]
two modes in which arbitrary data can be multiplexed into
the Luma channel of the video data stream. A maximum of
255 user data words can be multiplexed in one packet.
Figure 29 shows the structure of the arbitrary data packet.
1.11 ARBITRARY DATA PACKETS
The GS1503 can multiplex arbitrary data packets according
to SMPTE 291M. Typically, this consists of linear time code
(LTC), vertical interval time code (VITC) or other user data,
which is multiplexed once per video field. The GS1503 has
NOTE: Arbitrary data packets will not be multiplexed in the
two lines following the video switching point (see Section
1.8).
GS1503
CS
UDW254[1FE]
UDW253[1FD]
UDW251[1FB]
UDW252[1FC]
UDW3[103]
UDW2[102]
UDW0[100]
LSB
UDW1[101]
DC
DID
SDID
Not b8
Parity bit
ADF
MSB
User Data Words
Contents set in Host Interface registers
Fig. 29 Arbitrary Data Packet Structure
The user is required to enter the following arbitrary data:
Data ID (DID), Secondary Data ID (SDID), Data Count (DC)
and User Data Words (UDW: maximum of 255), via the
PKT[7-0] pins. This GS1503 automatically generates the
Ancillary Data Flag (ADF), Checksum (CS) and bit 8 (Parity
Bit) and bit 9 (Not bit 8).
1.11.1 Arbitrary Data Multiplexing In External Pin Mode
This is the default mode for multiplexing arbitrary data
packets. The GS1503 will set the PKTENO external pin
HIGH when arbitrary data can be input to the device. Two
VCLK cycles after PKTENO goes HIGH, the user should set
the PKTEN arbitrary packet enable pin HIGH. Two VCLK
cycles after PKTEN is set HIGH, arbitrary data can be input
at the PKT[7:0] bus. See Figure 30 for timing.
The PKTENO pin will be set HIGH on all video lines except
the two lines following the video switching point. For
example, with the default setting of line 7 field 1, PKTENO
will not be set HIGH on lines 8 and 9. The switching point is
set in the SW_LNA[12:0] and SW_LNB[12:0] Host Interface
registers for field 1 and field 2 respectively. See Section 1-8.
GS1503
Y/C / C [19:0]
b r
VIN[19:0]
Arbitrary Data Packet Timing
PKTENO
Arbitrary Data Input Enable
PKTEN
Arbitrary Data
PKT[7:0]
2 CLKs
2 CLKs
2 CLKs
2 CLKs
VCLK
PKTENO
PKTEN
CS
UDW254
UDW253
UDW252
UDW251
UDW250
UDW2
UDW1
UDW0
DC
SDID
DID
ADF
ADF
Packet
ADF
Arbitrary
UDW3
Arbitrary Data
PKT[7:0]
Automatically generated by the GS1503
Fig. 30 Arbitrary Data Packet Input Timing Diagram
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1.11.2 Arbitrary Data Multiplexing in Host Interface Mode
ARBITLINEA[11:0] and ARBITLINEB[11:0] should not be
set to the two line numbers following the line number set in
the SW_LNA[12:0] and SW_LNB[12:0] Host Interface
registers. For example, with the default setting of line 7
field 1, ARBITLINEA[11:0] should not be set to line 8 or 9.
Register Settings
NAME
ARBITON
DESCRIPTION
Arbitrary packet multiplex enable (1: Enabled)
ADDRESS
BIT
SETTING
DEFAULT
050
1
1
0
0
1
0
Valid only when ARBITMODE is HIGH
ARBITMODE
Arbitrary packet mode selection
(0: External pin mode; 1: Host mode)
ARBITDID[7-0]
ARBITSDID[7-0]
ARBITDC[7-0]
ARBITLINEA[11:0]
ARBITLINEB[11:0]
ARBITUDW
Arbitrary packet DID setting
051
7-0
-
0
Arbitrary packet SDID setting
052
7-0
-
0
Arbitrary packet DC setting
053
7-0
-
0
Field 1 multiplexing line
054
3-0
-
0
055
7-0
056
3-0
-
0
057
7-0
100-1FE
7-0
-
0
Field 2 multiplexing line
Arbitrary packet UDW setting
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GS1503
To select this mode, set ARBITMODE bit 0 in Host Interface
register 050h HIGH. In this mode, the DID, SDID, DC and
User Data Words must be programmed via the
corresponding Host Interface registers. Set the video line
number for field 1 and field 2 in which the arbitrary data
packets are to be multiplexed using the ARBITLINEA[11:0]
and
ARBITLINEB[11:0]
Host
Interface
registers
respectively. The arbitrary data packet is multiplexed when
ARBITON bit 1 in Host Interface register 050h is set HIGH.
ARBITON should be set LOW during the programming of
the arbitrary data packet in the Host Interface.
Table 8: Multiplex Mode Host Interface Registers
NAME
Video
VM_SEL
Video input format (external pin/internal register)
configuration select. When set LOW, the video
input format is configured via the VM[3:0] pins.
When set HIGH, the video input format is
configured via the "VM[3:0]" bits.
VIDEO_DET
DESCRIPTION
ADDRESS
BIT
R/W
DEFAULT
000
7
R/W
0
Video signal detection flag. Set HIGH when 3
consecutive TRS are detected in the input video
signal.
6
R
0
CRC_ERR
Video input signal CRC error detection. Set HIGH
when a CRC error is detected in the input video
signal. This register is refreshed on every video
frame.
5
R
0
CRC_INS
Video CRC insertion. When set HIGH, the Luma
and Chroma line CRC words are re-calculated
and inserted into the output video signal.
4
R/W
1
VM[3:0]
Video input format selection. See Table 2. Valid
when "VM_SEL" is HIGH.
3-0
R/W
0
EXT_SEL
External EXTH/EXTF input select. When set LOW,
the EXTH and EXTF pins are configured as
outputs. When set HIGH, the GS1503 will insert
TRS and Line Numbers based on signals input at
the EXTH and EXTF pins.
3
R/W
0
SCRBYPASS
Scramble processing bypass select. When set
HIGH, the internal scrambler and NRZ(I) encoder
is bypassed.
2
R/W
0
8-bit input selection. When set HIGH, the GS1503
will accept an 8-bit input video signal.
1
R/W
0
Descramble process bypass select. When set
HIGH, the internal SMPTE 292M descrambler is
bypassed.
0
R/W
0
R/W
569d
R/W
7d
R
0
001
NOTE: The status of the SCRBYPASS external pin
is not updated in this register. The value
programmed in this register is logical OR'd with
the SCRBYPASS external pin setting.
8BIT_SEL
DSCBYPASS
NOTE: The status of the DSCBYPASS external pin
is not updated in this register. The value
programmed in this register is logical OR'd with
the DSCBYPASS external pin setting.
SW_LNB[12:0]
SW_LNA[12:0]
CRC_CNT[11:0]
RSV
Video Field 2 switching line setting. Designates
the video switching point for field 2. The default
line number is 569, as defined by SMPTE 299M.
002
4-0
003
7-0
Video Field 1 switching line setting. Designates
the video switching point for field 1. The default
line number is 7, as defined by SMPTE 299M.
004
4-0
005
7-0
CRC error accumulation. Reports the
accumulated number of CRC errors in one video
frame.
006
3-0
007
7-0
Not used.
008
7-5
-
0
LIMIT_ON
Illegal code re-mapping select. When set HIGH,
input video words between 000-003 are remapped to 004, and values between 3FC-3FF are
re-mapped to 3FB. Valid only when "EXT_SEL" is
set HIGH.
4
R/W
0
VBLK_INS
Vertical blanking enable. When set HIGH, the
output video vertical blanking will be set to 040h
for the Luma channel and 200h for the Chroma
channel.
3
R/W
0
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GS1503
CONTROL
ITEM
Table 8: Multiplex Mode Host Interface Registers (Continued)
CONTROL
ITEM
NAME
HBLK_INS
DESCRIPTION
ADDRESS
Horizontal blanking enable. When set HIGH, the
output video horizontal blanking, including TRS,
line numbers and line CRC words, will be set to
040h for the Luma channel and 200h for the
Chroma channel.
BIT
R/W
DEFAULT
2
R/W
0
Audio
LN_INS
Line insertion enable. When set HIGH, the
GS1503 will insert line numbers into the video
data stream. When set LOW, existing line
numbers will remain in the output video stream.
1
R/W
1
TRS_INS
TRS insertion enable. When set HIGH, the
GS1503 will insert TRS codes into the video data
stream. When set LOW, existing TRS codes will
remain in the output video stream.
0
R/W
1
AM_SEL
Audio input format (external pin/register)
configuration select. When set LOW, the audio
input format is configured via the AM[1:0] pins.
When set HIGH, the audio input format is
configured via the "AM[1:0]" bits.
7
R/W
0
AUD7/8_DET
Ch7/8 audio input signal detection. When set
HIGH, an audio signal has been detected at the
AIN7/8 input pin.
6
R
0
AUD5/6_DET
Ch5/6 audio input signal detection. When set
HIGH, an audio signal has been detected at the
AIN5/6 input pin.
5
R
0
AUD3/4_DET
Ch3/4 audio input signal detection. When set
HIGH, an audio signal has been detected at the
AIN3/4 input pin.
4
R
0
AUD1/2_DET
Ch1/2 audio input signal detection. When set
HIGH, an audio signal has been detected at the
AIN1/2 input pin.
3
R
0
Not used.
2
-
0
1-0
R/W
0
RSV
AM[1:0]
Audio input format select. See Table 3. Valid when
"AM_SEL" is HIGH.
010
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GS1503
NOTE: If blanking of line numbers and TRS words
is required, LN_INS and TRS_INS must be set
LOW.
Table 8: Multiplex Mode Host Interface Registers (Continued)
CONTROL
ITEM
DESCRIPTION
ADDRESS
BIT
R/W
DEFAULT
ACRC7/8_INS
Ch7/8 audio Channel Status CRC insertion. When
set HIGH, the Ch7/8 audio input Channel Status
CRC is re-calculated before being multiplexed
into the Audio Data Packet. Valid only when AES/
EBU audio input format is selected.
011
7
R/W
0
ACRC5/6_INS
Ch5/6 audio Channel Status CRC addition. When
set HIGH, the Ch5/6 audio input Channel Status
CRC is re-calculated before being multiplexed
into the Audio Data Packet. Valid only when AES/
EBU audio input format is selected.
6
R/W
0
ACRC3/4_INS
Ch3/4 audio Channel Status CRC addition. When
set HIGH, the Ch3/4 audio input Channel Status
CRC is re-calculated before being multiplexed
into the Audio Data Packet. Valid only when AES/
EBU audio input format is selected.
5
R/W
0
ACRC1/2_INS
Ch1/2 audio Channel Status CRC addition. When
set HIGH, the Ch1/2 audio input Channel Status
CRC is re-calculated before being multiplexed
into the Audio Data Packet. Valid only when AES/
EBU audio input format is selected.
4
R/W
0
ACS7/8_ERR
Ch7/8 audio Channel Status error detection. When
set HIGH, a Channel Status CRC error has been
detected in the Ch7/8 audio input. Valid only when
AES/EBU audio input format is selected.
3
R
0
ACS5/6_ERR
Ch5/6 audio Channel Status error detection. When
set HIGH, a Channel Status CRC error has been
detected in the Ch5/6 audio input. Valid only when
AES/EBU audio input format is selected.
2
R
0
ACS3/4_ERR
Ch3/4 audio Channel Status error detection. When
set HIGH, a Channel Status CRC error has been
detected in the Ch3/4 audio input. Valid only when
AES/EBU audio input format is selected.
1
R
0
ACS1/2_ERR
Ch1/2 audio Channel Status error detection. When
set HIGH, a Channel Status CRC error has been
detected in the Ch1/2 audio input. Valid only when
AES/EBU audio input format is selected.
0
R
0
AP7/8_ERR
Ch7/8 audio parity error detection. When set
HIGH, an audio parity error has been detected in
the Ch7/8 audio input. Valid only when AES/EBU
audio input format is selected.
3
R
0
AP5/6_ERR
Ch5/6 audio parity error detection. When set
HIGH, an audio parity error has been detected in
the Ch5/6 audio input. Valid only when AES/EBU
audio input format is selected.
2
R
0
AP3/4_ERR
Ch3/4 audio parity error detection. When set
HIGH, an audio parity error has been detected in
the Ch3/4 audio input. Valid only when AES/EBU
audio input format is selected.
1
R
0
AP1/2_ERR
Ch1/2 audio parity error detection. When set
HIGH, an audio parity error has been detected in
the Ch1/2 audio input. Valid only when AES/EBU
audio input format is selected.
0
R
0
AUDIO_CS[7:0]
Audio Channel Status set. Valid in Serial Audio
Input modes. Used to enter the 23 8-bit bytes of
the Audio Channel Status Block, as defined in
AES3-1992.
058
7-0
R/W
:
:
06E
7-0
:
AUDIO_CS
[183:176]
012
See
Table 9
NOTE: The CRC byte is generated internally by
the GS1503.
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GS1503
Audio
Channel
Status
Block
NAME
Table 8: Multiplex Mode Host Interface Registers (Continued)
CONTROL
ITEM
Audio
Data
Packet
DESCRIPTION
ADDRESS
BIT
R/W
DEFAULT
CHACT[7-0]
Audio channel multiplex enable. When set HIGH,
the corresponding audio channel is multiplexed
into the Chroma video data stream. "CHACT[7]"
corresponds to audio input channel 8 and
"CHACT[0]" corresponds to audio input channel 1.
When all bits are set LOW, no audio data packets
will be multiplexed and the GS1503 will be in
bypass mode.
013
7-0
R/W
FFh
CASCADE
Cascade select. When set HIGH, the GS1503 will
default to audio groups 3 and 4. When set LOW,
the GS1503 will default to audio groups 1 and 2.
014
7
R/W
0
Not used.
6
-
-
Ch5-8 audio mute enable. When set HIGH, the
multiplexed audio packets for audio channels 5 to
8 are forced to zero.
5
R/W
0
4
R/W
0
NOTE: The status of the CASCADE external pin is
not updated in this register. The value
programmed in this register is logical OR'd with
the CASCADE external pin setting.
RSV
AMUTEB
NOTE: The status of the MUTE external pin is not
updated in this register. The value programmed in
this register is logical OR'd with the MUTE
external pin setting.
AMUTEA
Ch1-4 audio mute enable. When set HIGH, the
multiplexed audio packets for audio channels 1 to
4 are forced to zero.
NOTE: The status of the MUTE external pin is not
updated in this register. The value programmed in
this register is logical OR'd with the MUTE
external pin setting.
Audio
Control
Packet
DATAIDB[1:0]
Ch5-8 audio group DID setting. Designates the
audio group DID for audio channels 5 to 8.
See Table 5. When CASCADE (external pin or
register) is set LOW, the default setting is audio
group 2. When CASCADE is set HIGH, the default
setting is audio group 4.
3-2
R/W
10b
DATAIDA[1:0]
Ch1-4 audio group DID setting. Designates the
audio group DID for audio channels 1 to 4.
See
Table 5. When CASCADE (external pin or register)
is set LOW, the default setting is audio group 1.
When CASCADE is set HIGH, the default setting is
audio group 3.
1-0
R/W
11b
7-3
-
0
CTRONB
RSV
Not used.
Ch5-8 audio control packet multiplex enable.
When set HIGH, the audio control packets for
audio channels 5 to 8 will be multiplexed into the
Luma channel of the video data stream.
020
2
R/W
1
CTRIDB[1:0]
Ch5-8 audio control packet DID setting.
Designates the audio control packet DID for audio
channels 5 to 8. See Table 7. The default setting is
audio group 2.
1-0
R/W
10b
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GS1503
NAME
Table 8: Multiplex Mode Host Interface Registers (Continued)
CONTROL
ITEM
DESCRIPTION
ADDRESS
AF_NOB[8:0]
Ch5-8 audio frame number. Designates the audio
frame number for audio channels 5 to 8. Will be
multiplexed into the audio control packet as per
SMPTE 299M.
Ch5-8 sampling frequency set. Designates the
audio sampling frequency for audio channels 5 to
8. Will be multiplexed into the RATE word of the
audio control packet as per SMPTE 299M. The
default setting is 48kHz.
RATEB[2:0]
ASXB
DEL1-2B[25:0]
DEL3-4B[25:0]
RSRVB[17:0]
BIT
R/W
DEFAULT
021
0
R/W
0
022
7-0
023
3-1
R/W
0
0
R/W
0
R/W
0
R/W
0
R/W
0
Ch5-8 synchronization set. When set HIGH, the
"asx" bit of the audio control packet RATE word
designates audio channels 5 to 8 as
asynchronous, as per SMPTE 299M. When set
LOW, the "asx" bit of the audio control packet
RATE word designates synchronous audio
(default setting).
Ch5/6 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 5 and 6. Will be multiplexed into the
audio control packet as per SMPTE 299M.
024
1-0
025
7-0
026
7-0
027
7-0
Ch7/8 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 7 and 8. Will be multiplexed into the
audio control packet as per SMPTE 299M.
028
1-0
029
7-0
02A
7-0
02B
7-0
02C
1-0
02D
7-0
02E
7-0
02F
7-3
-
0
Ch5-8 reserve words. Designates the value set in
the RSRV words of the audio control packet for
audio channels 5 to 8, as per SMPTE 299M.
NOTE: As these words are reserved for future use,
they should be set to zero.
RSV
Not used.
CTRONA
Ch1-4 audio control packet multiplex enable.
When set HIGH, the audio control packets for
audio channels 1 to 4 will be multiplexed into the
Luma channel of the video data stream.
2
R/W
1
CTRIDA[1:0]
Ch1-4 audio control packet DID setting.
Designates the audio control packet DID for audio
channels 1 to 4. See Table 7. The default setting is
audio group 1.
1-0
R/W
11b
AF_NOA[8:0]
Ch1-4 audio frame number. Designates the audio
frame number for audio channels 5 to 8. Will be
multiplexed into the audio control packet as per
SMPTE 299M.
030
0
R/W
0
031
7-0
Ch1-4 sampling frequency set. Designates the
audio sampling frequency for audio channels 1 to
4. Will be multiplexed into the RATE word of the
audio control packet as per SMPTE 299M. The
default setting is 48kHz.
032
3-1
R/W
0
0
R/W
0
RATEA[2:0]
ASXA
Ch1-4 synchronization set. When set HIGH, the
"asx" bit of the audio control packet RATE word
designates audio channels 1 to 4 as
asynchronous, as per SMPTE 299M. When set
LOW, the "asx" bit of the audio control packet
RATE word designates synchronous audio
(default setting).
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GS1503
NAME
Table 8: Multiplex Mode Host Interface Registers (Continued)
CONTROL
ITEM
DESCRIPTION
ADDRESS
BIT
R/W
DEFAULT
DEL1-2A[25:0]
Ch1/2 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 1 and 2. Will be multiplexed into the
audio control packet as per SMPTE 299M.
033
1-0
R/W
0
034
7-0
035
7-0
036
7-0
Ch3/4 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 3 and 4. Will be multiplexed into the
audio control packet as per SMPTE 299M.
037
1-0
R/W
0
038
7-0
039
7-0
R/W
0
DEL3-4A[25:0]
RSRVA[17:0]
Ch1-4 reserve words. Designates the value set in
the RSRV words of the audio control packet for
audio channels 1 to 4, as per SMPTE 299M.
03A
7-0
03B
1-0
03C
7-0
03D
7-0
050
1
R/W
0
0
R/W
0
NOTE: As these words are reserved for future use,
they should be set to zero.
Arbitrary
Data
Packet
ARBITON
Arbitrary data packet multiplex. Valid only when
"ARBITMODE" is HIGH. When set HIGH, arbitrary
data packets will be multiplexed into the Luma
video data stream using the Host Interface
register settings.
ARBITMODE
Arbitrary packet mode select. When set HIGH,
arbitrary data packets are multiplexed using the
Host Interface register settings. When set LOW,
arbitrary data packets are multiplexed using the
external pin inputs.
Arbitrary packet Data ID setting. Designates the 8
LSBs of the arbitrary data packet DID word. The 2
MSBs are internally generated. "ARBITDID[7]" is
the MSB and "ARBITDID[0]" is the LSB. Valid only
when "ARBITMODE" is HIGH.
051
7-0
R/W
0
ARBITSDID[7:0]
Arbitrary packet Secondary Data ID setting.
Designates the 8 LSBs of the arbitrary data
packet secondary DID word. The 2 MSBs are
internally generated. "ARBITSDID[7]" is the MSB
and "ARBITSDID[0]" is the LSB. Valid only when
"ARBITMODE" is HIGH.
052
7-0
R/W
0
ARBITDC[7:0]
Arbitrary packet DC setting. Designates the 8
LSBs of the arbitrary data packet Data Count
word. The 2 MSBs are internally generated.
"ARBITDC[7]" is the MSB and "ARBITDC[0]" is the
LSB. Valid only when "ARBITMODE" is HIGH.
053
7-0
R/W
0
ARBITLINEB[11:0]
Field 2 arbitrary packet multiplex line number
setting. Designates the field 2 video line in which
the arbitrary data packets will be multiplexed.
Valid only when "ARBITMODE" is HIGH.
054
3-0
R/W
0
055
7-0
Field 1 arbitrary packet multiplex line number
setting. Designates the field 1 video line in which
the arbitrary data packets will be multiplexed.
Valid only when "ARBITMODE" is HIGH.
056
3-0
R/W
0
057
7-0
Arbitrary packet User Data Word set. Designates
the 8 LSBs for each of the 255 arbitrary packet
User Data Words. The 2 MSBs are internally
generated. Valid only when "ARBITMODE" is HIGH.
100
7-0
R/W
0
:
:
1FE
7-0
ARBITDID[7:0]
ARBITLINEA[11:0]
ARBITUDW0
:
ARBITUDW254
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GS1503
NAME
Table 9: Audio Channel Status Default Values
ADDRESS
VALUE
058
85
CHANNEL STATUS
Professional; Valid Audio; No Emphasis (manual override disabled); 48kHz Sampling Frequency
(manual override disabled).
059
08
Two-Channel Mode (manual override disabled).
05A
2C
Maximum Audio Sample Word Length is 24bits; Encoded Audio Word Length is 24-bit.
Others
00
-
GS1503
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2. DEMULTIPLEX MODE
2.1 FUNCTIONAL OVERVIEW
The video input format can be one of the following
configurations:
10-bit Y and Cb/Cr input with TRS and Line Numbers
20-bit scrambled input
The video output format can be one of the following
configurations:
20-bit scrambled output
10-bit Y and Cb/Cr output
Up to a maximum of 8 channels of 48kHz digital audio can
be demultiplexed per device. The audio output format can
be selected as either AES/EBU, or one of two serial audio
data output modes. A maximum of 16 channels of audio
can be demultiplexed by cascading two devices in parallel.
The GS1503 will also demultiplex arbitrary data packets as
defined in SMPTE 291M. The arbitrary data packets can
serve as an auxiliary data signal for proprietary
applications. The GS1503 can be configured to demultiplex
arbitrary data packets and output them at dedicated
external pins or via the Host Interface registers. Up to a
maximum of 255 8-bit words can be demultiplexed
(excluding Ancillary Data Flags and Checksum).
To use the GS1503 in Demultiplex Mode, set the
MUX/DEMUX external pin HIGH.
2.2 VIDEO STANDARD
The video standard is selected from the VM[3:0] external
pins or VM[3:0] bits 3-0 in Host Interface register 000h. To
configure the video standard via the Host Interface, VM_SEL
bit 7 in Host Interface register 000h must be set HIGH. The
GS1503 will default to the VM[3:0] external pin setting. The
supported video standards are listed in Table 10.
.
Table 10: Supported Video Standards
VM [3:0]
INPUT FORMAT
REFERENCE SMPTE DOCUMENT
SMPTE 292M LEVEL
1110b
1035i (30 & 30/1.001 Hz)
260M
A, B
1100b
1080i (25 Hz)
295M
C
1000b
1080i/1080sF (30 & 30/1.001 Hz)
274M, RP211
D, E
1010b
1080i/1080sF (25 Hz)
274M, RP211
F
1111b
1080sF (24 & 24/1.001 Hz)
RP211
0010b
1080p (30 & 30/1.001 Hz)
274M
G, H
0100b
1080p (25 Hz)
274M
I
0110b
1080p (24 & 24/1.001 Hz)
274M
J, K
0000b
720p (60 & 60/1.001 Hz)
296M
L, M
0001b
720p (30 & 30/1.001 Hz)
296M
0011b
720p (50 Hz)
296M
0101b
720p (25 Hz)
296M
0111b
720p (24 & 24/1.001 Hz)
296M
All other settings are reserved
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GS1503
The GS1503 HD Embedded Audio CODEC fully supports
the demultiplexing of Audio Data Packets, Audio Control
Packets and Arbitrary Data Packets as per SMPTE 291M
and 299M. The device can be configured to operate with all
video standards defined in SMPTE 292M, levels A through
M. The GS1503 also supports the 1080/24PsF, 25PsF and
30PsF video formats as described in SMPTE RP211.
Audio control packets, as defined in SMPTE 299M, can also
be demultiplexed to obtain information about the nature of
the embedded audio data. The contents of the audio
control packet are stored in registers of the Host Interface.
Register Settings
NAME
VM_SEL
DESCRIPTION
0: External pin select
ADDRESS
BIT
SETTING
DEFAULT
000
7
1
0
See
0
1: Register select
VM[3:0]
Video formal selection (VM[3] is MSB)
3-0
Table 10
GS1503
2.3 VIDEO INPUT FORMAT
2.3.1 20-bit Scrambled Input
GS1503
Y/C b / Cr [19:0]
VIN[19:0]
DSCBYPASS
Fig. 31 20-bit Scrambled Input Configuration
Register Settings (Default Mode)
NAME
EXT_SEL
DESCRIPTION
0: EXTH/EXTF output select
ADDRESS
BIT
SETTING
DEFAULT
001
3
0
0
1
0
0
0
0
0
1: EXTH/EXTF input select
8BIT_SEL
0: 10-bit mode select
1: 8-bit mode select
DSCBYPASS
0: Descrambling enabled
1: Bypass descrambling
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2.3.2 10-bit Y and Cb/Cr Input with TRS and Line Numbers
GS1503
Y[9:0]
VIN[19:10]
C b/ C r[9:0]
GS1503
VIN[9:0]
EXTF
+3.3V
EXTH
DSCBYPASS
Vn
V0
XYZ
000
000
3FF
CRC1
LN1
CRC0
8
3
LN0
XYZ
000
000
3FF
Y, C b / Cr
10-bit
0
Fig. 32 10-bit Y and Cb/Cr Input with TRS and Line Numbers Configuration
Video
4 VCLK
EXTH
EXTF
Fig. 33 Video Input Format (10-bit with TRS and Line Numbers)
Register Settings
NAME
EXT_SEL
DESCRIPTION
0: EXTH/EXTF output select
ADDRESS
BIT
SETTING
DEFAULT
001
3
0
0
1
0
0
0
1
0
1: EXTH/EXTF input select
8BIT_SEL
0: 10-bit mode select
1: 8-bit mode select
DSCBYPASS
0: Descrambling enabled
1: Bypass descrambling
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2.4 VIDEO OUTPUT FORMAT
2.4.1 10-bit Y and Cb/Cr Output
GS1503
Y[9:0]
VOUT[19:10]
GS1503
VOUT[9:0]
C b / C r [9:0]
+3.3V
SCRBYPASS
Fig. 34 10-bit Y and Cb/Cr Output Configuration
Register Settings
NAME
SCRBYPASS
DESCRIPTION
0: SMPTE 292M scrambling enabled
ADDRESS
BIT
SETTING
DEFAULT
001
2
1
0
1: Bypass SMPTE 292M scrambling
2.4.2 20-bit Scrambled Output
GS1503
VOUT[19:0]
Y/C b / Cr [19:0]
SCRBYPASS
Fig. 35 20-bit Scrambled Output Configuration
Register Settings (Default Mode)
NAME
SCRBYPASS
DESCRIPTION
0: SMPTE 292M scrambling enabled
ADDRESS
BIT
SETTING
DEFAULT
001
2
0
0
1: Bypass SMPTE 292M scrambling
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2.5 VIDEO DATA PROCESSING
2.5.1 Video Signal Input Detection
The GS1503 will set the VIDEO_DET external pin HIGH
when three consecutive TRS are detected in the input video
signal. Also, the VIDEO_DET bit of Host Interface register
000h is set HIGH.
NAME
VIDEO_DET
DESCRIPTION
Video input signal detection (1: Detection)
ADDRESS
BIT
SETTING
DEFAULT
000
6
-
0
ADDRESS
BIT
SETTING
DEFAULT
2.5.2 Video Input CRC Error Detection
The GS1503 will set the CRC_ERR external pin HIGH when
a CRC error is detected in the input video signal. Also, the
CRC_ERR bit 5 of Host Interface register 000h is set HIGH.
The number of CRC errors accumulated in one video frame
can be read form CRC_CNT[11:0] in Host Interface
registers 006h and 007h.
Register Settings
NAME
DESCRIPTION
CRC_ERR
Video input signal CRC error detection (1: Detection)
000
5
-
0
CRC_CNT[11:0]
Video input signal CRC error accumulation in 1 video
frame
006
3-0
-
0
007
7-0
ADDRESS
BIT
SETTING
DEFAULT
000
4
1
1
2.5.3 Video Output CRC Insertion
When the CRC_INS bit 4 of Host Interface register 000h is
set HIGH, the GS1503 will re-calculate the video line CRC
words. The re-calculated CRC words are inserted in the
video output signal. When CRC_INS is set LOW, the line
CRC words are not updated and existing CRC words at the
input of the device will be output unchanged.
Register Settings
NAME
CRC_INS
DESCRIPTION
Video line CRC insertion (1: Insertion)
2.5.4 Input Blanking
When VBLK_INS bit 3 of Host Interface register 008h is set
HIGH, the input video vertical blanking will be set to 040h
for the Luma channel and 200h for the Chroma channel.
When HBLK_INS bit 2 of Host Interface register 008h is set
HIGH, the input video horizontal blanking will be set to 040h
for the Luma channel and 200h for the Chroma channel.
The TRS, line number and CRC words will also be set to
blanking values.
The blanking function is performed at the output of the
GS1503 video data stream. If the HBLK_INS bit is set HIGH,
any embedded audio or control packets will be replaced
with blanking codes. The GS1503 will demultiplex data
contained in the packets, prior to the blanking function, and
output at the corresponding pins.
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GS1503
Register Settings
Register Settings
NAME
DESCRIPTION
VBLK_INS
Input vertical blanking (1: Enabled)
HBLK_INS
Input horizontal blanking (1: Enabled)
ADDRESS
BIT
SETTING
DEFAULT
008
3
1
0
2
1
0
ADDRESS
BIT
SETTING
DEFAULT
008
1
1
1
GS1503
2.5.5 Line Number Insertion
When LN_INS bit 1 of Host Interface register 008h is set
HIGH, the GS1503 will insert line numbers into the video
data stream. When set LOW, existing line numbers will
remain in the output video stream.
Register Settings
NAME
LN_INS
DESCRIPTION
Line number insertion (1: Enabled)
2.5.6 TRS Word Insertion
When TRS_INS bit 0 of Host Interface register 008h is set
HIGH, the GS1503 will insert TRS codes into the video data
stream. When set LOW, existing TRS codes will remain in
the output video stream.
Register Settings
NAME
TRS_INS
DESCRIPTION
TRS word insertion (1: Enabled)
ADDRESS
BIT
SETTING
DEFAULT
008
0
1
1
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Table 11: Audio Output Formats
2.6 AUDIO DATA PROCESSING
AM[1:0]
2.6.1 Digital Audio Output Format
The GS1503 has two audio output formats, AES/EBU digital
audio output and serial output, as listed in Table 11. The
serial audio output can be formatted in the following two
modes. See Figure 36:
AUDIO OUTPUT FORMAT
0
Serial audio output: 24-bit Left Justified; MSB first
1
Serial audio output: 24-bit Right Justified; MSB last
2
AES/EBU audio output
GS1503
24-bit Left Justified; MSB first
24-bit Right Justified; MSB last
The audio output format is configured using the AM[1:0]
external pins or via AM[1:0] bits 1-0 in Host Interface
register 010h. To configure the audio output format via the
Host Interface, AM_SEL bit 7 in Host Interface register 010h
must be set HIGH. The GS1503 will default to the AM[1:0]
external pin setting.
NOTE: When configured in AES/EBU audio mode, the
GS1503 will not output a 48kHz (fs) word clock at the
WCOUTA and WCOUTB pins.
Register Settings
NAME
DESCRIPTION
AM_SEL
ADDRESS
BIT
SETTING
DEFAULT
010
7
1
0
See
0
0: External pin setting
1: Register setting
AM[1:0]
Audio output format selection (AM[1] is MSB)
1-0
Table 11
Channel 1
WCOUTA/WCOUTB
Channel 2
MSB
MODE0
MSB
23
0
23
0
LSB
0
MODE2
(AES/EBU)
LSB
0
MODE1
23
3 4
Sync
Preamble
2728293031 0
0
3 4
Sync
V U C P Preamble
24-bit Audio Sample Word
23
2728293031
24-bit Audio Sample Word
V UC P
Validity Bit
User Data Bit
Channel Status Bit
Parity Bit
Fig. 36 Audio Output Formats
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2.6.2 Digital Audio Output Timing
2.6.2.1 AES/EBU Format Output
The user can access the Audio Channel Status Block
information via the AUDIO_CS[183:0] bits in Host Interface
registers 058h to 06Eh. To read the Audio Channel Status
information, the CS_MODE bit 3 of Host Interface register
06Fh should be set HIGH. The embedded audio channel
When CS_MODE is set LOW, the Audio Channel Status
information in the AES/EBU audio outputs will be replaced
with data programmed in the AUDIO_CS[183:0] bits of Host
Interface registers 058h to 06Eh.
Register Settings
NAME
DESCRIPTION
CS_WEND
ADDRESS
BIT
SETTING
DEFAULT
06F
5
-
0
4
1
0
3
1
0
2-0
-
000b
Audio Channel Status write flag
(1: Data ready)
CS_RQST
Audio Channel Status request
(1: enable)
CS_MODE
0: Audio Channel Status replace
1: Audio Channel Status demultiplex
CH_SEL[2:0]
Audio Channel Status select
GS1503
Y/C b / Cr [19:0]
VIN[19:0]
AOUT1/2
AOUT3/4
6.144MHz (128 fs)
Audio Channels 3 & 4
ACLKA
AOUT5/6
AOUT7/8
6.144MHz (128 fs)
Audio Channels 1 & 2
Audio Channels 5 & 6
Audio Channels 7 & 8
ACLKB
6.144MHz
ACLKA/B
AOUT1/2, AOUT3/4
AOUT5/6, AOUT7/8
Fig. 37 AES/EBU Audio Output Configuration and Timing
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GS1503
A 6.144MHz (128fs) audio clock must be supplied to the
ACLKA and ACLKB inputs. ACLKA is used to clock AES/
EBU digital audio signal for channels 1 to 4 (AOUT1/2 and
AOUT3/4). ACLKB is used to clock AES/EBU digital audio
signal for channels 5 to 8 (AOUT5/6 and AOUT7/8). In AES/
EBU output mode, the audio word clock inputs WCINB and
WCINB should be grounded. See Figure 37 for timing.
from which the Channel Status information is to be
extracted is set in the CH_SEL[2:0] bits 2-0 of Host
Interface register 06Fh. The CH_SEL[2:0] setting for audio
channel 1 is 000b, through to 111b for channel 8. The
CS_RQST bit must be set HIGH to begin the process of
extracting the Audio Channel Status information. Once
extracted, the GS1503 will set CS_WEND bit HIGH and the
user can access the data for Host Interface registers 058h
to 06Eh.
2.6.2.2
Serial Audio Output Modes
A 6.144MHz (128fs) audio clock must be supplied to the
ACLKA and ACLKB inputs. An audio word clock at 48kHz
(fs) will be output at the WCOUTA and WCOUTB external
pins, as shown in Figure 38.
When DEC_MODE (external pin or register setting) is set
LOW, the audio word clock inputs WCINB and WCINB
should be grounded.
GS1503
Y/C b / Cr [19:0]
VIN[19:0]
AOUT1/2
AOUT3/4
6.144MHz (128 fs)
ACLKA
WCOUTA
AOUT5/6
AOUT7/8
6.144MHz (128 fs)
ACLKB
WCOUTB
64 CLKs
Audio Channels 1 & 2
Audio Channels 3 & 4
48kHz (fs)
Audio Channels 5 & 6
Audio Channels 7 & 8
48kHz (fs)
64 CLKs
ACLKA/B
WCOUTA/B
AOUT1/2, AOUT3/4
AOUT5/6, AOUT7/8
Fig. 38 Serial Audio Output Configuration and Timing
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GS1503
The user can access the Audio Channel Status Block
information via the AUDIO_CS[183:0] bits in Host Interface
registers 058h to 06Eh. To read the Audio Channel Status
information, the CS_MODE bit 3 of Host Interface register
06Fh should be set HIGH. The embedded audio channel
from which the Channel Status information is to be
extracted is set in the CH_SEL[2:0] bits 2-0 of Host
Interface register 06Fh. The CH_SEL[2:0] setting for audio
channel 1 is 000b, through to 111b for channel 8.
The CS_RQST bit must be set HIGH to begin the process of
extracting the Audio Channel Status information. Once
extracted, the GS1503 will set CS_WEND bit HIGH and the
user can access the data for Host Interface registers 058h
to 06Eh.
2.6.3 Audio Clock Phase Locked Loop
Figure 39 shows the configuration for deriving the
6.144MHz audio clock in AES/EBU and serial audio output
modes. The GS1503 will internally synchronize the audio
output to the corresponding ACLK. This configuration is not
required when DEC_MODE is set HIGH. See the Reference
Design Section 3 for circuit specifics.
GS1503
6.144MHz (128 fs)
GS1503
Y/C b / C r [19:0]
VIN[19:0]
Audio Channels 1 & 2
AOUT1/2
Audio Channels 3 & 4
AOUT3/4
Low
ACLKA
VCXO
Pass
PLLCNTA
Filter
Audio Channels 5 & 6
AOUT5/6
Audio Channels 7 & 8
AOUT7/8
Low
ACLKB
÷4
24.576MHz
VCXO
Pass
PLLCNTB
÷4
24.576MHz
Filter
6.144MHz (128 fs)
Fig. 39 Block Diagram of GS1503 Audio Clock PLL
2.6.4 Audio Data Packet Detection
The audio data packet detect registers will be set HIGH
when a corresponding audio group DID has been detected
in the Chroma channel of the input video stream. Host
Interface register 013h, bits 7-4, report the individual audio
groups detected.
Register Settings
NAME
DESCRIPTION
ADDRESS
BIT
SETTING
DEFAULT
013
7
-
0
ADPG4_DET
Audio group 4 data packet detection (1:Detection)
ADPG3_DET
Audio group 3 data packet detection (1:Detection)
6
-
0
ADPG2_DET
Audio group 2 data packet detection (1:Detection)
5
-
0
ADPG1_DET
Audio group 1 data packet detection (1:Detection)
4
-
0
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2.6.5 ECC Error Detection & Correction
When a one-bit error is detected in a bit array of the ECC
protected region of the audio data packet with audio group
DID set in DATAIDA[1:0], ECCA_ERR bit 1 in Host Interface
register 015h is set HIGH. When a one-bit error is detected
in the ECC protected region of the audio data packet with
audio group DID set in DATAIDB[1:0], the ECCB_ERR bit 5
in Host Interface register 015h is set HIGH. In both cases,
the ERROR external pin will also be set HIGH.
The number of audio data packets corrected in one video
frame will be reported in the corresponding Host Interface
registers CORRECTA[11:0] and CORRECTB[11:0]. The
GS1503 will also report the number of audio data packets
which could not be corrected in one video frame in the
corresponding Host Interface registers NO_CORRECTA[11:0]
and NO_CORRECTB[11:0].
Register Settings
NAME
ECCB_ERR
DESCRIPTION
Ch5-8 Audio data packet ECC error detection
ADDRESS
BIT
SETTING
DEFAULT
015
5
-
0
1
-
0
016
3-0
-
0
017
7-0
018
3-0
-
0
019
7-0
01A
3-0
-
0
01B
7-0
01C
3-0
-
0
01D
7-0
013
1
1
1
0
1
1
(1: Detection)
ECCA_ERR
Ch1-4 Audio data packet ECC error detection
(1: Detection)
CORRECTB[11:0]
NO_CORRECTB[11:0]
CORRECTA[11:0]
NO_CORRECTA[11:0]
Ch5-8 correctable packets in one video frame
Ch5-8 un-correctable packets in one video frame
Ch1-4 correctable packets in one video frame
Ch5-8 un-correctable packets in one video frame
ECCB_ON
Ch5-8 Audio data packet error correction (1: ON)
ECCA_ON
Ch1-4 Audio data packet error correction (1: ON)
2.6.6 Audio Data Packet Error Detection
When the 1-255 count sequence in the Data Block Number
(DBN) word of audio data packets with audio group DID set
in DATAIDA[1:0] is discontinuous, the DBNA_ERR bit 3 of
Host Interface register 015h will be set HIGH. When the1255 count sequence in the DBN word of audio data packets
with audio group DID set in DATAIDB[1:0] is discontinuous,
the DBNB_ERR bit 7 of Host Interface register 015h will be
set HIGH.
The GS1503 will check the parity (bit 8) for the CLK, CH1-4
and ECC0-5 words in the embedded audio data packets.
When a parity bit error is detected in audio data packets
with audio group DID set in DATAIDA[1:0], the
ADPB8A_ERR bit 2 of Host Interface register 015h will be
set HIGH. When a parity bit error is detected in audio data
packets with audio group DID set in DATAIDB[1:0], the
ADPB8B_ERR bit 6 of Host Interface register 015h will be
set HIGH.
The GS1503 will re-calculate the audio data packets
Checksum and compare against the embedded Checksum
word. When a Checksum error is detected in audio data
packets with audio group DID set in DATAIDA[1:0], the
ADPCSA_ERR bit 0 of Host Interface register 015h will be
set HIGH. When a Checksum error is detected in audio
data packets with audio group DID set in DATAIDB[1:0], the
ADPCSB_ERR bit 4 of Host Interface register 015h will be
set HIGH.
When any of the above errors are detected, the ERROR
external pin will also be set HIGH.
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GS1503
The GS1503 performs BCH(31,25) forward error detection
and correction as described in SMPTE 299M. The error
correction for audio data packets with audio group DID set
in DATAIDA[1:0] is activated when ECCA_ON bit 0 of Host
Interface register 013h is set HIGH. Similarly, error
correction for audio data packets with audio group DID set
in DATAIDB[1:0] is activated when ECCB_ON bit 1 of Host
Interface register 013h is set HIGH
A bit array is defined as all 24 bits of bit 0. The next bit
array is all 24 bits of bit 1, and so on through to bit 7. Up to
8 bits in error can be corrected, providing each bit error is
in a different bit array. When there are two bits in error in the
same 24-bit array, the errors will be detected, but not
corrected. When there are more than two bits in error in a
single bit array, the errors will not be detected or corrected.
Register Settings
NAME
DESCRIPTION
ADDRESS
BIT
SETTING
DEFAULT
015
7
-
0
Ch5-8 Audio data packet DBN error detection
(1:Detection)
ADPB8B_ERR
Ch5-8 Audio data packet bit8 error detection
(1:Detection)
6
-
0
ADPCSB_ERR
Ch5-8 Audio data packet CS error detection
(1:Detection)
4
-
0
DBNA_ERR
Ch1-4 Audio data packet DBN error detection
(1:Detection)
3
-
0
ADPB8A_ERR
Ch1-4 Audio data packet bit8 error detection
(1:Detection)
2
-
0
ADPCSA_ERR
Ch1-4 Audio data packet CS error detection
(1:Detection)
0
-
0
2.6.7 Audio Data Packet DID Setting
The audio group DID for audio output channels 1 to 4
(AOUT1/2 and AOUT3/4) is set in DATAIDA[1:0] bits 1-0 of
Host Interface register 014h. The audio group DID for audio
output channels 5 to 8 (AOUT5/6 and AOUT7/8) is set in
DATAIDB[1:0] bits 3-2 of Host Interface register 014h. Table
12 shows the 2-bit Host Interface setting for the
corresponding audio group DID.
Table 12: Audio Group DID Host Interface Settings
When CASCADE is set LOW (external pin or register), the
GS1503 will default to audio groups 1 and 2, where AOUT1/
2 and AOUT3/4 will be demultiplexed from audio data
packets with group 1 DID, and AOUT5/6 and AOUT7/8 will
be demultiplexed from audio data packets with group 2
DID.
AUDIO
GROUP
10-BIT DATA
HOST INTERFACE
REGISTER SETTING (2-BIT)
1
2E7h
11b
2
1E6h
10b
3
1E5h
01b
4
2E4h
00b
Register Settings (CASCADE set LOW)
NAME
DATAIDA[1-0]
DATAIDB[1-0]
DESCRIPTION
Ch1-4 Audio data packet DID setting
ADDRESS
BIT
014
1-0
Ch5-8 Audio data packet DID setting
3-2
SETTING
DEFAULT
See
11b
Table 12
10b
When CASCADE is set HIGH (external pin or register), the
GS1503 will default to audio groups 3 and 4, where
AOUT1/2 and AOUT3/4 will be demultiplexed from audio
data packets with group 3 DID, and AOUT5/6 and AOUT7/8
will be demultiplexed from audio data packets with group 4
DID.
Register Settings (CASCADE set HIGH)
NAME
DATAIDA[1-0]
DATAIDB[1-0]
DESCRIPTION
Ch1-4 Audio data packet DID setting
Ch5-8 Audio data packet DID setting
ADDRESS
BIT
014
1-0
3-2
SETTING
DEFAULT
See
01b
Table 12
00b
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GS1503
DBNB_ERR
external pin or CASCADE bit 7 of Host Interface register
014h is set HIGH. When set HIGH, the GS1503 will default
to audio groups 3 and 4. When set LOW, the GS1503 will
default to audio groups 1 and 2.
2.7 DEMULTIPLEX CASCADE MODE
Two GS1503 devices can be cascaded in parallel to allow
up to 16 channels of audio to be demultiplexed (only one
device requires CASCADE to be set HIGH). Figure 40
shows the cascade architecture for a 16-channel system. To
configure the GS1503 for cascade mode, the CASCADE
GS1503
GS1503
Y/C b /Cr [19:0]
VOUT[19:0]
VIN[19:0]
AOUT1/2
AOUT3/4
AOUT5/6
AOUT7/8
Y/C b /Cr [19:0]
Audio Channels 1 & 2
Audio Channels 3 & 4
Audio Channels 5 & 6
Audio Channels 7 & 8
Audio
Group 1
Audio
Group 2
CASCADE
GS1503
VIN[19:0]
VOUT[19:0]
AOUT1/2
AOUT3/4
AOUT5/6
AOUT7/8
Y/C b /Cr [19:0]
Audio Channels 9 & 10
Audio Channels 11 & 12
Audio Channels 13 & 14
Audio Channels 15 & 16
Audio
Group 3
Audio
Group 4
+3.3V
CASCADE
Fig. 40 Demultiplexing 16 Channels of Audio using Cascade Architecture
Register Settings
NAME
CASCADE
DESCRIPTION
Cascade enable (1: Enabled)
2.8 AUDIO CONTROL PACKETS
ADDRESS
BIT
SETTING
DEFAULT
014
7
1
0
2.8.2 Audio Control Packet DID Setting
2.8.1 Audio Control Packet Detection
The audio control packet detect registers will be set HIGH
when a corresponding audio group DID has been detected
in the Luma channel of the input video stream. Host
Interface register 020h, bits 7-4, report the individual audio
groups detected.
To demultiplex audio control packets for audio channels 1
to 4 (AOUT1/2 and AOUT3/4), the CTRONA bit 2 of Host
Interface register 02Fh is set HIGH. To demultiplex audio
control packets for audio channels 5 to 8 (AOUT5/6 and
AOUT7/8), the CTRONB bit 2 of Host Interface register
020h is set HIGH.
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Register Settings
NAME
DESCRIPTION
ADDRESS
BIT
SETTING
DEFAULT
020
7
-
0
Audio group 4 control packet detection (1: Detection)
ACPG3_DET
Audio group 3 control packet detection (1: Detection)
6
-
0
ACPG2_DET
Audio group 2 control packet detection (1: Detection)
5
-
0
ACPG1_DET
Audio group 1 control packet detection (1: Detection)
4
-
0
The audio control packet group DID for audio output
channels 1 to 4 is set in CTRIDA[1:0] bits 1-0 of Host
Interface register 02Fh. The audio control packet group DID
for audio output channels 5 to 8 is set in CTRIDB[1:0] bits
3-2 of Host Interface register 020h. Table 13 shows the 2-bit
Host Interface setting for the corresponding audio control
packet group DID.
Table 13: Audio Control Packet Group DID Host
Interface Settings
When CASCADE is set LOW (external pin or register), the
GS1503 will default to audio groups 1 and 2, where audio
control packet data for channels 1 to 4 will be
demultiplexed from packets with group 1 DID, and audio
control packet data for channels 5 to 8 will be
demultiplexed from packets with group 2 DID.
AUDIO
GROUP
10-BIT DATA
HOST INTERFACE
REGISTER SETTING (2-BIT)
1
1E3h
11b
2
2E2h
10b
3
2E1h
01b
4
1E0h
00b
Control packet data is accessible via the corresponding
registers in the Host Interface.
Register Settings
NAME
CTRONA
DESCRIPTION
Ch1-4 Audio control packet demultiplex enable
ADDRESS
BIT
SETTING
DEFAULT
02F
2
1
1
See
11b
(1: Enabled)
CTRIDA[1:0]
Ch1-4 Audio control packet DID set
1-0
Table 13
AF_NOA[8:0]
RATEA[2:0]
ASXA
Ch1-4 Audio frame number
Ch1-4 Sampling frequency data
030
0
031
7-0
032
3-1
-
0
0
-
0
-
0
-
0
-
0
Ch1-4 Synchronization
0
(0: Synchronous; 1: Non-synchronous)
DEL1-2A[25:0]
DEL3-4A[25:0]
RSRVA[17:0]
Ch1/2 Delay data
Ch3/4 Delay data
Ch1-4 Reserved words
033
1-0
034
7-0
035
7-0
036
7-0
037
1-0
038
7-0
039
7-0
03A
7-0
03B
1-0
03C
7-0
03D
7-0
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GS1503
ACPG4_DET
Register Settings
NAME
CTRONB
DESCRIPTION
Ch5-8 Audio control packet demultiplex enable
ADDRESS
BIT
SETTING
DEFAULT
020
2
1
1
See
10b
(1: Enabled)
CTRIDB[1:0]
Ch5-8 Audio control packet DID set
1-0
Table 13
RATEB[2:0]
ASXB
Ch5-8 Audio frame number
Ch5-8 Sampling frequency data
021
0
022
7-0
023
Ch5-8 Synchronization
-
0
3-1
-
0
0
-
0
-
0
-
0
-
0
(0: Synchronous; 1: Non-synchronous)
DEL1-2B[25:0]
DEL3-4B[25:0]
RSRVB[17:0]
Ch5/6 Delay data
Ch7/8 Delay data
Ch5-8 Reserved words
024
1-0
025
7-0
026
7-0
027
7-0
028
1-0
029
7-0
02A
7-0
02B
7-0
02C
1-0
02D
7-0
02E
7-0
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GS1503
AF_NOB[8:0]
data can be demultiplexed from the Luma channel of the
video data stream. A maximum of 255 user data words can
be demultiplexed. Figure 41 shows the structure of the
arbitrary data packet.
2.9 ARBITRARY DATA PACKETS
The GS1503 can demultiplex arbitrary data packets
according to SMPTE 291M. Typically, arbitrary data packets
consist of linear time code (LTC), vertical interval time code
(VITC) or other user data, which is multiplexed once per
video field. The GS1503 has two modes in which arbitrary
GS1503
CS
UDW254[1FE]
UDW253[1FD]
UDW251[1FB]
UDW252[1FC]
UDW3[103]
UDW2[102]
DC
UDW1[101]
LSB
UDW0[100]
DID
SDID
Not b8
Parity bit
ADF
MSB
User Data Words
Contents available in Host Interface registers
Fig. 41 Arbitrary Data Packet Structure
2.9.1 Arbitrary Data Demultiplexing in External Pin Mode
This is the default mode for demultiplexing arbitrary data
packets. The GS1503 will set the PKTEN external pin HIGH
before arbitrary data will be output. Two VCLK cycles after
PKTEN goes HIGH, arbitrary data is output on the PKT[7:0]
bus. See Figure 42 for timing.
The following arbitrary data is output on the PKT[7:0] bus:
Data ID (DID), Secondary Data ID (SDID), Data Count (DC)
and User Data Words (UDW: up to a maximum of 255
words).
GS1503
Y/C b / Cr [19:0]
VIN[19:0]
PKTEN
Arbitrary Data Output Enable
Arbitrary Data
PKT[7:0]
2 CLKs
2 CLKs
VCLK
PKTEN
CS
UDW254
UDW253
UDW252
UDW251
UDW250
UDW2
UDW1
UDW0
DC
SDID
DID
ADF
ADF
Packet
ADF
Arbitrary
UDW3
Arbitrary Data
PKT[7:0]
Fig. 42 Arbitrary Data Packet Output Timing Diagram
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2.9.2 Arbitrary Data Demultiplexing in Host Interface Mode
GS1503
To select this mode, set ARBITMODE bit 0 in Host Interface
register 050h HIGH. In this mode, the DID, SDID, DC and
User Data Words must be programmed in the
corresponding Host Interface registers. Set the video line
number for field 1 and field 2 from which the arbitrary data
packets
are
to
be
demultiplexed
using
the
ARBITLINEA[11:0] and ARBITLINEB[11:0] Host Interface
registers respectively. The arbitrary data packet is
demultiplexed when the ARBITON bit 1 in Host Interface
register 050h is set HIGH. ARBITON should be set LOW
when reading the arbitrary data packet User Data Words
from the ARBITUDW Host Interface registers.
Register Settings
NAME
ARBITON
DESCRIPTION
Arbitrary packet demultiplex enable (1: Enabled)
ADDRESS
BIT
SETTING
DEFAULT
050
1
1
0
0
1
0
Valid only when ARBITMODE is HIGH
ARBITMODE
Arbitrary packet mode selection
(0: External pin mode; 1: Host mode)
ARBITDID[7-0]
ARBITSDID[7-0]
ARBITDC[7-0]
ARBITLINEA[11:0]
ARBITLINEB[11:0]
ARBITUDW
Arbitrary packet DID setting
051
7-0
-
0
Arbitrary packet SDID setting
052
7-0
-
0
Arbitrary packet DC setting
053
7-0
-
0
Field 1 multiplexing line
054
3-0
-
0
055
7-0
056
3-0
-
0
057
7-0
100-1FE
7-0
-
0
Field 2 multiplexing line
Arbitrary packet UDW
2.10 ANCILLARY DATA DELETION
The GS1503 can be configured to delete the embedded
ancillary data packets, after demultiplexing. There are two
modes for ancillary data deletion.
2.10.1 Entire Ancillary Data Deletion
When the ANCI external pin or ANCI bit 1 of Host Interface
register 040h is set HIGH, all ancillary data packets in both
the Luma and Chroma channel of the input video stream
are deleted. The data is replaced with blanking values 040h
in the Luma channel and 200h in the Chroma channel. The
DEL_SEL bit 0 of Host Interface register 040h must be set
LOW.
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2.10.2 Audio Group Designation Ancillary Data Deletion
When the ANCI bit 1 of Host Interface register 040h is set
HIGH, and DEL_SEL bit 0 of Host Interface register 040h is
HIGH, only audio data and control packets which are
designated in Host Interface registers 041h will be deleted.
To delete the arbitrary data packets, the corresponding DID
must be set in the NDID[7:0] Host Interface register 042h.
NAME
ANCI
DEL_SEL
DESCRIPTION
Ancillary data packet delete (1: Deletion enabled)
ADDRESS
BIT
SETTING
DEFAULT
040
1
1
0
0
1
0
7
-
0
Ancillary data packet delete mode select
(0: Entire data delete; 1: Group designated data delete)
ADPG4_DEL
Audio group 4 data packet delete (1: Delete)
ADPG3_DEL
Audio group 3 data packet delete (1: Delete)
6
-
0
ADPG2_DEL
Audio group 2 data packet delete (1: Delete)
5
-
0
ADPG1_DEL
Audio group 1 data packet delete (1: Delete)
4
-
0
ACPG4_DEL
Audio group 4 control packet delete (1: Delete)
3
-
0
ACPG3_DEL
Audio group 3 control packet delete (1: Delete)
2
-
0
ACPG2_DEL
Audio group 2 control packet delete (1: Delete)
1
-
0
ACPG1_DEL
Audio group 1 control packet delete (1: Delete)
0
-
0
7-0
-
0
NDID[7:0]
041
Arbitrary packet DID delete setting
042
2.11 DEMULTIPLEX MODE WITH WORD CLOCK INPUT
Some commercially available HD audio embedding
modules do not encode the audio word clock phase
information correctly in the CLK words of the audio data
packet. If this clock information is not correctly encoded,
the GS1503 will not output the audio data correctly. Also,
the GS1503 will be unable to reproduce the 48kHz audio
word clock (fs) at the WCOUTA and WCOUTB pins in serial
audio output modes.
If the GS1503 is to be used in conjunction with a HD audio
module, which encodes audio clock phase information
incorrectly, the DEC_MODE external pin or DECMODE bit 2
of Host Interface register 01Eh must be set HIGH. When
HIGH, an audio word clock synchronous to the original
word clock used for embedding must be input at the
WCINA and WCINB pins. Figure 43 shows a system
example.
When the embedded clock phase data for audio channel 1
to 4 is detected as being in error, the MUXERRA bit 0 of
Host Interface register 01Eh will be set HIGH. Similarly,
when the embedded clock phase data for audio channel 5
to 8 is detected as being in error, the MUXERRB bit 1 of
Host Interface register 01Eh will be set HIGH
Register Settings
NAME
DECMODE
DESCRIPTION
Demultiplex Mode with word clock input enable
ADDRESS
BIT
SETTING
DEFAULT
01E
2
1
0
(1: Enabled)
MUXERRB
Ch5-8 embedded clock phase information error detect
(1: Detected)
1
-
0
MUXERRA
Ch1-4 embedded clock phase information error detect
(1: Detected)
0
-
0
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GS1503
Register Settings
HD Audio
Embedding
GS1503
Module
Y/C b / C r [19:0]
Audio Channels 1 & 2
48kHz (fs)
Audio Channels 5 & 6
Audio Channels 7 & 8
48kHz (fs)
VOUT[19:0]
AIN1/2
AOUT1/2
AIN3/4
AOUT3/4
WCINA
Y/C b /Cr [19:0]
Audio Channels 1 & 2
Audio Channels 3 & 4
WCINA
AIN5/6
AIN7/8
AOUT5/6
WCINA
WCINA
AOUT7/8
Audio Channels 5 & 6
Audio Channels 7 & 8
+3.3V
DEC_MODE
MUX/DEMUX
Fig. 43 Demultiplex Mode with 48kHz Word Clock Input System Example
Figure 44 shows the timing relationship between the audio
word clock inputs and word clock outputs when the
GS1503 is configured to serial audio output mode.
1 CLK
ACLKA/B
WCINA/B
WCOUTA/B
Fig. 44 WCINA/B Input to WCOUTA/B Output Timing Diagram
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GS1503
Audio Channels 3 & 4
VIN[19:0]
Table 14: Demultiplex Mode Host Interface Registers
NAME
DESCRIPTION
ADDRESS
BIT
R/W
DEFAULT
Video
VM_SEL
Video input format (external pin/internal register)
configuration select. When set LOW, the video input
format is configured via the VM[3:0] pins.
When set HIGH, the video input format is
configured via the "VM[3:0]" bits.
000
7
R/W
0
VIDEO_DET
Video signal detection flag. Set HIGH when 3
consecutive TRS are detected in the input video
signal.
6
R
0
CRC_ERR
Video input signal CRC error detection. Set HIGH
when a CRC error is detected in the input video
signal. This register is refreshed on every video
frame.
5
R
0
CRC_INS
Video CRC insertion. When set HIGH, the Luma and
Chroma line CRC words are re-calculated and
inserted into the output video signal.
4
R/W
1
3-0
R/W
0
3
R/W
0
2
R/W
0
8-bit input selection. When set HIGH, the GS1503
will accept an 8-bit input video signal.
1
R/W
0
Descramble process bypass select.
When set HIGH, the internal SMPTE 292M
descrambler is bypassed.
0
R/W
0
R
0
VM[3:0]
Video input format selection. See Table 10. Valid
when "VM_SEL" is HIGH.
EXT_SEL
External EXTH/EXTF input select. When set LOW,
the EXTH and EXTF pins are configured as outputs.
When set HIGH, the GS1503 will insert TRS and
Line Numbers based on signals input at the EXTH
and EXTF pins.
SCRBYPASS
Scramble processing bypass select.
When set HIGH, the internal scrambler and NRZ(I)
encoder is bypassed.
001
NOTE: The status of the SCRBYPASS external pin is
not updated in this register. The value programmed
in this register is logical OR'd with the SCRBYPASS
external pin setting.
8BIT_SEL
DSCBYPASS
NOTE: The status of the DSCBYPASS external pin is
not updated in this register. The value programmed
in this register is logical OR'd with the DSCBYPASS
external pin setting.
CRC_CNT[11:0]
RSV
CRC error accumulation. Reports the accumulated
number of CRC errors in one video frame.
006
3-0
007
7-0
Not used.
008
7-4
R/W
0
VBLK_INS
Vertical blanking enable. When set HIGH, the
output video vertical blanking will be set to 040h for
the Luma channel and 200h for the Chroma
channel.
3
R/W
0
HBLK_INS
Horizontal blanking enable. When set HIGH, the
output video horizontal blanking, including TRS,
line numbers and line CRC words, will be set to
040h for the Luma channel and 200h for the
Chroma channel.
2
R/W
0
NOTE: If blanking of line numbers and TRS words
is required, LN_INS and TRS_INS must be set
LOW.
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GS1503
CONTROL
ITEM
Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL
ITEM
DESCRIPTION
LN_INS
BIT
R/W
DEFAULT
Line insertion enable. When set HIGH, the GS1503
will insert line numbers into the video data stream.
When set LOW, existing line numbers will remain in
the output video stream.
1
R/W
1
TRS_INS
TRS insertion enable. When set HIGH, the GS1503
will insert TRS codes into the video data stream.
When set LOW, existing TRS codes will remain in
the output video stream.
0
R/W
1
AM_SEL
Audio input format (external pin/register)
configuration select. When set LOW, the audio input
format is configured via the AM[1:0] pins. When set
HIGH, the audio input format is configured via the
"AM[1:0]" bits.
7
R/W
0
Not used.
6-2
-
0
Audio input format select. See Table 11. Valid when
"AM_SEL" is HIGH.
1-0
R/W
0
7-3
-
0
2
R/W
0
RSV
AM[1:0]
RSV
DECMODE
Not used.
ADDRESS
010
01E
Demultiplex Mode select. When set HIGH, the
GS1503 requires a 48kHz word clock input at
WCINA and WCINB. This word clock must be
synchronous to the word clock used to embed the
audio data. The embedded clock information in the
audio data packet will be ignored.
See Section 2-11.
NOTE: The status of the DEC_MODE external pin is
not updated in this register. The value programmed
in this register is logical OR'd with the DEC_MODE
external pin setting.
Audio
Channel
Status
Block
MUXERRB
Ch5-8 audio sample clock error. When set HIGH,
the GS1503 is unable to recover the audio clock
phase data in the embedded audio data packet for
audio channels 5 to 8. See Section 2-11.
1
R
0
MUXERRA
Ch1-4 audio sample clock error. When set HIGH,
the GS1503 is unable to recover the audio clock
phase data in the embedded audio data packet for
audio channels 1 to 4. See Section 2-11.
0
R
0
AUDIO_CS[7:0]
Audio Channel Status. When "CS_MODE" is set
HIGH, the 23 8-bit bytes of the Audio Channel
Status Block, as defined in AES3-1992, are
available in these registers. Valid in both AES/EBU
and serial audio modes.
058
7-0
R
0
:
:
06E
7-0
06F
7-6
-
0
:
AUDIO_CS
[183:176]
When "CS_MODE" is set LOW, the Audio Channel
Status information in the AES/EBU audio outputs will
be replaced with data programmed in these
registers. Valid only in AES/EBU audio mode.
RSV
Not used
61 of 83
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GS1503
Audio
NAME
Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL
ITEM
NAME
DESCRIPTION
CS_WEND
ADDRESS
R/W
DEFAULT
Audio Channel Status write flag. When set HIGH,
indicates that the audio channel status information
has been written into the Host Interface registers
058h to 06Eh and can be read by the user. Valid
only when "CS_MODE" is set HIGH.
5
R
0
CS_RQST
Audio Channel Status request. When set HIGH, the
GS1503 will read and store the Audio Channel
Status information from the audio channel set in
Host Interface register "CH_SEL[2:0]". Valid only
when "CS_MODE" is set HIGH.
4
R/W
0
CS_MODE
Audio Channel Status mode. When set HIGH, the
user can access the embedded Audio Channel
Status information from the Host Interface registers
058h to 06Eh. Valid in both AES/EBU and serial
audio modes.
3
R/W
0
2-0
R/W
000b
When set LOW, the Audio Channel Status
information for all audio outputs will be replaced
with data programmed in Host Interface registers
058h - 06Eh. Valid only in AES/EBU audio mode.
CH_SEL[2:0]
Audio Channel Status select. Designates the
embedded audio channel from which the Audio
Channel Status information will be demultiplexed.
The setting 000b represent audio channel 1,
through to 111b for channel 8. Valid only when
"CS_MODE" is set HIGH.
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GS1503
BIT
Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL
ITEM
Audio Data
Packet
DESCRIPTION
ADDRESS
BIT
R/W
DEFAULT
ADPG4_DET
Audio group 4 data packet detect. When set HIGH,
audio data packets with group 4 DID have been
detected in the incoming Chroma video data
stream.
013
7
R
0
6
R
0
5
R
0
4
R
0
3-2
-
0
NOTE: Once this bit has been set, it will remain set
until a device reset is performed.
ADPG3_DET
Audio group 3 data packet detect. When set HIGH,
audio data packets with group 3 DID have been
detected in the incoming Chroma video data
stream.
NOTE: Once this bit has been set, it will remain set
until a device reset is performed.
ADPG2_DET
Audio group 2 data packet detect. When set HIGH,
audio data packets with group 2 DID have been
detected in the incoming Chroma video data
stream.
NOTE: Once this bit has been set, it will remain set
until a device reset is performed.
ADPG1_DET
Audio group 1 data packet detect. When set HIGH,
audio data packets with group 1 DID have been
detected in the incoming Chroma video data
stream.
NOTE: Once this bit has been set, it will remain set
until a device reset is performed.
RSV
Not used.
ECCB_ON
Ch5-8 error correction enable. When set HIGH, the
GS1503 will perform error correction on audio data
packets for channels 5 to 8, based on the six ECC
words.
1
R/W
1
ECCA_ON
Ch1-4 error correction enable. When set HIGH, the
GS1503 will perform error correction on audio data
packets for channels 1 to 4, based on the six ECC
words.
0
R/W
1
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GS1503
NAME
Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL
ITEM
DESCRIPTION
ADDRESS
BIT
R/W
DEFAULT
CASCADE
Cascade select. When set HIGH, the GS1503 will
default to audio groups 3 and 4. When set LOW, the
GS1503 will default to audio groups 1 and 2.
014
7
R/W
0
Not used.
6
-
0
Ch5-8 audio mute enable. When set HIGH, the
multiplexed audio packets for audio channels 5 to 8
are forced to zero.
5
R/W
0
4
R/W
0
NOTE: The status of the CASCADE external pin is
not updated in this register. The value programmed
in this register is logical OR'd with the CASCADE
external pin setting.
RSV
AMUTEB
NOTE: The status of the MUTE external pin is not
updated in this register. The value programmed in
this register is logical OR'd with the MUTE external
pin setting.
AMUTEA
Ch1-4 audio mute enable. When set HIGH, the
multiplexed audio packets for audio channels 1 to 4
are forced to zero.
NOTE: The status of the MUTE external pin is not
updated in this register. The value programmed in
this register is logical OR'd with the MUTE external
pin setting.
DATAIDB[1:0]
Ch5-8 audio group DID setting. Designates the
audio group DID for audio channels 5 to 8. See
Table 12. When CASCADE (external pin or register)
is set LOW, the default setting is audio group 2.
When CASCADE is set HIGH, the default setting is
audio group 4.
3-2
R/W
10b
DATAIDA[1:0]
Ch1-4 audio group DID setting. Designates the
audio group DID for audio channels 1 to 4. See
Table 12. When CASCADE (external pin or register)
is set LOW, the default setting is audio group 1.
When CASCADE is set HIGH, the default setting is
audio group 3.
1-0
R/W
11b
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GS1503
NAME
Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL
ITEM
NAME
DBNB_ERR
DESCRIPTION
Ch5-8 audio data packet DBN error. When set
HIGH, a Data Block Number error has been
detected in the audio data packet for audio
channels 5 to 8.
ADDRESS
BIT
R/W
DEFAULT
015
7
R
0
Ch5-8 audio data packet 'bit 8' error. When set
HIGH, a 'bit 8' error has been detected in the audio
data packet for audio channels 5 to 8.
6
R
0
ECCB_ERR
Ch5-8 audio data packet error. When set HIGH, an
error has been detected in the audio data packet
for audio channels 5 to 8, based on the six ECC
words.
5
R
0
ADPCSB_ERR
Ch5-8 audio data packet CS error. When set HIGH,
a Checksum error has been detected with the audio
data packet for audio channels 5 to 8.
4
R
0
Ch1-4 audio data packet DBN error.
When set HIGH, a Data Block Number error has
been detected in the audio data packet for audio
channels 1 to 4.
3
R
0
ADPB8A_ERR
Ch1-4 audio data packet 'bit 8' error.
When set HIGH, a 'bit 8' error has been detected in
the audio data packet for audio channels 1 to 4.
2
R
0
ECCA_ERR
Ch1-4 audio data packet error. When set HIGH, an
error has been detected in the audio data packet
for audio channels 1 to 4, based on the six
ECC words.
1
R
0
ADPCSA_ERR
Ch1-4 audio data packet CS error. When set HIGH,
a Checksum error has been detected with the audio
data packet for audio channels 1 to 4.
0
R
0
CORRECTB
Ch5-8 ECC correctable packets. Designates the
number of audio data packets for channels 5 to 8
that have been corrected in one video frame using
the BCH forward error correction system.
016
3-0
R
0
017
7-0
Ch5-8 ECC un-correctable packets. Designates the
number of audio data packets for channels 5 to 8
that could not be corrected in one video frame
using the BCH forward error correction system.
018
3-0
R
0
019
7-0
Ch1-4 ECC correctable packets. Designates the
number of audio data packets for channels 1 to 4
that have been corrected in one video frame using
the BCH forward error correction system.
01A
3-0
R
0
01B
7-0
Ch1-4 ECC un-correctable packets. Designates the
number of audio data packets for channels 1 to 4
that could not be corrected in one video frame
using the BCH forward error correction system.
01C
3-0
R
0
01D
7-0
DBNA_ERR
[11:0]
NO_CORRECTB
[11:0]
CORRECTA
[11:0]
NO_CORRECTA
[11:0]
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GS1503
ADPB8B_ERR
Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL
ITEM
Audio
Control
Packet
DESCRIPTION
ADDRESS
BIT
R/W
DEFAULT
ACPG4_DET
Audio group 4 control packet detect. When set
HIGH, audio control packets with group 4 DID have
been detected in the incoming Luma video
data stream.
020
7
R
0
ACPG3_DET
Audio group 3 control packet detect. When set
HIGH, audio control packets with group 3 DID have
been detected in the incoming Luma video
data stream.
6
R
0
ACPG2_DET
Audio group 2 control packet detect. When set
HIGH, audio control packets with group 2 DID have
been detected in the incoming Luma video
data stream.
5
R
0
ACPG1_DET
Audio group 1 control packet detect. When set
HIGH, audio control packets with group 1 DID have
been detected in the incoming Luma video
data stream.
4
R
0
Not used.
3
-
0
Ch5-8 audio control packet demultiplex enable.
When set HIGH, the audio control packets in the
Luma channel of the video data stream for audio
channels 5 to 8 will be demultiplexed.
2
R/W
1
1-0
R/W
10b
R/W
0
RSV
CTRONB
CTRIDB[1:0]
Ch5-8 audio control packet DID setting. Designates
the audio control packet DID for audio channels 5
to 8. See Table 13. The default setting is audio
group 2.
AF_NOB[8:0]
Ch5-8 audio frame number. Designates the audio
frame number for audio channels 5 to 8.
021
0
022
7-0
RATEB[2:0]
Ch5-8 sampling frequency. Designates the audio
sampling frequency for audio channels 5 to 8, taken
from the RATE word of the audio control packet as
defined in SMPTE 299M.
023
3-1
R/W
0
ASXB
Ch5-8 synchronization. When set HIGH, the "asx" bit
of the audio control packet RATE word designates
audio channels 5 to 8 as asynchronous, as per
SMPTE 299M. When set LOW, the "asx" bit of the
audio control packet RATE word designates
synchronous audio.
0
R/W
0
024
1-0
R/W
0
025
7-0
026
7-0
027
7-0
028
1-0
R/W
0
029
7-0
02A
7-0
02B
7-0
02C
1-0
R/W
0
02D
7-0
02E
7-0
DEL1-2B[25:0]
DEL3-4B[25:0]
RSRVB[17:0]
Ch5/6 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 5 and 6.
Ch7/8 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 7 and 8.
Ch5-8 reserve words. Designates the value set in
the RSRV words of the audio control packet for
audio channels 5 to 8, as per SMPTE 299M.
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NAME
Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL
ITEM
NAME
RSV
CTRONA
Not used.
BIT
R/W
DEFAULT
02F
7-3
-
0
2
R/W
1
1-0
R/W
11b
R/W
0
Ch1-4 audio control packet demultiplex enable.
When set HIGH, the audio control packets in the
Luma channel of the video data stream for audio
channels 1 to 4 will be demultiplexed.
Ch1-4 audio control packet DID setting. Designates
the audio control packet DID for audio channels 1
to 4. See Table 13. The default setting is audio
group 1.
AF_NOA[8:0]
Ch1-4 audio frame number. Designates the audio
frame number for audio channels 1 to 4.
030
0
031
7-0
RATEA[2:0]
Ch1-4 sampling frequency. Designates the audio
sampling frequency for audio channels 1 to 4, taken
from the RATE word of the audio control packet as
defined in SMPTE 299M.
032
3-1
R/W
0
ASXA
Ch1-4 synchronization. When set HIGH, the "asx" bit
of the audio control packet RATE word designates
audio channels 1 to 4 as asynchronous, as per
SMPTE 299M. When set LOW, the "asx" bit of the
audio control packet RATE word designates
synchronous audio.
0
R/W
0
033
1-0
R/W
0
034
7-0
035
7-0
036
7-0
037
1-0
R/W
0
038
7-0
R/W
0
DEL3-4A[25:0]
Ch1/2 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 1 and 2.
Ch3/4 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 3 and 4.
039
7-0
03A
7-0
Ch1-4 reserve words. Designates the value set in
the RSRV words of the audio control packet for
audio channels 1 to 4, as per SMPTE 299M.
03B
1-0
03C
7-0
03D
7-0
RSV
Not used.
040
7-2
-
0
ANCI
Ancillary data delete. When set HIGH, all ancillary
data packets ("DEL_SEL" is LOW) or ancillary data
packets with DIDs designated in Host Interface
registers 041h and 042h ("DEL_SEL" is HIGH) are
removed from the video signal. The ancillary data
packets are replaced with blanking codes. The data
contained in the packets are output at the
corresponding pins. When set LOW, all ancillary
data packets remain in the video signal.
1
R/W
0
0
R/W
0
RSRVA[17:0]
NOTE: The status of the ANCI external pin is not
updated in this register. The value programmed in
this register is logical OR'd with the ANCI external
pin setting
DEL_SEL
Ancillary data delete mode select. When set HIGH,
individual audio groups can be deleted from the
video signal by programming Host Interface
register 041h. When set LOW, all ancillary data
packets are deleted from the video signal.
67 of 83
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GS1503
ADDRESS
CTRIDA[1:0]
DEL1-2A[25:0]
Packet
Delete
DESCRIPTION
Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL
ITEM
DESCRIPTION
ADDRESS
BIT
R/W
DEFAULT
ADPG4_DEL
Audio group 4 data packet delete. When set HIGH,
all audio data packets with group 4 DID will be
deleted from the Chroma video data stream. Valid
only when "DEL_SEL" is HIGH.
041
7
R/W
0
ADPG3_DEL
Audio group 3 data packet delete. When set HIGH,
all audio data packets with group 3 DID will be
deleted from the Chroma video data stream. Valid
only when "DEL_SEL" is HIGH.
6
R/W
0
ADPG2_DEL
Audio group 2 data packet delete. When set HIGH,
all audio data packets with group 2 DID will be
deleted from the Chroma video data stream. Valid
only when "DEL_SEL" is HIGH.
5
R/W
0
ADPG1_DEL
Audio group 1 data packet delete. When set HIGH,
all audio data packets with group 1 DID will be
deleted from the Chroma video data stream. Valid
only when "DEL_SEL" is HIGH.
4
R/W
0
ACPG4_DEL
Audio group 4 control packet delete. When set
HIGH, all audio control packets with group 4 DID
will be deleted from the Luma video data stream.
Valid only when "DEL_SEL" is set HIGH. To be fixed.
3
R/W
0
ACPG3_DEL
Audio group 3 control packet delete. When set
HIGH, all audio control packets with group 3 DID
will be deleted from the Luma video data stream.
Valid only when "DEL_SEL" is HIGH. To be fixed.
2
R/W
0
ACPG2_DEL
Audio group 2 control packet delete. When set
HIGH, all audio control packets with group 2 DID
will be deleted from the Luma video data stream.
Valid only when "DEL_SEL" is HIGH. To be fixed.
1
R/W
0
ACPG1_DEL
Audio group 1 control packet delete. When set
HIGH, all audio control packets with group 1 DID
will be deleted from the Luma video data stream.
Valid only when "DEL_SEL" is HIGH. To be fixed.
0
R/W
0
7-0
R/W
0
NDID[7:0]
Arbitrary data packet delete. Designates the DID for
the arbitrary data packets to be deleted from the
Luma video data stream. Valid only when
"DEL_SEL" is HIGH.
042
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NAME
Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL
ITEM
Arbitrary
Data
NAME
DESCRIPTION
Arbitrary data packet demultiplex. Valid only when
"ARBITMODE" is HIGH. When set HIGH, arbitrary
data packets will be demultiplexed from the Luma
video data stream. Must be set LOW again to
access valid data in the "ARBITUDW" registers.
ARBITMODE
Arbitrary packet mode select. When set HIGH,
arbitrary data packets are demultiplexed and the
User Data Words are stored in Host Interface
registers 100h to 1FEh. No data will be output on
the PKT[7:0] external pins and PTKTEN will be
LOW. When set LOW, arbitrary data packets are
demultiplexed and output at the PKT[7:0]
external pins.
Packet
BIT
R/W
DEFAULT
050
1
R/W
0
0
R/W
0
ARBITDID[7:0]
Arbitrary packet Data ID setting. Designates the 8
LSBs of the DID word of the arbitrary data packet to
be demultiplexed. The 2 MSBs are internally
generated. "ARBITDID[7]" is the MSB and
"ARBITDID[0]" is the LSB. Valid only when
"ARBITMODE" is HIGH.
051
7-0
R/W
0
ARBITSDID[7:0]
Arbitrary packet Secondary Data ID setting.
Designates the 8 LSBs of the secondary DID word
of the arbitrary data packet to be demultiplexed.
The 2 MSBs are internally generated.
"ARBITSDID[7]" is the MSB and "ARBITSDID[0]" is
the LSB. Valid only when "ARBITMODE" is HIGH.
052
7-0
R/W
0
ARBITDC[7:0]
Arbitrary packet DC setting. Designates the 8 LSBs
of the Data Count word of the arbitrary data packet
to be demultiplexed. The 2 MSBs are internally
generated. "ARBITDC[7]" is the MSB and
"ARBITDC[0]" is the LSB. Valid only when
"ARBITMODE" is HIGH.
053
7-0
R/W
0
ARBITLINEB
Field 2 arbitrary packet demultiplex line number
setting. Designates the field 2 video line from which
the arbitrary data packets will be demultiplexed.
Valid only when "ARBITMODE" is HIGH.
054
3-0
R/W
0
055
7-0
Field 1 arbitrary packet demultiplex line number
setting. Designates the field 1 video line from which
the arbitrary data packets will be demultiplexed.
Valid only when "ARBITMODE" is HIGH.
056
3-0
R/W
0
057
7-0
Arbitrary packet User Data Word. Designates the 8
LSBs for up to 255 arbitrary packet User Data
Words. Arbitrary data can be read from these
registers once "ARBITON" has been set HIGH to
LOW. Valid only when "ARBITMODE" is HIGH.
100
7-0
R/W
0
:
:
1FE
7-0
[11:0]
ARBITLINEA
[11:0]
ARBITUDW0
:
ARBITUDW254
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GS1503
ARBITON
ADDRESS
3
SDI LOOP
THRU
VCC
J7
BNC_BCJ_RPC_01
1
A_GND
CPU
INTERFACE
3
SDI IN
AESIN7/8
AESIN5/6
3
AESIN3/4
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
JP1
C102
100n
R78
75R
R74
75R
R9
75R
R4
75R
VCLK_CPU
CPUADR8
CPUADR7
CPUADR6
CPUADR5
CPUADR4
CPUADR3
CPUADR2
CPUADR1
CPUADR0
CPUDAT0
CPUDAT1
CPUDAT2
CPUDAT3
CPUDAT4
CPUDAT5
CPUDAT6
CPUDAT7
CPUCSn
CPUREn
CPUWEn
RESETn
RECEIVER
LT_SDO
SDI
GS1545
J12
BNC_BCJ_RPC_01
1
C100
100n
J10
BNC_BCJ_RPC_01
1
C4
100n
J3
BNC_BCJ_RPC_01
1
C2
100n
1
J1
BNC_BCJ_RPC_01
8
5
T7
1
4
VCLK_CPU
CPUDAT[7..0]
R
VCC
VCC
R
VCC
VCC
R
GND / R E DE
7 B
6 A
VCLK_1522
VCC
GND / RE DE
7 B
6 A
VCLK_1503
VCC
U2
VCLK_CPU
VCLK_1522
VCLK_1503
VIN[19..0]
SN75176B(R)
1
U15
SN75176B(R)
1
U13
SN75176B(R)
1
U4
SN75176B(R)
R 1
GND / RE DE
7 B
6 A
VIN[19..0]
VCC
GND / RE DE
7 B
6 A
CPUADR[8..0]
PE-65812
T5
1
8
1
4
1
4
4
PE-65812
T3
PE-65812
T1
PE-65812
5
8
5
8
5
3
2
CONN 24X2
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
3
3
3
2
8
2
2
2
8
2
8
5
5
5
5
RESETn
AIN5/6
RESETn
VCLK_1503
VIN[19..0]
AIN7/8
POWER & RESET
MISC
AUDIO ENDEC
GS1503
AOUT7/8
AOUT5/6
AOUT3/4
RESETn
CPUCSn
CPUREn
CPUWEn
CPUDAT[7..0]
CPUADR[8..0]
VOUT[19..0]
RESETn
CPUCSn
CPUREn
CPUWEn
CPUDAT[7..0]
CPUADR[8..0]
VCC
VCC
4 D
VCC
4 D
7
B
VCC
4 D
GND
7
B
8
VCLK_1522
SERIALIZER
VCLK_1522
VOUT[19..0]
GS1522
PE-65812
8
1
R77
55R
5
4
7
T8
PE-65812
5
1
T6
4
8
B
R75
55R
T4
PE-65812
1
4
5
8
PE-65812
5
1
T2
4
6
SN75176B(D)
GND
VOUT[19..0]
4 D
R72
55R
R70
55R
R8
55R
R6
55R
R3
55R
R1
55R
A
/ RE DE VCC
U14
SN75176B(D)
6
A
/ RE DE VCC
U12
SN75176B(D)
GND
6
A
/ RE DE VCC
U3
SN75176B(D)
GND
U1
6
B 7
A
/ RE DE VCC
2
2
2
2
2
8
2
8
8
8
8
3
3
3
3
5
3
5
3
5
3
5
C101
220n
C99
220n
C3
220n
C1
220n
R76
191R
R71
191R
R7
191R
R2
191R
J4
SDO1
SDO0
R79
100R
BNC_BCJ_RPC_01
1
R73
100R
J11
BNC_BCJ_RPC_01
1
R10
100R
BNC_BCJ_RPC_01
1
R5
100R
J2
BNC_BCJ_RPC_01
1
2
2
J13
2
2
AESIN1/2
J5
BNC_BCJ_RPC_01
1
2
2
3
3
3
3
BNC_BCJ_RPC_01
1
BNC_BCJ_RPC_01
1
AESOUT7/8
AESOUT5/6
AESOUT3/4
AESOUT1/2
J6
J8
2
2
3
3
SDI
OUT
2
SDI
OUT
1
GS1503
VCC
3. REFERENCE DESIGN
3.1 CIRCUIT SCHEMATICS
70 of 83
15879 - 4
AOUT1/2
AIN1/2
AIN3/4
VCC
C68
10u
C69
100n
R59
R58
0R
0R
SDI
C70
10n
A_GND
A_VCC
C53
100n
R56
75
R50
A_GND
ANALOG POWER PLANE
C71
1u
10n
75
L3
1.5p
C52
10u
R55
C65
VCC
R49
R57
37R5
47p
C67
C72
10n
A_VCC
R54
5k
C73
10n
A_GND
A_GND
A_VCC
GND_VCO1
A_GND
47p
C66
22k
R53
VCC_VCO1
2
GND_VCO1
VCC_VCO1
VCC_VCO1
D6
R51
150
VCC_VCO1
C55
1u
Q2
2N3904/TO
C54
10n
GND_VCO1
0R
0R
2
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
nc
nc
BYPASS
DDI_VTT
nc
DDI
DDI
PD_VCC
A/D
PDSUB_VEE
PD_VEE
nc
nc
nc
EQI_VCC
nc
nc
EQI_VEE
nc
SDI
nc
SDI
nc
EQI_VEE
nc
nc
GND_VCO1
C56
10n
VCC_VCO1
C57
10n
GND_VCO1
4
10n
C59
GND
10u
100n
C51
C50
U7
GO1515
10n
C58
GND_VCO1
GND_VCO1
8
1u
C60
1u
C61
GND_VCO1
GND_VCO1
GND
GND_VCO1
R52
0
VCC_VCO1
U8
GS1545
A_GND
R64
50
A_VCC
C86
10n
2
1
C83
R65
50
VCC
SDI
SDI
100n
VCC
5
VCC
VEE
GND
3
6
11
VCC_VCO1
VCC_VCO1
GS1508
RSET
SDO
SDO
U9
VCC
4
7
8
R61
75
VCC
VCC
R66
53R6
C82
R62
37R4
10n
DATA_OUT19
DATA_OUT18
DATA_OUT17
DATA_OUT16
DATA_OUT15
DATA_OUT14
nc
nc
DATA_OUT13
DATA_OUT12
DATA_OUT11
DATA_OUT10
nc
nc
DATA_OUT9
DATA_OUT8
DATA_OUT7
DATA_OUT6
DATA_OUT5
DATA_OUT4
DATA_OUT3
DATA_OUT2
DATA_OUT1
DATA_OUT0
nc
nc
nc
nc
nc
nc
MCLADJ
nc
CLI
nc
nc
nc
nc
CD
EQO_VEE
nc
nc
EQO_VCC
SDO
SDO
SDO_VEE
SDO_EN
SDO_VCC
nc
nc
nc
nc
nc
nc
nc
nc
SP_VCC
SP_VCC
SP_VEE
SP_VEE
PCLK_OUT
PCLK_VCC
PCLK_VEE
nc
nc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
3
2
GND
1
VCTR
3
VCC
O/P
5
GND
6
NC
7
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
nc
nc
nc
nc
PLL_LOCK
nc
PLCAP
nc
nc
PLCAP
nc
VCO
nc
VCO
nc
nc
IJI
LFS
nc
nc
nc
LFS
DM
DM
nc
nc
DFT_VEE
LFA_VEE
LBCONT
LFA
LFA_VCC
nc
nc
nc
nc
nc
nc
nc
GS1545 VCO POWER PLANE
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
R60
0.5p
75
R63
12n
+3.3V
C84
L4
22
VIN9
VIN8
VIN7
VIN6
VIN5
VIN4
VIN3
VIN2
VIN1
VIN0
VIN13
VIN12
VIN11
VIN10
VIN19
VIN18
VIN17
VIN16
VIN15
VIN14
C85
4u7
BLM11A601S
EMF4
C62
10n
+3.3V
C77
10u
100n
C75
VCLKIN
VCC
10u
C74
EMF3
BLM11A601S
VIN[19..0]
C64
10n
C79
100n
C80
100n
100n
C76
LT_SDO
C78
100n
C63
10n
VIN[19..0]
C81
100n
2
10
14
22
6
7
18
19
1
23
13
24
11
IC5
CDC2510C
VCC
VCC
VCC
VCC
GND
GND
GND
GND
AGND
AVCC
FBIN
CLK
G
FBOUT
1Y0
1Y1
1Y2
1Y3
1Y4
1Y5
1Y6
1Y7
1Y8
1Y9
12
3
4
5
8
9
15
16
17
20
21
GS1503
71 of 83
15879 - 4
VCLK_1522
VCLK_1503
VCLK_CPU
CPUDAT[7..0]
CPUADR[8..0]
VCLK_150 3
RESETn
AIN1/2
AIN3/4
AIN5/6
AIN7/8
CPUCSn
CPUREn
CPUWEn
R20
*
PLACE
CLOSE TO
GS1503
INPUT
C9
PIN
*
VIN[19..0]
105
106
107
CPUCSn
CPUREn
CPUWEn
+3.3V
103
102
101
100
99
98
96
95
CPUDAT7
CPUDAT6
CPUDAT5
CPUDAT4
CPUDAT3
CPUDAT2
CPUDAT1
CPUDAT0
GS1503
RSV
RSV
RSV
RSV
CPUCSn
CPUREn
CPUWEn
CPUDAT7
CPUDAT6
CPUDAT5
CPUDAT4
CPUDAT3
CPUDAT2
CPUDAT1
CPUDAT0
CPUADR8
CPUADR7
CPUADR6
CPUADR5
CPUADR4
CPUADR3
CPUADR2
CPUADR1
CPUADR0
RESETn
VCLK
ACLKA
ACLKB
MUXn/DEMUX
VM3
VM2
VM1
VM0
CPU_SEL
AM1
AM0
ANCI
CASCADE
MUTE
AIN1/2
AIN3/4
AIN5/6
AIN7/8
WCINA
WCINB
PKT7
PKT6
PKT5
PKT4
PKT3
PKT2
PKT1
PKT0
PKTEN
EXTH
EXTF
VIN19
VIN18
VIN17
VIN16
VIN15
VIN14
VIN13
VIN12
VIN11
VIN10
VIN9
VIN8
VIN7
VIN6
VIN5
VIN4
VIN3
VIN2
VIN1
VIN0
10u
C104
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DSCBYPASS
SCRBYPASS
DEC_MODE
PLLCNTA
PLLCNTB
AOUT1/2
AOUT3/4
AOUT5/6
AOUT7/8
WCOUTA
WCOUTB
PKTENO
VIDEO_DET
OPERATE
ERROR
CRC_ERR
VOUT19
VOUT18
VOUT17
VOUT16
VOUT15
VOUT14
VOUT13
VOUT12
VOUT11
VOUT10
VOUT9
VOUT8
VOUT7
VOUT6
VOUT5
VOUT4
VOUT3
VOUT2
VOUT1
VOUT0
10u
144
129
121
113
108
88
86
80
72
64
56
48
36
20
18
16
133
125
117
109
104
97
84
73
68
60
52
37
31
27
14
1
8
38
85
10
9
76
77
78
79
74
75
24
45
22
21
23
71
70
69
67
66
65
63
62
61
59
58
57
55
54
53
51
50
49
47
46
PLLCNTA
PLLCNTB
AOUT1/2
AOUT3/4
AOUT5/6
AOUT7/8
VIDEO_DET
OPERATE
ERROR
CRC_ERR
VOUT19
VOUT18
VOUT17
VOUT16
VOUT15
VOUT14
VOUT13
VOUT12
VOUT11
VOUT10
VOUT9
VOUT8
VOUT7
VOUT6
VOUT5
VOUT4
VOUT3
VOUT2
VOUT1
VOUT0
+3.3V
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C94 C95 C96 C97
39
40
41
42
81
82
83
89
94
93
92
91
90
+3.3V
143
87
17
19
15
139
140
141
142
136
137
138
13
11
12
5
4
3
2
7
6
26
28
29
30
32
33
34
35
25
43
44
110
111
112
114
115
116
118
119
120
122
123
124
126
127
128
130
131
132
134
135
CPUADR8
CPUADR7
CPUADR6
CPUADR5
CPUADR4
CPUADR3
CPUADR2
CPUADR1
CPUADR0
MUTE
ANCI
RESETn
VCLK_150 3
ACLKA
ACLKB
MUXn/DEMUX
VM3
VM2
VM1
VM0
CPU_SEL
AIN1/2
AIN3/4
AIN5/6
AIN7/8
VIN19
VIN18
VIN17
VIN16
VIN15
VIN14
VIN13
VIN12
VIN11
VIN10
VIN9
VIN8
VIN7
VIN6
VIN5
VIN4
VIN3
VIN2
VIN1
VIN0
IC1
C103
1
2
1
2
+3.3V
100n
C98
AOUT1/2
AOUT3/4
AOUT5/6
AOUT7/8
2
2
2
2
1
1
1
1
180R
R24
180R
R18
D4
BR1101W
D3
BR1101W
D2
PG1101W
D1
PG1101W
VOUT[19..0]
R14
1k
R13
1k
R12
1k
R11
1k
C5
R25
10k
R22
10k
1
2
3
4
5
6
7
8
9
10
10n
C10
R19
10k
R16
10k
10n
-
+
VCC
-
+
KHS10
S1
2
3
2
3
VCC
8
4
8
4
1
1
20
19
18
17
16
15
14
13
12
11
TLC2272
IC7A
TLC2272
IC6A
100k
R15
VM3
VM2
VM1
VM0
1
1
R31 R33
10K 10K
R30 R32
10K 10K
R27 R29
10K 10K
R26 R28
10K 10K
MUTE
ANCI
MUXn/DEMUX
CPU_SEL
680p
C11
100k
R21
680p
C6
+3.3V
+3.3V
NC
X2
NC
X1
14
VCC
GND
7
14
VCC
GND
7
8
8
VCXO-920B1-24.576MHz
OUT
C12
100n
VCC
EMF2
DSS310-55D-223 S
3
1
O
I
VCXO-920B1-24.576MHz
OUT
C7
100n
VCC
EMF1
DSS310-55D-223 S
3
1
I
O
G
2
G
2
C13
100n
C8
100n
+3.3V
74FCT7 4
3
2
+3.3V
74FCT7 4
3
2
C
D
+3.3V
C
D
+3.3V
4
S
R
1
4
S
R
1
Q
VCC
GND
Q
Q
VCC
GND
Q
11
6
14
7
+3.3V
+3.3V
12
+3.3V
5
IC4A
11
6
14
7
+3.3V
12
5
IC2A
C
D
+3.3V
C
D
+3.3V
10
S
R
13
10
S
R
13
Q
Q
Q
Q
GS1503
72 of 83
15879 - 4
IC2B
74FCT7 4
8
9
IC4B
74FCT7 4
8
9
33R
R23
33R
R17
ACLKB
ACLKA
VCLK_1522
VOUT[19..0]
Q1
2N3904/TO
VCC
D5
DATA_IN19
DATA_IN18
DATA_IN17
DATA_IN16
DATA_IN15
nc
nc
DATA_IN14
DATA_IN13
DATA_IN12
DATA_IN11
DATA_IN10
DATA_IN9
nc
nc
DATA_IN8
DATA_IN7
nc
nc
DATA_IN6
DATA_IN5
DATA_IN4
DATA_IN3
DATA_IN2
DATA_IN1
DATA_IN0
22k
R46
*
PLACE
CLOSE TO
GS1522
INPUT
C49
PIN
*
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
C38
10n
2 R48
R47
150R
VOUT6
VOUT5
VOUT4
VOUT3
VOUT2
VOUT1
VOUT0
VOUT8
VOUT7
VOUT14
VOUT13
VOUT12
VOUT11
VOUT10
VOUT9
VOUT19
VOUT18
VOUT17
VOUT16
VOUT15
VCC
VCC
VCC
0
R37
VCC_VCO2
1u
C33
1u
C34
GND_VCO2
GND
GND_VCO2
VCC_VCO2
GND_VCO2
4
10u
100n
C28
C27
VCC_VCO2
U5
GO1515
10n
C35
GND_VCO2
U6
GS1522
LOCK_DETECT
VCC
C48
1u
10n
C47
GND_VCO2
8
1u
C26
C29
1u
GND_VCO2
GND_VCO2
VCC_VCO2
49R9
OSC_VEE
A0
nc
nc
nc
VEE2
RSET0
VCC2
nc
SDO0
SDO0_NC
SDO0
nc
nc
nc
SDO1
SDO_NC
SDO1
nc
VCC2
RSET1
nc
nc
nc
nc
nc
GND_VCO2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
C46
10n
VCC
VCC
C37
10n
R45
53.6
R40 53.6
GND_VCO2
C36
10n
0R
C44
10n
C30 0R
10n
VCC_VCO2
GS1522 VCO POWER PLANE
GND
GND_VCO2
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
nc
nc
nc
nc
nc
nc
SYN_DETECT_DISABLE
VEE3
VCC3
nc
LFA_VCC
LBCONT
LFA
LFA_VEE
DFT_VEE
PLCAP
DM
PLCAP
LFS
nc
LFS
nc
nc
PD_VCC
IJI
PDSUB_VEE
PD_VEE
VCO
VCO
nc
nc
nc
nc
nc
nc
nc
nc
nc
VEE3
PCLK_IN
nc
nc
nc
nc
nc
nc
nc
BUF_VEE
nc
nc
XDIV20
nc
PLL_LOCK
BYPASS
RESET
VEE2
nc
nc
VCC2
VCC2
VCC2
VCC2
VCC2
VEE2
VEE2
VEE2
VEE2
VEE2
SDO1_EN
nc
nc
nc
nc
nc
nc
nc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VOUT[19..0]
2
11
3
2
GND
1
VCTR
3
VCC
O/P
5
GND
6
NC
7
R34
VCC
R36
R35
VCC
C31
100n
VCC
C32
10u
C45
R43
37R4
R38
75
10n
C39
VCC
10n
R44
75
R39
37R4
0.5p
0.5p
12n
75R
C42
L2
R42
12n
75R
R41
C40
L1
C43
C41
4u7
4u7
SDO1
SDO0
GS1503
73 of 83
15879 - 4
GS1503
J9
1
2
3
4
VCC
R67
470R
C87
100uF/6.3V
2
1
2
3
4
C88
100n
LP 5.00/4/90
1
D7
5V PWR
U10
VOUT
VIN
3
2
1
ADJ
LM1085_M
EMF5
BLM31P330S G
VCC
C89
100uF/6.3V
C90
100n
+3.3V
R68
300R
C92
100n
2
C91
100uF/6.3V
1
D8
3.3V PWR
VCC
MR
PFI
GND
S2
STM1- 01
4
RESET
RESET
NC
PFO
8
7
6
5
RESETn
MAX707
3
1
VCC
VCC
U11
2
VCC
R69
4K7
VCC
C93
100n
74 of 83
15879 - 4
3.2 BOARD LAYOUTS
GS1503
75 of 83
15879 - 4
GS1503
76 of 83
15879 - 4
GS1503
77 of 83
15879 - 4
GS1503
78 of 83
15879 - 4
3.3
BILL OF MATERIALS
QUANTITY
REFERENCE
PART
1
4
C1,C3,C99,C101
220n
2
41
C2,C4,C7,C8, C12,C13,C14,
C15,C16,C17, C18,C19,C20,
C21,C22,C23, C24,C25,C27,
C31,C50,C53, C69,C75,C76,
C78,C79,C80, C81,C83,C88,
C90,C92,C93,C94,C95,C96,
C97,C98,C100, C102
100n
3
26
L3,C5,C10,C30,C35,C36,
C37,C38,C39,C44,C45,C46,
C47,C54,C56,C57,C58,C59,
C62,C63,C64,C70,C72,C73, C82,C86
10n
4
2
C6,C11
680p
5
4
C9,R20,R46,C49
*
6
9
C26,C29,C33,C34,C48,C55,
C60,C61,C71
1u
7
9
C28,C32,C51,C52,C68,C74,
C77,C103,C104
10u
8
3
C40,C42,C84
0.5p
9
3
C41,C43,C85
4u7
10
1
C65
1.5p
11
2
C66,C67
47p
12
3
C87,C89,C91
100uF/6.3V
13
4
D1,D2,D3,D4,D5,D6,D7,D8
PG1101W
14
2
EMF1,EMF2
DSS310-55D-223S
15
2
EMF3,EMF4
BLM11A601S
16
1
EMF5
BLM31P330SG
17
1
IC1
GS1503
18
2
IC2,IC4
74FCT74
19
1
IC5
CDC2510C
20
2
IC6,IC7
TLC2272
21
1
JP1
CONN 24X2
22
12
J1,J2,J3,J4,J5,J6,J7,J8,
J10,J11,J12,J13
BNC_BCJ_RPC_01
23
1
J9
LP 5.00/4/90
24
3
L1,L2,L4
12n
25
2
Q2,Q1
2N3904/TO
26
8
R1,R3,R6,R8,R70,R72,R75, R77
55R
27
4
R2,R7,R71,R76
191R
28
6
R4,R9,R41,R42,R74,R78
75R
29
4
R5,R10,R73,R79
100R
30
4
R11,R12,R13,R14
1k
31
2
R21,R15
100k
GS1503
ITEM
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3.3
BILL OF MATERIALS (Continued)
QUANTITY
REFERENCE
PART
32
12
R16,R19,R22,R25,R26,R27,
R28,R29,R30,R31,R32,R33
10K
33
2
R17,R23
33R
34
2
R24,R18
180R
35
3
R34,R64,R65
49R9
36
8
R35,R36,R37,R49,R50,R52,R58, R59
0R
37
6
R38,R44,R55,R56,R61,R63
75R
38
3
R39,R43,R62
37R4
39
3
R40,R45,R66
53R6
40
1
R47
150R
41
2
R53,R48
22k
42
1
R51
150R
43
1
R54
5k
44
1
R57
37R5
45
1
R60
22R
46
1
R67
470R
47
1
R68
300R
48
1
R69
4K7
49
1
S1
KHS10
50
1
S2
STM1-01
51
8
T1,T2,T3,T4,T5,T6,T7,T8
PE-65812
52
4
U1,U3,U12,U14
SN75176B(D)
53
4
U2,U4,U13,U15
SN75176B(R)
54
2
U7,U5
GO1515
55
1
U6
GS1522
56
1
U8
GS1545
57
1
U9
GS1508
58
1
U10
LM1085_M
59
1
U11
MAX707
60
2
X2,X1
VCXO-920B1-24.576MHz
GS1503
ITEM
NOTE: This design is recommended for reference only. The AES/EBU inputs do not utilize equalization;
therefore cable length performance may be limited. For improved AES/EBU input and output performance,
it is recommended that examples in the AES-3id-2001 standard Annex B are consulted. This standard
includes alternative schematics for both input and output networks for 75Ω coaxial cable transmission. For
the transmission of AES/EBU over balanced 110Ω twisted pair cable, using XLR type connectors, please
consult the AES3-1992 standard
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4. REFERENCES & BIBLIOGRAPHY
SMPTE 260M-1999 1125/60 High-Definition Production System - Digital Representation and Bit-Parallel Interface
SMPTE 274M-1998 1920 x 1080 Scanning and Analog and Parallel Digital Interfaces for Multiple Picture Rates
SMPTE 291M-1998 Ancillary Data Packet and Space Formatting
SMPTE 292M-1998 Bit-Serial Digital Interface for High-Definition Television Systems
GS1503
SMPTE 295M-1997 1920 x 1080 50 Hz - Scanning and Interfaces
SMPTE 296M- 2001 1280 x 720 Scanning, Analog and Digital Representation and Analog Interface
SMPTE 299M-1997 24-Bit Digital Audio Format for HDTV Bit-Serial Interface
SMPTE RP211-2000 Implementation of 24P, 25P and 30P Segmented Frames for 1920 x 1080 Production Format
AES3-1992 (ANSI S4.40-1992) AES Recommended practice for digital audio engineering - Serial transmission format for
two-channel linearly represented digital audio data
AES-3id-2001 AES information document for digital audio engineering - Transmission of AES3 formatted data by unbalanced
coaxial cable
EBU Tech. 3250-E Specification of the Digital Audio Interface (The AES/EBU Interface) (Second Edition 1992)
Society of Motion Picture and Television Engineers: http://www.smpte.org
Audio Engineering Society: http://www.aes.org
European Broadcast Union: http://www.ebu.ch
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PACKAGING INFORMATION
22 ±0.4
20 ±0.1
108
73
GS1503
109
72
View on A-A
22 ±0.4
12˚ NOM
20 ±0.1
+0.05
0.125 -0.025
A
0˚ MIN
10˚ MAX
12˚ NOM
0.50
±0.2
INDEX
144
1.0
REF
37
1
36
1.40 ±0.1
1.70 MAX
144 pin LQFP (FZ)
Dimensions in millimetres
0.5
0.2 +0.1
-0.05
0.1
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REVISION HISTORY
VERSION
ECR
DATE
CHANGES AND/OR MODIFICATIONS
2
132133
September 2003
3
133576
June 2004
Fixed typing errors (page 24 and 33, Table 8, and Table 14). Added note to Section
1.11.
4
136656
May 2005
Added note to Section 1.6.2.2 clarifying that serial audio data is clocked by the
GS1503 using a 3.072MHz clock. Corrected Packaging Information.
Modified Host Interface Register 014 description (multiplex mode only). Added
revision history.
CAUTION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes at any time to improve reliability, function or design, in order to
provide the best product possible.
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
GENNUM CORPORATION
Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
GENNUM JAPAN CORPORATION
Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo,
160-0023 Japan
Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505
GENNUM UK lIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no liability for any errors or omissions in this
document, or for the use of the circuits or devices described herein. The sale
of the circuit or device described herein does not imply any patent license,
and Gennum makes no representation that the circuit or device is free from
patent infringement.
GENNUM and the G logo are registered trademarks of Gennum Corporation.
© Copyright 2001 Gennum Corporation. All rights reserved.
Printed in Canada.
www.gennum.com
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GS1503
DOCUMENT IDENTIFICATION