GENNUM GS1503B

GS1503B HD Embedded Audio CODEC Data Sheet
Features
Description
•
complies with SMPTE 292M and SMPTE 299M
•
single chip HD embedded audio solution
•
operates as an embedded audio multiplexer or
demultiplexer
•
full support for 48kHz synchronous 24-bit audio
•
support for 8 channels of audio per device
The GS1503B is a highly integrated, single chip solution for
embedding/extracting digital audio streams into and out of
high definition digital video signals. The GS1503B supports
insertion/extraction of 24-bit synchronous audio data with
a 48kHz sample rate. Audio signals with different sample
rates may be converted to 48kHz by using audio sample
rate converters before or after the GS1503B.
•
cascadable architecture supports up to 16 audio
channels
•
integrated scrambler/descrambler and word alignment
•
CRC error detection and insertion
•
audio control packet insertion and extraction
•
arbitrary data packet insertion and extraction
•
3.3V power supply with 5V tolerant I/O
•
144 pin TQFP package
Applications
HD SDI Embedded Audio
Each GS1503B supports all processing required for
embedding/extracting up to eight digital audio channels in
the horizontal ancillary data space of the video chroma
channel. Two GS1503B’s can be cascaded for
insertion/extraction of up to 16 audio channels with no
external glue logic.
The GS1503B supports embedding/extracting of audio
control and arbitrary data packets in the horizontal
ancillary data space of the video luma channel. It also
supports line CRC detection and insertion.
The GS1503B supports HD video standards at 74.25MHz
and 74.25/1.001MHz rates. It has an on chip SMPTE
compliant scrambler/de-scrambler, and integrated word
alignment. Use the GS1503B with Gennum’s GS1545 or
GS1522 for two chip HD SDI receive or transmit solutions.
The GS1503B operates from a single 3.3V power supply
with 5V tolerant I/O and is packaged in a 144 pin TQFP
package.
GS1503B HD Embedded Audio CODEC
Data Sheet
37953 - 1
December 2009
www.gennum.com
1 of 90
DSCBYPASS
VIN[19:0]
VM[3:0]
CPUADR[8:0]
CPUDAT[7:0]
CPUCS, CPUWE,
CPURE
PKT[7:0]
PKTEN
AIN1/2
AIN3/4
AIN5/6
AIN7/8
WCINA/B
20
EXTH
De-scrambler &
Word Alignment
EXTF
SCRBYPASS
20
20
TRS
Inserter
20
CRC Inserter &
Scrambler
Video Detection &
Synchronization
4
9
ANCI Timing
Generation
Host
Interface
8
3
8
20
4
Control
Packet
Mux
HOST INTERFACE
Arbitrary
Packet
Mux
HOST INTERFACE
VOUT[19:0]
VIDEO_DET
OPERATE
ERROR
CRC_ERR
PKTENO
4
2
Audio
Input
Interface
Audio
Packet
Mux
2
AM[1:0]
MUTE
Multiplex Mode Block Diagram
DSCBYPASS
VIN[19:0]
VM[3:0]
20
ANCI
De-scrambler &
Word Alignment
20
SCRBYPASS
Delete
ANCI
Arbitrary
Packet
Demux
CPUCS, CPUWE,
CPURE
8
Host
Interface
VIDEO_DET
OPERATE
ERROR
CRC_ERR
PKT[7:0]
PKTEN
HOST INTERFACE
4
3
VOUT[19:0]
HOST INTERFACE
9
8
20
4
Control
Packet
Demux
CPUDAT[7:0]
CRC Inserter &
Scrambler
Video Detection &
Synchronization
4
ANCI Timing
Generation
CPUADR[8:0]
20
Audio
Packet
Demux
Audio
Output
Interface
2
AOUT1/2
AOUT3/4
AOUT5/6
AOUT7/8
WCOUTA/B
2
AM[1:0]
MUTE
Demultiplex Mode Block Diagram
Contents
Features.................................................................................................................................................................1
Applications.........................................................................................................................................................1
Description...........................................................................................................................................................1
1. Pin Connections .............................................................................................................................................5
1.1 Pin Descriptions ................................................................................................................................6
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2. Electrical Characteristics ......................................................................................................................... 10
2.1 Absolute Maximum Ratings ....................................................................................................... 10
2.2 DC Electrical Characteristics ..................................................................................................... 10
2.3 AC Electrical Characteristics ..................................................................................................... 11
2.4 Solder Reflow Profiles .................................................................................................................. 13
3. Host Interface .............................................................................................................................................. 14
4. Detailed Description.................................................................................................................................. 17
4.1 Multiplex Mode .............................................................................................................................. 17
4.1.1 Functional Overview........................................................................................................ 17
4.2 Video Standard ............................................................................................................................... 18
4.3 Video Input Format ....................................................................................................................... 19
4.3.1 10-bit Y and Cb/Cr Input Video with TRS and Line Numbers ............................ 19
4.3.2 8-bit Y and Cb/Cr Input Video With TRS and Line Numbers.............................. 20
4.3.3 10-bit or 8-bit Y and Cb/Cr Input Without TRS and Line Numbers .................. 21
4.3.4 20-bit Scrambled Input .................................................................................................... 22
4.4 Video Output Format ................................................................................................................... 23
4.4.1 20-bit Scrambled Output................................................................................................. 23
4.4.2 10-bit Y and Cb/Cr Output ............................................................................................. 23
4.5 Video Data Processing ................................................................................................................. 24
4.5.1 Video Signal Input Detection......................................................................................... 24
4.5.2 Video Input CRC Error Detection................................................................................. 24
4.5.3 Video Output CRC Insertion .......................................................................................... 25
4.5.4 Illegal Code Re-mapping................................................................................................. 25
4.5.5 Input Blanking .................................................................................................................... 25
4.5.6 Line Number Insertion..................................................................................................... 26
4.5.7 TRS Word Insertion........................................................................................................... 26
4.6 Audio Data Processing ................................................................................................................. 27
4.6.1 Digital Audio Input Format ............................................................................................ 27
4.6.2 Digital Audio Input Timing............................................................................................. 28
4.6.3 Audio Clock Phase Locked Loop .................................................................................. 30
4.6.4 Audio Signal Input Detection ........................................................................................ 30
4.6.5 Audio Channel Status CRC Error Detection ............................................................. 31
4.6.6 Audio Input Parity Error Detection ............................................................................. 31
4.6.7 Audio Channel Status CRC Insert Function.............................................................. 32
4.7 Audio Data Packets ....................................................................................................................... 32
4.7.1 Audio Data Packet Structure ......................................................................................... 32
4.7.2 Audio Data Packet DID Setting ..................................................................................... 33
4.7.3 Audio Channel Multiplex Enable................................................................................. 34
4.8 Video Switching Line Setting ..................................................................................................... 35
4.9 Multiplex Cascade Mode ............................................................................................................ 36
4.10 Audio Control Packets ............................................................................................................... 38
4.10.1 Audio Control Packet Structure ................................................................................. 38
4.10.2 Audio Control Packet DID Setting ............................................................................. 39
4.11 Arbitrary Data Packets .............................................................................................................. 41
4.11.1 Arbitrary Data Multiplexing In External Pin Mode............................................. 42
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4.11.2 Arbitrary Data Multiplexing in Host Interface Mode ......................................... 43
5. Demultiplex Mode ..................................................................................................................................... 52
5.1 Functional Overview .................................................................................................................... 52
5.2 Video Standard ............................................................................................................................... 53
5.3 Video Input Format ....................................................................................................................... 54
5.3.1 20-bit Scrambled Input .................................................................................................... 54
5.3.2 10-bit Y and Cb/Cr Input with TRS and Line Numbers ......................................... 55
5.4 Video Output Format ................................................................................................................... 56
5.4.1 10-bit Y and Cb/Cr Output ............................................................................................. 56
5.4.2 20-bit Scrambled Output................................................................................................. 56
5.5 Video Data Processing ................................................................................................................. 57
5.5.1 Video Signal Input Detection......................................................................................... 57
5.5.2 Video Input CRC Error Detection................................................................................. 57
5.5.3 Video Output CRC Insertion .......................................................................................... 58
5.5.4 Input Blanking .................................................................................................................... 58
5.5.5 Line Number Insertion..................................................................................................... 58
5.5.6 TRS Word Insertion........................................................................................................... 59
5.6 Audio Data Processing ................................................................................................................. 59
5.6.1 Digital Audio Output Format......................................................................................... 59
5.6.2 Digital Audio Output Timing ......................................................................................... 60
5.6.3 Audio Clock Phase Locked Loop .................................................................................. 63
5.6.4 Audio Data Packet Detection ........................................................................................ 64
5.6.5 ECC Error Detection & Correction ............................................................................... 64
5.6.6 Audio Data Packet Error Detection ............................................................................. 65
5.6.7 Audio Data Packet DID Setting ..................................................................................... 66
5.7 Demultiplex Cascade Mode ....................................................................................................... 67
5.8 Audio Control Packets ................................................................................................................. 68
5.8.1 Audio Control Packet Detection................................................................................... 68
5.8.2 Audio Control Packet DID Setting ............................................................................... 68
5.9 Arbitrary Data Packets ................................................................................................................. 70
5.9.1 Arbitrary Data Demultiplexing in External Pin Mode .......................................... 71
5.9.2 Arbitrary Data Demultiplexing in Host Interface Mode ...................................... 71
5.10 Ancillary Data Deletion ............................................................................................................ 72
5.10.1 Entire Ancillary Data Deletion ................................................................................... 72
5.10.2 Audio Group Designation Ancillary Data Deletion............................................. 72
5.11 Demultiplex Mode With Word Clock Input ....................................................................... 73
6. Using the GS1503B with the GS4911B or GS4910B ........................................................................ 86
7. References & Bibliography ...................................................................................................................... 87
8. Packaging & Ordering Information ...................................................................................................... 88
8.1 Package Dimensons ...................................................................................................................... 88
8.2 Packaging Data ............................................................................................................................... 88
8.3 Ordering Information ................................................................................................................... 89
9. Revision History.......................................................................................................................................... 90
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108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
GND
CPUWE
CPURE
CPUCS
VDD
CPUDAT7
CPUDAT6
CPUDAT5
CPUDAT4
CPUDAT3
CPUDAT2
VDD
CPUDAT1
CPUDAT0
CPUADR4
CPUADR3
CPUADR2
CPUADR1
CPUADR0
CPUADR5
GND
VCLK
GND
DEC_MODE
VDD
CPUADR6
CPUADR7
CPUADR8
GND
AOUT7/8
AOUT5/6
AOUT3/4
AOUT1/2
WCOUTB
WCOUTA
VDD
1. Pin Connections
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
GS1503B
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
GND
VOUT19
VOUT18
VOUT17
VDD
VOUT16
VOUT15
VOUT14
GND
VOUT13
VOUT12
VOUT11
VDD
VOUT10
VOUT9
VOUT8
GND
VOUT7
VOUT6
VOUT5
VDD
VOUT4
VOUT3
VOUT2
GND
VOUT1
VOUT0
VIDEO_DET
EXTF
EXTH
RSV
RSV
RSV
RSV
SCRBYPASS
VDD
VDD
AIN7/8
AIN5/6
AIN3/4
AIN1/2
WCINB
WCINA
DSCBYPASS
PLLCNTB
PLLCNTA
CASCADE
MUTE
ANCI
VDD
MUX/DEMUX
GND
ACLKA
GND
ACLKB
GND
ERROR
OPERATE
CRC_ERROR
PKTENO
PKTEN
PKT7
VDD
PKT6
PKT5
PKT4
VDD
PKT3
PKT2
PKT1
PKT0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VDD
VIN19
VIN18
VIN17
GND
VIN16
VIN15
VIN14
VDD
VIN13
VIN12
VIN11
GND
VIN10
VIN9
VIN8
VDD
VIN7
VIN6
VIN5
GND
VIN4
VIN3
VIN2
VDD
VIN1
VIN0
CPU_SEL
AM1
AM0
VM3
VM2
VM1
VM0
RESET
GND
GS1503B HD Embedded Audio CODEC
Data Sheet
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December 2009
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1.1 Pin Descriptions
Table 1-1: Pin Descriptions
Number
Symbol
Type
Description
1, 14, 27,
31, 37, 52,
60, 68, 73,
84, 97, 104,
109, 117,
125, 133
VDD
–
+3.3V power supply pins.
2
AIN7/8
I
Audio signal input for channels 7 and 8. AES/EBU digital audio data is bi-phase mark
encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required.
3
AIN5/6
I
Audio signal input for channels 5 and 6. AES/EBU digital audio data is bi-phase mark
encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required.
4
AIN3/4
I
Audio signal input for channels 3 and 4. AES/EBU digital audio data is bi-phase mark
encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required.
5
AIN1/2
I
Audio signal input for channels 1 and 2. AES/EBU digital audio data is bi-phase mark
encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required.
6
WCINB
I
48kHz word clock for channels 5 to 8. Used only when operating in Multiplex Mode
and when the audio source is not an AES/EBU data stream. This pin should be
grounded when inputting AES/EBU digital audio data or when operating in
Demultiplex Mode (DEC_MODE set LOW).
7
WCINA
I
48kHz word clock for channels 1 to 4. Used only when operating in Multiplex Mode
and when the audio source is not an AES/EBU data stream. This pin should be
grounded when inputting AES/EBU digital audio data or when operating in
Demultiplex Mode (DEC_MODE set LOW).
8
DSCBYPASS
I
Descrambler bypass. When set LOW, the internal SMPTE 292M descrambler is enabled.
When set HIGH, the internal SMPTE 292M descrambler is bypassed. The video input to
the device must be word aligned.
9
PLLCNTB
O
Audio clock PLL control signal for channels 5 to 8.
10
PLLCNTA
O
Audio clock PLL control signal for channels 1 to 4.
11
CASCADE
I
Cascade mode select. When set HIGH, the GS1503B will default to audio groups 3 and
4. Two GS1503B devices can then be cascaded in series to allow up to 16 channels of
audio to be multiplexed or demultiplexed (only one device requires CASCADE to be set
HIGH). When set LOW, the GS1503B will default to audio groups 1 and 2.
12
MUTE
I
Audio mute. In Multiplex Mode, when set HIGH, the embedded audio packets are
forced to '0'. In Demultiplex Mode, when set HIGH, the audio output data is forced to
"0".
13
ANCI
I
Ancillary data delete select. Valid in Demultiplex Mode only. When set HIGH, all
ancillary data packets are removed from both the Luma and Chroma channels of the
input video signal. The data contained in the packets are output at the corresponding
pins. When set LOW, all ancillary data packets remain in the video signal. See
Demultiplex Mode With Word Clock Input on page 73.
15
MUX/DEMUX
I
Mode of operation. When set LOW, the GS1503B operates in Multiplex Mode.
When set HIGH, the GS1503B operates in Demultiplex Mode.
GS1503B HD Embedded Audio CODEC
Data Sheet
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December 2009
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Table 1-1: Pin Descriptions (Continued)
Number
Symbol
Type
Description
16, 18, 20,
36, 48, 56,
64, 72, 80,
86, 88, 108,
113, 121,
129, 144
GND
–
Device ground.
17
ACLKA
I
Input audio signal clock at 6.144 MHz (128 fs) for channels 1 to 4.
19
ACLKB
I
Input audio signal clock at 6.144 MHz (128 fs) for channels 5 to 8.
21
ERROR
O
Format error indicator. When HIGH, the incoming video data stream contains TRS
errors or there are errors within the incoming ancillary data packets.
22
OPERATE
O
Audio processing indicator. When HIGH, audio data is being multiplexed or
demultiplexed.
23
CRC_ERROR
O
CRC error indicator. Will be set HIGH when a CRC error is detected in the incoming
video data stream.
24
PKTENO
O
Arbitrary data packet timing signal. Valid in Multiplex Mode only. Will be HIGH when
arbitrary data packets can be input to the device. This signal is only valid when
multiplexing arbitrary data packets via the PKT[7:0] bus. See Figure 4-22 for timing.
25
PKTEN
I/O
Arbitrary data packet enable. In Multiplex Mode, PKTEN is an input and must be set
HIGH two VCLK cycles after the PKTENO signal goes HIGH. Arbitrary packet data is
input to the device two VCLK cycles after PKTEN is set HIGH. In Demultiplex Mode,
PKTEN is an output and is set HIGH two VCLK cycles before the device outputs
arbitrary packet data. See Figure 4-22 and Figure 5-12.
26, 28, 29,
30, 32, 33,
34, 35
PKT[7:0]
I/O
Arbitrary data I/O bus. PKT[7] is the MSB and PKT[0] is the LSB. In Multiplex Mode, the
user must input the arbitrary data packet words starting from the data identification
(DID) to the last user data word (UDW) according to SMPTE 291M. The GS1503B
internally converts the data to 10 bits by generating the parity bit (bit 8) and inversion
bit (bit 9). The checksum (CS) word is also generated internally. In Demultiplex Mode,
the GS9023 outputs the arbitrary data packet words starting from the DID to the last
UDW. See Figure 4-22 and Figure 5-12.
38
SCRBYPASS
I
Scrambler bypass. When set LOW, the output video stream is scrambled according to
SMPTE 292M and NRZ(I) encoded. When set HIGH, the scrambler and NRZ(I) encoder
are bypassed.
39, 40, 41,
42
RSV
–
Connect to ground.
43
EXTH
I/O
Horizontal sync signal. The GS1503B outputs a horizontal sync signal derived from the
incoming TRS. In Multiplex Mode, with EXT_SEL set HIGH in the Host Interface, a
horizontal sync signal can be input to the device for TRS and line number insertion.
44
EXTF
I/O
Field sync signal. The GS1503B outputs a field sync signal derived from the incoming
TRS. In Multiplex Mode, with EXT_SEL set HIGH in the Host Interface, a field sync signal
can be input to the device for TRS and line number insertion. For progressive formats,
a signal with a high to low transition at the position of line one must be provided. See
Figure 4-6 and Figure 4-7.
45
VIDEO_DET
O
Video input signal detection. Indicates that the device has detected a valid video input
stream.
NOTE: When EXT_SEL is set HIGH in the Host Interface, VIDEO_DET will indicate when
valid EXTH and EXTF signals have been detected.
GS1503B HD Embedded Audio CODEC
Data Sheet
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December 2009
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Table 1-1: Pin Descriptions (Continued)
Number
Symbol
Type
Description
71, 70, 69,
67, 66, 65,
63, 62, 61,
59, 58, 57,
55, 54, 53,
51, 50, 49,
47, 46
VOUT[19:0]
O
Parallel digital video signal output. VOUT[19] is the MSB and VOUT[0] is the LSB.
74
WCOUTA
O
48kHz word clock for channels 1 to 4. Valid only when operating in Demultiplex Mode.
75
WCOUTB
O
48kHz word clock for channels 5 to 8. Valid only when operating in Demultiplex Mode.
76
AOUT1/2
O
Audio signal output for channels 1 and 2. The AES/EBU digital audio output is bi-phase
mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded.
77
AOUT3/4
O
Audio signal output for channels 3 and 4. The AES/EBU digital audio output is bi-phase
mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded.
78
AOUT5/6
O
Audio signal output for channels 5 and 6. The AES/EBU digital audio output is bi-phase
mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded.
79
AOUT7/8
O
Audio signal output for channels 7 and 8. The AES/EBU digital audio output is bi-phase
mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded.
85
DEC_MODE
I
Demultiplex Mode select. Valid in Demultiplex Mode only. When set HIGH, the
GS1503B requires a 48kHz word clock input at WCINA and WCINB. This word clock
must be synchronous to the word clock used to embed the audio data. The embedded
audio clock phase information in the ancillary data packet will be ignored. See
Demultiplex Mode With Word Clock Input on page 73.
87
VCLK
I
Video clock signal input.
81, 82, 83,
89, 94, 93,
92, 91, 90
CPUADR[8:0]
I
Host Interface address bus. CPUADR[8] is the MSB and CPUADR[0] is the LSB.
In
Host Interface Mode B (CPU_SEL set LOW), CPUADR[1:0] are used as the Host Interface
control bus. See Table 3-4.
103, 102,
101, 100,
99, 98, 96,
95
CPUDAT[7:0]
I/O
Host Interface data bus. CPUDAT[7] is the MSB and CPUDAT[0] is the LSB.
In Host Interface Mode B (CPU_SEL set LOW), CPUDAT[7:0] are used as the Host
Interface address and data bus.
105
CPUCS
I
Chip select for Host Interface. Active LOW.
106
CPURE
I
Read enable for Host Interface. Active LOW. In Host Interface Mode B (CPU_SEL set
LOW), this input is not used.
107
CPUWE
I
Write enable for Host Interface. Active LOW. In Host Interface Mode B (CPU_SEL set
LOW), this input is used as the Host Interface control enable.
110, 111,
112, 114,
115, 116,
118, 119,
120, 122,
123, 124,
126, 127,
128, 130,
131, 132,
134, 135
VIN[19:0]
I
Parallel digital video signal input. VIN[19] is the MSB and VIN[0] is the LSB.
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December 2009
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Table 1-1: Pin Descriptions (Continued)
Number
Symbol
Type
Description
136
CPU_SEL
I
Host Interface mode select. When set HIGH, the GS1503B is configured for Host
Interface Mode A. When set LOW, the GS1503B is configured for Host Interface Mode
B.
137, 138
AM[1:0]
I
Audio format select. In Multiplex Mode, AM[1:0] indicates the input audio data
format.
In Demultiplex Mode, AM[1:0] indicates the output audio data format.
AM[1] is the MSB and AM[0] is the LSB. See Table 4-16 and Table 5-13.
139, 140,
141, 142
VM[3:0]
I
Video standard select. VM[3] is the MSB and VM[0] is the LSB. See Table 4-1 or
Table 5-1.
143
RESET
I
Device reset. Active LOW.
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December 2009
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Table 2-1: Absolute Maximum Ratings
Parameter
Value
Supply Voltage
-0.3V to 4.0V
Input Voltage (any input)
-0.3 to 5.5V
Operating Temperature
0°C to 70°C
Storage temperature
-65°C to 150°C
Lead Temperature (soldering, 10 sec.)
260°C
2.2 DC Electrical Characteristics
Table 2-2: DC Electrical Characteristics
TA = 0°C to 70°C unless otherwise shown.
Parameter
Symbol
Conditions
Supply Voltage
VDD
3.3V operating range
Supply Current
IDD
VDD = 3.3V
Input Current
IIN
–
-1
–
1
μA
Hi-Z Output Leakage Current
IOZ
–
-1
–
1
μA
Output Voltage, Logic High
VOH
IOH = -12mA
VDD-0.4
–
–
V
Output Voltage, Logic Low
VOL
IOL = 12mA
–
–
0.4
V
Input Voltage, Logic High
VIH
TTL Level
2.0
–
–
V
Input Voltage, Logic Low
VIL
TTL Level
–
–
0.8
V
Input Capacitance
CI
f = 1MHz, VDD = 0V
–
–
10
pF
Output Capacitance
CO
f = 1MHz, VDD = 0V
–
–
10
pF
I/O Capacitance
CIO
f = 1MHz, VDD = 0V
–
–
10
pF
GS1503B HD Embedded Audio CODEC
Data Sheet
37953 - 1
December 2009
Min
3.0
Typ
3.3
Max
3.6
270
Units
V
mA
10 of 90
2.3 AC Electrical Characteristics
Table 2-3: AC Electrical Characteristics
VDD = 3.3V ± 5%, TA = 0°C to 70°C unless otherwise shown.
Parameter
Symbol
Video Clock Frequency
Conditions
Min
Typ
Max
Units
–
–
74.25
80
MHz
Video Clock Pulse Width Low
tVPWL
–
5.0
–
–
ns
Video Clock Pulse Width High
tVPWH
–
5.0
–
–
ns
Video Input Data Setup Time
tVS
–
3.5
–
–
ns
Video Input Data Hold Time
tVH
–
1.0
–
–
ns
Video Output Data Delay Time
tVOD
With 10pF loading
–
–
8.5
ns
Video Output Data Hold Time
tVOH
With 10pF loading
1.0
–
–
ns
–
–
6.144
–
MHz
Audio Clock Frequency
Audio Clock Pulse Width Low
tAPWL
–
60
–
–
ns
Audio Clock Pulse Width High
tAPWH
–
60
–
–
ns
Audio Input Data Setup Time
tAS
–
10.5
–
–
ns
Audio Input Data Hold Time
tAH
–
1.0
–
–
ns
Audio Output Data Delay Time
tAOD
With 10pF loading
–
–
20.0
ns
Audio Output Data Hold Time
tAOH
With 10pF loading
1.0
–
–
ns
Reset Pulse Width
tRESET
–
1
–
–
ms
Device Latency
–
Multiplexer Mode
53
53
53
PCLKs
Demultiplexer Mode
53
53
53
t VS
t VH
VCLK
Data*
* VIN[19:0],
EXTF, EXTH, PKTEN, PKT[7:0]
Figure 2-1: Video Data Input Setup & Hold Time
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t VOH
t VOD
VCLK
Data*
* VOUT[19:0], EXTF, EXTH, PKTEN, PKT[7:0]
Figure 2-2: Video Data Output Delay & Hold Time
t AS
t AH
ACLKA/B
Data*
* WCINA, AIN1/2, AIN3/4, WCINB, AIN5/6, AIN7/8
Figure 2-3: Audio Data Input Setup & Hold Time
t AOH
t AOD
ACLKA/B
Data*
* AOUT1/2, AOUT3/4, AOUT5/6, AOUT7/8
Figure 2-4: Audio Data Output Delay & Hold Time
VDD(min)
VDD
t RESET
t RESET
RESET
Figure 2-5: Reset Timing
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2.4 Solder Reflow Profiles
60-150 sec.
Temperature
10-20 sec.
230˚C
220˚C
3˚C/sec max
183˚C
6˚C/sec max
150˚C
100˚C
25˚C
Time
120 sec. max
6 min. max
Figure 2-6: Maximum Pb-Free Solder Reflow Profile (Preferred)
Temperature
60-150 sec.
20-40 sec.
260˚C
250˚C
3˚C/sec max
217˚C
6˚C/sec max
200˚C
150˚C
25˚C
Time
60-180 sec. max
8 min. max
Figure 2-7: Standard Eutectic Solder Reflow Profile
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3. Host Interface
Table 3-1: Mode A (CPU_SEL set HIGH)
Parameter
Number
Min
Typ
Max
Units
Read Cycle Time
1
50
–
–
ns
Read Chip Select Setup Time
2
0
–
–
ns
Read Address Setup Time
3
15
–
–
ns
Read Data Output Delay Time
4
–
–
15
ns
Read Data Hold Time
5
0
–
–
ns
Write Cycle Time
6
50
–
–
ns
Write Chip Select Setup Time
7
10
–
–
ns
Write Address Setup Time
8
10
–
–
ns
Write Data Setup Time
9
10
–
–
ns
Write Data Hold Time
10
0
–
–
ns
Read Cycle
CPUADR[8:0]
Write Cycle
1
6
Address
Address
2
7
CPUCS
CPURE
3
CPUWE
8
Valid Data
CPUDAT[7:0]
4
Valid Data
5
9
10
Figure 3-1: Host Interface Mode A Timing (CPU_SEL set HIGH)
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Table 3-2: Mode B Read Cycle (CPU_SEL set LOW)
Parameter
Number
Min
Typ
Max
Units
Read Address Cycle Time
1
80
–
–
ns
Read Cycle Time
2
80
–
–
ns
Read Enable Setup Time
3
20
–
–
ns
Read Address Setup Time
4
20
–
–
ns
Read Chip Select Setup Time
5
10
–
–
ns
Read Chip Select Hold Time
6
0
–
–
ns
Read Data Output Delay Time
7
–
–
10
ns
Read Data Hold Time
8
0
–
–
ns
CPUADR[1:0]
1
1
2
01
00
11
8
Upper Address
CPUDAT[7:0]
Read
Data
Lower Address
7
CPUCS
CPUWE
5
5
4
4
6
3
5
6
3
6
3
Figure 3-2: Host Interface Mode B Read Cycle Timing (CPU_SEL set LOW)
Table 3-3: Mode B Write Cycle (CPU_SEL set LOW)
Parameter
Number
Min
Typ
Max
Units
Write Address Cycle Time
1
80
–
–
ns
Write Cycle Time
2
80
–
–
ns
Write Enable Setup Time
3
20
–
–
ns
Write Address Setup Time
4
20
–
–
ns
Write Chip Select Setup Time
5
10
–
–
ns
Write Chip Select Hold Time
6
0
–
–
ns
Write Data Setup Time
7
30
–
–
ns
Write Data Hold Time
8
0
–
–
ns
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CPUADR[1:0]
1
1
2
01
00
10
8
Upper Address
CPUDAT[7:0]
Write
Data
Lower Address
7
CPUCS
CPUWE
5
5
4
4
6
3
5
6
3
6
3
Figure 3-3: Host Interface Mode B Write Cycle Timing (CPU_SEL set LOW)
Table 3-4: Host Interface Mode B Control Codes
CPUADR[1:0]
Data Bus Operation
01
Upper Address
00
Lower Address
11
Read Data
10
Write Data
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4. Detailed Description
4.1 Multiplex Mode
4.1.1 Functional Overview
The GS1503B HD Embedded Audio CODEC fully supports the multiplexing of Audio
Data Packets, Audio Control Packets and Arbitrary Data Packets as per SMPTE 291M
and 299M. The device can be configured to operate with all video standards defined in
SMPTE 292M, levels A through M. The GS1503B also supports the 1080/24PsF, 25PsF
and 30PsF video formats as described in SMPTE RP211.
The video input format can be one of the following configurations:
•
10-bit Y and Cb/Cr input with TRS and Line Numbers
•
8-bit Y and Cb/Cr input with TRS and Line Numbers
10-bit or 8-bit Y and Cb/Cr input without TRS and Line Numbers (GS1503B will insert TRS
and Line Numbers based on EXTF and EXTH inputs)
•
20-bit scrambled input
The video output format can be one of the following configurations:
•
20-bit scrambled output
•
10-bit Y and Cb/Cr output
Up to a maximum of 8 channels of 48kHz digital audio can be multiplexed per device.
The audio input format can be selected as either AES/EBU, or one of two serial audio
data input modes. A maximum of 16 channels of audio can be multiplexed by serially
cascading two devices.
Audio control packets, as defined in SMPTE 299M, can also be multiplexed to provide
information to receivers about the nature of the embedded audio data. The contents of
the audio control packet can be programmed via the Host Interface.
The GS1503B will also multiplex arbitrary data packets as defined in SMPTE 291M. The
arbitrary data packets can serve as an auxiliary data signal for proprietary applications.
The GS1503B can be configured to multiplex arbitrary data packets, input via the Host
Interface or using dedicated external pins. Up to a maximum of 255 8-bit words can be
multiplexed (excluding Ancillary Data Flags and Checksum).
To use the GS1503B in Multiplex Mode, set the MUX/DEMUX external pin LOW.
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4.2 Video Standard
The video standard is selected from the VM[3:0] external pins or VM[3:0] bits 3-0 in Host
Interface register 000h. To configure the video standard via the Host Interface, VM_SEL
bit 7 in Host Interface register 000h must be set HIGH. The GS1503B will default to the
VM[3:0] external pin setting. The supported video standards are listed in Table 4-1.
Table 4-1: Supported Video Standards
VM [3:0]
Input Format
Reference SMPTE Document
SMPTE 292M Level
1110b
1035i (30 & 30/1.001 Hz)
260M
A, B
1100b
1080i (25 Hz)
295M
C
1000b
1080i/1080sF (30 & 30/1.001 Hz)
274M, RP211
D, E
1010b
1080i/1080sF (25 Hz)
274M, RP211
F
1111b
1080sF (24 & 24/1.001 Hz)
RP211
0010b
1080p (30 & 30/1.001 Hz)
274M
G, H
0100b
1080p (25 Hz)
274M
I
0110b
1080p (24 & 24/1.001 Hz)
274M
J, K
0000b
720p (60 & 60/1.001 Hz)
296M
L, M
0001b
720p (30 & 30/1.001 Hz)
296M
0011b
720p (50 Hz)
296M
0101b
720p (25 Hz)
296M
0111b
720p (24 & 24/1.001 Hz)
296M
All other settings are reserved
Table 4-2: Register Settings
Name
VM_SEL
Description
0: External pin select
Address
Bit
000
7
000
3-0
Setting
Default
1
0
See
0
1: Register select
VM[3:0]
Video formal selection (VM[3] is MSB)
Table 4-1
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4.3 Video Input Format
4.3.1 10-bit Y and Cb/Cr Input Video with TRS and Line Numbers
GS1503B
Y[9:0]
VIN[19:10]
Cb / Cr [9:0]
VIN[9:0]
EXTF
+3.3V
EXTH
DSCBYPASS
EAV
Vn
V0
XYZ
000
000
3FF
8
CRC1
LN1
CRC0
LN0
XYZ
000
000
3FF
Y, C b/Cr
10-bit
0
3
Figure 4-1: Configuration for 10-bit Y and Cb/Cr Input Video with TRS and Line
Numbers
Video
SAV
Figure 4-2: Video Input Format 10-bit with TRS and Line Numbers
Table 4-3: Register Settings
Name
EXT_SEL
Description
0: EXTH/EXTF output select
Address
Bit
Setting
Default
001
3
0
0
001
1
0
0
001
0
1
0
1: EXTH/EXTF input select
8BIT_SEL
0: 10-bit mode select
1: 8-bit mode select
DSCBYPASS
0: Descrambling enabled
1: Bypass descrambling
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4.3.2 8-bit Y and Cb/Cr Input Video With TRS and Line Numbers
GS1503B
Y[9:0]
VIN[19:12]
VIN[11:10]
C b/ C r[9:0]
VIN[9:2]
EXTF
VIN[1:0]
+3.3V
EXTH
DSCBYPASS
EAV
Vn
V0
00
XY
00
FF
LN1
3
XY
LN0
00
0
00
FF
8-bit
Y, C b/Cr
8
Figure 4-3: Configuration for 8-bit Y and Cb/Cr Input Video with TRS and Line
Numbers
Video
SAV
Figure 4-4: Video Input Format 8-bit with TRS and Line Numbers
Table 4-4: Register Settings
Name
EXT_SEL
Description
0: EXTH/EXTF output select
Address
Bit
Setting
Default
001
3
0
0
001
1
1
0
001
0
1
0
1: EXTH/EXTF input select
8BIT_SEL
0: 10-bit mode select
1: 8-bit mode select
DSCBYPASS
0: Descrambling enabled
1: Bypass descrambling
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4.3.3 10-bit or 8-bit Y and Cb/Cr Input Without TRS and Line Numbers
The GS1503B will insert TRS and Line Numbers based on EXTF and EXTH inputs. See
Figure 4-6 for timing. In progressive format video standards, a high-to-low edge signal
must be input at the EXTF external pin on every frame to indicate the position of line 1.
See Figure 4-7.
GS1503B
Y[9:0]
VIN[19:10]
C b / Cr [9:0]
VIN[9:0]
EXTF
EXTH
+3.3V
DSCBYPASS
V0
Video
Vn
3
0
8/10-bit
Y, Cb /C r
8
Figure 4-5: Configuration for 10-bit or 8-bit Y and Cb/Cr Input Video without
TRS and Line Numbers
4 VCLK
EXTH
EXTF
V0
Video
Vn
3
0
8/10-bit
Y, C b/C r
8
Figure 4-6: Video Input Format (8/10-bit without TRS and Line Numbers)
4 VCLK
EXTH
EXTF
Line 1
Figure 4-7: 15 Video Input Format (Progressive)
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Table 4-5: Register Settings
Name
EXT_SEL
Description
0: EXTH/EXTF output select
Address
Bit
Setting
Default
001
3
1
0
001
1
0 or 1
0
001
0
1
0
1: EXTH/EXTF input select
8BIT_SEL
0: 10-bit mode select
1: 8-bit mode select
DSCBYPASS
0: Descrambling enabled
1: Bypass descrambling
4.3.4 20-bit Scrambled Input
GS1503B
Y/C b / Cr [19:0]
VIN[19:0]
DSCBYPASS
Figure 4-8: Configuration for 20-bit Scrambled Input
Table 4-6: Register Settings (Default Mode)
Name
EXT_SEL
Description
0: EXTH/EXTF output select
Address
Bit
Setting
Default
001
3
0
0
001
1
0
0
001
0
0
0
1: EXTH/EXTF input select
8BIT_SEL
0: 10-bit mode select
1: 8-bit mode select
DSCBYPASS
0: Descrambling enabled
1: Bypass descrambling
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4.4 Video Output Format
4.4.1 20-bit Scrambled Output
GS1503B
VOUT[19:0]
Y/Cb / C r [19:0]
SCRBYPASS
Figure 4-9: Configuration for 20-bit Scrambled Output
Table 4-7: Register Settings (Default Mode)
Name
Description
SCRBYPASS
Address
0: SMPTE 292M scrambling enabled
001
Bit
2
Setting
0
Default
0
1: Bypass SMPTE 292M scrambling
4.4.2 10-bit Y and Cb/Cr Output
GS1503B
Y[9:0]
VOUT[19:10]
VOUT[9:0]
C b / Cr [9:0]
+3.3V
SCRBYPASS
Figure 4-10: Configuration for 10-bit Y and Cb/Cr Output
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Table 4-8: Register Settings
Name
SCRBYPASS
Description
0: SMPTE 292M scrambling enabled
Address
Bit
001
Setting
2
1
Default
0
1: Bypass SMPTE 292M scrambling
4.5 Video Data Processing
4.5.1 Video Signal Input Detection
The GS1503B will set the VIDEO_DET external pin HIGH when three consecutive TRS
are detected in the input video signal. Also, the VIDEO_DET bit of Host Interface register
000h is set HIGH.
Table 4-9: Register Settings
Name
Description
VIDEO_DET
Video input signal detection (1: Detection)
Address
000
Bit
Setting
Default
6
–
0
Bit
Setting
Default
4.5.2 Video Input CRC Error Detection
The GS1503B will set the CRC_ERR external pin HIGH when a CRC error is detected in
the input video signal. Also, the CRC_ERR bit 5 of Host Interface register 000h is set
HIGH. The number of CRC errors accumulated in one video frame can be read form
CRC_CNT[11:0] in Host Interface registers 006h and 007h.
Table 4-10: Register Settings
Name
Description
CRC_ERR
Video input signal CRC error detection (1: Detection)
000
5
–
0
CRC_CNT[11:0]
Video input signal CRC error accumulation in 1 video
frame
006
3-0
–
0
007
7-0
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Address
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4.5.3 Video Output CRC Insertion
When the CRC_INS bit 4 of Host Interface register 000h is set HIGH, the GS1503B will
re-calculate the video line CRC words. The re-calculated CRC words are inserted in the
video output signal. When CRC_INS is set LOW, the line CRC words are not updated and
existing CRC words at the input of the device will be output unchanged.
Table 4-11: Register Settings
Name
Description
CRC_INS
Video line CRC insertion (1: Insertion)
Address
Bit
000
4
Setting
Default
1
1
Setting
Default
4.5.4 Illegal Code Re-mapping
When LIMIT_ON bit 4 of Host Interface register 008h is set HIGH, input video words
between 000-003 are re-mapped to 004, and values between 3FC-3FF are re-mapped to
3FB. Valid only when the EXT_SEL bit 3 of Host Interface register 000h is set HIGH.
Table 4-12: Register Settings
Name
EXT_SEL
Description
0: EXTH/EXTF output select
Address
Bit
001
3
1
0
008
4
1
0
1: EXTH/EXTF input select
LIMIT_ON
Illegal code re-mapping (1: Enabled)
4.5.5 Input Blanking
When VBLK_INS bit 3 of Host Interface register 008h is set HIGH, the input video vertical
blanking will be set to 040h for the Luma channel and 200h for the Chroma channel.
When HBLK_INS bit 2 of Host Interface register 008h is set HIGH, the input video
horizontal blanking will be set to 040h for the Luma channel and 200h for the Chroma
channel. The TRS, line number and CRC words will also be set to blanking values.
The blanking function is performed at the output of the GS1503B video data stream. If
the HBLK_INS bit is set HIGH, any multiplexed audio will be replaced with blanking
codes.
Table 4-13: Register Settings
Name
Description
VBLK_INS
Input vertical blanking (1: Enabled)
008
3
1
0
HBLK_INS
Input horizontal blanking (1: Enabled)
008
2
1
0
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Address
Bit
Setting
Default
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4.5.6 Line Number Insertion
When LN_INS bit 1 of Host Interface register 008h is set HIGH, the GS1503B will insert
line numbers into the video data stream. When set LOW, existing line numbers will
remain in the output video stream.
When EXT_SEL bit 3 of Host Interface register 001h is set HIGH, line numbers will be
inserted based on the timing of EXTH and EXTF input signals.
Table 4-14: Register Settings
Name
Description
LN_INS
Line number insertion (1: Enabled)
Address
Bit
008
Setting
1
1
Default
1
4.5.7 TRS Word Insertion
When TRS_INS bit 0 of Host Interface register 008h is set HIGH, the GS1503B will insert
TRS codes into the video data stream. When set LOW, existing TRS codes will remain in
the output video stream.
When EXT_SEL bit 3 of Host Interface register 001h is set HIGH, TRS codes will be
inserted based on the timing of EXTH and EXTF input signals.
Table 4-15: Register Settings
Name
Description
TRS_INS
TRS word insertion (1: Enabled)
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Address
008
Bit
Setting
0
1
Default
1
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4.6 Audio Data Processing
4.6.1 Digital Audio Input Format
The GS1503B will accept two audio input formats, AES/EBU digital audio input and
serial input, as listed in Table 4-16. Serial input can be formatted in the following two
modes. See Figure 4-11.
•
24-bit Left Justified; MSB first
•
24-bit Right Justified; MSB last
The audio input format is configured using the AM[1:0] external pins or via AM[1:0] bits
1-0 in Host Interface register 010h. To configure the audio input format via the Host
Interface, AM_SEL bit 7 in Host Interface register 010h must be set HIGH. The GS1503B
will default to the AM[1:0] external pin setting.
Table 4-16: Audio Input Formats
AM[1:0]
Audio Input Format
0
Serial audio input: 24-bit Left Justified; MSB first
1
Serial audio input: 24-bit Right Justified; MSB last
2
AES/EBU audio input
Table 4-17: Register Settings
Name
Description
AM_SEL
Address
0: External pin setting
Bit
Setting
Default
010
7
1
0
010
1-0
See
Table 4-11
0
1: Register setting
AM[1:0]
Audio input format selection (AM[1] is MSB)
Channel 1
Channel 2
WCINA/WCINB
MSB
MODE0
MSB
23
0
23
0
LSB
0
MODE2
(AES/EBU)
LSB
0
MODE1
23
3 4
Sync
Preamble
2728293031 0
24-bit Audio Sample Word
0
23
3 4
Sync
V U C P Preamble
2728293031
24-bit Audio Sample Word
V UC P
Validity Bit
User Data Bit
Channel Status Bit
Parity Bit
Figure 4-11: Audio Input Formats
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4.6.2 Digital Audio Input Timing
4.6.2.1 AES/EBU Format Input
A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs.
ACLKA is used to clock the AES/EBU digital audio signal for channels 1 to 4 (AIN1/2 and
AIN3/4) into the device. ACLKB is used to clock the AES/EBU digital audio signal for
channels 5 to 8 (AIN5/6 and AIN7/8) into the device. In AES/EBU input mode, the
WCINB and WCINB external pins should be grounded. See Figure 4-12 for timing.
GS1503B
Y/C b / Cr [19:0]
Audio Channels 1 & 2
Audio Channels 3 & 4
6.144MHz (128 fs)
VIN[19:0]
AIN1/2
AIN3/4
ACLKA
WCINA
Audio Channels 5 & 6
Audio Channels 7 & 8
6.144MHz (128 fs)
AIN5/6
AIN7/8
ACLKB
WCINB
6.144MHz
ACLKA/B
AIN1/2, AIN3/4
AIN5/6, AIN7/8
Figure 4-12: AES/EBU Input Configuration and Timing
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4.6.2.2 Serial Audio Input Modes
A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs. The
GS1503B divides this clock by 2 to clock the 3.072MHz audio data. An audio word clock
at 48kHz (fs) must also be supplied to the WCINA and WCINB inputs, as shown in
Figure 4-13. The AUDIO_CS[183:0] bits in Host Interface registers 058h to 06Eh can be
used to enter the 23 8-bit bytes of the Audio Channel Status Block, as defined in
AES3-1992. NOTE: The CRC byte is generated internally by the GS1503B. The GS1503B
will default to Professional audio mode with 24-bit word length and emphasis off. See
Table 4-34.
GS1503B
Y/C b / Cr [19:0]
VIN[19:0]
Audio Channels 1 & 2
AIN1/2
Audio Channels 3 & 4
AIN3/4
6.144MHz (128 fs)
ACLKA
48kHz (fs)
WCINA
Audio Channels 5 & 6
AIN5/6
Audio Channels 7 & 8
AIN7/8
6.144MHz (128 fs)
ACLKB
48kHz (fs)
WCINB
64 CLKs
64 CLKs
ACLKA/B
WCINA/B
AIN1/2, AIN3/4
AIN5/6, AIN7/8
Figure 4-13: Serial Audio Input Configuration and Timing
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4.6.3 Audio Clock Phase Locked Loop
Figure 4-14 shows the configuration for deriving the 6.144MHz audio clock in AES/EBU
audio input mode. The GS1503B will internally synchronize the AES/EBU audio input to
the corresponding ACLK, using the clock extracted from the AES/EBU bi-phase mark
encoding. This configuration is not required for serial audio input modes.
6.144MHz (128 fs)
GS1503B
Y/C b / Cr [19:0]
VIN[19:0]
Audio Channels 1 & 2
AIN1/2
Audio Channels 3 & 4
AIN3/4
ACLKA
Audio Channels 5 & 6
PLLCNTA
Low
Pass
Filter
24.576MHz
Low
Pass
Filter
24.576MHz
VCXO
4
÷
AIN5/6
Audio Channels 7 & 8
AIN7/8
ACLKB
PLLCNTB
VCXO
4
÷
6.144MHz (128 fs)
Figure 4-14: Block Diagram of GS1503B Audio Clock PLL
4.6.4 Audio Signal Input Detection
The audio input signal detect registers will be set HIGH in AES/EBU audio mode when
the preamble of the audio input data is detected 3 times consecutively. In serial audio
input mode, the GS1503B will set the audio input signal detect registers HIGH when a
48kHz word clock is detected at the corresponding inputs. Audio channels 1 to 4 will be
set when WCINA is validated, and audio channels 5 to 8 when WCINB is validated. Host
Interface register 010h, bits 6-3, report the individual audio channels pairs detected.
Table 4-18: Register Settings
Name
Description
AUD7/8_DET
Ch7/8 Audio input signal detection (1:Detection)
010
6
–
0
AUD5/6_DET
Ch5/6 Audio input signal detection (1:Detection)
010
5
–
0
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Address
Bit
Setting
Default
30 of 90
Table 4-18: Register Settings
Name
Description
Address
Bit
Setting
Default
AUD3/4_DET
Ch3/4 Audio input signal detection (1:Detection)
010
4
–
0
AUD1/2_DET
Ch1/2 Audio input signal detection (1:Detection)
010
3
–
0
4.6.5 Audio Channel Status CRC Error Detection
In AES/EBU audio mode, the GS1503B will check the Channel Status CRC for errors. If
any Channel Status CRC errors are detected in an AES/EBU audio input channel pair, the
corresponding bit in Host Interface register 011h will be set HIGH. In serial audio input
mode, the CRC error flags are always set LOW.
Table 4-19: Register Settings
Name
Description
ACRC7/8_ERR
Ch7/8 Audio Channel Status CRC error detection
Address
Bit
Setting
Default
011
3
–
0
011
2
–
0
011
1
–
0
011
0
–
0
(1: Detection)
ACRC5/6_ERR
Ch5/6 Audio Channel Status CRC error detection
(1: Detection)
ACRC3/4_ERR
Ch3/4 Audio Channel Status CRC error detection
(1: Detection)
ACRC1/2_ERR
Ch1/2 Audio Channel Status CRC error detection
(1: Detection)
4.6.6 Audio Input Parity Error Detection
In AES/EBU audio mode, the GS1503B will check for Audio Parity errors. If any Audio
Parity errors are detected in an AES/EBU audio input channel pair, the corresponding bit
in Host Interface register 012h will be set HIGH. In serial audio input mode, the Audio
Parity error flags are always set LOW.
Table 4-20: Register Settings
Name
Description
AP7/8_ERR
Ch7/8 Audio parity error detection (1: Detection)
012
3
–
0
AP5/6_ERR
Ch5/6 Audio parity error detection (1: Detection)
012
2
–
0
AP3/4_ERR
Ch3/4 Audio parity error detection (1: Detection)
012
1
–
0
AP1/2_ERR
Ch1/2 Audio parity error detection (1: Detection)
012
0
–
0
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Address
Bit
Setting
Default
31 of 90
4.6.7 Audio Channel Status CRC Insert Function
When bits 7-4 of Host Interface register 011h are set HIGH, the GS1503B will
re-calculate the Channel Status CRC word for the corresponding audio input channel
pair. The re-calculated Channel Status CRC word is multiplexed into the audio data
packet as per SMPTE 299M. When bits 3-0 of Host Interface register 011h are set LOW,
the Channel Status CRC word is not updated and the existing Channel Status CRC word
will be multiplexed. In serial audio input mode, these registers should be set LOW.
Table 4-21: Register Settings
Name
Description
Address
Bit
Setting
Default
ACRC7/8_INS
Ch7/8 Audio Channel Status CRC insertion (1: Insertion)
011
7
1
0
ACRC5/6_INS
Ch5/6 Audio Channel Status CRC insertion (1: Insertion)
011
6
1
0
ACRC3/4_INS
Ch3/4 Audio Channel Status CRC insertion (1: Insertion)
011
5
1
0
ACRC1/2_INS
Ch1/2 Audio Channel Status CRC insertion (1: Insertion)
011
4
1
0
4.7 Audio Data Packets
4.7.1 Audio Data Packet Structure
Figure 4-15 shows the structure of the audio data packets as defined in SMPTE 299M.
The audio data packets are multiplexed into the Chroma channel of the video data
stream. Table 4-22 lists the description of the individual audio data packet words. Note
that the GS1503B will automatically generate certain audio data packet words.
CS
ECC5
ECC3
ECC4
ECC2
ECC0
ECC1
CH4
CH3
CH2
CH1
CLK
DC
DID
DBN
ADF
10-bit
User Data Words
ECC Protected
Figure 4-15: Audio Data Packet Structure
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Table 4-22: Audio Data Packet Word Descriptions
Name
No of Words
Description
Data
Auto-Generation
ADF
3
Ancillary Data Flag
000h
Yes
3FFh
3FFh
DID
1
Audio Group Data ID
2E7h
See Table 4-23 in
1E6h
Section 4.7.2
1E5h
2E4h
DBN
1
Data Block Number
Repeat 1-255
Yes
DC
1
Data Count
218h
Yes
CLK
2
Audio Clock Phase Data
–
Yes
CH1
4
Channel 1 audio data
–
CH2
4
Channel 2 audio data
–
CH3
4
Channel 3 audio data
–
CH4
4
Channel 4 audio data
–
ECC0-5
6
Error correction code for lower 8 bits of first 24
words
–
Yes
CS
1
Checksum. Calculates the sum of lower 9 bits of 22
words from DID
–
Yes
4.7.2 Audio Data Packet DID Setting
The audio group DID for audio input channels 1 to 4 (AIN1/2 and AIN3/4) is set in
DATAIDA[1:0] bits 1-0 of Host Interface register 014h. The audio group DID for audio
input channels 5 to 8 (AIN5/6 and AIN7/8) is set in DATAIDB[1:0] bits 3-2 of Host
Interface register 014h. Table 4-23 shows the 2-bit Host Interface setting for the
corresponding audio group DID.
When CASCADE is set LOW (external pin or register), the GS1503B will default to audio
groups 1 and 2, where AIN1/2 and AIN3/4 will be multiplexed with audio group 1 DID,
and AIN5/6 and AIN7/8 with audio group 2 DID.
Table 4-23: Audio Data Packet Group DID Host Interface Setting
Audio Group
10-bit Data
Host Interface Register Setting (2-bit)
1
2E7h
11b
2
1E6h
10b
3
1E5h
01b
4
2E4h
00b
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Table 4-24: Register Settings (CASCADE set LOW)
Name
Description
Address
Bit
Setting
DATAIDA [1-0]
Ch1-4 Audio data packet DID setting
014
1-0
DATAIDB [1-0]
Ch5-8 Audio data packet DID setting
014
3-2
See
Table 4-23
Default
11b
10b
When CASCADE is set HIGH (external pin or register), the GS1503B will default to audio
groups 3 and 4, where AIN1/2 and AIN3/4 will be multiplexed with audio group 3 DID,
and AIN5/6 and AIN7/8 with audio group 4 DID.
Table 4-25: Register Settings (CASCADE set HIGH)
Name
Description
Address
Bit
Setting
DATAIDA [1-0]
Ch1-4 Audio data packet DID setting
014
1-0
DATAIDB [1-0]
Ch5-8 Audio data packet DID setting
014
3-2
See
Table 4-23
Default
01b
00b
4.7.3 Audio Channel Multiplex Enable
Multiplexing of individual audio channels is enabled using the CHACT[7:0] bits 7-0 of
Host Interface register 013h. When set HIGH, the corresponding audio channel is
multiplexed into the audio data packet in the Chroma video data stream. CHACT7
corresponds to audio input channel 8 and CHACT0 corresponds to audio input channel
1. When all bits are set LOW, no audio data packets will be multiplexed and the GS1503B
will be in bypass mode.
Table 4-26: Register Settings
Name
Description
CHACT7
Ch8 multiplex enable (1: Enabled)
013
7
–
1
CHACT6
Ch7 multiplex enable (1: Enabled)
013
6
–
1
CHACT5
Ch6 multiplex enable (1: Enabled)
013
5
–
1
CHACT4
Ch5 multiplex enable (1: Enabled)
013
4
–
1
CHACT3
Ch4 multiplex enable (1: Enabled)
013
3
–
1
CHACT2
Ch3 multiplex enable (1: Enabled)
013
2
–
1
CHACT1
Ch2 multiplex enable (1: Enabled)
013
1
–
1
CHACT0
Ch1 multiplex enable (1: Enabled)
013
0
–
1
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Address
Bit
Setting
Default
34 of 90
4.8 Video Switching Line Setting
The video switching point for field 1 and field 2 can be configured via the GS1503B Host
Interface. The SW_LNA[12:0] register is used to configure the video switching line for
field 1, and SW_LNB[12:0] to set video switching line for field 2. In progressive format
video standards, only the SW_LNA[12:0] register is used. The default settings are line 7
for field 1 and line 569 for field 2 as defined in SMPTE 299M.
The GS1503B will not multiplex any audio data packets in the line immediately after the
video switching point. For example, with the default setting of line 7 field 1, there will be
no audio data packets in line 8. The next packets will appear on line 9. Audio control
packets will be multiplexed once per field, two lines after the video switching point (on
line 9, using the previous example). Arbitrary data packets will not be multiplexed in the
two lines following the video switching point .
NOTE: The SMPTE 299M standard defines the video switching point as lines 7 and 569.
If the SW_LNA[12:0] and SW_LNB[12:0] registers are programmed with values other
than lines 7 and 569, the output of the GS1503B is not guaranteed to be compatible with
all HD audio demultiplex systems. With non-SMPTE 299M compliant switch line
settings, the user should avoid inputting a video data stream to the GS1503B, which
already contains embedded audio data and control packets.
For reliable operation, non-SMPTE 299M compliant video data streams with embedded
audio should not be used in conjunction with the GS1503B in Multiplex Mode.
Table 4-27: Register Settings
Name
Description
SW_LNA[12:0]
Video Field 1 switching point setting
SW_LNB[12:0]
Video Field 2 switching point setting
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Address
Bit
004
4-0
005
7-0
002
4-0
003
7-0
Setting
Default
–
7d
–
569d
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4.9 Multiplex Cascade Mode
Two GS1503B devices can be cascaded in series to allow up to 16 channels of audio to
be multiplexed (only one device requires CASCADE to be set HIGH). Figure 4-16 shows
the cascade architecture for a 16-channel system. To configure the GS1503B for cascade
mode, the CASCADE external pin or CASCADE bit 7 of Host Interface register 014h is set
HIGH. When set HIGH, the GS1503B will default to audio groups 3 and 4. When set
LOW, the GS1503B will default to audio groups 1 and 2.
GS1503B
Y/Cb /Cr [19:0]
Audio
Group 1
Audio
Group 2
Audio Channels 1 & 2
Audio Channels 3 & 4
Audio Channels 5 & 6
Audio Channels 7 & 8
VIN[19:0]
GS1503B
Y/C b /Cr [19:0]
VOUT[19:0]
AIN1/2
Audio
Group 3
AIN3/4
AIN5/6
Audio
Group 4
AIN7/8
Audio Channels 9 & 10
Y/C b /C r [19:0]
VOUT[19:0]
VIN[19:0]
AIN1/2
Audio Channels 11 & 12
AIN3/4
Audio Channels 13 & 14
AIN5/6
Audio Channels 15 & 16
AIN7/8
+3.3V
CASCADE
CASCADE
Figure 4-16: Multiplexing 16 Channels of Audio using Cascade Architecture
Table 4-28: Register Settings
Name
Description
CASCADE
Cascade enable (1: Enabled)
Address
014
Bit
Setting
7
1
Default
0
When CASCADE is set LOW, the GS1503B will multiplex audio data and control packets
as shown in Figure 4-17 (NOTE: Only the Chroma channel of the video data stream is
shown). Any existing audio data or control packets will be deleted and replaced with
blanking data before the new packets are multiplexed. New packets are multiplexed
immediately after the two video line CRC words.
When CASCADE is set HIGH, the GS1503B will multiplex the audio data and control
packets immediately after the existing packets, as shown in Figure 4-18. Avoid
multiplexing new ancillary data packets with the same audio group DID as existing
packets.
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SAV
LN
CRC
EAV
Blank (200 h )
SAV
Audio
Group 2
Audio
Group 1
LN
CRC
EAV
Video Signal before GS1503B (no existing Audio Data Packets)
Blank (200h)
SAV
Audio
Group 2
(New)
Audio
Group 1
(New)
LN
CRC
EAV
Video Signal before GS1503B (with existing Audio Data Packets)
Blank (200h )
Video Signal after GS1503B Insertion of Audio Groups 1 & 2 (CASCADE = 0)
SAV
Audio
Group 2
Audio
Group 1
LN
CRC
EAV
Figure 4-17: Insertion of Audio Groups 1 & 2, without / with existing packets)
Blank (200h)
Blank (200 h)
SAV
Audio
Group 4
(New)
Audio
Group 3
(New)
Audio
Group 2
(Old)
Audio
Group 1
(Old)
LN
CRC
EAV
Video Signal before GS1503B (with existing Audio Data Packets)
Video Signal after GS1503B Insertion of Audio Groups 3 & 4 (CASCADE = 1)
Figure 4-18: Insertion of Audio Groups 3 & 4 in Cascade mode
The GS1503B assumes that the ancillary data space from the first blanking location to
the SAV contains no ancillary data packets. Existing ancillary data packets must be
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Blank (200 h)
SAV
Blank
(200h)
Audio
Group 2
Audio
Group 1
LN
CRC
EAV
contiguous from the beginning of the HANC space or the GS1503B will overwrite
existing packets with blanking before multiplexing new packets. See Figure 4-19.
Blank (200 h )
SAV
Audio
Group 4
(New)
Audio
Group 3
(New)
LN
CRC
EAV
Video Signal before GS1503B (with space between EAV and existing Audio Data Packets)
Video Signal after GS1503B Insertion of Audio Groups 3 & 4 (CASCADE = 1)
Figure 4-19: Insertion of Audio Groups 3 & 4 with space between EAV and
audio
4.10 Audio Control Packets
4.10.1 Audio Control Packet Structure
Figure 4-20 shows the structure of the audio control packet as defined in SMPTE 299M.
An audio control packet is multiplexed once per field in the Luma channel of the video
data stream. Table 4-29 lists descriptions of the individual audio control packet words.
The GS1503B will automatically generate certain audio control packet words.
CS
RSRV
DEL3-4
DEL1-2
ACT
AF
RATE
DC
DBN
DID
ADF
10-bit
User Data Words
Figure 4-20: Audio Control Packet Structure
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Table 4-29: Audio Control Packet Word Descriptions
Name
No of Words
Description
ADF
3
Ancillary Data Flag
Data
Auto-Generation
000h
Yes
3FFh
3FFh
DID
1
Audio Group Data ID
1E3h
2E2h
See Table 4-30 in
Section 5.8.2
2E1h
1E0h
DBN
1
Data Block Number
200h
Yes
DC
1
Data Count
10Bh
Yes
AF
1
Audio Frame Number
–
9-bit Host Interface
Setting
RATE
1
Sampling Frequency
–
4-bit Host Interface
Setting
ACT
1
Active Channel
–
CHACT[7:0] setting
DEL1-2
3
Ch1/2 Delay Data
–
26-bit Host Interface
setting
DEL3-4
3
Ch3/4 Delay Data
–
26-bit Host Interface
setting
RSRV
2
Reserved Words
200h
18-bit Host Interface
setting
CS
1
Checksum. Calculates
the sum of lower 9 bits
of 15 words from DID
–
Yes
4.10.2 Audio Control Packet DID Setting
To multiplex audio control packets for audio channels 1 to 4 (inputs AIN1/2 and AIN3/4),
the CTRONA bit 2 of Host Interface register 02Fh must be set HIGH. To multiplex audio
control packets for audio channels 5 to 8 (inputs AIN5/6 and AIN7/8), the CTRONB bit 2
of Host Interface register 020h must be set HIGH.
The audio control packet group DID for audio input channels 1 to 4 is set in CTRIDA[1:0]
bits 1-0 of Host Interface register 02Fh. The audio control packet group DID for audio
input channels 5 to 8 is set in CTRIDB[1:0] bits 3-2 of Host Interface register 020h.
Table 4-30 shows the 2-bit Host Interface setting for the corresponding audio control
packet group DID.
When CASCADE is set LOW (external pin or register), the GS1503B will default to audio
groups 1 and 2, where the audio control packet for AIN1/2 and AIN3/4 will be
multiplexed with group 1 DID, and AIN5/6 and AIN7/8 with group 2 DID.
Control packet data can be programmed via the corresponding registers in the Host
Interface.
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Table 4-30: Audio Control Packet Group DID Host Interface Settings
Audio Group
10-bit Data
Host Interface Register Setting (2-bit)
1
1E3h
11b
2
2E2h
10b
3
2E1h
01b
4
1E0h
00b
Table 4-31: Register Settings
Name
Description
Address
Bit
Setting
Default
CTRONA
Ch1-4 Audio control packet multiplex enable
(1: Enabled)
02F
2
1
1
CTRIDA[1:0]
Ch1-4 Audio control packet DID set
02F
1-0
See
Table 4-30
11b
AF_NOA[8:0]
Ch1-4 Audio frame number
030
0
–
0
031
7-0
Ch1-4 Sampling frequency data
032
3-1
–
0
Ch1-4 Synchronization
032
0
–
0
–
0
–
0
–
0
RATEA[2:0]
ASXA
(0:Synchronous; 1: Non-synchronous)
DEL1-2A[25:0]
DEL3-4A[25:0]
RSRVA[17:0]
Ch1/2 Delay data
Ch3/4 Delay data
Ch1-4 Reserved words
033
1-0
034
7-0
035
7-0
036
7-0
037
1-0
038
7-0
039
7-0
03A
7-0
03B
1-0
03C
7-0
03D
7-0
CTRONB
Ch5-8 Audio control packet multiplex enable
(1:Enabled)
020
2
1
1
CTRIDB[1:0]
Ch5-8 Audio control packet DID set
020
1-0
See
Table 4-30
10b
AF_NOB[8:0]
Ch5-8 Audio frame number
–
0
021
0
022
7-0
RATEB[2:0]
Ch5-8 Sampling frequency data
023
3-1
–
0
ASXB
Ch5-8 Synchronization
(0:Synchronous; 1: Non-synchronous)
023
0
–
0
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Table 4-31: Register Settings
Name
Description
DEL1-2B[25:0]
Ch5/6 Delay data
DEL3-4B[25:0]
Ch7/8 Delay data
RSRVB[17:0]
Ch5-8 Reserved words
Address
Bit
Setting
Default
–
0
–
0
–
0
024
1-0
025
7-0
026
7-0
027
7-0
028
1-0
029
7-0
02A
7-0
02B
7-0
02C
1-0
02D
7-0
02E
7-0
4.11 Arbitrary Data Packets
The GS1503B can multiplex arbitrary data packets according to SMPTE 291M. Typically,
this consists of linear time code (LTC), vertical interval time code (VITC) or other user
data, which is multiplexed once per video field. The GS1503B has two modes in which
arbitrary data can be multiplexed into the Luma channel of the video data stream. A
maximum of 255 user data words can be multiplexed in one packet. Figure 4-21 shows
the structure of the arbitrary data packet.
NOTE: Arbitrary data packets will not be multiplexed in the two lines following the
video switching point (see Video Switching Line Setting on page 35).
CS
UDW254[1FE]
UDW253[1FD]
UDW251[1FB]
UDW252[1FC]
UDW3[103]
UDW2[102]
UDW1[101]
DC
SDID
UDW0[100]
LSB
DID
Not b8
Parity bit
ADF
MSB
User Data Words
Contents set in Host Interface registers
Figure 4-21: Arbitrary Data Packet Structure
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4.11.1 Arbitrary Data Multiplexing In External Pin Mode
This is the default mode for multiplexing arbitrary data packets. The GS1503B will set
the PKTENO external pin HIGH when arbitrary data can be input to the device. Two
VCLK cycles after PKTENO goes HIGH, the user should set the PKTEN arbitrary packet
enable pin HIGH. Two VCLK cycles after PKTEN is set HIGH, arbitrary data can be input
at the PKT[7:0] bus. See Figure 4-22 for timing.
The user is required to enter the following arbitrary data: Data ID (DID), Secondary Data
ID (SDID), Data Count (DC) and User Data Words (UDW: maximum of 255), via the
PKT[7-0] pins. This GS1503B automatically generates the Ancillary Data Flag (ADF),
Checksum (CS) and bit 8 (Parity Bit) and bit 9 (Not bit 8).
The PKTENO pin will be set HIGH on all video lines except the two lines following the
video switching point. For example, with the default setting of line 7 field 1, PKTENO
will not be set HIGH on lines 8 and 9. The switching point is set in the SW_LNA[12:0] and
SW_LNB[12:0] Host Interface registers for field 1 and field 2 respectively. See Video
Switching Line Setting on page 35.
GS1503B
Y/C / C [19:0]
b r
VIN[19:0]
Arbitrary Data Packet Timing
PKTENO
Arbitrary Data Input Enable
PKTEN
Arbitrary Data
PKT[7:0]
2 CLKs
2 CLKs
2 CLKs
2 CLKs
VCLK
PKTENO
PKTEN
CS
UDW254
UDW253
UDW252
UDW251
UDW250
UDW2
UDW1
UDW0
DC
SDID
DID
ADF
ADF
Packet
ADF
Arbitrary
UDW3
Arbitrary Data
PKT[7:0]
Automatically generated by the GS1503B
Figure 4-22: Arbitrary Data Packet Input Timing Diagram
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4.11.2 Arbitrary Data Multiplexing in Host Interface Mode
To select this mode, set ARBITMODE bit 0 in Host Interface register 050h HIGH. In this
mode, the DID, SDID, DC and User Data Words must be programmed via the
corresponding Host Interface registers. Set the video line number for field 1 and field 2
in which the arbitrary data packets are to be multiplexed using the ARBITLINEA[11:0]
and ARBITLINEB[11:0] Host Interface registers respectively. The arbitrary data packet is
multiplexed when ARBITON bit 1 in Host Interface register 050h is set HIGH. ARBITON
should be set LOW during the programming of the arbitrary data packet in the Host
Interface.
ARBITLINEA[11:0] and ARBITLINEB[11:0] should not be set to the two line numbers
following the line number set in the SW_LNA[12:0] and SW_LNB[12:0] Host Interface
registers. For example, with the default setting of line 7 field 1, ARBITLINEA[11:0]
should not be set to line 8 or 9.
Table 4-32: Register Settings
Name
Description
ARBITON
Arbitrary packet multiplex enable (1: Enabled)
Address
Bit
Setting
Default
050
1
1
0
050
0
1
0
Valid only when ARBITMODE is HIGH
ARBITMODE
Arbitrary packet mode selection
(0: External pin mode; 1: Host mode)
ARBITDID[7-0]
Arbitrary packet DID setting
051
7-0
–
0
ARBITSDID[7-0]
Arbitrary packet SDID setting
052
7-0
–
0
ARBITDC[7-0]
Arbitrary packet DC setting
053
7-0
–
0
ARBITLINEA[11:0]
Field 1 multiplexing line
–
0
–
0
–
0
ARBITLINEB[11:0]
ARBITUDW
Field 2 multiplexing line
Arbitrary packet UDW setting
054
3-0
055
7-0
056
3-0
057
7-0
100-1FE
7-0
Table 4-33: Multiplex Mode Host Interface Registers
Control
Item
Video
Name
Description
Address
Bit
R/W
Default
VM_SEL
Video input format (external pin/internal
register) configuration select. When set LOW,
the video input format is configured via the
VM[3:0] pins. When set HIGH, the video input
format is configured via the "VM[3:0]" bits.
000
7
R/W
0
VIDEO_DET
Video signal detection flag. Set HIGH when 3
consecutive TRS are detected in the input video
signal.
000
6
R
0
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Table 4-33: Multiplex Mode Host Interface Registers (Continued)
Control
Item
Name
Description
Address
Bit
R/W
Default
CRC_ERR
Video input signal CRC error detection. Set
HIGH when a CRC error is detected in the input
video signal. This register is refreshed on every
video frame.
000
5
R
0
CRC_INS
Video CRC insertion. When set HIGH, the Luma
and Chroma line CRC words are re-calculated
and inserted into the output video signal.
000
4
R/W
1
VM[3:0]
Video input format selection. See Table 4-1.
Valid when "VM_SEL" is HIGH.
000
3-0
R/W
0
EXT_SEL
External EXTH/EXTF input select. When set
LOW, the EXTH and EXTF pins are configured
as outputs. When set HIGH, the GS1503B will
insert TRS and Line Numbers based on signals
input at the EXTH and EXTF pins.
001
3
R/W
0
Scramble processing bypass select. When set
HIGH, the internal scrambler and NRZ(I)
encoder is bypassed.
001
2
R/W
0
SCRBYPASS
NOTE: The status of the SCRBYPASS external
pin is not updated in this register. The value
programmed in this register is logical OR'd
with the SCRBYPASS external pin setting.
8BIT_SEL
8-bit input selection. When set HIGH, the
GS1503B will accept an 8-bit input video signal.
001
1
R/W
0
DSCBYPASS
Descramble process bypass select. When set
HIGH, the internal SMPTE 292M descrambler is
bypassed.
001
0
R/W
0
Video Field 2 switching line setting. Designates
the video switching point for field 2. The
default line number is 569, as defined by
SMPTE 299M.
002
4-0
R/W
569d
003
7-0
Video Field 1 switching line setting. Designates
the video switching point for field 1. The
default line number is 7, as defined by SMPTE
299M.
004
4-0
R/W
7d
005
7-0
CRC error accumulation. Reports the
accumulated number of CRC errors in one
video frame.
006
3-0
R
0
007
7-0
Not used.
008
7-5
–
0
Illegal code re-mapping select. When set HIGH,
input video words between 000-003 are
re-mapped to 004, and values between 3FC-3FF
are re-mapped to 3FB. Valid only when
"EXT_SEL" is set HIGH.
008
4
R/W
0
NOTE: The status of the DSCBYPASS external
pin is not updated in this register. The value
programmed in this register is logical OR'd
with the DSCBYPASS external pin setting.
SW_LNB[12:0]
SW_LNA[12:0]
CRC_CNT[11:0]
RSV
LIMIT_ON
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Table 4-33: Multiplex Mode Host Interface Registers (Continued)
Control
Item
Name
Description
Address
Bit
R/W
Default
VBLK_INS
Vertical blanking enable. When set HIGH, the
output video vertical blanking will be set to
040h for the Luma channel and 200h for the
Chroma channel.
008
3
R/W
0
HBLK_INS
Horizontal blanking enable. When set HIGH,
the output video horizontal blanking,
including TRS, line numbers and line CRC
words, will be set to 040h for the Luma channel
and 200h for the Chroma channel.
008
2
R/W
0
NOTE: If blanking of line numbers and TRS
words is required, LN_INS and TRS_INS must be
set LOW.
Audio
LN_INS
Line insertion enable. When set HIGH, the
GS1503B will insert line numbers into the video
data stream. When set LOW, existing line
numbers will remain in the output video
stream.
008
1
R/W
1
TRS_INS
TRS insertion enable. When set HIGH, the
GS1503B will insert TRS codes into the video
data stream. When set LOW, existing TRS codes
will remain in the output video stream.
008
0
R/W
1
AM_SEL
Audio input format (external pin/register)
configuration select. When set LOW, the audio
input format is configured via the AM[1:0] pins.
When set HIGH, the audio input format is
configured via the "AM[1:0]" bits.
010
7
R/W
0
AUD7/8_DET
Ch7/8 audio input signal detection. When set
HIGH, an audio signal has been detected at the
AIN7/8 input pin.
010
6
R
0
AUD5/6_DET
Ch5/6 audio input signal detection. When set
HIGH, an audio signal has been detected at the
AIN5/6 input pin.
010
5
R
0
AUD3/4_DET
Ch3/4 audio input signal detection. When set
HIGH, an audio signal has been detected at the
AIN3/4 input pin.
010
4
R
0
AUD1/2_DET
Ch1/2 audio input signal detection. When set
HIGH, an audio signal has been detected at the
AIN1/2 input pin.
010
3
R
0
Not used.
010
2
–
0
AM[1:0]
Audio input format select. See Table 4-16. Valid
when "AM_SEL" is HIGH.
010
1-0
R/W
0
ACRC7/8_INS
Ch7/8 audio Channel Status CRC insertion.
When set HIGH, the Ch7/8 audio input Channel
Status CRC is re-calculated before being
multiplexed into the Audio Data Packet. Valid
only when AES/EBU audio input format is
selected.
011
7
R/W
0
RSV
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Table 4-33: Multiplex Mode Host Interface Registers (Continued)
Control
Item
Name
Description
Address
Bit
R/W
Default
ACRC5/6_INS
Ch5/6 audio Channel Status CRC addition.
When set HIGH, the Ch5/6 audio input Channel
Status CRC is re-calculated before being
multiplexed into the Audio Data Packet. Valid
only when AES/EBU audio input format is
selected.
011
6
R/W
0
ACRC3/4_INS
Ch3/4 audio Channel Status CRC addition.
When set HIGH, the Ch3/4 audio input Channel
Status CRC is re-calculated before being
multiplexed into the Audio Data Packet. Valid
only when AES/EBU audio input format is
selected.
011
5
R/W
0
ACRC1/2_INS
Ch1/2 audio Channel Status CRC addition.
When set HIGH, the Ch1/2 audio input Channel
Status CRC is re-calculated before being
multiplexed into the Audio Data Packet. Valid
only when AES/EBU audio input format is
selected.
011
4
R/W
0
ACS7/8_ERR
Ch7/8 audio Channel Status error detection.
When set HIGH, a Channel Status CRC error has
been detected in the Ch7/8 audio input. Valid
only when AES/EBU audio input format is
selected.
011
3
R
0
ACS5/6_ERR
Ch5/6 audio Channel Status error detection.
When set HIGH, a Channel Status CRC error has
been detected in the Ch5/6 audio input. Valid
only when AES/EBU audio input format is
selected.
011
2
R
0
ACS3/4_ERR
Ch3/4 audio Channel Status error detection.
When set HIGH, a Channel Status CRC error has
been detected in the Ch3/4 audio input. Valid
only when AES/EBU audio input format is
selected.
011
1
R
0
ACS1/2_ERR
Ch1/2 audio Channel Status error detection.
When set HIGH, a Channel Status CRC error has
been detected in the Ch1/2 audio input. Valid
only when AES/EBU audio input format is
selected.
011
0
R
0
AP7/8_ERR
Ch7/8 audio parity error detection. When set
HIGH, an audio parity error has been detected
in the Ch7/8 audio input. Valid only when
AES/EBU audio input format is selected.
012
3
R
0
AP5/6_ERR
Ch5/6 audio parity error detection. When set
HIGH, an audio parity error has been detected
in the Ch5/6 audio input. Valid only when
AES/EBU audio input format is selected.
012
2
R
0
AP3/4_ERR
Ch3/4 audio parity error detection. When set
HIGH, an audio parity error has been detected
in the Ch3/4 audio input. Valid only when
AES/EBU audio input format is selected.
012
1
R
0
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Table 4-33: Multiplex Mode Host Interface Registers (Continued)
Control
Item
Audio
Channel
Status
Block
Name
Address
Bit
R/W
Default
AP1/2_ERR
Ch1/2 audio parity error detection. When set
HIGH, an audio parity error has been detected
in the Ch1/2 audio input. Valid only when
AES/EBU audio input format is selected.
012
0
R
0
AUDIO_CS[7:0]
Audio Channel Status set. Valid in Serial Audio
Input modes. Used to enter the 23 8-bit bytes
of the Audio Channel Status Block, as defined
in AES3-1992.
058
7-0
R/W
See
:
AUDIO_CS
[183:176]
Audio
Data
Packet
Description
:
:
06E
7-0
Table 4-34
NOTE: The CRC byte is generated internally by
the GS1503B.
CHACT[7-0]
Audio channel multiplex enable. When set
HIGH, the corresponding audio channel is
multiplexed into the Chroma video data
stream. "CHACT[7]" corresponds to audio input
channel 8 and "CHACT[0]" corresponds to
audio input channel 1. When all bits are set
LOW, no audio data packets will be
multiplexed and the GS1503B will be in bypass
mode.
013
7-0
R/W
FFh
CASCADE
Cascade select. When set HIGH, the GS1503B
will default to audio groups 3 and 4. When set
LOW, the GS1503B will default to audio groups
1 and 2.
014
7
R/W
0
Not used.
014
6
–
–
Ch5-8 audio mute enable. When set HIGH, the
multiplexed audio packets for audio channels 5
to 8 are forced to zero.
014
5
R/W
0
014
4
R/W
0
014
3-2
R/W
10b
NOTE: The status of the CASCADE external pin
is not updated in this register. The value
programmed in this register is logical OR'd
with the CASCADE external pin setting.
RSV
AMUTEB
NOTE: The status of the MUTE external pin is
not updated in this register. The value
programmed in this register is logical OR'd
with the MUTE external pin setting.
AMUTEA
Ch1-4 audio mute enable. When set HIGH, the
multiplexed audio packets for audio channels 1
to 4 are forced to zero.
NOTE: The status of the MUTE external pin is
not updated in this register. The value
programmed in this register is logical OR'd
with the MUTE external pin setting.
DATAIDB[1:0]
Ch5-8 audio group DID setting. Designates the
audio group DID for audio channels 5 to 8.
See Table 4-23. When CASCADE (external pin
or register) is set LOW, the default setting is
audio group 2. When CASCADE is set HIGH, the
default setting is audio group 4.
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Table 4-33: Multiplex Mode Host Interface Registers (Continued)
Control
Item
Name
DATAIDA[1:0]
Audio
Control
Packet
Description
Address
Bit
R/W
Default
Ch1-4 audio group DID setting. Designates the
audio group DID for audio channels 1 to 4.
See Table 4-23. When CASCADE (external pin
or register) is set LOW, the default setting is
audio group 1. When CASCADE is set HIGH, the
default setting is audio group 3.
014
1-0
R/W
11b
Not used.
020
7-3
–
0
Ch5-8 audio control packet multiplex enable.
When set HIGH, the audio control packets for
audio channels 5 to 8 will be multiplexed into
the Luma channel of the video data stream.
020
2
R/W
1
CTRIDB[1:0]
Ch5-8 audio control packet DID setting.
Designates the audio control packet DID for
audio channels 5 to 8. See Table 4-30. The
default setting is audio group 2.
020
1-0
R/W
10b
AF_NOB[8:0]
Ch5-8 audio frame number. Designates the
audio frame number for audio channels 5 to 8.
Will be multiplexed into the audio control
packet as per SMPTE 299M.
021
0
R/W
0
022
7-0
RATEB[2:0]
Ch5-8 sampling frequency set. Designates the
audio sampling frequency for audio channels 5
to 8. Will be multiplexed into the RATE word of
the audio control packet as per SMPTE 299M.
The default setting is 48kHz.
023
3-1
R/W
0
ASXB
Ch5-8 synchronization set. When set HIGH, the
"asx" bit of the audio control packet RATE
word designates audio channels 5 to 8 as
asynchronous, as per SMPTE 299M. When set
LOW, the "asx" bit of the audio control packet
RATE word designates synchronous audio
(default setting).
023
0
R/W
0
DEL1-2B[25:0]
Ch5/6 delay data. Designates the accumulated
audio processing delay relative to video for
audio channels 5 and 6. Will be multiplexed
into the audio control packet as per SMPTE
299M.
024
1-0
R/W
0
025
7-0
026
7-0
027
7-0
Ch7/8 delay data. Designates the accumulated
audio processing delay relative to video for
audio channels 7 and 8. Will be multiplexed
into the audio control packet as per SMPTE
299M.
028
1-0
R/W
0
R/W
0
RSV
CTRONB
DEL3-4B[25:0]
RSRVB[17:0]
Ch5-8 reserve words. Designates the value set
in the RSRV words of the audio control packet
for audio channels 5 to 8, as per SMPTE 299M.
NOTE: As these words are reserved for future
use, they should be set to zero.
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029
7-0
02A
7-0
02B
7-0
02C
1-0
02D
7-0
02E
7-0
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Table 4-33: Multiplex Mode Host Interface Registers (Continued)
Control
Item
Name
RSV
Description
Bit
R/W
Default
Not used.
02F
7-3
–
0
Ch1-4 audio control packet multiplex enable.
When set HIGH, the audio control packets for
audio channels 1 to 4 will be multiplexed into
the Luma channel of the video data stream.
02F
2
R/W
1
CTRIDA[1:0]
Ch1-4 audio control packet DID setting.
Designates the audio control packet DID for
audio channels 1 to 4. See Table 4-30. The
default setting is audio group 1.
02F
1-0
R/W
11b
AF_NOA[8:0]
Ch1-4 audio frame number. Designates the
audio frame number for audio channels 5 to 8.
Will be multiplexed into the audio control
packet as per SMPTE 299M.
030
0
R/W
0
031
7-0
RATEA[2:0]
Ch1-4 sampling frequency set. Designates the
audio sampling frequency for audio channels 1
to 4. Will be multiplexed into the RATE word of
the audio control packet as per SMPTE 299M.
The default setting is 48kHz.
02F
3-1
R/W
0
ASXA
Ch1-4 synchronization set. When set HIGH, the
"asx" bit of the audio control packet RATE
word designates audio channels 1 to 4 as
asynchronous, as per SMPTE 299M. When set
LOW, the "asx" bit of the audio control packet
RATE word designates synchronous audio
(default setting).
02F
0
R/W
0
DEL1-2A[25:0]
Ch1/2 delay data. Designates the accumulated
audio processing delay relative to video for
audio channels 1 and 2. Will be multiplexed
into the audio control packet as per SMPTE
299M.
033
1-0
R/W
0
034
7-0
035
7-0
036
7-0
Ch3/4 delay data. Designates the accumulated
audio processing delay relative to video for
audio channels 3 and 4. Will be multiplexed
into the audio control packet as per SMPTE
299M.
037
1-0
R/W
0
038
7-0
039
7-0
03A
7-0
03B
1-0
R/W
0
03C
7-0
03D
7-0
050
1
R/W
0
CTRONA
DEL3-4A[25:0]
RSRVA[17:0]
Ch1-4 reserve words. Designates the value set
in the RSRV words of the audio control packet
for audio channels 1 to 4, as per SMPTE 299M.
NOTE: As these words are reserved for future
use, they should be set to zero.
Arbitrary
Data
Packet
Address
ARBITON
Arbitrary data packet multiplex. Valid only
when "ARBITMODE" is HIGH. When set HIGH,
arbitrary data packets will be multiplexed into
the Luma video data stream using the Host
Interface register settings.
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Table 4-33: Multiplex Mode Host Interface Registers (Continued)
Control
Item
Name
Description
Address
Bit
R/W
Default
ARBITMODE
Arbitrary packet mode select. When set HIGH,
arbitrary data packets are multiplexed using
the Host Interface register settings. When set
LOW, arbitrary data packets are multiplexed
using the external pin inputs.
050
0
R/W
0
ARBITDID[7:0]
Arbitrary packet Data ID setting. Designates
the 8 LSBs of the arbitrary data packet DID
word. The 2 MSBs are internally generated.
"ARBITDID[7]" is the MSB and "ARBITDID[0]" is
the LSB. Valid only when "ARBITMODE" is
HIGH.
051
7-0
R/W
0
ARBITSDID[7:0]
Arbitrary packet Secondary Data ID setting.
Designates the 8 LSBs of the arbitrary data
packet secondary DID word. The 2 MSBs are
internally generated. "ARBITSDID[7]" is the
MSB and "ARBITSDID[0]" is the LSB. Valid only
when "ARBITMODE" is HIGH.
052
7-0
R/W
0
ARBITDC[7:0]
Arbitrary packet DC setting. Designates the 8
LSBs of the arbitrary data packet Data Count
word. The 2 MSBs are internally generated.
"ARBITDC[7]" is the MSB and "ARBITDC[0]" is
the LSB. Valid only when "ARBITMODE" is
HIGH.
053
7-0
R/W
0
ARBITLINEB[11:0]
Field 2 arbitrary packet multiplex line number
setting. Designates the field 2 video line in
which the arbitrary data packets will be
multiplexed. Valid only when "ARBITMODE" is
HIGH.
054
3-0
R/W
0
055
7-0
Field 1 arbitrary packet multiplex line number
setting. Designates the field 1 video line in
which the arbitrary data packets will be
multiplexed. Valid only when "ARBITMODE" is
HIGH.
056
3-0
R/W
0
057
7-0
Arbitrary packet User Data Word set.
Designates the 8 LSBs for each of the 255
arbitrary packet User Data Words. The 2 MSBs
are internally generated. Valid only when
"ARBITMODE" is HIGH.
100
7-0
R/W
0
:
:
1FE
7-0
ARBITLINEA[11:0]
ARBITUDW0
:
ARBITUDW254
Table 4-34: Audio Channel Status Default Values
Address
Value
Channel Status
058
85
Professional; Valid Audio; No Emphasis (manual
override disabled); 48kHz Sampling Frequency (manual
override disabled).
059
08
Two-Channel Mode (manual override disabled).
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Table 4-34: Audio Channel Status Default Values
Address
Value
Channel Status
05A
2C
Maximum Audio Sample Word Length is 24bits;
Encoded Audio Word Length is 24-bit.
Others
00
–
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5. Demultiplex Mode
5.1 Functional Overview
The GS1503B HD Embedded Audio CODEC fully supports the demultiplexing of Audio
Data Packets, Audio Control Packets and Arbitrary Data Packets as per SMPTE 291M
and 299M. The device can be configured to operate with all video standards defined in
SMPTE 292M, levels A through M. The GS1503B also supports the 1080/24PsF, 25PsF
and 30PsF video formats as described in SMPTE RP211.
The video input format can be one of the following configurations:
•
10-bit Y and Cb/Cr input with TRS and Line Numbers
•
20-bit scrambled input
The video output format can be one of the following configurations:
•
20-bit scrambled output
•
10-bit Y and Cb/Cr output
Up to a maximum of 8 channels of 48kHz digital audio can be demultiplexed per device.
The audio output format can be selected as either AES/EBU, or one of two serial audio
data output modes. A maximum of 16 channels of audio can be demultiplexed by
cascading two devices in parallel.
Audio control packets, as defined in SMPTE 299M, can also be demultiplexed to obtain
information about the nature of the embedded audio data. The contents of the audio
control packet are stored in registers of the Host Interface.
The GS1503B will also demultiplex arbitrary data packets as defined in SMPTE 291M.
The arbitrary data packets can serve as an auxiliary data signal for proprietary
applications. The GS1503B can be configured to demultiplex arbitrary data packets and
output them at dedicated external pins or via the Host Interface registers. Up to a
maximum of 255 8-bit words can be demultiplexed (excluding Ancillary Data Flags and
Checksum).
To use the GS1503B in Demultiplex Mode, set the MUX/DEMUX external pin HIGH.
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5.2 Video Standard
The video standard is selected from the VM[3:0] external pins or VM[3:0] bits 3-0 in Host
Interface register 000h. To configure the video standard via the Host Interface, VM_SEL
bit 7 in Host Interface register 000h must be set HIGH. The GS1503B will default to the
VM[3:0] external pin setting. The supported video standards are listed in Table 5-1.
Table 5-1: Supported Video Standards
VM [3:0]
Input Format
Reference SMPTE Document
SMPTE 292M Level
1110b
1035i (30 & 30/1.001 Hz)
260M
A, B
1100b
1080i (25 Hz)
295M
C
1000b
1080i/1080sF (30 & 30/1.001 Hz)
274M, RP211
D, E
1010b
1080i/1080sF (25 Hz)
274M, RP211
F
1111b
1080sF (24 & 24/1.001 Hz)
RP211
0010b
1080p (30 & 30/1.001 Hz)
274M
G, H
0100b
1080p (25 Hz)
274M
I
0110b
1080p (24 & 24/1.001 Hz)
274M
J, K
0000b
720p (60 & 60/1.001 Hz)
296M
L, M
0001b
720p (30 & 30/1.001 Hz)
296M
0011b
720p (50 Hz)
296M
0101b
720p (25 Hz)
296M
0111b
720p (24 & 24/1.001 Hz)
296M
All other settings are reserved
Table 5-2: Register Settings
Name
VM_SEL
Description
0: External pin select
Address
Bit
000
7
000
3-0
Setting
Default
1
0
See
0
1: Register select
VM[3:0]
Video formal selection (VM[3] is MSB)
Table 5-1
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5.3 Video Input Format
5.3.1 20-bit Scrambled Input
GS1503B
Y/C b / Cr [19:0]
VIN[19:0]
DSCBYPASS
Figure 5-1: 20-bit Scrambled Input Configuration
Table 5-3: Register Settings (Default Mode)
Name
EXT_SEL
Description
0: EXTH/EXTF output select
Address
Bit
Setting
Default
001
3
0
0
001
1
0
0
001
0
0
0
1: EXTH/EXTF input select
8BIT_SEL
0: 10-bit mode select
1: 8-bit mode select
DSCBYPASS
0: Descrambling enabled
1: Bypass descrambling
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5.3.2 10-bit Y and Cb/Cr Input with TRS and Line Numbers
GS1503B
Y[9:0]
VIN[19:10]
C b/ C r[9:0]
VIN[9:0]
EXTF
+3.3V
EXTH
DSCBYPASS
Vn
V0
000
XYZ
000
3FF
CRC0
CRC1
LN1
8
3
LN0
000
XYZ
000
3FF
Y, C b / Cr
10-bit
0
Figure 5-2: 10-bit Y and Cb/Cr Input with TRS and Line Numbers Configuration
Video
4 VCLK
EXTH
EXTF
Figure 5-3: Video Input Format (10-bit with TRS and Line Numbers)
Table 5-4: Register Settings
Name
EXT_SEL
Description
0: EXTH/EXTF output select
Address
Bit
Setting
Default
001
3
0
0
001
1
0
0
001
0
1
0
1: EXTH/EXTF input select
8BIT_SEL
0: 10-bit mode select
1: 8-bit mode select
DSCBYPASS
0: Descrambling enabled
1: Bypass descrambling
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5.4 Video Output Format
5.4.1 10-bit Y and Cb/Cr Output
GS1503B
Y[9:0]
VOUT[19:10]
VOUT[9:0]
C b / C r [9:0]
+3.3V
SCRBYPASS
Figure 5-4: 10-bit Y and Cb/Cr Output Configuration
Table 5-5: Register Settings
Name
Description
Address
SCRBYPASS
0: SMPTE 292M scrambling enabled
001
Bit
2
Setting
1
Default
0
1: Bypass SMPTE 292M scrambling
5.4.2 20-bit Scrambled Output
GS1503B
VOUT[19:0]
Y/C b / Cr [19:0]
SCRBYPASS
Figure 5-5: 20-bit Scrambled Output Configuration
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Table 5-6: Register Settings (Default Mode)
Name
SCRBYPASS
Description
0: SMPTE 292M scrambling enabled
Address
001
Bit
2
Setting
0
Default
0
1: Bypass SMPTE 292M scrambling
5.5 Video Data Processing
5.5.1 Video Signal Input Detection
The GS1503B will set the VIDEO_DET external pin HIGH when three consecutive TRS
are detected in the input video signal. Also, the VIDEO_DET bit of Host Interface register
000h is set HIGH.
Table 5-7: Register Settings
Name
Description
VIDEO_DET
Video input signal detection (1: Detection)
Address
000
Bit
6
Setting
–
Default
0
5.5.2 Video Input CRC Error Detection
The GS1503B will set the CRC_ERR external pin HIGH when a CRC error is detected in
the input video signal. Also, the CRC_ERR bit 5 of Host Interface register 000h is set
HIGH. The number of CRC errors accumulated in one video frame can be read form
CRC_CNT[11:0] in Host Interface registers 006h and 007h.
Table 5-8: Register Settings
Name
Description
CRC_ERR
Video input signal CRC error detection (1: Detection)
000
5
–
0
CRC_CNT[11:0]
Video input signal CRC error accumulation in 1 video
frame
006
3-0
–
0
007
7-0
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Address
Bit
Setting
Default
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5.5.3 Video Output CRC Insertion
When the CRC_INS bit 4 of Host Interface register 000h is set HIGH, the GS1503B will
re-calculate the video line CRC words. The re-calculated CRC words are inserted in the
video output signal. When CRC_INS is set LOW, the line CRC words are not updated and
existing CRC words at the input of the device will be output unchanged.
Table 5-9: Register Settings
Name
Description
CRC_INS
Video line CRC insertion (1: Insertion)
Address
Bit
000
Setting
4
1
Default
1
5.5.4 Input Blanking
When VBLK_INS bit 3 of Host Interface register 008h is set HIGH, the input video vertical
blanking will be set to 040h for the Luma channel and 200h for the Chroma channel.
When HBLK_INS bit 2 of Host Interface register 008h is set HIGH, the input video
horizontal blanking will be set to 040h for the Luma channel and 200h for the Chroma
channel. The TRS, line number and CRC words will also be set to blanking values.
The blanking function is performed at the output of the GS1503B video data stream. If
the HBLK_INS bit is set HIGH, any embedded audio or control packets will be replaced
with blanking codes. The GS1503B will demultiplex data contained in the packets, prior
to the blanking function, and output at the corresponding pins.
Table 5-10: Register Settings
Name
Description
Address
Bit
Setting
Default
VBLK_INS
Input vertical blanking (1: Enabled)
008
3
1
0
HBLK_INS
Input horizontal blanking (1: Enabled)
008
2
1
0
5.5.5 Line Number Insertion
When LN_INS bit 1 of Host Interface register 008h is set HIGH, the GS1503B will insert
line numbers into the video data stream. When set LOW, existing line numbers will
remain in the output video stream.
Table 5-11: Register Settings
Name
Description
LN_INS
Line number insertion (1: Enabled)
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Address
008
Bit
Setting
1
1
Default
1
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5.5.6 TRS Word Insertion
When TRS_INS bit 0 of Host Interface register 008h is set HIGH, the GS1503B will insert
TRS codes into the video data stream. When set LOW, existing TRS codes will remain in
the output video stream.
Table 5-12: Register Settings
Name
Description
TRS_INS
TRS word insertion (1: Enabled)
Address
Bit
008
Setting
0
1
Default
1
5.6 Audio Data Processing
5.6.1 Digital Audio Output Format
The GS1503B has two audio output formats, AES/EBU digital audio output and serial
output, as listed in Table 5-13. The serial audio output can be formatted in the following
two modes. See Figure 5-6:
•
24-bit Left Justified; MSB first
•
24-bit Right Justified; MSB last
The audio output format is configured using the AM[1:0] external pins or via AM[1:0] bits
1-0 in Host Interface register 010h. To configure the audio output format via the Host
Interface, AM_SEL bit 7 in Host Interface register 010h must be set HIGH. The GS1503B
will default to the AM[1:0] external pin setting.
NOTE: When configured in AES/EBU audio mode, the GS1503B will not output a 48kHz
(fs) word clock at the WCOUTA and WCOUTB pins.
Table 5-13: Audio Output Formats
AM[1:0]
Audio Output Format
0
Serial audio output: 24-bit Left Justified; MSB first
1
Serial audio output: 24-bit Right Justified; MSB last
2
AES/EBU audio output
Table 5-14: Register Settings
Name
AM_SEL
Description
0: External pin setting
Address
Bit
Setting
Default
010
7
1
0
010
1-0
See
0
1: Register setting
AM[1:0]
Audio output format selection (AM[1] is MSB)
Table 5-13
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Channel 1
WCOUTA/WCOUTB
Channel 2
MSB
MODE0
MSB
23
0
23
0
LSB
0
MODE2
(AES/EBU)
LSB
0
MODE1
23
3 4
Sync
Preamble
2728293031 0
24-bit Audio Sample Word
0
23
3 4
2728293031
Sync
V U C P Preamble
24-bit Audio Sample Word
V UC P
Validity Bit
User Data Bit
Channel Status Bit
Parity Bit
Figure 5-6: Audio Output Formats
5.6.2 Digital Audio Output Timing
5.6.2.1 AES/EBU Format Output
A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs.
ACLKA is used to clock AES/EBU digital audio signal for channels 1 to 4 (AOUT1/2 and
AOUT3/4). ACLKB is used to clock AES/EBU digital audio signal for channels 5 to 8
(AOUT5/6 and AOUT7/8). In AES/EBU output mode, the audio word clock inputs
WCINB and WCINB should be grounded. See Figure 5-7 for timing.
The user can access the Audio Channel Status Block information via the
AUDIO_CS[183:0] bits in Host Interface registers 058h to 06Eh. To read the Audio
Channel Status information, the CS_MODE bit 3 of Host Interface register 06Fh should
be set HIGH. The embedded audio channel from which the Channel Status information
is to be extracted is set in the CH_SEL[2:0] bits 2-0 of Host Interface register 06Fh. The
CH_SEL[2:0] setting for audio channel 1 is 000b, through to 111b for channel 8. The
CS_RQST bit must be set HIGH to begin the process of extracting the Audio Channel
Status information. Once extracted, the GS1503B will set CS_WEND bit HIGH and the
user can access the data for Host Interface registers 058h to 06Eh.
When CS_MODE is set LOW, the Audio Channel Status information in the AES/EBU
audio outputs will be replaced with data programmed in the AUDIO_CS[183:0] bits of
Host Interface registers 058h to 06Eh.
Table 5-15: Register Settings
Name
CS_WEND
Description
Audio Channel Status write flag
Address
Bit
Setting
Default
06F
5
–
0
06F
4
1
0
(1: Data ready)
CS_RQST
Audio Channel Status request
(1: enable)
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Table 5-15: Register Settings
Name
Description
CS_MODE
Address
0: Audio Channel Status replace
Bit
Setting
Default
06F
3
1
0
06F
2-0
–
000b
1: Audio Channel Status demultiplex
CH_SEL[2:0]
Audio Channel Status select
GS1503B
Y/C b / Cr [19:0]
VIN[19:0]
AOUT1/2
AOUT3/4
6.144MHz (128 fs)
Audio Channels 1 & 2
Audio Channels 3 & 4
ACLKA
AOUT5/6
AOUT7/8
6.144MHz (128 fs)
Audio Channels 5 & 6
Audio Channels 7 & 8
ACLKB
6.144MHz
ACLKA/B
AOUT1/2, AOUT3/4
AOUT5/6, AOUT7/8
Figure 5-7: AES/EBU Audio Output Configuration and Timing
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5.6.2.2 Serial Audio Output Modes
A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs. An
audio word clock at 48kHz (fs) will be output at the WCOUTA and WCOUTB external
pins, as shown in Figure 5-8.
The user can access the Audio Channel Status Block information via the
AUDIO_CS[183:0] bits in Host Interface registers 058h to 06Eh. To read the Audio
Channel Status information, the CS_MODE bit 3 of Host Interface register 06Fh should
be set HIGH. The embedded audio channel from which the Channel Status information
is to be extracted is set in the CH_SEL[2:0] bits 2-0 of Host Interface register 06Fh. The
CH_SEL[2:0] setting for audio channel 1 is 000b, through to 111b for channel 8.
The CS_RQST bit must be set HIGH to begin the process of extracting the Audio Channel
Status information. Once extracted, the GS1503B will set CS_WEND bit HIGH and the
user can access the data for Host Interface registers 058h to 06Eh.
When DEC_MODE (external pin or register setting) is set LOW, the audio word clock
inputs WCINB and WCINB should be grounded.
GS1503B
Y/C b / Cr [19:0]
VIN[19:0]
AOUT1/2
AOUT3/4
6.144MHz (128 fs)
WCOUTA
ACLKA
AOUT5/6
AOUT7/8
6.144MHz (128 fs)
WCOUTB
ACLKB
64 CLKs
Audio Channels 1 & 2
Audio Channels 3 & 4
48kHz (fs)
Audio Channels 5 & 6
Audio Channels 7 & 8
48kHz (fs)
64 CLKs
ACLKA/B
WCOUTA/B
AOUT1/2, AOUT3/4
AOUT5/6, AOUT7/8
Figure 5-8: Serial Audio Output Configuration and Timing
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5.6.3 Audio Clock Phase Locked Loop
Figure 5-9 shows the configuration for deriving the 6.144MHz audio clock in AES/EBU
and serial audio output modes. The GS1503B will internally synchronize the audio
output to the corresponding ACLK. This configuration is not required when DEC_MODE
is set HIGH.
6.144MHz (128 fs)
GS1503B
Y/C b / C r [19:0]
VIN[19:0]
AOUT1/2
AOUT3/4
Audio Channels 1 & 2
Audio Channels 3 & 4
Low
ACLKA
PLLCNTA
Pass
Filter
AOUT5/6
AOUT7/8
PLLCNTB
4
÷
Audio Channels 5 & 6
Audio Channels 7 & 8
Low
ACLKB
VCXO
24.576MHz
Pass
Filter
VCXO
24.576MHz
4
÷
6.144MHz (128 fs)
Figure 5-9: Block Diagram of GS1503B Audio Clock PLL
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5.6.4 Audio Data Packet Detection
The audio data packet detect registers will be set HIGH when a corresponding audio
group DID has been detected in the Chroma channel of the input video stream. Host
Interface register 013h, bits 7-4, report the individual audio groups detected.
Table 5-16: Register Settings
Name
Description
Address
Bit
Setting
Default
ADPG4_DET
Audio group 4 data packet detection
(1:Detection)
013
7
–
0
ADPG3_DET
Audio group 3 data packet detection
(1:Detection)
013
6
–
0
ADPG2_DET
Audio group 2 data packet detection
(1:Detection)
013
5
–
0
ADPG1_DET
Audio group 1 data packet detection
(1:Detection)
013
4
–
0
5.6.5 ECC Error Detection & Correction
The GS1503B performs BCH(31,25) forward error detection and correction as described
in SMPTE 299M. The error correction for audio data packets with audio group DID set in
DATAIDA[1:0] is activated when ECCA_ON bit 0 of Host Interface register 013h is set
HIGH. Similarly, error correction for audio data packets with audio group DID set in
DATAIDB[1:0] is activated when ECCB_ON bit 1 of Host Interface register 013h is set
HIGH
When a one-bit error is detected in a bit array of the ECC protected region of the audio
data packet with audio group DID set in DATAIDA[1:0], ECCA_ERR bit 1 in Host
Interface register 015h is set HIGH. When a one-bit error is detected in the ECC
protected region of the audio data packet with audio group DID set in DATAIDB[1:0], the
ECCB_ERR bit 5 in Host Interface register 015h is set HIGH. In both cases, the ERROR
external pin will also be set HIGH.
A bit array is defined as all 24 bits of bit 0. The next bit array is all 24 bits of bit 1, and so
on through to bit 7. Up to 8 bits in error can be corrected, providing each bit error is in a
different bit array. When there are two bits in error in the same 24-bit array, the errors
will be detected, but not corrected. When there are more than two bits in error in a single
bit array, the errors will not be detected or corrected.
The number of audio data packets corrected in one video frame will be reported in the
corresponding Host Interface registers CORRECTA[11:0] and CORRECTB[11:0]. The
GS1503B will also report the number of audio data packets which could not be corrected
in one video frame in the corresponding Host Interface registers NO_CORRECTA[11:0] and
NO_CORRECTB[11:0].
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Table 5-17: Register Settings
Name
Description
ECCB_ERR
Ch5-8 Audio data packet ECC error detection
Address
Bit
Setting
Default
015
5
–
0
015
1
–
0
016
3-0
–
0
017
7-0
–
0
–
0
–
0
(1: Detection)
ECCA_ERR
Ch1-4 Audio data packet ECC error detection
(1: Detection)
CORRECTB[11:0]
NO_CORRECTB[11:0]
CORRECTA[11:0]
NO_CORRECTA[11:0]
Ch5-8 correctable packets in one video frame
Ch5-8 un-correctable packets in one video frame
Ch1-4 correctable packets in one video frame
Ch5-8 un-correctable packets in one video frame
018
3-0
019
7-0
01A
3-0
01B
7-0
01C
3-0
01D
7-0
ECCB_ON
Ch5-8 Audio data packet error correction (1: ON)
013
1
1
1
ECCA_ON
Ch1-4 Audio data packet error correction (1: ON)
013
0
1
1
5.6.6 Audio Data Packet Error Detection
When the 1-255 count sequence in the Data Block Number (DBN) word of audio data
packets with audio group DID set in DATAIDA[1:0] is discontinuous, the DBNA_ERR bit
3 of Host Interface register 015h will be set HIGH. When the1-255 count sequence in the
DBN word of audio data packets with audio group DID set in DATAIDB[1:0] is
discontinuous, the DBNB_ERR bit 7 of Host Interface register 015h will be set HIGH.
The GS1503B will check the parity (bit 8) for the CLK, CH1-4 and ECC0-5 words in the
embedded audio data packets. When a parity bit error is detected in audio data packets
with audio group DID set in DATAIDA[1:0], the ADPB8A_ERR bit 2 of Host Interface
register 015h will be set HIGH. When a parity bit error is detected in audio data packets
with audio group DID set in DATAIDB[1:0], the ADPB8B_ERR bit 6 of Host Interface
register 015h will be set HIGH.
The GS1503B will re-calculate the audio data packets Checksum and compare against
the embedded Checksum word. When a Checksum error is detected in audio data
packets with audio group DID set in DATAIDA[1:0], the ADPCSA_ERR bit 0 of Host
Interface register 015h will be set HIGH. When a Checksum error is detected in audio
data packets with audio group DID set in DATAIDB[1:0], the ADPCSB_ERR bit 4 of Host
Interface register 015h will be set HIGH.
When any of the above errors are detected, the ERROR external pin will also be set
HIGH.
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Table 5-18: Register Settings
Name
Description
Address
Bit
Setting
Default
DBNB_ERR
Ch5-8 Audio data packet DBN error detection
(1:Detection)
015
7
–
0
ADPB8B_ERR
Ch5-8 Audio data packet bit8 error detection
(1:Detection)
015
6
–
0
ADPCSB_ERR
Ch5-8 Audio data packet CS error detection
(1:Detection)
015
4
–
0
DBNA_ERR
Ch1-4 Audio data packet DBN error detection
(1:Detection)
015
3
–
0
ADPB8A_ERR
Ch1-4 Audio data packet bit8 error detection
(1:Detection)
015
2
–
0
ADPCSA_ERR
Ch1-4 Audio data packet CS error detection
(1:Detection)
015
0
–
0
Address
Bit
Setting
Default
014
1-0
See
11b
5.6.7 Audio Data Packet DID Setting
The audio group DID for audio output channels 1 to 4 (AOUT1/2 and AOUT3/4) is set in
DATAIDA[1:0] bits 1-0 of Host Interface register 014h. The audio group DID for audio
output channels 5 to 8 (AOUT5/6 and AOUT7/8) is set in DATAIDB[1:0] bits 3-2 of Host
Interface register 014h. Table 5-19 shows the 2-bit Host Interface setting for the
corresponding audio group DID.
When CASCADE is set LOW (external pin or register), the GS1503B will default to audio
groups 1 and 2, where AOUT1/2 and AOUT3/4 will be demultiplexed from audio data
packets with group 1 DID, and AOUT5/6 and AOUT7/8 will be demultiplexed from
audio data packets with group 2 DID.
Table 5-19: Audio Group DID Host Interface Settings
Audio Group
10-bit Data
Host Interface Register Setting (2-bit)
1
2E7h
11b
2
1E6h
10b
3
1E5h
01b
4
2E4h
00b
Table 5-20: Register Settings (CASCADE set LOW)
Name
Description
DATAIDA[1-0]
Ch1-4 Audio data packet DID setting
DATAIDB[1-0]
Ch5-8 Audio data packet DID setting
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014
3-2
Table 5-19
10b
66 of 90
When CASCADE is set HIGH (external pin or register), the GS1503B will default to audio
groups 3 and 4, where AOUT1/2 and AOUT3/4 will be demultiplexed from audio data
packets with group 3 DID, and AOUT5/6 and AOUT7/8 will be demultiplexed from
audio data packets with group 4 DID.
Table 5-21: Register Settings (CASCADE set HIGH)
Name
Description
DATAIDA[1-0]
Ch1-4 Audio data packet DID setting
DATAIDB[1-0]
Ch5-8 Audio data packet DID setting
Address
Bit
014
1-0
014
3-2
Setting
Default
See
01b
Table 5-19
00b
5.7 Demultiplex Cascade Mode
Two GS1503B devices can be cascaded in parallel to allow up to 16 channels of audio to
be demultiplexed (only one device requires CASCADE to be set HIGH). Figure 5-10
shows the cascade architecture for a 16-channel system. To configure the GS1503B for
cascade mode, the CASCADE external pin or CASCADE bit 7 of Host Interface register
014h is set HIGH. When set HIGH, the GS1503B will default to audio groups 3 and 4.
When set LOW, the GS1503B will default to audio groups 1 and 2.
GS1503B
Y/C b /Cr [19:0]
VOUT[19:0]
VIN[19:0]
AOUT1/2
AOUT3/4
AOUT5/6
AOUT7/8
Y/C b /Cr [19:0]
Audio Channels 1 & 2
Audio Channels 3 & 4
Audio Channels 5 & 6
Audio Channels 7 & 8
Audio
Group 1
Audio
Group 2
CASCADE
GS1503B
VIN[19:0]
VOUT[19:0]
AOUT1/2
AOUT3/4
AOUT5/6
AOUT7/8
Y/C b /Cr [19:0]
Audio Channels 9 & 10
Audio Channels 11 & 12
Audio Channels 13 & 14
Audio Channels 15 & 16
Audio
Group 3
Audio
Group 4
+3.3V
CASCADE
Figure 5-10: Demultiplexing 16 Channels of Audio using Cascade Architecture
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Table 5-22: Register Settings
Name
Description
CASCADE
Cascade enable (1: Enabled)
Address
Bit
Setting
Default
014
7
1
0
5.8 Audio Control Packets
5.8.1 Audio Control Packet Detection
The audio control packet detect registers will be set HIGH when a corresponding audio
group DID has been detected in the Luma channel of the input video stream. Host
Interface register 020h, bits 7-4, report the individual audio groups detected.
Table 5-23: Register Settings
Name
Description
Address
Bit
Setting
Default
ACPG4_DET
Audio group 4 control packet detection (1:
Detection)
020
7
–
0
ACPG3_DET
Audio group 3 control packet detection (1:
Detection)
020
6
–
0
ACPG2_DET
Audio group 2 control packet detection (1:
Detection)
020
5
–
0
ACPG1_DET
Audio group 1 control packet detection (1:
Detection)
020
4
–
0
5.8.2 Audio Control Packet DID Setting
To demultiplex audio control packets for audio channels 1 to 4 (AOUT1/2 and
AOUT3/4), the CTRONA bit 2 of Host Interface register 02Fh is set HIGH. To demultiplex
audio control packets for audio channels 5 to 8 (AOUT5/6 and AOUT7/8), the CTRONB
bit 2 of Host Interface register 020h is set HIGH.
The audio control packet group DID for audio output channels 1 to 4 is set in
CTRIDA[1:0] bits 1-0 of Host Interface register 02Fh. The audio control packet group DID
for audio output channels 5 to 8 is set in CTRIDB[1:0] bits 3-2 of Host Interface register
020h. Table 5-24 shows the 2-bit Host Interface setting for the corresponding audio
control packet group DID.
When CASCADE is set LOW (external pin or register), the GS1503B will default to audio
groups 1 and 2, where audio control packet data for channels 1 to 4 will be
demultiplexed from packets with group 1 DID, and audio control packet data for
channels 5 to 8 will be demultiplexed from packets with group 2 DID.
Control packet data is accessible via the corresponding registers in the Host Interface.
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Table 5-24: Audio Control Packet Group DID Host Interface Settings
Audio Group
10-bit Data
Host Interface Register Setting (2-bit)
1
1E3h
11b
2
2E2h
10b
3
2E1h
01b
4
1E0h
00b
Table 5-25: Register Settings
Name
CTRONA
Description
Ch1-4 Audio control packet demultiplex enable
Address
Bit
Setting
Default
02F
2
1
1
(1: Enabled)
CTRIDA[1:0]
Ch1-4 Audio control packet DID set
02F
1-0
See
Table 5-24
11b
AF_NOA[8:0]
Ch1-4 Audio frame number
030
0
–
0
031
7-0
Ch1-4 Sampling frequency data
032
3-1
–
0
Ch1-4 Synchronization
032
0
–
0
033
1-0
–
0
034
7-0
035
7-0
036
7-0
–
0
–
0
RATEA[2:0]
ASXA
(0: Synchronous; 1: Non-synchronous)
DEL1-2A[25:0]
DEL3-4A[25:0]
RSRVA[17:0]
CTRONB
Ch1/2 Delay data
Ch3/4 Delay data
Ch1-4 Reserved words
Ch5-8 Audio control packet demultiplex enable
037
1-0
038
7-0
039
7-0
03A
7-0
03B
1-0
03C
7-0
03D
7-0
020
2
1
1
020
1-0
See
Table 5-24
10b
–
0
–
0
(1: Enabled)
CTRIDB[1:0]
Ch5-8 Audio control packet DID set
AF_NOB[8:0]
Ch5-8 Audio frame number
RATEB[2:0]
Ch5-8 Sampling frequency data
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021
0
022
7-0
023
3-1
69 of 90
Table 5-25: Register Settings
Name
Description
ASXB
Ch5-8 Synchronization
Address
Bit
Setting
Default
023
0
–
0
024
1-0
–
0
025
7-0
026
7-0
027
7-0
–
0
–
0
(0: Synchronous; 1: Non-synchronous)
DEL1-2B[25:0]
Ch5/6 Delay data
DEL3-4B[25:0]
Ch7/8 Delay data
RSRVB[17:0]
Ch5-8 Reserved words
028
1-0
029
7-0
02A
7-0
02B
7-0
02C
1-0
02D
7-0
02E
7-0
5.9 Arbitrary Data Packets
The GS1503B can demultiplex arbitrary data packets according to SMPTE 291M.
Typically, arbitrary data packets consist of linear time code (LTC), vertical interval time
code (VITC) or other user data, which is multiplexed once per video field. The GS1503B
has two modes in which arbitrary data can be demultiplexed from the Luma channel of
the video data stream. A maximum of 255 user data words can be demultiplexed.
Figure 5-11 shows the structure of the arbitrary data packet.
CS
UDW254[1FE]
UDW253[1FD]
UDW251[1FB]
UDW252[1FC]
UDW3[103]
UDW2[102]
UDW0[100]
DC
SDID
UDW1[101]
LSB
DID
Not b8
Parity bit
ADF
MSB
User Data Words
Contents available in Host Interface registers
Figure 5-11: Arbitrary Data Packet Structure
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5.9.1 Arbitrary Data Demultiplexing in External Pin Mode
This is the default mode for demultiplexing arbitrary data packets. The GS1503B will set
the PKTEN external pin HIGH before arbitrary data will be output. Two VCLK cycles
after PKTEN goes HIGH, arbitrary data is output on the PKT[7:0] bus. See Figure 5-12 for
timing.
The following arbitrary data is output on the PKT[7:0] bus: Data ID (DID), Secondary Data
ID (SDID), Data Count (DC) and User Data Words (UDW: up to a maximum of 255 words).
GS1503B
Y/C b / Cr [19:0]
VIN[19:0]
PKTEN
Arbitrary Data Output Enable
Arbitrary Data
PKT[7:0]
2 CLKs
2 CLKs
VCLK
PKTEN
CS
UDW254
UDW253
UDW252
UDW251
UDW250
UDW2
UDW1
UDW0
DC
SDID
DID
ADF
ADF
Packet
ADF
Arbitrary
UDW3
Arbitrary Data
PKT[7:0]
Figure 5-12: Arbitrary Data Packet Output Timing Diagram
5.9.2 Arbitrary Data Demultiplexing in Host Interface Mode
To select this mode, set ARBITMODE bit 0 in Host Interface register 050h HIGH. In this
mode, the DID, SDID, DC and User Data Words must be programmed in the
corresponding Host Interface registers. Set the video line number for field 1 and field 2
from which the arbitrary data packets are to be demultiplexed using the
ARBITLINEA[11:0] and ARBITLINEB[11:0] Host Interface registers respectively. The
arbitrary data packet is demultiplexed when the ARBITON bit 1 in Host Interface
register 050h is set HIGH. ARBITON should be set LOW when reading the arbitrary data
packet User Data Words from the ARBITUDW Host Interface registers.
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Table 5-26: Register Settings
Name
ARBITON
Description
Arbitrary packet demultiplex enable (1: Enabled)
Address
Bit
Setting
Default
050
1
1
0
050
0
1
0
Valid only when ARBITMODE is HIGH
ARBITMODE
Arbitrary packet mode selection
(0: External pin mode; 1: Host mode)
ARBITDID[7-0]
Arbitrary packet DID setting
051
7-0
–-
0
ARBITSDID[7-0]
Arbitrary packet SDID setting
052
7-0
–
0
ARBITDC[7-0]
Arbitrary packet DC setting
053
7-0
–
0
ARBITLINEA[11:0]
Field 1 multiplexing line
–
0
–
0
–
0
ARBITLINEB[11:0]
ARBITUDW
Field 2 multiplexing line
Arbitrary packet UDW
054
3-0
055
7-0
056
3-0
057
7-0
100-1FE
7-0
5.10 Ancillary Data Deletion
The GS1503B can be configured to delete the embedded ancillary data packets, after
demultiplexing. There are two modes for ancillary data deletion.
5.10.1 Entire Ancillary Data Deletion
When the ANCI external pin or ANCI bit 1 of Host Interface register 040h is set HIGH, all
ancillary data packets in both the Luma and Chroma channel of the input video stream
are deleted. The data is replaced with blanking values 040h in the Luma channel and
200h in the Chroma channel. The DEL_SEL bit 0 of Host Interface register 040h must be
set LOW.
5.10.2 Audio Group Designation Ancillary Data Deletion
When the ANCI bit 1 of Host Interface register 040h is set HIGH, and DEL_SEL bit 0 of
Host Interface register 040h is HIGH, only audio data and control packets which are
designated in Host Interface registers 041h will be deleted. To delete the arbitrary data
packets, the corresponding DID must be set in the NDID[7:0] Host Interface register
042h.
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Table 5-27: Register Settings
Name
Description
ANCI
DEL_SEL
Address
Bit
Setting
Default
Ancillary data packet delete (1: Deletion enabled)
040
1
1
0
Ancillary data packet delete mode select
040
0
1
0
(0: Entire data delete; 1: Group designated data
delete)
ADPG4_DEL
Audio group 4 data packet delete (1: Delete)
041
7
–
0
ADPG3_DEL
Audio group 3 data packet delete (1: Delete)
041
6
–
0
ADPG2_DEL
Audio group 2 data packet delete (1: Delete)
041
5
–
0
ADPG1_DEL
Audio group 1 data packet delete (1: Delete)
041
4
–
0
ACPG4_DEL
Audio group 4 control packet delete (1: Delete)
041
3
–
0
ACPG3_DEL
Audio group 3 control packet delete (1: Delete)
041
2
–
0
ACPG2_DEL
Audio group 2 control packet delete (1: Delete)
041
1
–
0
ACPG1_DEL
Audio group 1 control packet delete (1: Delete)
041
0
–
0
NDID[7:0]
Arbitrary packet DID delete setting
042
7-0
–
0
5.11 Demultiplex Mode With Word Clock Input
Some commercially available HD audio embedding modules do not encode the audio
word clock phase information correctly in the CLK words of the audio data packet. If this
clock information is not correctly encoded, the GS1503B will not output the audio data
correctly. Also, the GS1503B will be unable to reproduce the 48kHz audio word clock (fs)
at the WCOUTA and WCOUTB pins in serial audio output modes.
If the GS1503B is to be used in conjunction with a HD audio module, which encodes
audio clock phase information incorrectly, the DEC_MODE external pin or DECMODE
bit 2 of Host Interface register 01Eh must be set HIGH. When HIGH, an audio word clock
synchronous to the original word clock used for embedding must be input at the WCINA
and WCINB pins. Figure 5-13 shows a system example.
When the embedded clock phase data for audio channel 1 to 4 is detected as being in
error, the MUXERRA bit 0 of Host Interface register 01Eh will be set HIGH. Similarly,
when the embedded clock phase data for audio channel 5 to 8 is detected as being in
error, the MUXERRB bit 1 of Host Interface register 01Eh will be set HIGH.
Table 5-28: Register Settings
Name
DECMODE
Description
Demultiplex Mode with word clock input enable
Address
Bit
Setting
Default
01E
2
1
0
(1: Enabled)
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Table 5-28: Register Settings
Name
Description
Address
Bit
Setting
Default
MUXERRB
Ch5-8 embedded clock phase information error detect
(1: Detected)
01E
1
–
0
MUXERRA
Ch1-4 embedded clock phase information error detect
(1: Detected)
01E
0
–
0
HD Audio
Embedding
GS1503B
Module
Y/C b / C r [19:0]
Audio Channels 1 & 2
Audio Channels 3 & 4
48kHz (fs)
Audio Channels 5 & 6
Audio Channels 7 & 8
48kHz (fs)
VOUT[19:0]
VIN[19:0]
AIN1/2
AOUT1/2
AIN3/4
AOUT3/4
WCINA
Y/C b /Cr [19:0]
Audio Channels 1 & 2
Audio Channels 3 & 4
WCINA
AIN5/6
AIN7/8
AOUT5/6
WCINA
WCINA
AOUT7/8
Audio Channels 5 & 6
Audio Channels 7 & 8
+3.3V
DEC_MODE
MUX/DEMUX
Figure 5-13: Demultiplex Mode with 48kHz Word Clock Input System Example
Figure 5-14 shows the timing relationship between the audio word clock inputs and
word clock outputs when the GS1503B is configured to serial audio output mode.
1 CLK
ACLKA/B
WCINA/B
WCOUTA/B
Figure 5-14: WCINA/B Input to WCOUTA/B Output Timing Diagram
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Table 5-29: Demultiplex Mode Host Interface Registers
Control
Item
Name
Description
Address
Bit
R/W
Default
Video
VM_SEL
Video input format (external pin/internal
register) configuration select. When set LOW, the
video input format is configured via the VM[3:0]
pins.
When set HIGH, the video input
format is configured via the "VM[3:0]" bits.
000
7
R/W
0
VIDEO_DET
Video signal detection flag. Set HIGH when 3
consecutive TRS are detected in the input video
signal.
000
6
R
0
CRC_ERR
Video input signal CRC error detection. Set HIGH
when a CRC error is detected in the input video
signal. This register is refreshed on every video
frame.
000
5
R
0
CRC_INS
Video CRC insertion. When set HIGH, the Luma
and Chroma line CRC words are re-calculated and
inserted into the output video signal.
000
4
R/W
1
VM[3:0]
Video input format selection. See Table 5-1. Valid
when "VM_SEL" is HIGH.
000
3-0
R/W
0
EXT_SEL
External EXTH/EXTF input select. When set LOW,
the EXTH and EXTF pins are configured as
outputs. When set HIGH, the GS1503B will insert
TRS and Line Numbers based on signals input at
the EXTH and EXTF pins.
001
3
R/W
0
SCRBYPASS
Scramble processing bypass select.
When set HIGH, the internal scrambler and NRZ(I)
encoder is bypassed.
001
2
R/W
0
NOTE: The status of the SCRBYPASS external pin
is not updated in this register. The value
programmed in this register is logical OR'd with
the SCRBYPASS external pin setting.
8BIT_SEL
8-bit input selection. When set HIGH, the
GS1503B will accept an 8-bit input video signal.
001
1
R/W
0
DSCBYPASS
Descramble process bypass select.
When set HIGH, the internal SMPTE 292M
descrambler is bypassed.
001
0
R/W
0
CRC error accumulation. Reports the
accumulated number of CRC errors in one video
frame.
006
3-0
R
0
007
7-0
RSV
Not used.
008
7-4
R/W
VBLK_INS
Vertical blanking enable. When set HIGH, the
output video vertical blanking will be set to 040h
for the Luma channel and 200h for the Chroma
channel.
008
3
R/W
NOTE: The status of the DSCBYPASS external pin
is not updated in this register. The value
programmed in this register is logical OR'd with
the DSCBYPASS external pin setting.
CRC_CNT[11:0]
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Table 5-29: Demultiplex Mode Host Interface Registers (Continued)
Control
Item
Name
Description
HBLK_INS
Horizontal blanking enable. When set HIGH, the
output video horizontal blanking, including TRS,
line numbers and line CRC words, will be set to
040h for the Luma channel and 200h for the
Chroma channel.
Address
Bit
008
2
R/W
R/W
Default
0
NOTE: If blanking of line numbers and TRS words
is required, LN_INS and TRS_INS must be set LOW.
Audio
LN_INS
Line insertion enable. When set HIGH, the
GS1503B will insert line numbers into the video
data stream. When set LOW, existing line
numbers will remain in the output video stream.
008
1
R/W
1
TRS_INS
TRS insertion enable. When set HIGH, the
GS1503B will insert TRS codes into the video data
stream. When set LOW, existing TRS codes will
remain in the output video stream.
008
0
R/W
1
AM_SEL
Audio input format (external pin/register)
configuration select. When set LOW, the audio
input format is configured via the AM[1:0] pins.
When set HIGH, the audio input format is
configured via the "AM[1:0]" bits.
010
7
R/W
0
RSV
Not used.
010
6-2
–
0
AM[1:0]
Audio input format select. See Table 5-13. Valid
when "AM_SEL" is HIGH.
010
1-0
R/W
0
RSV
Not used.
01E
7-3
–
0
DECMODE
Demultiplex Mode select. When set HIGH, the
GS1503B requires a 48kHz word clock input at
WCINA and WCINB. This word clock must be
synchronous to the word clock used to embed
the audio data. The embedded clock information
in the audio data packet will be ignored.
01E
2
R/W
0
See Section 5.11.
NOTE: The status of the DEC_MODE external pin
is not updated in this register. The value
programmed in this register is logical OR'd with
the DEC_MODE external pin setting.
MUXERRB
Ch5-8 audio sample clock error. When set HIGH,
the GS1503B is unable to recover the audio clock
phase data in the embedded audio data packet
for audio channels 5 to 8. See Section 5.11.
01E
1
R
0
MUXERRA
Ch1-4 audio sample clock error. When set HIGH,
the GS1503B is unable to recover the audio clock
phase data in the embedded audio data packet
for audio channels 1 to 4. See Section 5.11.
01E
0
R
0
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Table 5-29: Demultiplex Mode Host Interface Registers (Continued)
Control
Item
Name
Description
Audio
Channel
Status
AUDIO_CS[7:0]
Audio Channel Status. When "CS_MODE" is set
HIGH, the 23 8-bit bytes of the Audio Channel
Status Block, as defined in AES3-1992, are
available in these registers. Valid in both AES/EBU
and serial audio modes.
Block
:
AUDIO_CS
[183:176]
Address
Bit
R/W
Default
058
7-0
R
0
:
:
06E
7-0
When "CS_MODE" is set LOW, the Audio Channel
Status information in the AES/EBU audio outputs
will be replaced with data programmed in these
registers. Valid only in AES/EBU audio mode.
RSV
Not used
06F
7-6
–
0
CS_WEND
Audio Channel Status write flag. When set HIGH,
indicates that the audio channel status
information has been written into the Host
Interface registers 058h to 06Eh and can be read
by the user. Valid only when "CS_MODE" is set
HIGH.
06F
5
R
0
CS_RQST
Audio Channel Status request. When set HIGH,
the GS1503B will read and store the Audio
Channel Status information from the audio
channel set in Host Interface register
"CH_SEL[2:0]". Valid only when "CS_MODE" is set
HIGH.
06F
4
R/W
0
CS_MODE
Audio Channel Status mode. When set HIGH, the
user can access the embedded Audio Channel
Status information from the Host Interface
registers 058h to 06Eh. Valid in both AES/EBU and
serial audio modes.
06F
3
R/W
0
R/W
000b
When set LOW, the Audio Channel Status
information for all audio outputs will be replaced
with data programmed in Host Interface registers
058h - 06Eh. Valid only in AES/EBU audio mode.
Audio Data
Packet
CH_SEL[2:0]
Audio Channel Status select. Designates the
embedded audio channel from which the Audio
Channel Status information will be
demultiplexed. The setting 000b represent audio
channel 1, through to 111b for channel 8. Valid
only when "CS_MODE" is set HIGH.
06F
2-0
ADPG4_DET
Audio group 4 data packet detect. When set
HIGH, audio data packets with group 4 DID have
been detected in the incoming Chroma video
data stream.
013
7
R
0
013
6
R
0
NOTE: Once this bit has been set, it will remain
set until a device reset is performed.
ADPG3_DET
Audio group 3 data packet detect. When set
HIGH, audio data packets with group 3 DID have
been detected in the incoming Chroma video
data stream.
NOTE: Once this bit has been set, it will remain
set until a device reset is performed.
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Table 5-29: Demultiplex Mode Host Interface Registers (Continued)
Control
Item
Name
Description
ADPG2_DET
Audio group 2 data packet detect. When set
HIGH, audio data packets with group 2 DID have
been detected in the incoming Chroma video
data stream.
Address
Bit
R/W
Default
013
5
R
0
013
4
R
0
NOTE: Once this bit has been set, it will remain
set until a device reset is performed.
ADPG1_DET
Audio group 1 data packet detect. When set
HIGH, audio data packets with group 1 DID have
been detected in the incoming Chroma video
data stream.
NOTE: Once this bit has been set, it will remain
set until a device reset is performed.
RSV
Not used.
013
3-2
–
0
ECCB_ON
Ch5-8 error correction enable. When set HIGH,
the GS1503B will perform error correction on
audio data packets for channels 5 to 8, based on
the six ECC words.
013
1
R/W
1
ECCA_ON
Ch1-4 error correction enable. When set HIGH,
the GS1503B will perform error correction on
audio data packets for channels 1 to 4, based on
the six ECC words.
013
0
R/W
1
CASCADE
Cascade select. When set HIGH, the GS1503B will
default to audio groups 3 and 4. When set LOW,
the GS1503B will default to audio groups 1 and 2.
014
7
R/W
0
NOTE: The status of the CASCADE external pin is
not updated in this register. The value
programmed in this register is logical OR'd with
the CASCADE external pin setting.
RSV
Not used.
014
6
–
0
AMUTEB
Ch5-8 audio mute enable. When set HIGH, the
multiplexed audio packets for audio channels 5
to 8 are forced to zero.
014
5
R/W
0
014
4
R/W
0
NOTE: The status of the MUTE external pin is not
updated in this register. The value programmed
in this register is logical OR'd with the MUTE
external pin setting.
AMUTEA
Ch1-4 audio mute enable. When set HIGH, the
multiplexed audio packets for audio channels 1
to 4 are forced to zero.
NOTE: The status of the MUTE external pin is not
updated in this register. The value programmed
in this register is logical OR'd with the MUTE
external pin setting.
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Table 5-29: Demultiplex Mode Host Interface Registers (Continued)
Control
Item
Name
Description
Address
Bit
R/W
Default
DATAIDB[1:0]
Ch5-8 audio group DID setting. Designates the
audio group DID for audio channels 5 to 8. See
Table 5-19. When CASCADE (external pin or
register) is set LOW, the default setting is audio
group 2. When CASCADE is set HIGH, the default
setting is audio group 4.
014
3-2
R/W
10b
DATAIDA[1:0]
Ch1-4 audio group DID setting. Designates the
audio group DID for audio channels 1 to 4. See
Table 5-19. When CASCADE (external pin or
register) is set LOW, the default setting is audio
group 1. When CASCADE is set HIGH, the default
setting is audio group 3.
014
1-0
R/W
11b
DBNB_ERR
Ch5-8 audio data packet DBN error. When set
HIGH, a Data Block Number error has been
detected in the audio data packet for audio
channels 5 to 8.
015
7
R
0
ADPB8B_ERR
Ch5-8 audio data packet 'bit 8' error. When set
HIGH, a 'bit 8' error has been detected in the
audio data packet for audio channels 5 to 8.
015
6
R
0
ECCB_ERR
Ch5-8 audio data packet error. When set HIGH,
an error has been detected in the audio data
packet for audio channels 5 to 8, based on the six
ECC words.
015
5
R
0
ADPCSB_ERR
Ch5-8 audio data packet CS error. When set
HIGH, a Checksum error has been detected with
the audio data packet for audio channels 5 to 8.
015
4
R
0
DBNA_ERR
Ch1-4 audio data packet DBN error.
When set HIGH, a Data Block Number error has
been detected in the audio data packet for audio
channels 1 to 4.
015
3
R
0
ADPB8A_ERR
Ch1-4 audio data packet 'bit 8' error.
When set HIGH, a 'bit 8' error has been detected
in the audio data packet for audio channels 1 to
4.
015
2
R
0
ECCA_ERR
Ch1-4 audio data packet error. When set HIGH,
an error has been detected in the audio data
packet for audio channels 1 to 4, based on the six
ECC words.
015
1
R
0
ADPCSA_ERR
Ch1-4 audio data packet CS error. When set
HIGH, a Checksum error has been detected with
the audio data packet for audio channels 1 to 4.
015
0
R
0
CORRECTB
Ch5-8 ECC correctable packets. Designates the
number of audio data packets for channels 5 to 8
that have been corrected in one video frame
using the BCH forward error correction system.
016
3-0
R
0
017
7-0
[11:0]
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Table 5-29: Demultiplex Mode Host Interface Registers (Continued)
Control
Item
Name
Description
NO_CORRECTB
[11:0]
CORRECTA
[11:0]
NO_CORRECTA
[11:0]
Audio
Control
Packet
Address
Bit
R/W
Default
Ch5-8 ECC un-correctable packets. Designates the
number of audio data packets for channels 5 to 8
that could not be corrected in one video frame
using the BCH forward error correction system.
018
3-0
R
0
019
7-0
Ch1-4 ECC correctable packets. Designates the
number of audio data packets for channels 1 to 4
that have been corrected in one video frame
using the BCH forward error correction system.
01A
3-0
R
0
01B
7-0
Ch1-4 ECC un-correctable packets. Designates the
number of audio data packets for channels 1 to 4
that could not be corrected in one video frame
using the BCH forward error correction system.
01C
3-0
R
0
01D
7-0
ACPG4_DET
Audio group 4 control packet detect. When set
HIGH, audio control packets with group 4 DID
have been detected in the incoming Luma video
data stream.
020
7
R
0
ACPG3_DET
Audio group 3 control packet detect. When set
HIGH, audio control packets with group 3 DID
have been detected in the incoming Luma video
data stream.
020
6
R
0
ACPG2_DET
Audio group 2 control packet detect. When set
HIGH, audio control packets with group 2 DID
have been detected in the incoming Luma video
data stream.
020
5
R
0
ACPG1_DET
Audio group 1 control packet detect. When set
HIGH, audio control packets with group 1 DID
have been detected in the incoming Luma video
data stream.
020
4
R
0
RSV
Not used.
020
3
–
0
CTRONB
Ch5-8 audio control packet demultiplex enable.
When set HIGH, the audio control packets in the
Luma channel of the video data stream for audio
channels 5 to 8 will be demultiplexed.
020
2
R/W
1
CTRIDB[1:0]
Ch5-8 audio control packet DID setting.
Designates the audio control packet DID for
audio channels 5 to 8. See Table 5-24. The default
setting is audio group 2.
020
1-0
R/W
10b
AF_NOB[8:0]
Ch5-8 audio frame number. Designates the audio
frame number for audio channels 5 to 8.
021
0
R/W
0
022
7-0
Ch5-8 sampling frequency. Designates the audio
sampling frequency for audio channels 5 to 8,
taken from the RATE word of the audio control
packet as defined in SMPTE 299M.
023
3-1
R/W
0
RATEB[2:0]
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Table 5-29: Demultiplex Mode Host Interface Registers (Continued)
Control
Item
Name
Description
ASXB
DEL1-2B[25:0]
DEL3-4B[25:0]
RSRVB[17:0]
Address
Bit
R/W
Default
Ch5-8 synchronization. When set HIGH, the "asx"
bit of the audio control packet RATE word
designates audio channels 5 to 8 as
asynchronous, as per SMPTE 299M. When set
LOW, the "asx" bit of the audio control packet
RATE word designates synchronous audio.
023
0
R/W
0
Ch5/6 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 5 and 6.
024
1-0
R/W
0
025
7-0
026
7-0
027
7-0
028
1-0
R/W
0
029
7-0
02A
7-0
02B
7-0
R/W
0
Ch7/8 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 7 and 8.
Ch5-8 reserve words. Designates the value set in
the RSRV words of the audio control packet for
audio channels 5 to 8, as per SMPTE 299M.
02C
1-0
02D
7-0
02E
7-0
RSV
Not used.
02F
7-3
–
0
CTRONA
Ch1-4 audio control packet demultiplex enable.
When set HIGH, the audio control packets in the
Luma channel of the video data stream for audio
channels 1 to 4 will be demultiplexed.
02F
2
R/W
1
CTRIDA[1:0]
Ch1-4 audio control packet DID setting.
Designates the audio control packet DID for
audio channels 1 to 4. See Table 5-24. The default
setting is audio group 1.
02F
1-0
R/W
11b
AF_NOA[8:0]
Ch1-4 audio frame number. Designates the audio
frame number for audio channels 1 to 4.
030
0
R/W
0
031
7-0
RATEA[2:0]
Ch1-4 sampling frequency. Designates the audio
sampling frequency for audio channels 1 to 4,
taken from the RATE word of the audio control
packet as defined in SMPTE 299M.
032
3-1
R/W
0
ASXA
Ch1-4 synchronization. When set HIGH, the "asx"
bit of the audio control packet RATE word
designates audio channels 1 to 4 as
asynchronous, as per SMPTE 299M. When set
LOW, the "asx" bit of the audio control packet
RATE word designates synchronous audio.
032
0
R/W
0
DEL1-2A[25:0]
Ch1/2 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 1 and 2.
033
1-0
R/W
0
034
7-0
035
7-0
036
7-0
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Table 5-29: Demultiplex Mode Host Interface Registers (Continued)
Control
Item
Name
Description
DEL3-4A[25:0]
Ch3/4 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 3 and 4.
RSRVA[17:0]
Ch1-4 reserve words. Designates the value set in
the RSRV words of the audio control packet for
audio channels 1 to 4, as per SMPTE 299M.
GS1503B HD Embedded Audio CODEC
Data Sheet
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December 2009
Address
Bit
R/W
Default
037
1-0
R/W
0
038
7-0
039
7-0
03A
7-0
03B
1-0
R/W
0
03C
7-0
03D
7-0
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Table 5-29: Demultiplex Mode Host Interface Registers (Continued)
Control
Item
Name
Description
Address
Bit
R/W
Default
Packet
Delete
RSV
Not used.
040
7-2
–
0
ANCI
Ancillary data delete. When set HIGH, all ancillary
data packets ("DEL_SEL" is LOW) or ancillary data
packets with DIDs designated in Host Interface
registers 041h and 042h ("DEL_SEL" is HIGH) are
removed from the video signal. The ancillary data
packets are replaced with blanking codes. The
data contained in the packets are output at the
corresponding pins. When set LOW, all ancillary
data packets remain in the video signal.
040
1
R/W
0
NOTE: The status of the ANCI external pin is not
updated in this register. The value programmed
in this register is logical OR'd with the ANCI
external pin setting
DEL_SEL
Ancillary data delete mode select. When set
HIGH, individual audio groups can be deleted
from the video signal by programming Host
Interface register 041h. When set LOW, all
ancillary data packets are deleted from the video
signal.
040
0
R/W
0
ADPG4_DEL
Audio group 4 data packet delete. When set
HIGH, all audio data packets with group 4 DID
will be deleted from the Chroma video data
stream. Valid only when "DEL_SEL" is HIGH.
041
7
R/W
0
ADPG3_DEL
Audio group 3 data packet delete. When set
HIGH, all audio data packets with group 3 DID
will be deleted from the Chroma video data
stream. Valid only when "DEL_SEL" is HIGH.
041
6
R/W
0
ADPG2_DEL
Audio group 2 data packet delete. When set
HIGH, all audio data packets with group 2 DID
will be deleted from the Chroma video data
stream. Valid only when "DEL_SEL" is HIGH.
041
5
R/W
0
ADPG1_DEL
Audio group 1 data packet delete. When set
HIGH, all audio data packets with group 1 DID
will be deleted from the Chroma video data
stream. Valid only when "DEL_SEL" is HIGH.
041
4
R/W
0
ACPG4_DEL
Audio group 4 control packet delete. When set
HIGH, all audio control packets with group 4 DID
will be deleted from the Luma video data stream.
Valid only when "DEL_SEL" is set HIGH. To be
fixed.
041
3
R/W
0
ACPG3_DEL
Audio group 3 control packet delete. When set
HIGH, all audio control packets with group 3 DID
will be deleted from the Luma video data stream.
Valid only when "DEL_SEL" is HIGH. To be fixed.
041
2
R/W
0
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Table 5-29: Demultiplex Mode Host Interface Registers (Continued)
Control
Item
Arbitrary
Data
Name
Description
Address
Bit
R/W
Default
ACPG2_DEL
Audio group 2 control packet delete. When set
HIGH, all audio control packets with group 2 DID
will be deleted from the Luma video data stream.
Valid only when "DEL_SEL" is HIGH. To be fixed.
041
1
R/W
0
ACPG1_DEL
Audio group 1 control packet delete. When set
HIGH, all audio control packets with group 1 DID
will be deleted from the Luma video data stream.
Valid only when "DEL_SEL" is HIGH. To be fixed.
041
0
R/W
0
NDID[7:0]
Arbitrary data packet delete. Designates the DID
for the arbitrary data packets to be deleted from
the Luma video data stream. Valid only when
"DEL_SEL" is HIGH.
042
7-0
R/W
0
ARBITON
Arbitrary data packet demultiplex. Valid only
when "ARBITMODE" is HIGH. When set HIGH,
arbitrary data packets will be demultiplexed from
the Luma video data stream. Must be set LOW
again to access valid data in the "ARBITUDW"
registers.
050
1
R/W
0
ARBITMODE
Arbitrary packet mode select. When set HIGH,
arbitrary data packets are demultiplexed and the
User Data Words are stored in Host Interface
registers 100h to 1FEh. No data will be output on
the PKT[7:0] external pins and PTKTEN will be
LOW. When set LOW, arbitrary data packets are
demultiplexed and output at the PKT[7:0]
external pins.
050
0
R/W
0
ARBITDID[7:0]
Arbitrary packet Data ID setting. Designates the 8
LSBs of the DID word of the arbitrary data packet
to be demultiplexed. The 2 MSBs are internally
generated. "ARBITDID[7]" is the MSB and
"ARBITDID[0]" is the LSB. Valid only when
"ARBITMODE" is HIGH.
051
7-0
R/W
0
ARBITSDID[7:0]
Arbitrary packet Secondary Data ID setting.
Designates the 8 LSBs of the secondary DID word
of the arbitrary data packet to be demultiplexed.
The 2 MSBs are internally generated.
"ARBITSDID[7]" is the MSB and "ARBITSDID[0]" is
the LSB. Valid only when "ARBITMODE" is HIGH.
052
7-0
R/W
0
ARBITDC[7:0]
Arbitrary packet DC setting. Designates the 8
LSBs of the Data Count word of the arbitrary
data packet to be demultiplexed. The 2 MSBs are
internally generated. "ARBITDC[7]" is the MSB
and "ARBITDC[0]" is the LSB. Valid only when
"ARBITMODE" is HIGH.
053
7-0
R/W
0
ARBITLINEB
Field 2 arbitrary packet demultiplex line number
setting. Designates the field 2 video line from
which the arbitrary data packets will be
demultiplexed. Valid only when "ARBITMODE" is
HIGH.
054
3-0
R/W
0
055
7-0
Packet
[11:0]
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Table 5-29: Demultiplex Mode Host Interface Registers (Continued)
Control
Item
Name
Description
ARBITLINEA
[11:0]
ARBITUDW0
:
ARBITUDW254
Address
Bit
R/W
Default
Field 1 arbitrary packet demultiplex line number
setting. Designates the field 1 video line from
which the arbitrary data packets will be
demultiplexed. Valid only when "ARBITMODE" is
HIGH.
056
3-0
R/W
0
057
7-0
Arbitrary packet User Data Word. Designates the
8 LSBs for up to 255 arbitrary packet User Data
Words. Arbitrary data can be read from these
registers once "ARBITON" has been set HIGH to
LOW. Valid only when "ARBITMODE" is HIGH.
100
7-0
R/W
0
:
:
1FE
7-0
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6. Using the GS1503B with the GS4911B or GS4910B
In Serial Audio multiplex mode, the GS4911B or GS4901B can be used to provide clocks
for the input audio. Figure 6-1 shows this arrangement.
Video Data
Video
Chain
PCLK (74.25MHz)
H V F
FSYNC
VSYNC
HSYNC
Audio
Chain
GS49X1B
ACLK1
ACLK2
ACLK3
MCLK (256fs)*
SCLK (128fs)
VIN[19:0]
PCLK
ACLKA (128fs)
WCLKA (48kHz)
AIN1/2
AIN3/4
ACLKA
WCINA
AIN1/2
AIN3/4
ACLKB (128fs)
WCLKB (48kHz)
AIN5/6
AIN7/8
ACLKB
WCINB
AIN5/6
AIN7/8
GS1503B
WCLK (48kHz)
*Optional
Figure 6-1: Using the GS1503B with the GS4911B or GS4910B in Serial Audio
Mode
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7. References & Bibliography
SMPTE 260M
1999 1125/60 High-Definition Production System - Digital
Representation and Bit-Parallel Interface
SMPTE 274M
1998 1920 x 1080 Scanning and Analog and Parallel Digital Interfaces for
Multiple Picture Rates
SMPTE 291M
1998 Ancillary Data Packet and Space Formatting
SMPTE 292M
1998 Bit-Serial Digital Interface for High-Definition Television Systems
SMPTE 295M
1997 1920 x 1080 50 Hz - Scanning and Interfaces
SMPTE 296M
2001 1280 x 720 Scanning, Analog and Digital Representation and
Analog Interface
SMPTE 299M
1997 24-Bit Digital Audio Format for HDTV Bit-Serial Interface
SMPTE RP211
2000 Implementation of 24P, 25P and 30P Segmented Frames for 1920 x
1080 Production Format
AES3-1992 (ANSI S4.40-1992) AES Recommended practice for digital audio engineering Serial transmission format for two-channel linearly represented digital audio data
AES-3id-2001 AES information document for digital audio engineering - Transmission of AES3
formatted data by unbalanced coaxial cable
EBU Tech. 3250-E Specification of the Digital Audio Interface (The AES/EBU Interface) (Second
Edition 1992)
Society of Motion Picture and Television Engineers: http://www.smpte.org
Audio Engineering Society: http://www.aes.org
European Broadcast Union: http://www.ebu.ch
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8. Packaging & Ordering Information
8.1 Package Dimensons
18.0 ± 0.4
16.0 ± 0.1
108
73
109
72
View on A-A
18.0 ± 0.4
16.0 ± 0.1
0.09-0.20
A
0˚ MIN
8˚ MAX
0.50
±0.2
INDEX
144
1.0
REF
37
1
36
1.0 ± 0.1
1.20 MAX
144 pin TQFP
Dimensions in millimetres
0.4
0.13-0.23
0.1
8.2 Packaging Data
Parameter
Value
Package Type
144 pin TQFP
Moisture Sensitivity Level
3
Junction to Case Thermal Resistance, θj-c
4°C/W
Junction to Air Thermal Resistance, θj-a (at zero
airflow)
39°C/W
Pb-free and RoHS Compliant
Yes
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8.3 Ordering Information
Part Number
Package
Temperature
Pb-Free
RoHS-Compliant
GS1503BCVE2
144 pin TQFP
0°C to 70°C
Yes
Yes
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9. Revision History
Version
ECR
Date
Changes / Modifications
1
153293
December 2009
Updated document format.
0
139048
August 2006
New document.
DOCUMENT IDENTIFICATION
CAUTION
DATA SHEET
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Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of
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All other trademarks mentioned are the properties of their respective owners.
GENNUM and the Gennum logo are registered trademarks of Gennum Corporation.
© Copyright 2006 Gennum Corporation. All rights reserved.
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